Motor driver circuit and hard disk device

Abstract

To provide a motor driver circuit that can make a clamp operation and an operation of a motor drive part independent to achieve simplification of the control.SOLUTION: A motor driver circuit 2 includes: a motor drive part 10 that drives a motor; a capacitor C0 charged by regenerative current from the motor drive part 10; a clamp circuit 20; and a clamp control circuit 30. The clamp circuit 20 includes: a transistor Q1 through which a reference current I3 flows; and a first current mirror circuit 21 having a transistor Q0 whose first main electrode is connected to the capacitor C0, whose second main electrode is connected to ground, and through which a mirror current Iout of the reference current I3 flows. The clamp control circuit 30 controls the transistor Q0 in such a manner that the regenerative current flows to the ground as the mirror current Iout, by flowing the reference current I3 to the transistor Q1 when voltage Vp at a junction point between the first capacitor C0 and the motor drive part 10 rises to first threshold voltage V1 due to the regenerative current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a motor driver circuit and a hard disk drive. [Background technology]

[0002] Patent Document 1 describes a motor driver circuit for driving a motor in a hard disk drive. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-044704

[0004] [overview] An object of the present disclosure is to provide a motor driver circuit and a hard disk drive that can simplify control by separating the clamp operation that absorbs regenerative current from the operation of the motor drive unit.

[0005] To solve the above-described problems, a first aspect of the present disclosure provides a motor driver circuit for controlling a motor, the motor driver circuit comprising: a motor drive unit that drives the motor; a first capacitor that is charged by regenerative current from the motor drive unit; a clamp circuit; and a clamp control circuit. The clamp circuit comprises a first current mirror circuit having a first transistor through which a reference current flows; and a clamp transistor having a first main electrode connected to the first capacitor and a second main electrode connected to ground, and through which a mirror current of the reference current flows. When the voltage at the connection point between the first capacitor and the motor drive unit rises to a predetermined first threshold voltage due to the regenerative current, the clamp control circuit controls the first transistor to pass a reference current of a predetermined current value, thereby causing the clamp transistor to pass the regenerative current to ground as a mirror current.

[0006] A second aspect of the present disclosure is a hard disk drive comprising a voice coil motor for driving a head, a spindle motor for rotating a disk, and a motor driver circuit according to the first aspect for controlling the voice coil motor and the spindle motor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram showing an example of the configuration of a hard disk drive and a motor driver circuit according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of a clamp circuit of the motor driver circuit according to the embodiment. [Figure 3] FIG. 3 is a time chart showing the time changes in the voltages at the VDD terminal and the VPWR terminal and the output signals of the first comparator and the second comparator of the clamp control circuit in the motor driver circuit according to the embodiment. [Figure 4] FIG. 4 is a time chart showing the voltage of the VPWR terminal, the output signal of the second comparator, the third current flowing through the first transistor and the second transistor, and the clamp current flowing through the clamp transistor in the motor driver circuit according to the embodiment.

[0008] [Detailed explanation] Hereinafter, a motor driver circuit and a hard disk drive according to an embodiment will be described in detail with reference to the drawings. However, it should be noted that the drawings are schematic and may differ from the actual ones.

[0009] The embodiments described below are comprehensive or specific examples. The numerical values, shapes, materials, components, installation positions, and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts are described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the following embodiments and their variations may include similar components, and the same reference numerals will be used to denote similar components, and redundant explanations will be omitted.

[0010] The configurations of a hard disk drive 1 and a motor driver circuit 2 according to an embodiment will be described with reference to FIG.

[0011] The hard disk device 1 includes a motor driver circuit 2, a voice coil motor (VCM) M1, and a spindle motor M2. In this embodiment, the motor driver circuit 2 is configured as a single semiconductor integrated circuit. The voice coil motor M1 is a motor for driving the head of the hard disk device 1. The voice coil motor M1 is connected to the AOUT terminal and the BOUT terminal of the motor driver circuit 2. The spindle motor M2 is a three-phase DC motor, and is a motor for rotating the disk of the hard disk device 1. The spindle motor M2 is connected to the SPA terminal, the SPB terminal, and the SPC terminal of the motor driver circuit 2.

[0012] The positive electrode of the variable DC power supply 3 is connected to the VDD terminal of the motor driver circuit 2, and a voltage Vi is supplied to it. The negative electrode of the variable DC power supply 3 is connected to the ground. A first end of a capacitor C0 is connected to the VPWR terminal of the motor driver circuit 2. A second end of the capacitor C0 is connected to the ground. The capacitor C0 is used to charge and discharge the regenerative current Ir from the spindle motor M2, and may have a capacitance of 47 μF, for example.

[0013] The motor driver circuit 2 includes a motor drive unit 10, a clamp circuit 20, a clamp control circuit 30, and a power supply line 40.

[0014] A first end of the power supply line 40 is connected to the VDD terminal via a transistor Q10 of the clamp control circuit 30, and is also connected to the VPWR terminal. A second end of the power supply line 40 is connected to ground via a clamp transistor Q0 of the clamp circuit 20.

[0015] The motor driving unit 10 includes a VCM driving unit 11 for controlling the driving of the voice coil motor M1 and a spindle driving unit 12 for controlling the driving of the spindle motor M2.

[0016] The VCM driver 11 has an input terminal connected to a power line 40 to receive power, and an output terminal connected to the voice coil motor M1 via the AOUT and BOUT terminals. The VCM driver 11 can control the operation of the voice coil motor M1 by switching between a linear mode that moves the head slightly and a pulse width modulation mode that allows for large head movements.

[0017] The spindle driver 12 has an input terminal connected to a power supply line 40 to receive power, and an output terminal connected to the spindle motor M2 via an SPA terminal, an SPB terminal, and an SPC terminal. The spindle driver 12 can recover the regenerative current Ir generated in the spindle motor M2 from the spindle motor M2 and pass it through the power supply line 40.

[0018] The clamp control circuit 30 includes a transistor Q10, a diode D1, a first comparator 31, a second comparator 32, and a gate driver 33.

[0019] In this embodiment, the transistor Q10 is configured as an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The transistor Q10 has a drain serving as a first main electrode connected to the power supply line 40, a source serving as a second main electrode connected to the variable DC power supply 3 via the VDD terminal, and a gate serving as a control electrode connected to the gate driver 33. A diode D1 is connected in parallel to the transistor Q10. The cathode of the diode D1 is connected to the first main electrode of the transistor Q10 and the power supply line 40, and the anode is connected to the variable DC power supply 3 via the second main electrode of the transistor Q10 and the VDD terminal. The diode D1 may be a parasitic diode of the transistor Q10.

[0020] The first comparator 31 has a negative input terminal − connected to the first main electrode of the transistor Q10 and the power supply line 40, and a positive input terminal + connected to the second main electrode of the transistor Q10 and the variable DC power supply 3 via the VDD terminal. The output terminal of the first comparator 31 is connected to the clamp circuit 20.

[0021] When the voltage Vp at the VPWR terminal is lower than the second threshold voltage V2, the gate driver 33 outputs an output signal VC0 at H level, turning on the transistor Q10. On the other hand, when the voltage Vp at the VPWR terminal reaches the second threshold voltage V2, the output signal VC0 of the gate driver 33 switches from H level to L level, turning off the transistor Q10. The second threshold voltage V2 is set to a value greater than the voltage Vi at the VDD terminal, for example, Vi + 10 mV. Furthermore, when the voltage Vp at the VPWR terminal reaches the second threshold voltage V2, the voltage Vp at the VPWR terminal becomes higher than the voltage Vi at the VDD terminal, and the output signal VC1 of the first comparator 31 switches from H level to L level.

[0022] The second comparator 32 has a negative input terminal − connected to the power supply line 40 and a positive input terminal + to which a first threshold voltage V1, for example, 15 V, is input. The output terminal of the second comparator 32 is connected to the clamp circuit 20.

[0023] Next, the configuration of the clamp circuit 20 will be described with reference to FIG.

[0024] The clamp circuit 20 includes a clamp transistor Q0, first to ninth transistors Q1 to Q9, a constant current source 24, and an RC circuit 25. The clamp transistor Q0 and the first transistor Q1 form a first current mirror circuit 21. The third transistor Q3 and the fourth transistor Q4 form a second current mirror circuit 22. The seventh transistor Q7 and the eighth transistor Q8 form a third current mirror circuit 23.

[0025] Next, the configuration of the third current mirror circuit 23 will be described. The first main electrode of the seventh transistor Q7 is connected to the control electrodes of the seventh transistor Q7 and the eighth transistor Q8 to form the third current mirror circuit 23. The second main electrodes of the seventh transistor Q7 and the eighth transistor Q8 are connected to the AGND terminal, which is the analog small signal ground. In the third current mirror circuit 23, a first current I1, which serves as a reference current, flows through the first main electrode of the seventh transistor Q7, and a second current I2, which serves as a mirror current, flows through the first main electrode of the eighth transistor Q8.

[0026] In this embodiment, the sizes of the seventh transistor Q7 and the eighth transistor Q8 are set so that the mirror ratio between the first current I1, which is the reference current of the third current mirror circuit 23, and the second current I2, which is the mirror current, is 1:32.

[0027] A first main electrode of the seventh transistor Q7 is connected to a constant current source 24 connected to a DC power supply VCC. The constant current source 24 outputs a first current I1 as a constant DC current. In this embodiment, the first current I1 is set to 20 μA. When the third current mirror circuit 23 is operating, the second current I2 becomes 0.64 mA, which is 32 times 20 μA. A first main electrode of the eighth transistor Q8 is connected to the third transistor Q3 of the second current mirror circuit 22 via the fifth transistor Q5.

[0028] A ninth transistor Q9 is connected in parallel to the seventh transistor Q7. More specifically, a first main electrode of the ninth transistor Q9 is connected to the first main electrode of the seventh transistor Q7, and a second main electrode of the ninth transistor Q9 is connected to the AGND terminal. A control electrode of the ninth transistor Q9 is connected to the output terminal of the first comparator 31 and receives the output signal VC1 of the first comparator 31.

[0029] When the output signal VC1 of the first comparator 31 is at H level, the ninth transistor Q9 is turned on, and the first current I1 is bypassed by the ninth transistor Q9 and flows to the AGND terminal without passing through the seventh transistor Q7. When the output signal VC1 of the first comparator 31 is at L level, the ninth transistor Q9 is turned off, and the first current I1 is not bypassed by the ninth transistor Q9 but flows from the seventh transistor Q7 to the AGND terminal. The ninth transistor Q9 also functions as part of the clamp control circuit 30.

[0030] In the embodiment, the seventh to ninth transistors Q7 to Q9 are N-channel MOSFETs, with the first main electrode serving as the drain, the second main electrode serving as the source, and the control electrode serving as the gate.

[0031] Next, the configuration of the second current mirror circuit 22 will be described. The first main electrode of the third transistor Q3 is connected to the control electrodes of the third transistor Q3 and the fourth transistor Q4 to form the second current mirror circuit 22. The second main electrodes of the third transistor Q3 and the fourth transistor Q4 are connected to the VPWR terminal. In the second current mirror circuit 22, the second current I2 as a reference current flows through the first main electrode of the third transistor Q3, and the third current I3 as a mirror current flows through the first main electrode of the fourth transistor Q4.

[0032] In this embodiment, the magnitudes of the third transistor Q3 and the fourth transistor Q4 are set so that the mirror ratio between the second current I2, which is the reference current of the second current mirror circuit 22, and the third current I3, which is the mirror current, is 1:25. When the third current mirror circuit 23 and the second current mirror circuit 22 are operating, the third current I3 is 16 mA, which is 25 times the second current I2=0.64 mA.

[0033] A first main electrode of the third transistor Q3 is connected to a first main electrode of the fifth transistor Q5, and a second main electrode of the fifth transistor Q3 is connected to a first main electrode of the eighth transistor Q8 of the third current mirror circuit 23. The fifth transistor Q5 is used to protect the third transistor Q3 and has a higher withstand voltage than the eighth transistor Q8. The fifth transistor Q5 is turned on in a range where the second current I2 of 0.64 mA can flow due to the voltage VB1 input to the control electrode.

[0034] A first main electrode of the fourth transistor Q4 is connected to a second main electrode of the sixth transistor Q6, and a first main electrode of the sixth transistor Q6 is connected to a first main electrode of the first transistor Q1 of the first current mirror circuit 21. The sixth transistor Q6 is used to protect the fourth transistor Q4 and has a higher withstand voltage than the fourth transistor Q4. The sixth transistor Q6 is turned on in a range where a voltage VB2 input to the control electrode allows the third current I3 to flow at 16 mA.

[0035] In this embodiment, the third transistor Q3, the fourth transistor Q4, and the sixth transistor Q6 are P-channel MOSFETs, and the fifth transistor Q5 is an N-channel MOSFET. The first main electrode is the drain, the second main electrode is the source, and the control electrode is the gate.

[0036] Next, the configuration of the first current mirror circuit 21 will be described. The first main electrode of the first transistor Q1 is connected to the control electrodes of the first transistor Q1 and the clamp transistor Q0 to form the first current mirror circuit 21. The second main electrodes of the first transistor Q1 and the clamp transistor Q0 are connected to the PGND terminal, which is the power ground. In the first current mirror circuit 21, a third current I3 as a reference current flows to the first main electrode of the first transistor Q1, and a clamp current Iout as a mirror current flows to the first main electrode of the clamp transistor Q0.

[0037] In this embodiment, the sizes of the first transistor Q1 and the clamp transistor Q0 are set so that the mirror ratio between the third current I3, which is the reference current of the first current mirror circuit 21, and the clamp current Iout, which is the mirror current, is 1:190. When the third current mirror circuit 23, the second current mirror circuit 22, and the first current mirror circuit 21 are operating, the clamp current Iout is 3.04 A, which is 190 times the third current I3=16 mA.

[0038] A first main electrode of the first transistor Q1 is connected to a first main electrode of the fourth transistor Q4 via a sixth transistor Q6. A terminal T0 of the first main electrode of the clamp transistor Q0 is connected to a VPWR terminal of the motor driver circuit 2 via an electric wire L0 that is part of the power supply line 40. Control electrodes of the first transistor Q1 and the clamp transistor Q0 are connected to a PGND terminal via a resistor R0.

[0039] A wire L0 connects a terminal T0 of the first main electrode of the clamp transistor Q0 to a VPWR terminal of the motor driver circuit 2. The wire L0 may be an internal wiring of the motor driver circuit 2 configured as a semiconductor integrated circuit. By using the wire L0 as an internal wiring of the motor driver circuit 2, the configuration of the power supply line 40 of the motor driver circuit 2 configured as a semiconductor integrated circuit can be simplified.

[0040] The electric wire L0 may be an external wire not included in the semiconductor integrated circuit, such as a wire arranged in a package that mounts the semiconductor integrated circuit, a wire arranged on a printed circuit board on which the package is mounted, or a bonding wire. By using the electric wire L0 as an external wire not included in the semiconductor integrated circuit, it is possible to reduce internal interference caused by a common impedance inside the motor driver circuit 2 that is configured as a semiconductor integrated circuit.

[0041] A second transistor Q2 is connected in parallel to the first transistor Q1. More specifically, a first main electrode of the second transistor Q2 is connected to the first main electrode of the first transistor Q1, and a second main electrode of the second transistor Q2 is connected to the PGND terminal. A control electrode of the second transistor Q2 is connected to the output terminal of the second comparator 32 via the RC circuit 25, and receives the output signal VC2 of the second comparator 32.

[0042] When the output signal VC2 of the second comparator 32 is at H level, the second transistor Q2 is turned on, and the third current I3 from the fourth transistor Q4 is bypassed by the second transistor Q2 and flows to the PGND terminal without passing through the first transistor Q1. When the output signal VC2 of the second comparator 32 is at L level, the second transistor Q2 is turned off, and the third current I3 from the fourth transistor Q4 is not bypassed by the second transistor Q2 and flows from the first transistor Q1 to the PGND terminal.

[0043] The RC circuit 25 includes resistors R1, R2, a capacitor C1, and a switch S1. The resistor R1 has a first terminal connected to the output terminal of the second comparator 32 and a second terminal connected to the control electrode of the second transistor Q2. The resistor R2 has a first terminal connected to the control electrode of the second transistor Q2 and a second terminal connected to the PGND terminal via the switch S1. The capacitor C1 has a first terminal connected to the control electrode of the second transistor Q2 and a second terminal connected to the PGND terminal. The capacitance of the capacitor C1 is variable, for example, within a range of 5 pF to 20 pF. The switch S1 is turned off when the output signal VC2 of the second comparator 32 is at H level, and turned on when it is at L level.

[0044] With this configuration, when the output signal VC2 of the second comparator 32 switches from H level to L level, the second transistor Q2 turns off within a time period determined by the time constant of the capacitor C1 and the resistors R1 and R2 connected in parallel with the capacitor C1. On the other hand, when the output signal VC2 of the second comparator 32 switches from L level to H level, the second transistor Q2 turns on within a time period determined by the time constant of the resistor R1 and the capacitor C1. By setting the resistor R1 to different values, e.g., 500 kΩ and the resistor R2 to different values, e.g., 100 kΩ, the time it takes for the second transistor Q2 to change from ON to OFF and the time it takes for the second transistor Q2 to change from OFF to ON can be set to different values. The second transistor Q2 and the RC circuit 25 also function as part of the clamp control circuit 30.

[0045] In the embodiment, N-channel MOSFETs are used for the clamp transistor Q0, the first transistor Q1, the second transistor Q2, and the switch S1, with the first main electrode being the drain, the second main electrode being the source, and the control electrode being the gate.

[0046] Next, the operation of the motor driver circuit 2 will be described with reference to Fig. 3. Fig. 3 is a time chart that schematically shows the relationship between the voltage Vi at the VDD terminal, the voltage Vp at the VPWR terminal, and the output signal VC1 of the first comparator 31 and the output signal VC2 of the second comparator 32 of the clamp control circuit 30 as they change over time.

[0047] The motor driver circuit 2 operates in a normal operation mode until time t1, in which regenerative current Ir from the spindle motor M2 does not flow into the motor driver circuit 2. In the normal operation mode, the output signal VC0 of the gate driver 33 is at the H level, turning on the transistor Q10. This causes the voltage Vi of the variable DC power supply 3 to be supplied to the power supply line 40 via the transistor Q10. The voltage at the VDD terminal is equal to the voltage Vi of the variable DC power supply 3 and changes as the voltage Vi of the variable DC power supply 3 changes from 12 V to 16 V to 12 V. The voltage Vp at the VPWR terminal is lower by ΔV than the voltage Vi of the variable DC power supply 3 due to the on-resistance Ron of the transistor Q10. For example, if the on-resistance Ron of the transistor Q10 is 50 mΩ and the current IDD supplied from the variable DC power supply 3 is 2 A, then Δ=0.1 V, and the voltage at the VDD terminal Vi - 0.1 V = the voltage Vp at the VPWR terminal.

[0048] The voltage at the positive input terminal + of the first comparator 31 is equal to the voltage Vi at the VDD terminal, and the voltage at the negative input terminal - is equal to the voltage Vp at the VPWR terminal, so the output signal VC1 is always at H level. The second comparator 32 receives 15 V as a first threshold voltage V1 at its positive input terminal + and the voltage Vp at the VPWR terminal at its negative input terminal -. Therefore, the output signal VC2 of the second comparator 32 is at H level when the voltage Vp at the VPWR terminal is smaller than the first threshold voltage V1, and is at L level when the voltage Vp at the VPWR terminal reaches the first threshold voltage V1.

[0049] In the normal operating mode, the output signal VC1 of the first comparator 31 is always high. This means that a high signal is always input to the control electrode of the ninth transistor Q9 of the clamp circuit 20, keeping the ninth transistor Q9 always on. At this time, the first current I1 from the constant current source 24 is bypassed by the ninth transistor Q9 and flows to the AGND terminal, but not to the seventh transistor Q7. Therefore, regardless of whether the output signal VC2 of the second comparator 32 is high or low, the third current mirror circuit 23 does not operate, and I2 = I3 = Iout = 0 A. In other words, because the clamp transistor Q0 is off, the clamp current Iout is 0 A. At this time, of the current IDD = 2 A supplied from the variable DC power supply 3, a current Iv = 0.5 A is supplied to the VCM driver 11 to drive the voice coil motor M1, and a current Ip = 1.5 A is supplied to the spindle driver 12 to drive the spindle motor M2.

[0050] Next, at time t1, the motor driver circuit 2 enters a regenerative current mode in which a regenerative current Ir=1.5 A generated in the spindle motor M2 is supplied to the power supply line 40 via the spindle drive unit 12. At this time, the voltage Vi of the variable DC power supply 3 is constant at 12 V. Of the regenerative current Ir=1.5 A, a current Iv=0.5 A is supplied to the VCM drive unit 11 to drive the voice coil motor M1, and a current Ic=1.0 A is supplied from the VPWR terminal to the capacitor C0. At this time, the current IDD supplied from the variable DC power supply 3 becomes 0 A.

[0051] Then, because capacitor C0 is charged by current Ic, voltage Vp at the VPWR terminal rises from 12V-ΔV=11.9V and reaches second threshold voltage V2=12.01V at time t2. When voltage Vp at the VPWR terminal reaches second threshold voltage V2 at time t2, output signal VC0 of gate driver 33 switches from H level to L level, turning off transistor Q10. Furthermore, because voltage Vp at the VPWR terminal becomes larger than voltage Vi at the VDD terminal, output signal VC1 of first comparator 31 switches from H level to L level.

[0052] As a result, the ninth transistor Q9 of the motor driver circuit 2 changes from on to off, the first current I1 = 20 μA from the constant current source 24 flows to the seventh transistor Q7, and the third current mirror circuit 23 operates. As a result, the second current I2 = 0.64 mA flows to the eighth transistor Q8. Then, the second current mirror circuit 22 also operates, and the third current I3 = 16 mA flows from the fourth transistor Q4.

[0053] However, because the voltage Vp of the VPWR terminal is smaller than the first threshold voltage V1=15, the output signal VC2 of the second comparator 32 is at H level, and the second transistor Q2 is turned on. The third current I3=16 mA from the fourth transistor Q4 is bypassed by the second transistor Q2 and flows to the PGND terminal, and does not flow to the first current mirror circuit 21. For this reason, the first current mirror circuit 21 does not operate, and the clamp current Iout is maintained at 0 A.

[0054] Then, capacitor C0 is charged by current Ic, and at time t3, when voltage Vp at the VPWR terminal reaches first threshold voltage V1=15 V, output signal VC2 of second comparator 32 switches from H level to L level. Then, second transistor Q2 switches from ON to OFF in a time period determined by the time constant set by RC circuit 25. As a result, third current I3=16 mA switches from flowing through second transistor Q2 to flowing through first transistor Q1. During the time until third current I3 switches from flowing through second transistor Q2 to flowing through first transistor Q1 of first current mirror circuit 21, capacitor C0 is further charged by current Ic, and voltage Vp at the VPWR terminal becomes greater than first threshold voltage V1=15 V.

[0055] When the third current (=16 mA) flows through the first transistor Q1 of the first current mirror circuit 21, the clamp current Iout (=3.04 A) flows to the PGND terminal via the clamp transistor Q0. In other words, the clamp transistor Q0 is turned on within a range in which the second transistor Q2 flows the clamp current Iout (=3.04 A) to the PGND terminal for a time period according to the time constant set by the RC circuit 25.

[0056] At this time, of the regenerative current Ir=1.5A from the spindle motor M2, Iv=0.5A flows to the VCM driver 11. Then, the remaining 1.0A of the regenerative current Ir=1.5A and the current Ic=2.04A from the capacitor C0 flow to the PGND terminal via the clamp transistor Q0.

[0057] When the current Ic=2.04 A from the capacitor C0 begins to flow to the PGND terminal, the capacitor C0 is discharged, and the voltage Vp at the VPWR terminal decreases. Then, at time t4, when the voltage Vp at the VPWR terminal becomes smaller than the first threshold voltage V1=15 V, the output signal VC2 of the second comparator 32 switches from L level to H level. Then, the second transistor Q2 switches from OFF to ON after a period of time corresponding to the time constant set by the RC circuit 25. As a result, the third current I3=16 mA switches from flowing through the first transistor Q1 to the second transistor Q2.

[0058] Furthermore, during the time until the third current I3 switches from the first transistor Q1 to the second transistor Q2 of the first current mirror circuit 21 and flows, capacitor C0 is further discharged, and the voltage Vp at the VPWR terminal becomes even smaller than the first threshold voltage V1=15 V. When the third current flowing through the second transistor Q2 increases from 0 A to 16 mA, the third current flowing through the first transistor Q1 decreases from 16 mA to 0 A, and the clamp current Iout decreases from 3.04 A to 0 A. Then, of the regenerative current Ir=1.5 A from the spindle motor M2, current Iv=0.5 A is supplied to the VCM driver 11 to drive the voice coil motor M1, and current Ic=1.0 A supplied from the VPWR terminal charges capacitor C0.

[0059] Then, at time t5, when the voltage Vp at the VPWR terminal again reaches the first threshold voltage V1=15 V, the output signal VC2 of the second comparator 32 switches from H level to L level, and the same operation as from time t3 onwards is performed. Also, at time t6, when the voltage Vp at the VPWR terminal becomes smaller than the first threshold voltage V1=15 V, the output signal VC2 of the second comparator 32 switches from L level to H level, and the same operation as from time t4 onwards is performed.

[0060] Next, the operation of the motor driver circuit 2 will be further described with reference to Fig. 4. Fig. 4 is a time chart showing the simulation results of the voltage Vp at the VPWR terminal, the output signal VC2 of the second comparator, the third current I3 flowing through the first transistor Q1 and the second transistor Q2, and the clamp current Iout flowing through the clamp transistor Q0.

[0061] As described with reference to FIG. 3, the current Ic=1.0 A supplied from the VPWR terminal out of the regenerative current Ir=1.5 A charges the capacitor C0, and at time t3, the voltage Vp at the VPWR terminal reaches the first threshold voltage V1=15 V. Then, the output signal VC2 of the second comparator 32 switches from H level to L level. Then, the second transistor Q2 turns off for a period of time corresponding to the time constant of the RC circuit 25, causing the third current I3 flowing through the second transistor Q2 to decrease from 16.11 mA to 0 A, and the third current I3 flowing through the first transistor Q1 to increase from 0 A to 16.11 mA. In response to this, the clamp current Iout flowing through the clamp transistor Q0 increases from 0 A to 3.33 A.

[0062] During this time, capacitor C0 is charged by current Ic supplied from the VPWR terminal, and the voltage Vp of the VPWR terminal rises to 15.12 V. Then, when clamp current Iout flowing through clamp transistor Q0 reaches 3.33 A, capacitor C0 is discharged by clamp current Iout, and the voltage Vp of the VPWR terminal drops from 15.12 V.

[0063] Then, at time t4, when the voltage Vp of the VPWR terminal becomes smaller than the first threshold voltage V1 (=15 V), the output signal VC2 of the second comparator 32 switches from low to high. Then, the second transistor Q2 switches from off to on in a time period determined by the time constant set by the RC circuit 25. The third current I3 flowing through the second transistor Q2 increases from 0 A to 16.11 mA, and the third current I3 flowing through the first transistor Q1 decreases from 16.11 mA to 0 A. In response to this, the clamp current Iout flowing through the clamp transistor Q0 decreases from 3.33 A to A0 A.

[0064] During this time, the capacitor C0 is discharged by the clamp current Iout, and the voltage Vp at the VPWR terminal drops to 14.95 V. Then, the second transistor Q2 is turned on, causing the clamp current Iout flowing through the clamp transistor Q0 to become 0 A.

[0065] As a result, the current Ic=1.0 A supplied from the VPWR terminal, out of the regenerative current Ir=1.5 A, begins to charge the capacitor C0, and at time t5, the voltage Vp at the VPWR terminal again reaches the first threshold voltage V1=15 V. This causes the output signal VC2 of the second comparator 32 to switch from H level to L level. The second transistor Q2 then turns off for a period of time that depends on the time constant of the RC circuit 25, causing the third current I3 flowing through the second transistor Q2 to decrease from 16.11 mA to 0 A, and the third current I3 flowing through the first transistor Q1 to increase from 0 A to 16.11 mA. In response to this, the clamp current Iout flowing through the clamp transistor Q0 increases from 0 A to 3.33 A.

[0066] During this time, capacitor C0 is charged by current Ic supplied from the VPWR terminal, and the voltage Vp of the VPWR terminal rises to 15.04 V. When clamp current Iout flowing through clamp transistor Q0 reaches 3.33 A, capacitor C0 is discharged by clamp current Iout, and the voltage Vp of the VPWR terminal drops from 15.04 V. When the voltage Vp of the VPWR terminal becomes smaller than the first threshold voltage V1 (=15 V) at time t6, the output signal VC2 of the second comparator 32 switches from L level to H level.

[0067] In the regenerative current mode, the motor driver circuit 2 then repeats the operation from time t4 to time t6 at a period corresponding to the time constant of the RC circuit 25. The simulation results shown in Figure 5 show that the motor driver circuit 2 repeats the operation from time t4 to time t6 at a period of 7.17 μs corresponding to the time constant of the RC circuit 25, i.e., at a frequency of 139 kHz.

[0068] As described above, the motor driver circuit 2 and hard disk drive 1 according to the embodiment enable the clamping operation of the clamp circuit 20 to absorb the regenerative current Ir from the spindle motor M2 to be performed independently of the operation of the motor drive unit 10, thereby simplifying control. Furthermore, because the clamp circuit 20 is independent of the motor drive unit 10, noise generated at the AOUT and BOUT terminals due to the regenerative current Ir can be reduced during the clamping operation of the clamp circuit 20 to absorb the regenerative current Ir from the spindle motor M2. This prevents a deterioration in the accuracy of speed control of the voice coil motor M1 connected to the AOUT and BOUT terminals. Furthermore, because the clamp circuit 20 is independent of the motor drive unit 10, the clamping operation by the clamp circuit 20 can be performed in both linear mode and pulse width modulation mode of operation of the voice coil motor M1 by the VCM drive unit 11 of the motor drive unit 10.

[0069] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment may be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and explanatory, and is not intended to be limiting of the present disclosure.

[0070] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0071] (Appendix 1) The motor driver circuit 2 for controlling the motors M1 and M2 includes a motor drive unit 10 that drives the motors M1 and M2, a capacitor C0 that is charged by regenerative current from the motor drive unit 10, a clamp circuit 20, and a clamp control circuit 30. The clamp circuit 20 includes a first current mirror circuit 21. The first current mirror circuit 21 includes a first transistor Q1 through which a reference current I3 flows, and a clamp transistor Q0 that has a first main electrode connected to the capacitor C0 and a second main electrode connected to ground and through which a mirror current Iout of the reference current I3 flows. When the voltage Vp at the connection point between the capacitor C0 and the motor drive unit 10 rises to a predetermined first threshold voltage V1 due to the regenerative current, the clamp control circuit 30 controls the clamp transistor Q0 to pass the regenerative current to ground as the mirror current Iout by passing a predetermined value of reference current I3 through the first transistor Q1.

[0072] According to the motor driver circuit 2 described in Supplementary Note 1, the clamping operation of absorbing the regenerative current from the motor M2 by the clamp circuit 20 and the operation of the motor drive unit 10 are independent of each other, which simplifies the control.

[0073] (Appendix 2) In the motor driver circuit 2 described in Appendix 1, when the voltage Vp at the connection point between the capacitor C0 and the motor drive unit 10 is smaller than the first threshold voltage V1, the clamp control circuit 30 controls the clamp transistor Q0 not to pass the regenerative current to ground as the mirror current Iout by not passing the reference current I3 through the first transistor Q1.

[0074] (Appendix 3) In the motor driver circuit 2 described in Supplementary Note 1 or 2, the clamp control circuit 30 includes a second transistor Q2, a second comparator 32, and an RC circuit 25. The second transistor Q2 is capable of bypassing the reference current I3 to ground without passing through the first transistor Q1. The second comparator 32 controls the second transistor Q2 to turn off when the voltage Vp at the connection point between the capacitor C0 and the motor drive unit 10 rises to a first threshold voltage V1, and to turn on when the voltage Vp at the connection point between the capacitor C0 and the motor drive unit 10 is lower than the first threshold voltage V1. The RC circuit 25 includes resistors R1 and R2 and a capacitor C1 connected between the output terminal of the second comparator 32 and the control electrode of the second transistor Q2. The on and off times of the second transistor Q2 can be adjusted by the time constant of the RC circuit 25.

[0075] (Appendix 4) In the motor driver circuit 2 described in any one of Supplementary Notes 1 to 3, the motor drive unit 10, the clamp circuit 20, and the clamp control circuit 30 are configured in a single semiconductor integrated circuit. A first main electrode of the clamp transistor Q0 is connected to a terminal of the semiconductor integrated circuit by an external wiring that is not included in the semiconductor integrated circuit.

[0076] Since the first main electrode of the clamp transistor Q0 is connected to a terminal of the semiconductor integrated circuit by external wiring that is not included in the semiconductor integrated circuit, it is possible to reduce internal interference caused by common impedance inside the motor driver circuit 2 that is made up of the semiconductor integrated circuit.

[0077] (Appendix 5) In the motor driver circuit 2 described in Supplementary Note 4, bonding wires are used for the external wiring.

[0078] (Appendix 6) In the motor driver circuit 2 described in Supplementary Note 4, the external wiring is wiring arranged in a package that mounts a semiconductor integrated circuit, or wiring arranged on a printed circuit board on which the package is mounted.

[0079] (Appendix 7) In the motor driver circuit 2 described in any one of Supplementary Notes 1 to 3, the motor drive unit 10, the clamp circuit 20, and the clamp control circuit 30 are configured as a single semiconductor integrated circuit. A first main electrode of the clamp transistor Q0 is connected to a terminal of the semiconductor integrated circuit by an internal wiring of the semiconductor integrated circuit.

[0080] The first main electrode of the clamp transistor Q0 is connected to a terminal of the semiconductor integrated circuit by an internal wiring of the semiconductor integrated circuit, so that the configuration of the power supply line 40 of the motor driver circuit 2 can be simplified.

[0081] (Appendix 8) The hard disk drive 1 includes a voice coil motor M1 for driving the head, a spindle motor M2 for rotating the disk, and a motor driver circuit 2 described in any one of Supplementary Notes 1 to 7 for controlling the voice coil motor M1 and the spindle motor M2.

[0082] According to the hard disk device 1 described in Supplementary Note 8, the clamping operation of absorbing the regenerative current from the spindle motor M2 by the clamp circuit 20 and the operation of the motor drive unit 10 are independent, which simplifies the control. [Explanation of symbols]

[0083] 1. Hard disk drive 2 Motor driver circuit 3 Variable DC power supply 10 Motor drive unit 11 VCM drive unit 12 Spindle drive unit 20 Clamp Circuit 21 First current mirror circuit 22 Second current mirror circuit 23 Third current mirror circuit 24 Constant current source 25 RC circuit 30 Clamp control circuit 31 First Comparator 32 Second Comparator 33 Gate Driver 40 Power Line C0 First capacitor C1 capacitor D1 Diode I1 1st current I2 2nd current I3 3rd current Ic Current supplied to the capacitor from the regenerative current IDD Current supplied to the VDD pin from the variable DC power supply Iout clamp current Ir Regenerative current Iv Current supplied from regenerative current to the voice coil motor L0 electric wire M1 voice coil motor M2 spindle motor Q0 clamp transistor Q1 First transistor Q2 Second transistor Q3 Third transistor Q4 Fourth transistor Q5 5th transistor Q6 6th transistor Q7 7th transistor Q8 8th transistor Q9 9th transistor Q10 transistor R0, R1, R2 resistors S1 Switch T0 Terminal of the first main electrode of the clamping transistor V1 First threshold voltage V2 Second threshold voltage VC0 Gate driver output signal VCC DC power supply Vi VDD pin voltage Vp VPWR terminal voltage

Claims

1. A motor driver circuit for controlling a motor, a motor driving unit that drives the motor; a first capacitor that is charged by a regenerative current from the motor drive unit; a clamp circuit including a first current mirror circuit having a first transistor through which a reference current flows, and a clamp transistor having a first main electrode connected to the first capacitor and a second main electrode connected to ground, and through which a mirror current of the reference current flows; a clamp control circuit that controls the clamp transistor to pass the regenerative current to the ground as the mirror current by passing the reference current of a predetermined current value through the first transistor when the voltage at the connection point between the first capacitor and the motor drive unit rises to a predetermined first threshold voltage due to the regenerative current; A motor driver circuit comprising:

2. 2. The motor driver circuit according to claim 1, wherein the clamp control circuit controls the clamp transistor not to pass the regenerative current to the ground as the mirror current by not passing the reference current through the first transistor when the voltage at the connection point between the first capacitor and the motor drive unit is smaller than the first threshold voltage.

3. The clamp control circuit a second transistor capable of bypassing the reference current to the ground without passing through the first transistor; a comparator that controls the second transistor to be turned off when a voltage at a connection point between the first capacitor and the motor drive unit rises to the first threshold voltage, and to be turned on when the voltage at the connection point between the first capacitor and the motor drive unit is lower than the first threshold voltage; an RC circuit including a resistor and a second capacitor connected between the output terminal of the comparator and the control electrode of the second transistor; Equipped with The on and off times of the second transistor can be adjusted by the time constant of the RC circuit.

2. The motor driver circuit according to claim 1.

4. the motor drive unit, the clamp circuit, and the clamp control circuit are configured as a single semiconductor integrated circuit, the first main electrode of the clamp transistor is connected to a terminal of the semiconductor integrated circuit by an external wiring that is not included in the semiconductor integrated circuit; 2. The motor driver circuit according to claim 1.

5. 5. The motor driver circuit according to claim 4, wherein the external wiring is a bonding wire.

6. 5. The motor driver circuit according to claim 4, wherein the external wiring is wiring arranged on a package that mounts the semiconductor integrated circuit, or wiring arranged on a printed circuit board on which the package is mounted.

7. the motor drive unit, the clamp circuit, and the clamp control circuit are configured as a single semiconductor integrated circuit, the first main electrode of the clamp transistor is connected to a terminal of the semiconductor integrated circuit by an internal wiring of the semiconductor integrated circuit; 2. The motor driver circuit according to claim 1.

8. a voice coil motor for driving the head; a spindle motor for rotating the disk; a motor driver circuit according to any one of claims 1 to 7, which controls the voice coil motor and the spindle motor; A hard disk drive comprising:

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