Semiconductor device

Abstract

To provide a semiconductor device capable of reducing both leakage current in an off state and resistance in an on state.SOLUTION: A semiconductor device includes: a first electrode; a first semiconductor layer of a first conductivity type disposed over the first electrode; a second semiconductor layer of a second conductivity type disposed over the first semiconductor layer and including a first part and a plurality of second parts of which the distance from the first electrode is shorter than the distance between the first electrode and the first part; a third semiconductor layer of a first conductivity type disposed over the second semiconductor layer; a second electrode facing the second semiconductor layer with an insulating layer interposed therebetween; a plurality of contacts respectively disposed in a region immediately above the plurality of second parts and connected to the second semiconductor layer and the third semiconductor layer; and a third electrode connected to the plurality of contacts.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] In recent years, vertical MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have been used as semiconductor devices for power control. Such semiconductor devices are required to suppress leakage current between the source and drain in the off state while reducing the electrical resistance between the source and drain in the on state. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-006639 [Patent Document 2] U.S. Patent No. 9,847,395 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment is to provide a semiconductor device that can achieve both a reduction in leakage current in the off state and a reduction in resistance in the on state. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor layer of a first conductivity type arranged on the first electrode, a second semiconductor layer of a second conductivity type arranged on the first semiconductor layer, the second semiconductor layer having a first portion and a plurality of second portions whose distance from the first electrode is shorter than the distance between the first electrode and the first portion, a third semiconductor layer of the first conductivity type arranged on the second semiconductor layer, a second electrode facing the second semiconductor layer via an insulating layer, a plurality of contacts arranged in regions directly above the plurality of second portions and connected to the second semiconductor layer and the third semiconductor layer, and a third electrode connected to the plurality of contacts. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line BB' shown in FIG. [Figure 4] FIG. 4 is a plan view showing the semiconductor device according to the second embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along line CC' shown in FIG. [Figure 6] FIG. 6 is a plan view showing a semiconductor device according to the third embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line DD' shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line EE' shown in FIG. [Figure 9] FIG. 9 is a plan view showing a semiconductor device according to the fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line FF' shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line GG' shown in FIG. [Figure 12] FIG. 12 is a plan view showing a semiconductor device according to the fifth embodiment. [Figure 13]FIG. 13 is a cross-sectional view taken along line HH' shown in FIG. [Figure 14] FIG. 14(a) is a plan view showing a semiconductor device according to the sixth embodiment, and FIG. 14(b) is a partially enlarged plan view showing region I in FIG. 14(a). [Figure 15] FIG. 15 is a cross-sectional view taken along line JJ' shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along the line KK' shown in FIG. [Figure 17] FIG. 17(a) is a plan view showing a semiconductor device according to the seventh embodiment, and FIG. 17(b) is a partially enlarged plan view showing a region L in FIG. 17(a). [Figure 18] FIG. 18 is a cross-sectional view taken along line MM' shown in FIG. 17(a). [Figure 19] FIG. 19(a) is a plan view showing a semiconductor device according to the eighth embodiment, and FIG. 19(b) is a partially enlarged plan view showing a region N in FIG. 19(a). [Figure 20] FIG. 20 is a cross-sectional view taken along line OO' shown in FIG. [Figure 21] FIG. 21(a) is a plan view showing a semiconductor device according to the ninth embodiment, and FIG. 21(b) is a partially enlarged plan view showing a region P in FIG. 21(a). [Figure 22] FIG. 22 is a cross-sectional view taken along line QQ' shown in FIG. 21(a). [Figure 23] FIG. 23(a) is a plan view showing a semiconductor device according to the tenth embodiment, and FIG. 23(b) is a partially enlarged plan view showing a region R in FIG. 23(a). DETAILED DESCRIPTION OF THE INVENTION

[0007] First Embodiment FIG. 1 is a plan view showing a semiconductor device according to this embodiment. FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. FIG. 3 is a cross-sectional view taken along line BB' shown in FIG.

[0008] Please note that each figure is a schematic representation and has been exaggerated or simplified as appropriate. For example, the dimensional ratios of each part have been adjusted to prioritize ease of understanding of the technical concept over accurately representing the actual product. Furthermore, the dimensional ratios and positional relationships of the components between figures do not necessarily match exactly. This also applies to the other figures described below.

[0009] As shown in Figures 1 to 3, the semiconductor device 1 according to this embodiment includes a drain electrode 20 (first electrode), a semiconductor portion 30, an insulating film 40, a source electrode 50 (third electrode), an insulating member 60, a gate electrode 70 (second electrode), a field plate electrode 80 (fourth electrode, hereinafter referred to as "FP electrode 80"), and a contact 90.

[0010] The drain electrode 20, semiconductor portion 30, insulating film 40, and source electrode 50 are arranged in this order. The insulating member 60 is disposed above the semiconductor portion 30 and in contact with the insulating film 40. The gate electrode 70 and FP electrode 80 are disposed within the insulating member 60. The FP electrode 80 is disposed inside the insulating member 60 and below the gate electrode 70. In other words, the FP electrode 80 is disposed between the drain electrode 20 and the gate electrode 70. Note that the insulating film 40 and the source electrode 50 are not shown in FIG. 1 . The same applies to other plan views described later.

[0011] The drain electrode 20, the source electrode 50, and the contact 90 are made of a conductive material, such as a metal. The gate electrode 70 and the FP electrode 80 are also made of a conductive material, such as impurity-containing polysilicon or a metal. The insulating film 40 and the insulating member 60 are made of an insulating material, such as silicon oxide.

[0012] The semiconductor portion 30 is made of a semiconductor material, for example, single-crystal silicon (Si) containing impurities. + drain layer 31, conductivity type n -a drift layer 32 of p-type, a base layer 33 (second semiconductor layer) of p-type conductivity, and a + A source layer 34 (third semiconductor layer) of a type is provided. The drain layer 31 and the drift layer 32 form a first semiconductor layer. Along the direction from the drain electrode 20 toward the source electrode 50, the drain layer 31, the drift layer 32, the base layer 33, and the source layer 34 are arranged in this order.

[0013] "n + "N-type" means that the carrier concentration is higher than that of "n-type", and "n - "N-type" indicates a lower carrier concentration than "n-type." The same applies to p-type. "Carrier concentration" refers to the effective impurity concentration that contributes to the conductivity of a semiconductor, and when a region contains both impurities that act as acceptors and impurities that act as donors, it refers to the concentration excluding the offset amounts between them.

[0014] A plurality of insulating members 60 are provided, and extend in one direction above the semiconductor portion 30. The gate electrode 70 is disposed inside the insulating member 60, and faces the base layer 33 via a gate insulating layer 61 that is part of the insulating member 60. The gate electrode 70 is connected to a gate pad (not shown) disposed on the semiconductor portion 30. The FP electrode 80 faces the drift layer 32 via a portion 62 of the insulating member 60. The FP electrode 80 is connected to the source electrode 50. In this specification, "connection" means electrical connection.

[0015] For convenience of explanation, this specification employs an XYZ Cartesian coordinate system. The direction from the drain electrode 20 toward the source electrode 50 is referred to as the "Z direction," the direction in which the insulating members 60 are arranged is referred to as the "X direction," and the direction in which each insulating member 60 extends is referred to as the "Y direction." The Z direction is also referred to as "up" and the opposite direction as "down," but these expressions are also for convenience and are unrelated to the direction of gravity.

[0016] A plurality of contacts 90 are provided. Each contact 90 has a generally columnar shape with its axial direction extending in the Z direction. The upper end of the contact 90 is in contact with the lower surface of the source electrode 50. The upper part of the contact 90 is disposed within the insulating film 40. The lower part of the contact 90 is disposed within the source layer 34 and the base layer 33, and is in contact with the source layer 34 and the base layer 33. In this way, the contact 90 connects the base layer 33 and the source layer 34 to the source electrode 50. The contact 90 may be formed integrally with the source electrode 50.

[0017] The contacts 90 are arranged along a side surface 70a of the gate electrode 70 facing the base layer 33. In this embodiment, the contacts 90 are arranged in a line along the Y direction in a portion of the semiconductor portion 30 that is arranged between the insulating members 60. The contacts 90 are also spaced apart from the insulating members 60. For example, the contact 90 is arranged in the center in the X direction of the portion of the semiconductor portion 30 that is arranged between the insulating members 60.

[0018] The base layer 33 is provided with a first portion 33a and a plurality of second portions 33b. Each second portion 33b is disposed directly below a corresponding contact 90, and the lower surface of the second portion 33b protrudes downward below the lower surface of the first portion 33a. Therefore, the distance L2 between the drain electrode 20 and the second portion 33b is shorter than the distance L1 between the drain electrode 20 and the first portion 33a. That is, L2 <L1である。

[0019] In the manufacturing process of the semiconductor device 1, the second portion 33b is formed by forming a hole in the semiconductor portion 30 for forming the contact 90, and then ion-implanting an impurity that will become an acceptor through the hole. Then, the hole is filled with a conductive material to form the contact 90. Therefore, the shape of the second portion 33b is, for example, a substantially hemispherical shape that is convex downward and centered on the lower end of the contact 90. The center of the second portion 33b is located on an extension of the central axis of the contact 90. The multiple second portions 33b are arranged at a distance from each other along the Y direction.

[0020] The base layer 33 may contain platinum (Pt). The drift layer 32 may also contain platinum. Platinum is also ion-implanted into the semiconductor portion 30 through holes for forming the contacts 90 during the manufacturing process of the semiconductor device 1. For this reason, the platinum concentration reaches its maximum near the bottom end of the contacts 90 in the base layer 33.

[0021] Next, the operation of the semiconductor device 1 will be described. When a voltage is applied to the drain electrode 20 so that the electrode is positive and to the source electrode 50 so that the electrode is negative, n - A depletion layer spreads from the interface between the p-type drift layer 32 and the p-type base layer 33. In this state, when a potential higher than the threshold is applied to the gate electrode 70, an inversion layer is formed in the portion of the base layer 33 facing the gate electrode 70, i.e., in the portion of the base layer 33 in contact with the gate insulating layer 61, and a current flows from the drain electrode 20 to the source electrode 50. This turns the semiconductor device 1 on. On the other hand, when the potential of the gate electrode 70 is made lower than the threshold, the inversion layer disappears and no current flows. This turns the semiconductor device 1 off. When the semiconductor device 1 is turned off, the voltage between the drain electrode 20 and the source electrode 50 is applied to the depletion layer.

[0022] In the semiconductor device 1, the second portion 33b is provided in the base layer 33 directly below the contact 90. This makes it possible to distance the depletion layer from the contact 90, and to reduce the leakage current (hereinafter also referred to as "off current") that flows between the drain electrode 20 and the source electrode 50 in the off state.

[0023] Furthermore, the contacts 90 are arranged at intervals from one another along the Y direction, and the second portions 33b of the base layer 33 are also arranged at intervals from one another along the Y direction. For this reason, the second portions 33b are not disposed directly below the portions between the contacts 90 in the Y direction. As a result, the electrical resistance between the drain electrode 20 and the source electrode 50 in the on state (hereinafter also referred to as "on resistance") is less likely to increase.

[0024] For example, even if the positions of the contact 90 and the second portion 33b in the X direction are shifted from their designed positions due to manufacturing errors, causing the second portion 33b to come into contact with the insulating member 60, in the cross section not including the contact 90 shown in Figure 3, the second portion 33b is unlikely to come into contact with the insulating member 60, and the channel length is unlikely to increase. Therefore, the on-resistance is unlikely to increase.

[0025] Next, the effects of this embodiment will be described. According to this embodiment, by arranging the multiple contacts 90 at a distance from one another and providing the second portion 33b of the base layer 33 directly below each contact 90, the depletion layer is kept away from the contacts 90 in the off state, and a region where the second portion 33b is not located can be secured in the portion where the base layer 33 contacts the insulating member 60. As a result, a semiconductor device 1 can be realized that can achieve both reduced off-current and reduced on-resistance.

[0026] In this embodiment, the base layer 33 contains platinum. This causes a level derived from platinum to be formed in the silicon band gap of the base layer 33. As a result, n - When a forward voltage is applied to the pn interface between the p-type drift layer 32 and the p-type base layer 33, and then a reverse voltage is applied to this pn interface, the electrons and holes that have penetrated into the semiconductor portion 30 are recombined via the platinum-derived levels. As a result, the electrons and holes in the semiconductor portion 30 quickly disappear, and Qrr (reverse recovery charge) is reduced.

[0027] The platinum concentration distribution in the semiconductor portion 30 reaches a maximum near the bottom end of the contact 90. In this embodiment, the second portion 33b is provided in the base layer 33, so that the platinum-rich portion is kept away from the depletion layer when the semiconductor device 1 is in the off state. This reduces the electric field applied to the platinum-rich portion, thereby reducing leakage current.

[0028] <Second embodiment> FIG. 4 is a plan view showing the semiconductor device according to this embodiment. FIG. 5 is a cross-sectional view taken along line CC' shown in FIG.

[0029] As shown in Figures 4 and 5, the semiconductor device 2 of this embodiment differs from the semiconductor device 1 of the first embodiment in that the base layer 33 has multiple third portions 33c in addition to the first portion 33a and the second portion 33b.

[0030] The third portion 33c is disposed on the first portion 33a and between adjacent contacts 90. Therefore, the third portion 33c is in contact with the source layer 34 in the X direction, in contact with the contact 90 in the Y direction, and in contact with the insulating film 40 and the first portion 33a of the base layer 33 in the Z direction. The conductivity type of the third portion 33c is p + The carrier concentration of the third portion 33c is higher than the carrier concentrations of the first portion 33a and the second portion 33b.

[0031] In this embodiment, the third portion 33c is provided in the base layer 33, so that the source potential transmitted from the source electrode 50 via the contact 90 is easily transmitted to the entire base layer 33 via the third portion 33c of the base layer 33. As a result, compared to the first embodiment, it is possible to effectively suppress the rise in the potential of the base layer 33 and improve the avalanche resistance. Other configurations, operations, and effects of this embodiment are the same as those of the first embodiment.

[0032] <Third embodiment> FIG. 6 is a plan view showing the semiconductor device according to this embodiment. FIG. 7 is a cross-sectional view taken along line DD' shown in FIG. FIG. 8 is a cross-sectional view taken along line EE' shown in FIG.

[0033] 6 to 8, the semiconductor device 3 according to this embodiment differs from the semiconductor device 2 according to the second embodiment in that the third portion 33c of the base layer 33 extends across the entire width of the base layer 33 in the X direction. For example, the third portion 33c is in contact with the insulating member 60 on both sides in the X direction. In this case, the source layer 34 is not interposed between the third portion 33c and the insulating member 60.

[0034] The semiconductor device 3 according to this embodiment has a wider second portion 33c of the base layer 33 than the semiconductor device 2 according to the second embodiment, and therefore the source potential can be transmitted to the entire base layer 33 more effectively, thereby further improving the avalanche resistance. On the other hand, the semiconductor device 2 has a larger contact area between the source layer 34 and the insulating member 60 than the semiconductor device 3, and therefore has a larger channel width and a lower on-resistance. Other configurations, operations, and effects of this embodiment are the same as those of the second embodiment.

[0035] <Fourth embodiment> FIG. 9 is a plan view showing the semiconductor device according to this embodiment. FIG. 10 is a cross-sectional view taken along line FF' shown in FIG. FIG. 11 is a cross-sectional view taken along line GG' shown in FIG.

[0036] As shown in Figures 9 to 11, the semiconductor device 4 of this embodiment differs from the semiconductor device 2 of the second embodiment in that the third portions 33c of the base layer 33 are arranged not only between the contacts 90 in the Y direction but also on both sides of the contacts 90 in the X direction.

[0037] That is, the third portions 33c are arranged on both sides in the X direction and both sides in the Y direction of the contact 90. Of the third portions 33c, the portions arranged on both sides in the X direction of the contact 90 are in contact with the contact 90 on one side in the X direction and in contact with the insulating member 60 on the other side in the X direction.

[0038] In the semiconductor device 4 according to this embodiment, the second portion 33c of the base layer 33 is disposed on both sides of the contact 90 in the X direction and on both sides of the contact 90 in the Y direction, so that the potential of the source electrode 50 can be transmitted more effectively to the entire base layer 33. As a result, the avalanche resistance can be further improved. On the other hand, the semiconductor device 2 has a larger contact area between the source layer 34 and the insulating member 60 than the semiconductor device 4, so that the channel width is larger and the on-resistance is lower. Other configurations, operations, and effects of this embodiment are the same as those of the second embodiment.

[0039] <Fifth embodiment> FIG. 12 is a plan view showing the semiconductor device according to this embodiment. FIG. 13 is a cross-sectional view taken along line HH' shown in FIG.

[0040] 12 and 13 , the semiconductor device 5 according to this embodiment differs from the semiconductor device 1 according to the first embodiment in that the second portions 33b of the base layer 33 are disposed only in the regions directly below every other contact 90 among the plurality of contacts 90 arranged along the Y direction, and are not disposed in the regions directly below the other contacts 90. Furthermore, for the plurality of contacts 90 arranged along the X direction, the second portions 33b are disposed only in the regions directly below every other contact 90, and are not disposed in the regions directly below the other contacts 90. Therefore, when viewed from the Z direction, the contacts 90 are arranged in a matrix along the X and Y directions, while the second portions 33b are arranged in a staggered pattern.

[0041] The semiconductor device 5 according to this embodiment has a smaller number of second portions 33b than the semiconductor device 1 according to the first embodiment. This prevents the channel length from increasing due to the second portions 33b. That is, even if the positions of the contact 90 and the second portions 33b in the X direction are shifted from the center between the insulating members 60 due to manufacturing process errors or the like, the second portions 33b contact the insulating members 60, preventing an increase in the length of the region of the base layer 33 in contact with the insulating members 60 in the Z direction. As a result, the semiconductor device 5 has a lower on-resistance than the semiconductor device 1. Meanwhile, the semiconductor device 1 can more reliably distance the depletion layer from the contact 90 compared to the semiconductor device 5, resulting in a lower off-current. Other configurations, operations, and effects of this embodiment are similar to those of the first embodiment.

[0042] Sixth Embodiment FIG. 14(a) is a plan view showing the semiconductor device according to this embodiment, and FIG. 14(b) is a partially enlarged plan view showing region I in FIG. 14(a). FIG. 15 is a cross-sectional view taken along line JJ' shown in FIG. FIG. 16 is a cross-sectional view taken along the line KK' shown in FIG.

[0043] As shown in Figures 14 to 16, the semiconductor device 6 of this embodiment differs from the semiconductor device 1 of the first embodiment in the shape and arrangement of the gate electrode 70 and FP electrode 80, the provision of a gate insulating layer 63 and an insulating member 64 instead of the insulating member 60, and the provision of a contact 91.

[0044] When viewed from the Z direction, the gate electrode 70 has a lattice shape. That is, the gate electrode 70 has a plurality of portions extending in the X direction and a plurality of portions extending in the Y direction. The gate insulating layer 63 is disposed between the gate electrode 70 and the semiconductor portion 30. Therefore, when viewed from the Z direction, the gate insulating layer 63 also has a lattice shape. The gate electrode 70 faces the semiconductor portion 30 with the gate insulating layer 63 interposed therebetween.

[0045] The FP electrodes 80 are arranged in a dot pattern. A plurality of FP electrodes 80 are provided and arranged in a matrix along the X and Y directions. When viewed from the Z direction, each of the plurality of FP electrodes 80 is surrounded by a lattice-shaped gate electrode 70. The FP electrodes 80 are shaped like columns whose axial direction extends in the Z direction.

[0046] The insulating member 64 is disposed between the gate electrode 70 and the semiconductor portion 30. In other words, each FP electrode 80 is disposed inside each insulating member 64 and faces the semiconductor portion 30 via the insulating member 64. The insulating member 64 is separated from the gate insulating layer 63 via the semiconductor portion 30.

[0047] The contacts 90 are spaced apart from one another at the boundary between the insulating member 64 and the semiconductor portion 30. The contacts 90 are arranged along the side surface 70a of the gate electrode 70 that faces the base layer 33. Therefore, when viewed from the Z direction, the contacts 90 are arranged to surround each FP electrode 80. A portion of each contact 90 is arranged in the semiconductor portion 30, and the remainder is arranged in the insulating member 64.

[0048] As in the first embodiment, the base layer 33 is provided with a first portion 33a and a second portion 33b. Each second portion 33b is disposed in a region directly below each contact 90 in the semiconductor portion 30. The second portion 33b protrudes downward relative to the first portion 33a. Therefore, the distance L2 between the drain electrode 20 and the second portion 33b is shorter than the distance L1 between the drain electrode 20 and the first portion 33a. The second portions 33b are spaced apart from one another, and the drift layer 32 is interposed between adjacent second portions 33b.

[0049] The contact 91 is disposed directly above the FP electrode 80. The upper end of the contact 91 is connected to the source electrode 50, and the lower end of the contact 91 is connected to the FP electrode 80. As a result, the FP electrode 80 is connected to the source electrode 50 via the contact 91. The shape of the contact 91 may be the same as or different from the shape of the contact 90. The contacts 90 and 91 may be formed integrally with the source electrode 50.

[0050] Next, the effects of this embodiment will be described. In this embodiment, the second portion 33b of the base layer 33 is also provided directly under the contact 90, so that the depletion layer can be kept away from the contact 90. This reduces the leakage current (off current) between the drain electrode 20 and the source electrode 50 in the off state.

[0051] Furthermore, because the second portions 33b of the base layer 33 are intermittently disposed along the gate electrode 70, the second portions 33b can be reliably separated from the gate insulating layer 63 in the portions of the base layer 33 where the second portions 33b are not disposed. This ensures that the channel length is not increased in portions due to the second portions 33b, and the on-resistance can be maintained low. In this way, both a low off-current and a low on-resistance can be achieved.

[0052] Furthermore, by arranging each contact 90 across the insulating member 64 and the semiconductor portion 30, it becomes easier to separate the second portion 33b from the gate insulating layer 63. This makes it possible to prevent the channel length from increasing due to the second portion 33b, and to prevent an increase in on-resistance. Other configurations, operations, and effects of this embodiment are the same as those of the first embodiment.

[0053] Seventh Embodiment FIG. 17(a) is a plan view showing the semiconductor device according to this embodiment, and FIG. 17(b) is a partially enlarged plan view showing a region L in FIG. 17(a). FIG. 18 is a cross-sectional view taken along line MM' shown in FIG. 17(a).

[0054] As shown in Figures 17 and 18, the semiconductor device 7 of this embodiment differs from the semiconductor device 6 of the sixth embodiment in that the base layer 33 has multiple third portions 33c in addition to the first portion 33a and the second portion 33b.

[0055] The third portion 33c is disposed on the first portion 33a and between adjacent contacts 90. Therefore, the third portion 33c is in contact with the source layer 34 on the gate electrode 70 side, in contact with the insulating member 64 on the FP electrode 80 side, in contact with the contact 90 in both directions along the interface between the base layer 33 and the insulating member 64, and in contact with the insulating film 40 and the first portion 33a of the base layer 33 in the Z direction. The carrier concentration of the third portion 33c is higher than the carrier concentrations of the first portion 33a and the second portion 33b.

[0056] The third portion 33c of the base layer 33 can be formed by, for example, ion implantation of impurities that will serve as acceptors using a mask having an opening in a region including the boundary between the semiconductor portion 30 and the insulating member 64. In this case, the impurities implanted into the insulating member 64 do not contribute to conductivity, but the portion of the third portion 33c with the highest carrier concentration can be located near the interface between the base layer 33 and the insulating member 64. As a result, it is possible to prevent the third portion 33c from being located near the gate insulating layer 63, and to suppress an increase in on-resistance.

[0057] In this embodiment, the third portion 33c is provided in the base layer 33, so that the source potential transmitted from the source electrode 50 via the contact 90 is easily transmitted to the entire base layer 33. As a result, compared to the sixth embodiment, the increase in the potential of the base layer 33 can be effectively suppressed, and the avalanche resistance can be improved. Other configurations, operations, and effects of this embodiment are the same as those of the sixth embodiment.

[0058] Eighth Embodiment FIG. 19(a) is a plan view showing the semiconductor device according to this embodiment, and FIG. 19(b) is a partially enlarged plan view showing a region N in FIG. 19(a). FIG. 20 is a cross-sectional view taken along line OO' shown in FIG.

[0059] 19 and 20 , the semiconductor device 8 according to this embodiment differs from the semiconductor device 7 according to the seventh embodiment in that the third portion 33c of the base layer 33 extends across the entire width of the base layer 33 in the direction from the insulating member 64 toward the gate insulating layer 63. For example, the third portion 33c is in contact with both the insulating member 64 and the gate insulating layer 63. In this case, the source layer 34 is not interposed between the third portion 33c and the gate insulating layer 63.

[0060] The semiconductor device 8 according to this embodiment has a larger area of ​​the third portion 33c of the base layer 33 than the semiconductor device 7 according to the seventh embodiment, and therefore can further improve the avalanche resistance. On the other hand, the semiconductor device 7 has a larger contact area between the source layer 34 and the gate insulating layer 63 than the semiconductor device 8, and therefore has a larger channel width and a lower on-resistance. Other configurations, operations, and effects of this embodiment are the same as those of the seventh embodiment.

[0061] <Ninth embodiment> FIG. 21(a) is a plan view showing the semiconductor device according to this embodiment, and FIG. 21(b) is a partially enlarged plan view showing a region P in FIG. 21(a). FIG. 22 is a cross-sectional view taken along line QQ' shown in FIG. 21(a).

[0062] 21 and 22 , the semiconductor device 9 according to this embodiment differs from the semiconductor device 7 according to the seventh embodiment in that the third portion 33c of the base layer 33 is also provided between the contact 90 and the gate insulating layer 63. For example, the third portion 33c provided between the contact 90 and the gate insulating layer 63 is in contact with both the contact 90 and the gate insulating layer 63.

[0063] The semiconductor device 9 according to this embodiment has a larger area of ​​the third portion 33c of the base layer 33 than the semiconductor device 7 according to the seventh embodiment, and therefore can further improve the avalanche resistance. On the other hand, the semiconductor device 7 has a larger contact area between the source layer 34 and the gate insulating layer 63 than the semiconductor device 9, and therefore has a larger channel width and a lower on-resistance. Other configurations, operations, and effects of this embodiment are the same as those of the seventh embodiment.

[0064] <Tenth embodiment> FIG. 23(a) is a plan view showing the semiconductor device according to this embodiment, and FIG. 23(b) is a partially enlarged plan view showing a region R in FIG. 23(a).

[0065] 23, the semiconductor device 10 according to this embodiment has a different diameter for some of the contacts 90 compared to the semiconductor device 7 according to the seventh embodiment. That is, the multiple contacts 90 include contacts 90b arranged between the intersections 70b of the lattice-shaped gate electrodes 70 and the corners 64b of the insulating members 64 when viewed from the Z direction, and other contacts 90a.

[0066] The diameter of the contact 90b is larger than the diameter of the contact 90a. The diameter of the contact 90 is the maximum diameter when viewed in the Z direction. For example, if the shape of the contact 90 is rectangular when viewed in the Z direction, the diameter of the contact 90 is the length of the diagonal of the rectangle. Furthermore, the distance between the intersection 70b of the gate electrode 70 and the contact 90b is shorter than the distance between the intersection 70b and the contact 90a. The contact 90b may be in contact with the gate insulating layer 63, may be separated from the gate insulating layer 63 via the source layer 34, or may be separated from the gate insulating layer 63 via the third portion 33c of the base layer 33.

[0067] Compared to the semiconductor device 7 of the seventh embodiment, the semiconductor device 10 of this embodiment can alleviate the concentration of the electric field at the bottom of the intersection 70b of the gate electrode 70. Furthermore, by reducing the volume of the base layer 33 near the intersection 70b of the gate electrode 70, depletion in the off state can be promoted, and the leakage current (off current) can be further reduced. On the other hand, the semiconductor device 7 has a larger contact area between the source layer 34 and the gate insulating layer 63 than the semiconductor device 10, and therefore has a larger channel width and a lower on-resistance. Other configurations, operations, and effects of this embodiment are the same as those of the seventh embodiment.

[0068] In the above-described embodiments, the FP electrode 80 has a rectangular shape when viewed from the Z direction, but the present invention is not limited to this. The shape of the FP electrode 80 when viewed from the Z direction may be, for example, a circle, an oval, or a polygon such as a hexagon.

[0069] Furthermore, in the sixth to tenth embodiments described above, examples have been shown in which the FP electrodes 80 are arranged in rows and columns along the X and Y directions, but the present invention is not limited to this. The FP electrodes 80 may be arranged, for example, at positions corresponding to the vertices of an equilateral triangle when viewed from the Z direction.

[0070] According to the embodiment described above, it is possible to realize a semiconductor device that can achieve both a reduction in leakage current in the off state and a reduction in resistance in the on state.

[0071] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can also be implemented in combination with each other.

[0072] The present invention includes the following aspects.

[0073] (Appendix 1) A first electrode; a first semiconductor layer of a first conductivity type disposed on the first electrode; a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer being of a second conductivity type, the second semiconductor layer having a first portion and a plurality of second portions, the distance between the first portion and the first electrode being shorter than the distance between the first electrode and the first portion; a third semiconductor layer of the first conductivity type disposed on the second semiconductor layer; a second electrode facing the second semiconductor layer via an insulating layer; a plurality of contacts respectively disposed in regions directly above the plurality of second portions and connected to the second semiconductor layer and the third semiconductor layer; a third electrode connected to the plurality of contacts; A semiconductor device comprising:

[0074] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the plurality of contacts are arranged along a side surface of the second electrode facing the second semiconductor layer.

[0075] (Appendix 3) 3. The semiconductor device according to claim 1, wherein the second semiconductor layer contains silicon and platinum.

[0076] (Appendix 4) The second electrode is provided in plurality, the plurality of second electrodes are arranged along a first direction, and each of the second electrodes extends in a second direction intersecting the first direction; 4. The semiconductor device according to claim 1, wherein the contact is spaced apart from the insulating layer.

[0077] (Appendix 5) 5. The semiconductor device according to claim 4, wherein the second portion is spaced apart from the insulating layer.

[0078] (Appendix 6) 6. The semiconductor device according to claim 4, wherein the second semiconductor layer further includes a third portion disposed between adjacent contacts, in contact with the contacts, and having a carrier concentration higher than the carrier concentration of the first portion.

[0079] (Appendix 7) 7. The semiconductor device according to claim 6, wherein a part of the third semiconductor layer is disposed between the second electrode and the third portion.

[0080] (Appendix 8) 7. The semiconductor device according to claim 6, wherein the third portion is in contact with the insulating layer.

[0081] (Appendix 9) 7. The semiconductor device according to claim 6, wherein the third portion is also disposed between the contact and the insulating layer.

[0082] (Appendix 10) The semiconductor device according to any one of appendixes 4 to 9, wherein the second portion is arranged in the area directly below every other one of the contacts arranged in the second direction, and is not arranged in the area directly below other of the contacts.

[0083] (Appendix 11) The semiconductor device according to any one of appendices 4 to 10, further comprising a fourth electrode arranged between the first electrode and the second electrode, connected to the third electrode, and facing the first semiconductor layer via an insulating member.

[0084] (Appendix 12) a plurality of fourth electrodes connected to the third electrodes, arranged in a matrix along a first direction and a second direction intersecting the first direction, and facing the second semiconductor layer via an insulating member; 4. The semiconductor device according to claim 1, wherein the second electrode has a portion extending in the first direction and a portion extending in the second direction.

[0085] (Appendix 13) 13. The semiconductor device according to claim 12, wherein the second electrodes have a lattice shape surrounding each of the fourth electrodes when viewed from a third direction perpendicular to the first direction and the second direction.

[0086] (Appendix 14) 14. The semiconductor device according to claim 12, wherein the second portion is in contact with the insulating layer.

[0087] (Appendix 15) The semiconductor device according to any one of appendices 12 to 14, wherein the second semiconductor layer further has a third portion disposed between adjacent contacts, in contact with the contacts, and having a carrier concentration higher than the carrier concentration of the second portion.

[0088] (Appendix 16) 16. The semiconductor device according to claim 15, wherein a part of the third semiconductor layer is disposed between the second electrode and the third portion.

[0089] (Appendix 17) 16. The semiconductor device according to claim 15, wherein the third portion is in contact with the insulating layer.

[0090] (Appendix 18) 16. The semiconductor device according to claim 15, wherein the third portion is also disposed between the contact and the insulating layer.

[0091] (Appendix 19) the plurality of contacts include a first contact and a second contact; the diameter of the second contact is larger than the diameter of the first contact; 19. The semiconductor device according to any one of claims 12 to 18, wherein the distance between the intersection of the second electrode and the second contact is shorter than the distance between the intersection and the first contact. [Explanation of symbols]

[0092] 1-10 Semiconductor devices 20 drain electrode 30 Semiconductor part 31 Drain layer 32 Drift Layer 33 Base Layer 33a Part 1 33b Part 2 33c Part 3 34 Source Layer 40 insulating film 50 Source electrode 60 Insulating material 61 Gate insulating layer 62 parts 63 Gate insulating layer 64 Insulating material 64b Corner 70 gate electrode 70a side 70b Intersection 80 FP electrode (field plate electrode) 90, 90a, 90b, 91 Contact L1: Distance between the drain electrode 20 and the first portion 33a L2: Distance between the drain electrode 20 and the second portion 33b

Claims

1. A first electrode; a first semiconductor layer of a first conductivity type disposed on the first electrode; a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer being of a second conductivity type, the second semiconductor layer having a first portion and a plurality of second portions, the distance between the first portion and the first electrode being shorter than the distance between the first electrode and the first portion; a third semiconductor layer of the first conductivity type disposed on the second semiconductor layer; a second electrode facing the second semiconductor layer via an insulating layer; a plurality of contacts disposed in regions directly above the second portions and connected to the second semiconductor layer and the third semiconductor layer; a third electrode connected to the plurality of contacts; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the plurality of contacts are arranged along a side surface of the second electrode facing the second semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the second semiconductor layer includes silicon and platinum.

4. The second electrode is provided in plurality, the plurality of second electrodes are arranged along a first direction, and each of the second electrodes extends in a second direction intersecting the first direction; 4. The semiconductor device according to claim 1, wherein the contact is spaced apart from the insulating layer.

5. The semiconductor device according to claim 4 , wherein the second portion is spaced apart from the insulating layer.

6. 5. The semiconductor device according to claim 4, wherein the second semiconductor layer further includes a third portion disposed between adjacent contacts, in contact with the contact, and having a carrier concentration higher than that of the first portion.

7. The semiconductor device according to claim 6 , wherein a part of the third semiconductor layer is disposed between the second electrode and the third portion.

8. The semiconductor device according to claim 6 , wherein the third portion is in contact with the insulating layer.

9. The semiconductor device according to claim 6 , wherein the third portion is also disposed between the contact and the insulating layer.

10. 5. The semiconductor device according to claim 4, wherein the second portions are disposed in regions directly below every other one of the contacts in the second direction, and are not disposed in regions directly below other of the contacts.

11. 5. The semiconductor device according to claim 4, further comprising a fourth electrode disposed between the first electrode and the second electrode, connected to the third electrode, and facing the first semiconductor layer via an insulating member.

12. a plurality of fourth electrodes connected to the third electrodes, arranged in a matrix along a first direction and a second direction intersecting the first direction, and facing the second semiconductor layer via an insulating member; 4. The semiconductor device according to claim 1, wherein the second electrode has a portion extending in the first direction and a portion extending in the second direction.

13. 13. The semiconductor device according to claim 12, wherein the second electrodes have a lattice shape surrounding the fourth electrodes when viewed from a third direction perpendicular to the first direction and the second direction.

14. The semiconductor device according to claim 12 , wherein the second portion is in contact with the insulating layer.

15. The semiconductor device according to claim 12 , wherein the second semiconductor layer further includes a third portion disposed between adjacent contacts, in contact with the contact, and having a carrier concentration higher than that of the second portion.

16. The semiconductor device according to claim 15 , wherein a part of the third semiconductor layer is disposed between the second electrode and the third portion.

17. The semiconductor device according to claim 15 , wherein the third portion is in contact with the insulating layer.

18. The semiconductor device according to claim 15 , wherein the third portion is also disposed between the contact and the insulating layer.

19. the plurality of contacts include a first contact and a second contact; the diameter of the second contact is greater than the diameter of the first contact; The semiconductor device according to claim 12 , wherein a distance between the intersection of the second electrode and the second contact is shorter than a distance between the intersection and the first contact.

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