Electronic circuit

Abstract

To obtain a delay time difference among multiple wires.SOLUTION: An electronic circuit is configured in a measurement mode of a delay time difference between a first wire and a second wire by connecting an input terminal of a first inverter section and an output terminal of a second inverter section, the other end of the first wire and the input terminal of the second inverter, an input terminal of a third inverter section and an output terminal of a fourth inverter section, and the other end of a second wire and the input terminal of the fourth inverter section, and is configured in a normal mode for transmitting a clock signal generated by a clock generator to a first logic circuit and a second logic circuit by connecting the input terminal of the first inverter and the output terminal of the clock generator, the other end of the first wire and the input terminal of the first logic circuit, the input terminal of the third inverter section and the output terminal of the clock generator, and the other end of the second wire and the input terminal of the second logic circuit.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present embodiment relates to an electronic circuit. [Background technology]

[0002] When supplying operating clock signals from a clock signal source to multiple logic circuits, differences in the lengths of the wiring to each logic circuit can cause differences in the operation timing of each logic circuit. Therefore, at the design stage, it is necessary to calculate as accurately as possible the delay time differences between multiple wiring lengths and reflect this in the timing design of each logic circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-030492 Summary of the Invention [Problem to be solved by the invention]

[0004] The present embodiment aims to provide an electronic circuit for determining the delay time difference between a plurality of wirings. [Means for solving the problem]

[0005] In order to solve the above problem, the electronic circuit of this embodiment is an electronic circuit that supplies a clock signal generated by a clock generator to a first logic circuit and a second logic circuit, and includes: a first inverter unit including an even number of inverters connected in series; a first wiring having one end connected to the output terminal of the first inverter unit; a second inverter unit including an odd number of inverters at least one connected in series; a third inverter unit including the same number of inverters connected in series as the first inverter unit; a second wiring having one end connected to the output terminal of the third inverter unit; and a fourth inverter unit including the same number of inverters connected in series as the second inverter unit.

[0006] The electronic circuit is configured in a mode for measuring the delay time difference between the first wiring and the second wiring by connecting the input terminal of the first inverter unit and the output terminal of the second inverter unit, the other end of the first wiring and the input terminal of the second inverter unit, the input terminal of the third inverter unit and the output terminal of the fourth inverter unit, and the other end of the second wiring and the input terminal of the fourth inverter unit.

[0007] The electronic circuit is configured in a normal mode in which the clock signal generated by the clock generator is transmitted to the first logic circuit and the second logic circuit by connecting the input terminal of the first inverter unit and the output terminal of the clock generator, the other end of the first wiring and the input terminal of the first logic circuit, the input terminal of the third inverter unit and the output terminal of the clock generator, and the other end of the second wiring and the input terminal of the second logic circuit. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing a configuration of an electronic device according to a first embodiment. [Figure 2] FIG. 10 is a diagram illustrating an example of a delay time difference TΔ. [Figure 3] FIG. 10 is a diagram showing the connection state of the electronic device in measurement mode. [Figure 4] FIG. 4 is a diagram showing a simplified configuration of the ring oscillator of FIG. [Figure 5] FIG. 2 is a diagram illustrating a connection state of the electronic device in normal mode. [Figure 6] FIG. 10 is a diagram showing a configuration of an electronic device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present embodiment will be described with reference to the drawings. In the drawings, the same or corresponding elements are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0010] (Embodiment 1) FIG. 1 is a diagram showing a configuration of an electronic device 100 including an electronic circuit 110 according to a first embodiment. The electronic device 100 includes a clock generator 1, the electronic circuit 110, a first logic circuit 10, and a second logic circuit 20. The electronic circuit 110 includes an IC package 2, a first wiring L1, a second wiring L2, a wiring La, a wiring Lb, a wiring Lc, a wiring Ld, and first to fourth connection switching terminal units 11 to 14. The clock generator 1, the electronic circuit 110, the first logic circuit 10, and the second logic circuit 20 are all mounted on the same substrate. The electronic circuit 110 has a measurement mode for measuring a delay time difference in a clock signal transmission path from the clock generator 1 to the first logic circuit 10 and the second logic circuit 20, and a normal mode for transmitting (providing) a clock signal generated by the clock generator 1 to the first logic circuit 10 and the second logic circuit 20. In the normal mode, the operation timings of the first logic circuit 10 and the second logic circuit 20 are set in consideration of the delay time difference calculated based on the measurement mode. The electronic device 100 of FIG. 1 will now be described in detail.

[0011] The first connection switching terminal section 11 includes an N10 terminal (fourth terminal), an N11 terminal (fifth terminal), and an N12 terminal (sixth terminal). The second connection switching terminal section 12 includes an N20 terminal (first terminal), an N21 terminal (second terminal), or an N22 terminal (third terminal). The third connection switching terminal section 13 includes an N30 terminal (tenth terminal), an N31 terminal (eleventh terminal), and an N32 terminal (twelfth terminal). The fourth connection switching terminal section 14 includes an N40 terminal (seventh terminal), an N41 terminal (eighth terminal), and an N42 terminal (ninth terminal).

[0012] The clock generator 1 generates a clock signal that periodically repeats Hi and Low. The output (output terminal) 3 of the clock generator 1 is connected to the N12 terminal (sixth terminal) of the first connection switching terminal unit 11 and the N32 terminal (twelfth terminal) of the third connection switching terminal unit 13.

[0013] The IC package 2 includes a first inverter section 15 configured with X inverters, where X is an even number, and a third inverter section 25 configured with the same number of inverters as the first inverter section 15. The IC package 2 also includes a second inverter section 16 configured with Y inverters, where Y is an odd number, and a fourth inverter section 26 configured with Y inverters, where Y is the same number of inverters as the second inverter section 16. X is an even number greater than or equal to 2, and Y is an odd number greater than or equal to 1.

[0014] The first inverter unit 15 and the third inverter unit 25 logically invert the input signal input to their input terminals 15a and 25a and output the resulting signal directly from their output terminals 15b and 25b, respectively. The second inverter unit 16 and the fourth inverter unit 26 logically invert the input signal input to their input terminals 16a and 26a and output the resulting signal from their output terminals 16b and 26b.

[0015] In the first embodiment, as an example, the first inverter unit 15 and the third inverter unit 25 are each composed of two inverters, and the second inverter unit 16 and the fourth inverter unit 26 are each composed of one inverter.

[0016] The input terminal 15a of the first inverter unit 15 is electrically connected to the N10 terminal (fourth terminal) of the first connection switching terminal unit 11.

[0017] The output terminal 15b of the first inverter unit 15 is connected via the first wiring L1 to the N20 terminal (first terminal) of the second connection switching terminal unit 12. That is, one end of the first wiring L1 is connected to the output terminal 15b of the first inverter unit 15, and the other end is connected to the N20 terminal (first terminal) of the second connection switching terminal unit 12.

[0018] The input terminal 16a of the second inverter unit 16 is connected to the N21 terminal (second terminal) of the second connection switching terminal unit 12 via a wiring La. That is, one end of the wiring La is connected to the input terminal 16a of the second inverter unit 16, and the other end is connected to the N21 terminal (second terminal) of the second connection switching terminal unit 12.

[0019] The output terminal 16b of the second inverter unit 16 is connected via a wire Lb to the N11 terminal (fifth terminal) of the first connection switching terminal unit 11. That is, one end of the wire Lb is connected to the output terminal 16b of the second inverter unit 16, and the other end is connected to the N11 terminal (fifth terminal) of the first connection switching terminal unit 11.

[0020] Similarly, the input terminal 25a of the third inverter unit 25 is electrically connected to the N30 terminal (tenth terminal) of the third connection switching terminal unit 13.

[0021] The output terminal 25b of the third inverter unit 25 is connected via the second wiring L2 to the N40 terminal (seventh terminal) of the fourth connection switching terminal unit 14. That is, one end of the second wiring L2 is connected to the output terminal 25b of the third inverter unit 25, and the other end is connected to the N40 terminal (seventh terminal) of the fourth connection switching terminal unit 14.

[0022] The input terminal 26a of the fourth inverter unit 26 is connected via a wiring Lc to the N41 terminal (eighth terminal) of the fourth connection switching terminal unit 14. That is, one end of the wiring Lc is connected to the input terminal 26a of the fourth inverter unit 26, and the other end is connected to the N41 terminal (eighth terminal) of the fourth connection switching terminal unit 14.

[0023] The output terminal 26b of the fourth inverter unit 26 is connected to the N31 terminal (11th terminal) of the third connection switching terminal unit 13 via the wiring Ld. That is, one end of the wiring Ld is connected to the output terminal 26b of the fourth inverter unit 26, and the other end is connected to the N31 terminal (11th terminal) of the third connection switching terminal unit 13.

[0024] In the first embodiment, the length of the first wiring L1 is approximately equal to the length of the wiring La. Similarly, the length of the second wiring L2 is approximately equal to the length of the wiring Lc. Furthermore, the lengths of the wirings Lb and Ld are sufficiently smaller than the lengths of the wirings La and Lc. Furthermore, the first wiring L1 and the wiring La are different from the second wiring L2 and the wiring Lc, and in this example, the first wiring L1 and the wiring La are longer than the second wiring L2 and the wiring Lc.

[0025] The electronic device 100 or the electronic circuit 110 has two operating modes: a measurement mode and a normal mode. The measurement mode is a mode for determining the difference between the delay time (first delay time) when the clock signal output from the clock generator 1 reaches the first logic circuit 10 via the first inverter unit 15 and the first wiring L1 and the delay time (second delay time) when the clock signal reaches the second logic circuit 20 via the third inverter unit 25 and the second wiring L2, i.e., the delay time difference TΔ between the first wiring L1 and the second wiring L2.

[0026] 2 shows an example of a delay time difference TΔ. A clock signal output from a clock generator 1 at time t0 is received by a first logic circuit 10 at time t1 and by a second logic circuit 20 at time t2. The delay time of the first logic circuit 10 is t1-t0, and the delay time of the second logic circuit 20 is t2-t0. The delay time difference TΔ=t1-t2. In this example, t1 is earlier than t2, so the delay time difference TΔ is a negative value.

[0027] Typically, the measurement mode is used when a developer performs timing design to absorb differences in input timing of clock signals between the first logic circuit 10 and the second logic circuit 20 before shipping the electronic device 100. The developer can perform timing design for the first logic circuit 10 and the second logic circuit 20 by taking into account the delay time difference TΔ between the first wiring L1 and the second wiring L2 obtained in the measurement mode.

[0028] On the other hand, the normal mode is a mode in which the first logic circuit 10 and the second logic circuit 20, whose operation timings are set or designed taking into account the delay time difference TΔ, are actually operated. Typically, the electronic device 100 is shipped in the normal mode.

[0029] (Measurement mode) 3 is a diagram showing a connection state in the measurement mode of the electronic device 100. In the measurement mode, the N10 terminal (fourth terminal) and the N11 terminal (fifth terminal) of the first connection switching terminal unit 11 are connected by a zero-ohm resistor R1, which is a conductive connecting member. This electrically connects the output terminal 16b of the second inverter unit 16 and the input terminal 15a of the first inverter unit 15. Furthermore, the N20 terminal (first terminal) and the N21 terminal (second terminal) of the second connection switching terminal unit 12 are connected by a zero-ohm resistor R2, which is a conductive connecting member. This connects the output terminal 15b of the first inverter unit 15 to the input terminal 16a of the second inverter unit 16 via the first wiring L1 and the wiring La. The connection using the zero-ohm resistors R1 and R2 can be easily made by a developer, for example, by soldering or the like. This forms a first ring oscillator 17 including the first inverter unit 15, the first wiring L1, the wiring La, the second inverter unit 16, and the wiring Lb. At this time, the clock generator 1 and the first logic circuit 10 are separated from the first ring oscillator 17.

[0030] Similarly, in the measurement mode, the N30 terminal (tenth terminal) and the N31 terminal (eleventh terminal) of the third connection switching terminal unit 13 are connected by a zero-ohm resistor R3, which is a conductive connecting member. This electrically connects the output terminal 26b of the fourth inverter unit 26 and the input terminal 25a of the third inverter unit 25. Furthermore, the N40 terminal (seventh terminal) and the N41 terminal (eighth terminal) of the fourth connection switching terminal unit 14 are connected by a zero-ohm resistor R4, which is a conductive connecting member. This connects the output terminal 25b of the third inverter unit 25 to the input terminal 26a of the fourth inverter unit 26 via the second wiring L2 and the wiring Lc. The connection by the zero-ohm resistors R3 and R4 can be easily performed by a developer, for example, by soldering. This forms a second ring oscillator 27 including the third inverter unit 25, the second wiring L2, the wiring Lc, the fourth inverter unit 26, and the wiring Ld. At this time, the clock generator 1 and the second logic circuit 20 are disconnected from the second ring oscillator 27.

[0031] Fig. 4 is a simplified diagram showing the configuration of the first ring oscillator 17 and the second ring oscillator 27 in Fig. 3. Generally, the period T of a ring oscillator is equal to twice the sum of the delay times included in the loop, in other words, two revolutions around the loop equal one period T.

[0032] Assuming that the number of inverters included in the first ring oscillator 17 is N, the delay time per inverter is dn, the sum of the delay times of the first wiring L1 and wiring La is d1, and the delay time of wiring Lb is ignored, the first oscillation frequency f1 of the first ring oscillator 17 can be expressed as follows:

[0033]

number

[0034] The first oscillation frequency f1 can be easily measured, for example, by connecting a probe of an external measurement device (first frequency measurement device) such as an oscilloscope to the zero-ohm resistor R2 of the second connection switching terminal unit 12. The external measurement device is not limited to being connected to the zero-ohm resistor R2 of the second connection switching terminal unit 12, and may be externally connected to any external connection point of the first ring oscillator 17.

[0035] Similarly, if the number of inverters included in the second ring oscillator 27 is N, the delay time per inverter is dn, the sum of the delay times of the second wiring L2 and wiring Lc is d2, and the delay time of wiring Ld is ignored, the second oscillation frequency f2 of the second ring oscillator 27 can be expressed as follows:

[0036]

number

[0037] The second oscillation frequency f2 can be easily measured, for example, by connecting a probe of an external measurement device (second frequency measurement device) such as an oscilloscope to the zero-ohm resistor R4 of the fourth connection switching terminal unit 14. The external measurement device is not limited to the zero-ohm resistor R4 of the fourth connection switching terminal unit 14, and may be externally connected to any externally connectable location of the second ring oscillator 27. The first frequency measurement device and the second frequency measurement device may be the same device or different devices.

[0038] If the delay time (first delay time) that the clock signal takes to travel through the first wiring L1 to the first logic circuit 10 and then return by turning around at the wiring La is defined as D1 = dn + d1 (assuming that the delay is increased by d1 only for the final stage inverter), then equation (1) can be rewritten as follows:

number

[0039] If the delay time (second delay time) that the clock signal takes to travel through the second wiring L2 to reach the second logic circuit 20 and then return via the wiring Lc is defined as D2 = dn + d2 (assuming that the delay is increased by d2 only in the final stage inverter), then equation (2) can be rewritten as follows:

[0040]

number

[0041] Therefore, D1-D2 can be calculated from the first oscillation frequency f1 and the second oscillation frequency f2 according to the following formula:

[0042]

number

[0043] The delay time difference TΔ between the first wiring L1 and the second wiring L2 is calculated by dividing the calculation result of equation (5) by 2. That is, the delay time difference TΔ is calculated according to the following equation.

number

[0044] Here, it is assumed that the lengths of the first wiring L1 and wiring La are approximately the same, the lengths of the second wiring L2 and wiring Lc are approximately the same, and the lengths of the wiring Lb and wiring Ld are approximately the same. In this case, D1-D2 calculated by equation (5) is the difference between the sum of the delay times of the first wiring L1, wiring La, and wiring Lb and the sum of the delay times of the second wiring L2, wiring Lc, and wiring Ld. If the delay times of wiring Lb and wiring Ld are ignored, this becomes the difference between twice the delay time of wiring L1 and twice the delay time of wiring L2. In other words, D1-D2 is equivalent to twice the difference between the delay time of wiring L1 and the delay time of wiring L2. Since the delay time difference we are interested in is the delay time difference between the first wiring L1 and the second wiring L2, we can calculate the delay time difference TΔ as shown in equation (6) by dividing D1-D2 by 2, i.e., by dividing the result of equation (5) above by 2.

[0045] Considering the delay time difference TΔ between the first wiring L1 and the second wiring L2 obtained as described above, the developer can design the timing of the first logic circuit 10 and the second logic circuit 20. In the normal mode described below, the first logic circuit 10 and the second logic circuit 20 are set to operate at a timing according to this delay time difference.

[0046] The electronic device of this embodiment may include a calculation device that receives information indicating the first oscillation frequency f1 and the second oscillation frequency f2 measured by the first frequency measurement device and the second frequency measurement device and calculates the delay time difference by calculating equation (6). In this case, the calculation device may present information about the calculated delay time difference to a user on a display device. The electronic device of this embodiment may also include a writing circuit that writes setting values ​​corresponding to the delay time difference into the first logic circuit 10 and the second logic circuit 20.

[0047] (Normal mode) 5 is a diagram illustrating a connection state in the normal mode of the electronic device 100. In the normal mode, the N10 terminal (fourth terminal) and the N12 terminal (sixth terminal) of the first connection switching terminal unit 11 are connected via a zero-ohm resistor R1, thereby connecting the output terminal 3 of the clock generator 1 and the input terminal 15a of the first inverter unit 15. Furthermore, the N20 terminal (first terminal) and the N22 terminal (third terminal) of the second connection switching terminal unit 12 are connected via a zero-ohm resistor R2, thereby connecting the output terminal 15b of the first inverter unit 15 and the input terminal 10_I of the first logic circuit 10 via the first wiring L1. The connection via the zero-ohm resistors R1 and R2 may be performed by, for example, a developer or a worker at a production site by soldering, or may be performed using an automatic soldering device, a robot, or the like. As a result, the output terminal 3 of the clock generator 1 is connected to the first logic circuit 10 via the first inverter unit 15 and the first wiring L1. The first logic circuit 10 operates in accordance with the clock signal supplied from the clock generator 1 via the first inverter unit 15 and the first wiring L1.

[0048] Similarly, in the normal mode, the N30 terminal (tenth terminal) and the N32 terminal (twelfth terminal) of the third connection switching terminal unit 13 are connected via a zero-ohm resistor R3, thereby connecting the output terminal 3 of the clock generator 1 to the input terminal 25a of the third inverter unit 25. Furthermore, the N40 terminal (seventh terminal) and the N42 terminal (ninth terminal) of the fourth connection switching terminal unit 14 are connected via a zero-ohm resistor R4, thereby connecting the output terminal 25b of the third inverter unit 25 to the input terminal 20_I of the second logic circuit 20 via the second wiring L2. The connection via the zero-ohm resistors R3 and R4 may be performed by, for example, a developer or a worker at the production site by soldering, or may be performed using an automatic soldering device, a robot, or the like. As a result, the output terminal 3 of the clock generator 1 is connected to the second logic circuit 20 via the third inverter unit 25 and the second wiring L2. The second logic circuit 20 operates in accordance with a clock signal supplied from the clock generator 1 via the third inverter section 25 and the second wiring L2.

[0049] As described above, the electronic device 100 according to the first embodiment includes the first ring oscillator 17 and the second ring oscillator 27 in the measurement mode, and the delay time difference TΔ between the first wiring L1 and the second wiring L2 is calculated from the first oscillation frequency f1 of the first ring oscillator 17 and the second oscillation frequency f2 of the second ring oscillator 27.

[0050] The developer can measure the first oscillation frequency f1 of the first ring oscillator 17 and the second oscillation frequency f2 of the second ring oscillator 27, and based on these, easily determine the delay time difference TΔ between the first wiring L1 and the second wiring L2. The delay time difference TΔ determined in this way is based on actual measurements in an actual circuit, and therefore is extremely accurate.

[0051] In the measurement mode, the clock generator 1 and the first logic circuit 10 are disconnected from the first ring oscillator 17. In addition, the clock generator 1 and the second logic circuit 20 are disconnected from the second ring oscillator 27. This prevents these circuits from negatively affecting the measurement of the oscillation frequency.

[0052] In the normal mode, the output terminal 3 of the clock generator 1 is connected to the first logic circuit 10 via the first inverter unit 15 and the first wiring L1. In addition, the output terminal 3 of the clock generator 1 is connected to the second logic circuit 20 via the third inverter unit 25 and the second wiring L2. In the normal mode, the first inverter unit 15 and the third inverter unit 25 function as buffers inserted in the path of the clock signal. In addition, the second inverter unit 16 and the fourth inverter unit 26 are separated from the path of the clock signal. This prevents these elements from negatively affecting the operation of the first logic circuit 10 and the second logic circuit 20.

[0053] Furthermore, in the electronic device 100, the first inverter unit 15, the third inverter unit 25, and the second inverter unit 16 and the fourth inverter unit 26 are all included in the same IC package 2. As described above, the first inverter unit 15 and the third inverter unit 25 function as buffers in the normal mode, and therefore the inverters that constitute these units are useful regardless of the measurement of the oscillation frequency. On the other hand, the second inverter unit 16 and the fourth inverter unit 26 are unnecessary in the normal mode, but the inverters that constitute these units can utilize the extra inverters included in the IC package 2. Therefore, there is no need to prepare additional components for measuring the oscillation frequency.

[0054] (Embodiment 2) FIG. 6 is a diagram illustrating a configuration of an electronic device 200 according to a second embodiment. In addition to the configuration of the first embodiment, the electronic circuit 210 in the electronic device 200 includes a first frequency divider circuit 218 that can be externally connected to the first ring oscillator 17 and a second frequency divider circuit 228 that can be externally connected to the second ring oscillator 27. The external connections are not limited to specific locations. In the example of FIG. 6, the first frequency divider circuit 218 is connected to a zero-ohm resistor R2, and the second frequency divider circuit 228 is connected to a zero-ohm resistor R4. The first frequency divider circuit 218 is provided in the first logic circuit 10, and the second frequency divider circuit 228 is provided in the second logic circuit 20. However, the first frequency divider circuit 218 and the second frequency divider circuit 228 may be provided outside the first logic circuit 10 and the second logic circuit 20. The first frequency divider circuit 218 receives as input a signal including the first oscillation frequency f1 of the first ring oscillator 17 and divides the signal by 1 / K. Then, it outputs a signal with a frequency of f1 / K after frequency division to an external measurement device (first frequency measurement device). The frequency of this signal is measured by the external measurement device (first frequency measurement device). The second frequency divider circuit 228 receives as input a signal including the second oscillation frequency f2 of the second ring oscillator 27 and divides the signal by 1 / K. Then, it outputs a signal with a frequency of f2 / K after frequency division to an external measurement device (second frequency measurement device). The frequency of this signal is measured by the external measurement device (second frequency measurement device).

[0055] Referring to the above-mentioned formulas (1) and (2), the oscillation frequency of the ring oscillator is inversely proportional to the delay time of the wiring. Therefore, when the delay time of the first wiring L1 or the second wiring L2 is short, the oscillation frequency of the ring oscillator becomes high, and depending on the performance of the external measurement device, it may be difficult to measure it as it is. In the second embodiment, it is sufficient to measure the signals of the oscillation frequencies f1 / K and f2 / K divided by the first frequency divider circuit 218 and the second frequency divider circuit 228. By estimating the original oscillation frequencies f1 and f2 based on these signals, the delay time difference TΔ can be calculated with high accuracy even when the delay time of the first wiring L1 or the second wiring L2 is short.

[0056] (Variation 1) In the above-described first and second embodiments, the zero-ohm resistors R1 to R4 are used to connect the terminals of the first to fourth connection switching terminal units 11 to 14. Instead of these, other types of conductive connecting members, such as jumper wires, may be used to connect the terminals of the first to fourth connection switching terminal units 11 to 14.

[0057] (Variation 2) The connections between the terminals included in each of the first to fourth connection switching terminal units 11 to 14 may be automatically switched by a switch. In this case, the first to fourth connection switching terminal units 11 to 14 may be provided with a switch to serve as the first to fourth switching units, and the first to fourth switching units may switch the switches in response to an external control signal.

[0058] (Variation 3) Even when the first wiring L1 and the second wiring L2 are wirings of different structures or materials but have the same length, and the signal delay times are different, the delay time difference can be calculated by the above-described embodiment.

[0059] Although several embodiments have been described, these embodiments are presented as examples and are not intended to limit the scope of the embodiments. These embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, combinations, etc. can be made without departing from the spirit of the embodiments. These embodiments and their modifications are included in the scope of the claims and their equivalents, as well as the scope and spirit of the embodiments.

[0060] This embodiment can also be configured as follows. [Item 1] An electronic circuit that supplies a clock signal generated by a clock generator to a first logic circuit and a second logic circuit, a first inverter unit including an even number of inverters connected in series; a first wiring having one end connected to an output terminal of the first inverter unit; a second inverter unit including one or more odd number of inverters connected in series; a third inverter unit including inverters connected in series in the same number as the first inverter unit; a second wiring having one end connected to the output terminal of the third inverter unit; a fourth inverter unit including inverters connected in series in the same number as the second inverter unit; Equipped with a mode for measuring a delay time difference between the first wiring and the second wiring is configured by connecting the input terminal of the first inverter unit and the output terminal of the second inverter unit, the other end of the first wiring and the input terminal of the second inverter unit, the input terminal of the third inverter unit and the output terminal of the fourth inverter unit, and the other end of the second wiring and the input terminal of the fourth inverter unit, the input terminal of the first inverter unit and the output terminal of the clock generator, the other end of the first wiring and the input terminal of the first logic circuit, the input terminal of the third inverter unit and the output terminal of the clock generator, and the other end of the second wiring and the input terminal of the second logic circuit are connected to each other, thereby achieving a normal mode configuration in which the clock signal generated by the clock generator is transmitted to the first logic circuit and the second logic circuit; electronic circuit. [Item 2] In the measurement mode, outputting a first signal including a first oscillation frequency of a first ring oscillator including the first inverter unit, the second inverter unit, and the first wiring to a first frequency measurement device; outputting a second signal including a second oscillation frequency of a second ring oscillator including the third inverter unit, the fourth inverter unit, and the second wiring to a second frequency measurement device; Item 1. The electronic circuit according to item 1. [Item 3] From the first oscillation frequency measured by the first frequency measurement device and the second oscillation frequency measured by the second frequency measurement device, the delay time difference between the first wiring and the second wiring is calculated by the following formula:

number

[0061] 1 Clock Generator 2. IC Package 3 Clock generator output terminal 11 First connection switching terminal section 12 Second connection switching terminal section 13 Third connection switching terminal 14 Fourth connection switching terminal 15 First inverter section 16 Second inverter section 17 First Ring Oscillator 25 Third inverter section 26 Fourth inverter section 27 Second Ring Oscillator 100 Electronic equipment 200 Electronic equipment 218 First frequency divider circuit 228 Second Divider Circuit D1 First delay time D2 Second delay time d1 Sum of delay times of first wiring L1 and wiring La d2 Sum of delay times of second wiring L2 and wiring Lc dn Delay time per inverter f1 First oscillation frequency f2 Second oscillation frequency K division ratio L1 First wiring L2 Second wiring La wiring Lb wiring Lc wiring Ld wiring N Number of inverters N10 terminal (4th terminal) N11 terminal (5th terminal) N12 terminal (6th terminal) N20 terminal (first terminal) N21 terminal (2nd terminal) N22 terminal (3rd terminal) N30 terminal (10th terminal) N31 terminal (11th terminal) N32 terminal (12th terminal) N40 terminal (7th terminal) N41 terminal (8th terminal) N42 terminal (9th terminal) R1 Zero ohm resistor (connection component) R2 Zero ohm resistor (connection component) R3 Zero ohm resistor (connector) R4 Zero ohm resistor (connector) TΔ delay time difference

Claims

1. An electronic circuit that supplies a clock signal generated by a clock generator to a first logic circuit and a second logic circuit, a first inverter unit including an even number of inverters connected in series; a first wiring having one end connected to an output terminal of the first inverter unit; a second inverter unit including one or more odd number of inverters connected in series; a third inverter unit including inverters connected in series in the same number as the first inverter unit; a second wiring having one end connected to the output terminal of the third inverter unit; a fourth inverter unit including inverters connected in series in the same number as the second inverter unit; Equipped with a mode for measuring a delay time difference between the first wiring and the second wiring is configured by connecting the input terminal of the first inverter unit and the output terminal of the second inverter unit, the other end of the first wiring and the input terminal of the second inverter unit, the input terminal of the third inverter unit and the output terminal of the fourth inverter unit, and the other end of the second wiring and the input terminal of the fourth inverter unit, The input terminal of the first inverter unit and the output terminal of the clock generator, the other end of the first wiring and the input terminal of the first logic circuit, the input terminal of the third inverter unit and the output terminal of the clock generator, and the other end of the second wiring and the input terminal of the second logic circuit are respectively connected to each other, thereby achieving a normal mode configuration in which the clock signal generated by the clock generator is transmitted to the first logic circuit and the second logic circuit. electronic circuit.

2. In the measurement mode, outputting a first signal including a first oscillation frequency of a first ring oscillator including the first inverter unit, the second inverter unit, and the first wiring to a first frequency measurement device; outputting a second signal including a second oscillation frequency of a second ring oscillator including the third inverter unit, the fourth inverter unit, and the second wiring to a second frequency measurement device; 10. The electronic circuit of claim 1.

3. From the first oscillation frequency measured by the first frequency measurement device and the second oscillation frequency measured by the second frequency measurement device, the delay time difference between the first wiring and the second wiring is calculated by the following formula: [Equation 1] It can be calculated according to where f1 is the first oscillation frequency and f2 is the second oscillation frequency.

3. The electronic circuit of claim 2.

4. a first frequency divider circuit that receives the first signal having the first oscillation frequency from the first ring oscillator, divides the first signal, and outputs the divided first signal to the first frequency measurement device; a second frequency divider circuit that receives the second signal having the second oscillation frequency from the second ring oscillator, divides the second signal, and outputs the divided second signal to the second frequency measurement device; The electronic circuit of claim 2 further comprising:

5. a first terminal connected to the other end of the first wiring, a second terminal connected to the input terminal of the second inverter unit, and a third terminal connected to the input terminal of the first logic circuit, wherein the first terminal and the second terminal or the third terminal are connected by a connecting member, thereby connecting the other end of the first wiring to the input terminal of the second inverter unit or the input terminal of the first logic circuit; a seventh terminal to which the other end of the second wiring is connected, an eighth terminal connected to the input terminal of the fourth inverter unit, and a ninth terminal connected to the input terminal of the second logic circuit, and the seventh terminal and the eighth terminal or the ninth terminal are connected by a connecting member, thereby connecting the other end of the second wiring to the input terminal of the fourth inverter unit or the input terminal of the second logic circuit; 10. The electronic circuit of claim 1.

6. a fourth terminal connected to an input terminal of the first inverter unit, a fifth terminal connected to an output terminal of the second inverter unit, and a sixth terminal connected to an output terminal of the clock generator, wherein the fourth terminal and the fifth terminal or the sixth terminal are connected by a connecting member, thereby connecting the input terminal of the first inverter unit to the output terminal of the second inverter unit or the output terminal of the clock generator; The inverter includes a tenth terminal connected to the input terminal of the third inverter unit, an eleventh terminal connected to the output terminal of the fourth inverter unit, and a twelfth terminal connected to the output terminal of the clock generator, and the tenth terminal and the eleventh terminal or the twelfth terminal are connected by a connecting member, thereby connecting the input terminal of the third inverter unit and the output terminal of the fourth inverter unit or the output terminal of the clock generator.

6. The electronic circuit of claim 5.

7. The first wiring has a first length, and the second wiring has a second length different from the first length.

10. The electronic circuit of claim 1.

8. the first inverter unit and the third inverter unit, and the second inverter unit and the fourth inverter unit are included in the same IC package; 10. The electronic circuit of claim 1.

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