Semiconductor device

Abstract

To provide a semiconductor device capable of improving voltage-withstanding.SOLUTION: A semiconductor device comprises a semiconductor substrate 1, an insulating layer 2, and a resistor. The resistor includes a first resistor layer (resistor R(1)), a first buried electrode BE(2) electrically connected to one end of the first resistor layer, a second resistor layer (resistor R(2)) arranged adjacent to the first resistor layer and electrically connected to the other end of the first resistor layer, a second buried electrode BE(N) electrically connected to one end of the second resistor layer, a first auxiliary electrode AX(11) that extends along the longitudinal direction of the first resistor layer in plan view, is electrically connected to the first buried electrode, and has a greater thickness than the first resistor layer, and a second auxiliary electrode AX(12) that extends along the longitudinal direction, is electrically connected to the second buried electrode BE(N), has a greater thickness than the second resistor layer (resistor R(2)), is adjacent to the first auxiliary electrode AX(11), and forms, together with the first auxiliary electrode AX(11), a capacitor C11.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a plurality of resistor elements within a chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 085026

[0004] [overview] The present disclosure provides a semiconductor device capable of improving the breakdown voltage.

[0005] The semiconductor device of the present disclosure comprises an insulating layer formed on a semiconductor substrate and a resistor embedded in the insulating layer, the resistor comprising a first resistive layer, a first buried electrode electrically connected to one end of the first resistive layer, a second resistive layer arranged adjacent to the first resistive layer and electrically connected to the other end of the first resistive layer, a second buried electrode electrically connected to one end of the second resistive layer, a first auxiliary electrode extending along the longitudinal direction of the first resistive layer in a planar view, electrically connected to the first buried electrode, and having a thickness greater than that of the first resistive layer, and a second auxiliary electrode extending along the longitudinal direction, electrically connected to the second buried electrode, having a thickness greater than that of the second resistive layer, adjacent to the first auxiliary electrode, and constituting a capacitor together with the first auxiliary electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor package equipped with a high-voltage detection device. [Figure 2] FIG. 2 is a circuit diagram of the high voltage detection device. [Figure 3]FIG. 3 is a circuit diagram of a resistor of a first example (FIG. 3(A)) and a circuit diagram of a resistor of a second example (FIG. 3(B)). [Figure 4] FIG. 4 is a circuit diagram of a resistor including a high resistance portion. [Figure 5] FIG. 5 is a plan view of a resistor including a high resistance portion. [Figure 6] 6A and 6B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 5 along the arrow AA (FIG. 6A), a diagram showing the longitudinal cross-sectional configuration along the arrow BB (FIG. 6B), and a diagram showing the longitudinal cross-sectional configuration along the arrow CC (FIG. 6C). [Figure 7] FIG. 7 is a circuit diagram of a resistor including a high resistance portion. [Figure 8] FIG. 8 is a plan view of a resistor including a high resistance portion. [Figure 9] 9A and 9B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 8 taken along the arrow AA (FIG. 9A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 9B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 9C). [Figure 10] FIG. 10 is a perspective view of an end structure including a spare electrode and a resistive layer. [Figure 11] FIG. 11 is a plan view of a resistor including a high resistance portion. [Figure 12] 12A and 12B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 11 taken along the arrow AA (FIG. 12A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 12B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 12C). [Figure 13] FIG. 13 is a plan view of a resistor including a high resistance portion. [Figure 14] 14A and 14B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 13 taken along the arrow AA (FIG. 14A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 14B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 14C). [Figure 15] FIG. 15 is a plan view of a resistor including a high resistance portion. [Figure 16]16A and 16B are diagrams showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 15 along the arrow AA (FIG. 16A), along the arrow BB (FIG. 16B), and along the arrow CC (FIG. 16C). [Figure 17] FIG. 17 is a perspective view of an end structure including a spare electrode and a resistive layer. [Figure 18] FIG. 18 is a plan view of a resistor including a high resistance portion. [Figure 19] 19A and 19B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 18 taken along the arrow AA (FIG. 19A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 19B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 19C). [Figure 20] FIG. 20 is a plan view of an example resistor chip. [Figure 21] 21A, 21B, and 21C are plan views of a low resistance portion for voltage detection.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] 1 is a plan view of a semiconductor package 100 equipped with a high-voltage detection device, with the top cover removed.

[0009] The semiconductor package 100 includes a case 30 having a recess D1. The case 30 is made of an insulating material such as resin or ceramic. The semiconductor package 100 includes a resistor chip 10 (semiconductor device) disposed on a first die pad 110 within the recess D1 and an amplifier chip 20 (semiconductor device) disposed on a second die pad 120 within the recess D1. The open end of the recess D1 of the semiconductor package 100 is sealed with a lid (not shown), creating an enclosed space within the recess D1. The lid may be made of an insulating material such as resin, and the recess D1 may be filled with a gas or an insulating material. An appropriate potential, such as ground potential, is applied to the first die pad 110 and the second die pad 120 via a lead frame. If necessary, the potential of the first die pad 110 may be set to a high potential, for example.

[0010] The output voltage of the resistor chip 10 is input to the amplifier chip 20. The amplifier chip 20 outputs an output voltage corresponding to the detected voltage.

[0011] The positive terminal of the battery 200 is electrically connected to the first inner lead 10a and is connected via a bonding wire to the first electrode E1 (see FIG. 2) of the resistor chip 10. The negative terminal of the battery 200 is electrically connected to the second inner lead 10b and is connected via a bonding wire to the second electrode E2 (see FIG. 2) of the resistor chip 10.

[0012] Each terminal of the amplifier chip 20 can be connected to the third inner lead 10c, the fourth inner lead 10d, the fifth inner lead 10e, the sixth inner lead 10f, the seventh inner lead 10g, the eighth inner lead 10h, and the ninth inner lead 10i via bonding wires.

[0013] For example, the third inner lead 10c is supplied with a power supply voltage Vcc and input to the amplifier chip 20. The ninth inner lead 10i is supplied with a ground potential GND and input to the amplifier chip 20. The sixth inner lead 10f can output an output voltage Vout. The fourth inner lead 10d can output a monitor signal corresponding to the potential of the first output electrode EP (see Figure 2). The eighth inner lead 10h can output a monitor signal corresponding to the potential of the second output electrode EN (see Figure 2). The fifth inner lead 10e and the seventh inner lead 10g can be used for other purposes as needed.

[0014] 2 is a circuit diagram of a high-voltage detection device. The high-voltage detection device includes a resistor circuit C10 (voltage divider circuit) and a voltage detection circuit C20. The resistor chip 10 described above includes the resistor circuit C10. The amplifier chip 20 includes the voltage detection circuit C20. A first input terminal HV(+) of the resistor circuit C10 is electrically connected to the positive electrode of the battery 200. A second input terminal HV(-) of the resistor circuit C10 is electrically connected to the negative electrode of the battery 200. The first input terminal HV(+) is electrically connected to a first electrode E1 (electrode pad). The second input terminal HV(-) is electrically connected to a second electrode E2 (electrode pad).

[0015] The resistance circuit C10 includes a first high resistance section RP (first resistor), a first low resistance section RPS, a second low resistance section RNS, and a second high resistance section RN (second resistor). The first high resistance section RP, the first low resistance section RPS, the second low resistance section RNS, and the second high resistance section RN are connected in series in this order between the first electrode E1 and the second electrode E2. The first high resistance section RP and the second high resistance section RN have a function of reducing a high voltage and each have a high resistance value. The first low resistance section RPS and the second low resistance section RNS have a function of detecting a voltage and each have a relatively low resistance value compared to the high resistance sections.

[0016] An exemplary resistance value of one high resistance section is 500 MΩ, but it can also be 1 MΩ or more and 1000 MΩ or less. The resistance value of the high resistance section can also be 100 MΩ or more and 800 MΩ or less. The resistance value of the high resistance section can also be 300 MΩ or more and 600 MΩ or less. This resistance value should be a resistance value that can withstand high voltages and allows voltage detection.

[0017] The resistance of one low resistance section (RPS or RNS) is equal to or less than K% of the resistance of the high resistance section. Exemplary values ​​of K are 5%, 3%, 1%, 0.5%, 0.3%, 0.1%, 0.05%, or 0.01%, and the resistance of the low resistance section can be, for example, 0.01 MΩ to 10 MΩ.

[0018] A first output electrode EP (electrode pad) is electrically connected to the connection point between the first high resistance section RP and the first low resistance section RPS. A second output electrode EN (electrode pad) is electrically connected to the connection point between the second high resistance section RN and the second low resistance section RNS. A reference electrode EG (electrode pad) is electrically connected between the first low resistance section RPS and the second low resistance section RNS.

[0019] The resistor circuit C10 is a voltage divider circuit, which can obtain a voltage corresponding to the resistance value between two selected points within the resistor circuit C10. The first output electrode EP is electrically connected to the first input terminal INP of the voltage detection circuit C20. The second output electrode EN is electrically connected to the second input terminal INN of the voltage detection circuit C20. The reference electrode EG is electrically connected to the reference terminal VC of the voltage detection circuit C20. The potential of the reference terminal VC can be set to, for example, ground potential. The voltage detection circuit C20 can output an output voltage Vout. The output voltage Vout can be the sum of a first potential difference between the first input terminal INP and the reference terminal VC and a second potential difference between the second input terminal INN and the reference terminal VC. The voltage detection circuit C20 can include a source follower (amplifier) ​​that amplifies the voltage input from the input terminals and a differential amplifier circuit that obtains the sum of the input voltages. The voltage detection circuit C20 has an input terminal for a power supply voltage Vcc for operating the internal circuit and an input terminal for setting the ground potential GND.

[0020] Resistor circuit C10 may include a dummy resistor.

[0021] FIG. 3 shows a circuit diagram of a resistor of a first example (FIG. 3(A)) and a circuit diagram of a resistor of a second example (FIG. 3(B)).

[0022] In the resistor circuit C10 of FIG. 3A, one end of a dummy resistor R (Dmy) is electrically connected to the input side of the first high resistance section RP. The dummy resistor R (Dmy) is electrically connected to the input side of the second high resistance section RN. The dummy resistor does not need to be electrically connected to a resistor. For example, resistors at both ends of a resistor chip may have different resistance characteristics compared to resistors near the center. Treating such resistors as dummy resistors may improve detection accuracy.

[0023] The resistor circuit C10 in FIG. 3B has a configuration that is a modification of the circuit of the first example. In this example, the first high resistance section RP is composed of a high resistance section RP1 and a high resistance section RP2 connected in series, and the second high resistance section RN is composed of a high resistance section RN1 and a high resistance section RN2 connected in series. In addition, the reference electrode EG is separated into a first reference electrode EG1 and a second reference electrode EG2, and these electrodes are electrically connectable on the voltage detection circuit side. Furthermore, compared to the circuit of the first example, one or more dummy resistors R (Dmy) are provided between each resistor section.

[0024] The dummy resistor is a resistor through which no current flows, and is provided to maintain electrical equivalence in the resistor circuit C10, maintain electrical stability, or reduce error factors that may occur during resistor manufacturing in the manufacturing process. The circuit configuration of the high voltage detection device is not limited to these, and the shape and arrangement of the resistor may be changed as long as the basic voltage detection function is achieved.

[0025] As described above, the high-voltage detection device can be housed in a single semiconductor package. Alternatively, the functions of each circuit can be separated into a resistor chip and an amplifier chip and mounted in the package. Modifications are also possible in which some of the circuit elements are moved to either chip or integrated into a single chip.

[0026] FIG. 4 is a circuit diagram of a resistor including a high resistance portion.

[0027] The high voltage (HV) input terminal is connected to the first electrode E1 (or the second electrode E2). The first electrode E1 is electrically connected to the first high resistance section RP. The second electrode E2 is electrically connected to the second high resistance section RN. The first high resistance section RP (or the second high resistance section RN) includes a plurality of resistors R connected in series. The node to which the high voltage (high potential) is first input in the first high resistance section RP (or the second high resistance section RN) is defined as the first node N1. Within the first high resistance section RP (or the second high resistance section RN), the second node N2 of the resistor R adjacent to the resistor R connected to the first node N1 is adjacent to the first node N1.

[0028] A dummy resistor R (Dmy) (extension region) is electrically connected to an end of the first high resistance portion RP (or the second high resistance portion RN). The dummy resistor R (Dmy) includes one or more resistors R. Each resistor R is a resistive layer, and a specific example of its planar shape is a linear shape extending linearly, so this resistor R can be called a linear resistor or a linear-shaped resistor. In the dummy resistor R (Dmy) of this example, both ends of each resistor R are short-circuited, and the multiple resistors R are connected in parallel. In this example, a buried electrode BE (buried wiring) located at the end short-circuits both ends of the resistor R in the dummy resistor R (Dmy), but short-circuiting may also be performed by other wiring.

[0029] This buried electrode BE (buried wiring) for short circuiting can be disposed directly below the dummy resistor R (Dmy).

[0030] When a voltage large relative to the ground potential is input to the first electrode E1 (or the second electrode E2), that voltage is transmitted to the first node N1. In a steady state, the potential of the first node N1 drops via one or more resistors R connected in series to it, and the potential after the voltage drop appears at the second node N2. If the potential of the first node N1 increases instantaneously, the potential of the second node N2 cannot immediately follow this change, and a large potential difference occurs between the first node N1 and the second node N2.

[0031] For example, if the gap between a first resistor R (R(1)) having a first node N1 at one end and a second resistor R (R(2)) having a second node N2 is 1 μm, breakdown may occur if a voltage (e.g., 4000 V) exceeding the voltage (e.g., 500 V) that provides an electric field that can be withstood by this gap is applied between the first node N1 and the second node N2.

[0032] In this example, a first capacitor C11 is connected between the first node N1 and the second node N2.

[0033] When the potential at the first node N1 suddenly increases, a current flows through the first capacitor C11, increasing the magnitude of the potential at the second node N2. This reduces the potential difference between the first node N1 and the second node N2, preventing damage near the nodes due to a sudden voltage change.

[0034] The capacitance of the exemplary first capacitor C11 or the combined capacitance is preferably at least 1 fF or more, and preferably 10 fF or more, in which case it is believed that sudden voltage changes can be sufficiently suppressed.

[0035] If the potential of the second node N2 suddenly increases, a potential difference may occur between the node of the adjacent resistor R on the lower potential side, which may cause breakdown. Therefore, it is preferable to electrically connect multiple capacitors between the ends of each resistor R.

[0036] The first capacitor C11 can be configured by a first auxiliary electrode electrically connected to the first node N1 and a second auxiliary electrode electrically connected to the second node N2, as will be explained in detail below.

[0037] Fig. 5 is a plan view of a resistor including the high resistance portion shown in Fig. 4. Note that the resistor, embedded electrode, and auxiliary electrode are actually embedded in an insulating layer, but for clarity of explanation, the insulating layer is not shown.

[0038] Each resistor R extends along the X-axis direction, and multiple resistors R are aligned along the Y-axis direction. The depth direction of the chip is the Z-axis, which is perpendicular to the X-axis and Y-axis. Via electrodes VE are physically and electrically connected to the undersides of both ends of each resistor R, and the via electrodes VE are physically and electrically connected to buried electrodes BE. Note that, because the physical connection of conductive elements involves electrical connection, in the explanation, the term "connection" may be used simply when the connection state is clear.

[0039] In the dummy resistor R (Dmy), the embedded electrode BE has a first connection region BE(1) that connects all of the ends on one side of the multiple resistors R, a second connection region BE(2) that connects all of the ends on the other side, and a third connection region BE(3) that connects these connection regions. The third connection region BE(3) is located directly below the resistor R located at the end in the longitudinal direction of the chip.

[0040] In the first high resistance section RP (or the second high resistance section RN), the embedded electrode BE connects one end of the nth and n+1th resistors R counting from the high voltage (HV) side along the Y-axis direction, and connects the other end of the n+1th and n+2th resistors R (n is a natural number, for example an odd number).

[0041] It is also possible to consider a structure in which the vertical positional relationship between the via electrodes VE and buried electrodes BE and the resistor R is reversed. In this case, the resistor R is positioned in a lower layer than the via electrodes VE and buried electrodes BE.

[0042] The buried electrode BE connected to the input side electrode that supplies high voltage (HV) is connected to one end of the input side of the first resistance layer (first resistance layer (resistor R(1))) through a via electrode VE via the buried electrode BE (second connection region BE(2)) located below one end of the dummy resistor R (Dmy).

[0043] One end of the final resistor R(f) (final dummy resistance layer) of the dummy resistor R(Dmy) is also connected to the buried electrode BE (second connection region BE(2)) through a via electrode VE. That is, one end of the final resistor R(f) of the dummy resistor R(Dmy) and one end of the first resistance layer (resistor R(1)) are both connected to the second connection region BE(2), which constitutes a buried electrode. A first preliminary electrode AX(11) is disposed above the region between the final resistor R(f) and the first resistance layer (resistor R(1)). The first preliminary electrode AX(11) is electrically connected to the second connection region BE(2) through a first via electrode VE11.

[0044] One end of the second resistance layer (resistor R(2)) next to the first is connected to the buried electrode BE(N) through a via electrode VE. Like the other buried electrodes BE, the buried electrode BE(N) connects one end of the adjacent resistor R through the via electrode VE. The buried electrode BE(N) is connected to the second preliminary electrode AX(12) located above it through a second via electrode VE12.

[0045] The first preliminary electrode AX(11) extends along the X-axis direction. The second preliminary electrode AX(12) extends along the X-axis direction. The first preliminary electrode AX(11) and the second preliminary electrode AX(12) are adjacent to each other along the Y-axis direction, with a gap between them. A dielectric constituting a protective layer or an insulating layer is located in this gap. Therefore, the first preliminary electrode AX(11) and the second preliminary electrode AX(12) form a capacitor. The thickness of the first preliminary electrode AX(11) is greater than the thickness of the first resistive layer (resistor R(1)). The thickness of the second preliminary electrode AX(12) is greater than the thickness of the second resistive layer (resistor R(2)). If the thickness of the preliminary electrodes is too thin, sufficient capacitance for transmitting AC cannot be obtained.

[0046] A plurality of resistors R in the high resistance section are connected in series between an electrode that applies a high voltage (HV) and an output electrode that becomes a low voltage (LV).

[0047] In a plan view, the area where the dummy resistor R (Dmy) is arranged is an extension area that extends in the longitudinal direction (Y-axis direction) of the resistor when viewed from the high resistance portion. Having an extension area in a resistor has the advantage of reducing error factors during the resistor manufacturing process. The extension area may be provided as needed.

[0048] 6A and 6B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 5 along the arrow AA (FIG. 6A), a diagram showing the longitudinal cross-sectional configuration along the arrow BB (FIG. 6B), and a diagram showing the longitudinal cross-sectional configuration along the arrow CC (FIG. 6C).

[0049] As shown in FIGS. 6(A) to 6(C), the resistor chip includes a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate 1, and a protective film 4 provided on the insulating layer 2.

[0050] The insulating layer 2 includes a plurality of laminated dielectric layers (first dielectric layer 2A, second dielectric layer 2B). At least one of the plurality of dielectric layers (first dielectric layer 2A) is made of a material containing silicon oxide. At least one of the plurality of dielectric layers (second dielectric layer 2B) is made of a material containing silicon nitride. In this example, the first dielectric layer 2A and the second dielectric layer 2B are alternately laminated. The silicon oxide in this example is SiO2, but the elemental composition ratio may be changed or other elements may be included as necessary. The silicon nitride in this example is Si3N4, but the elemental composition ratio may be changed or other elements may be included as necessary. The thickness of the insulating layer 2 may be, for example, 5 μm or more and 50 μm or less.

[0051] The insulating layer 2 is a lower dielectric layer 2A formed on a second dielectric layer 2B located at the top. L and the lower dielectric layer 2A L Upper dielectric layer 2A formed on H The lower dielectric layer 2A L and upper dielectric layer 2A H The exemplary material is the same as the material of the first dielectric layer 2A.

[0052] The protective film 4 includes a first protective film 4A, a second protective film 4B, and a third protective film 4C, which are sequentially stacked on the insulating layer 2. The first protective film 4A may be made of an inorganic insulator such as silicon oxide or silicon nitride, for example, SiO2. The second protective film 4B is formed on the first protective film 4A. The second protective film 4B is made of an inorganic insulator such as silicon oxide or silicon nitride, and may be the same as or different from the material of the first protective film 4A, for example, silicon nitride. The third protective film 4C is made of a resin (insulator) such as polyimide.

[0053] The buried electrodes BE (including BE(1) to BE(3) and BE(N)) are formed on the lower dielectric layer 2A. L An upper dielectric layer 2A is formed on the H The upper dielectric layer 2A is located within the H can have multiple dielectric layers (insulating layers), and the upper dielectric layer 2A H A resistor R (resistive layer) is formed on a specific dielectric layer in the semiconductor device, and the buried electrode BE and the resistor R are connected by a via electrode VE.

[0054] As shown in FIG. 6(B), the lower surface of one end of the first preliminary electrode AX(11) in the longitudinal direction is H It is connected to the buried electrode BE(2) below through a first via electrode VE11 passing through it.

[0055] As shown in FIG. 6(C), the lower surface of the longitudinal end of the second preliminary electrode AX(12) is HThe first preliminary electrode AX(11) is connected to the underlying buried electrode BE(N) via a second via electrode VE12 passing through the first preliminary electrode AX(11). The first preliminary electrode AX(11) and the second preliminary electrode AX(12) are disposed adjacent to each other in the Y-axis direction, forming a capacitor between them. A high potential is input to a resistor R (first resistance layer) from the buried electrode BE(2) on the high-voltage input side via the via electrode VE. The potential and charge of the buried electrode BE(2) are transmitted to the first preliminary electrode AX(11) via the first via electrode VE11 and then to the second preliminary electrode AX(12) capacitively coupled to it. The charge flowing through this capacitor flows to the buried electrode BE(N) located directly below the second preliminary electrode AX(12) and is transmitted to the resistor R (second resistance layer) connected to this buried electrode (N) via the via electrode VE.

[0056] As explained above, the resistor chip described above includes an insulating layer 2 formed on a semiconductor substrate 1 and a resistor embedded in the insulating layer 2. The resistor (first high resistance portion RP, second high resistance portion RN) includes a first resistive layer (resistor R(1)) and a first buried electrode (BE(2)) electrically connected to one end of the first resistive layer (resistor R(1)). The resistor includes a second resistive layer (resistor R(2)) disposed adjacent to the first resistive layer (resistor R(1)) and electrically connected to the other end of the first resistive layer (resistor R(1)), and a second buried electrode (BE(N)) electrically connected to one end of the second resistive layer (resistor R(2)). The resistor includes a first preliminary electrode AX(11). The first preliminary electrode AX(11) extends in the longitudinal direction (X-axis direction) of the first resistive layer (resistor R(1)) in a plan view, is electrically connected to the first embedded electrode (BE(2)), and has a thickness greater than that of the first resistive layer (resistor R(1)). The resistor includes a second preliminary electrode AX(12). The second preliminary electrode AX(12) extends in the longitudinal direction (X-axis direction), is electrically connected to the second embedded electrode (BE(N)), has a thickness greater than that of the second resistive layer (resistor R(2)), is adjacent to the first preliminary electrode AX(11), and together with the first preliminary electrode AX(11) forms a first capacitor C11.

[0057] The semiconductor device of the present disclosure can quickly transmit the potential of the first resistance layer (resistor R(1)) to the second resistance layer (resistor R(2)) via the first capacitor C11, so the potential difference between the first resistance layer (resistor R(1)) and the second resistance layer (resistor R(2)) is less likely to become large, improving the breakdown voltage.

[0058] In the semiconductor device of the present disclosure, if the direction from the end toward the center in the longitudinal direction (X-axis direction) of the first resistance layer (resistor R(1)) is defined as a first direction, in plan view, the first preliminary electrode AX(11) extends along the first direction from a position (connection position) directly above the first buried electrode BE(2). The second preliminary electrode AX(12) extends along the first direction from a position (connection position) directly above the second buried electrode BE(N).

[0059] In this structure, the potential of the first resistance layer (resistor R(1)) can be reliably and quickly transmitted to the second resistance layer (resistor R(2)). The first and second preliminary electrodes may be located deeper than the resistance layer, at the position of the buried electrode layer, or at a position deeper than the buried electrode.

[0060] Next, an example in which three or more spare electrodes are electrically connected to one end of each resistor R will be described.

[0061] FIG. 7 is a circuit diagram of a resistor including a high resistance portion.

[0062] The high voltage (HV) input terminal is connected to the first electrode E1 (or the second electrode E2). The first electrode E1 is electrically connected to the first high resistance section RP. The second electrode E2 is electrically connected to the second high resistance section RN. The first high resistance section RP (or the second high resistance section RN) includes a plurality of resistors R connected in series. The node to which the high voltage (high potential) is first input in the first high resistance section RP (or the second high resistance section RN) is defined as the first node N1. Within the first high resistance section RP (or the second high resistance section RN), the second node N2 of the resistor R adjacent to the resistor R connected to the first node N1 is adjacent to the first node N1.

[0063] A dummy resistor R (Dmy) is electrically connected to an end of the first high resistance portion RP (or the second high resistance portion RN). The dummy resistor R (Dmy) includes one or more resistors R. Each resistor R is a resistive layer, and an example of a specific planar shape is a linear shape extending linearly. In the dummy resistor R (Dmy) of this example, both ends of each resistor R are short-circuited, and the multiple resistors R are connected in parallel. In this example, the buried electrode BE (buried wiring) closest to the high-voltage input side short-circuits both ends of the resistor R in the dummy resistor R (Dmy), but short-circuiting may also be performed by other wiring. This short-circuiting buried electrode BE can be arranged directly below the dummy resistor R (Dmy).

[0064] When a voltage large relative to the ground potential is input to the first electrode E1 (or the second electrode E2), that voltage is transmitted to the first node N1. In a steady state, the potential of the first node N1 drops via one or more resistors R connected in series to it, and the potential after the voltage drop appears at the second node N2. If the potential of the first node N1 increases instantaneously, the potential of the second node N2 cannot immediately follow this change, and as explained in the above example, a large potential difference occurs between the first node N1 and the second node N2, which may result in breakdown.

[0065] A first capacitor C11 is formed between the first node N1 and the second node N2 by a pair of auxiliary electrodes, and therefore the potential of the first node N1 is transmitted to the second node N2 via the first capacitor C11.

[0066] When the magnitude of the potential at the first node N1 suddenly increases, the magnitude of the potential at the second node N2 increases via the first capacitor C11, which reduces the potential difference between the first node N1 and the second node N2 and prevents damage near the nodes due to a sudden voltage change.

[0067] When the magnitude of the potential at the second node N2 increases suddenly, a potential difference tends to occur between the node of the resistor R adjacent thereto.

[0068] Therefore, this device is provided with a second capacitor C12. A third auxiliary electrode is electrically connected to a third node Na adjacent to the second node N2 to which the second auxiliary electrode is connected. The second capacitor C12 is formed between the second auxiliary electrode connected to the second node N2 and the third auxiliary electrode connected to the third node Na. This reduces the potential difference between the second node N2 and the third node Na, suppressing breakdown near the contact point.

[0069] Similarly, this device includes a third capacitor C13. A fourth auxiliary electrode is electrically connected to a fourth node Nb adjacent to the third node Na to which the third auxiliary electrode is connected. The third capacitor C13 is formed between the third auxiliary electrode connected to the third node Na and the fourth auxiliary electrode connected to the fourth node Nb. This reduces the potential difference between the third node Na and the fourth node Nb, suppressing breakdown near the contact point.

[0070] Similarly, this device includes a fourth capacitor C14. A fifth auxiliary electrode is electrically connected to a fifth node Nc adjacent to the fourth node Nb to which the fourth auxiliary electrode is connected. The fourth capacitor C14 is formed between the fourth auxiliary electrode connected to the fourth node Nb and the fifth auxiliary electrode connected to the fifth node Nc. This reduces the potential difference between the fourth node Nb and the fifth node Nc, suppressing breakdown near the contact points. With a similar configuration, this device can include a fifth capacitor C15 or more capacitors.

[0071] On the opposite side of the first node N1 of the first resistance layer (resistor R(1)) in the high resistance section is a node Nd, to which an auxiliary electrode is connected, and which constitutes an opposite-side first capacitor (C21) together with an auxiliary electrode that faces and is capacitively coupled to this auxiliary electrode. The other auxiliary electrode of the opposite-side first capacitor (C21) is connected to a node Ne. The connection relationships of the opposite-side first to fifth capacitors (C21 to C25) are the same as those of the first to fifth capacitors (C11 to C15). The first capacitor (C21) on the opposite side is connected between the node Nd and the node Ne, the second capacitor (C22) on the opposite side is connected between the node Ne and the node Nf, the third capacitor (C23) on the opposite side is connected between the node Nf and the node Ng, the fourth capacitor (C24) on the opposite side is connected between the node Ng and the node Nh, and the fifth capacitor (C24) on the opposite side is connected between the node Nh and an appropriate potential.

[0072] The number of capacitors formed by the spare electrodes is illustrative, and for example, the number of spare electrodes connected to one end of the resistor R can be four or more, six or more, eight or more, or ten or more.

[0073] The range of the capacitance of the exemplary first capacitor (C11) (or the combined capacitance depending on the structure) can be set to the same as the range of the capacitance of the first capacitor C11 in the examples of Figures 4 to 6 described above. The range of the capacitance of each of the exemplary capacitors (C11 to C15, C21 to C25) (or the combined capacitance depending on the structure) can also be set to the same as the range of the capacitance of the first capacitor C11 in the examples described above. They may also be set to other ranges.

[0074] Fig. 8 is a plan view of a resistor including the high resistance portion shown in Fig. 7. Note that the resistor, embedded electrodes, and dummy wiring are actually embedded in an insulating layer, but for clarity of explanation, the insulating layer is not shown.

[0075] Each resistor R extends along the X-axis direction, and the resistors R are aligned along the Y-axis direction. Via electrodes VE are physically and electrically connected to the lower surfaces of both ends of each resistor R, and the via electrodes VE are physically and electrically connected to buried electrodes BE.

[0076] In the dummy resistor R (Dmy), the embedded electrode BE has a first connection region BE(1) that connects all of the ends on one side of the multiple resistors R, a second connection region BE(2) that connects all of the ends on the other side, and a third connection region BE(3) that connects these connection regions.

[0077] In the first high resistance section RP (or the second high resistance section RN), the embedded electrode BE connects one end of the nth and n+1th resistors R along the Y-axis direction, and connects the other end of the n+1th and n+2th resistors R (n is a natural number, and is illustratively an odd number).

[0078] It is also possible to consider a structure in which the vertical positional relationship between the via electrodes VE and buried electrodes BE and the resistor R is reversed. In this case, the resistor R is positioned in a lower layer than the via electrodes VE and buried electrodes BE.

[0079] The buried electrode BE connected to the electrode that supplies a high voltage (HV) is connected to one end of the input side of the first resistance layer (resistor R(1)) of the high resistance section through a via electrode VE via the buried electrode BE (second connection region BE(2)) located below one end of the dummy resistor R (Dmy).

[0080] One end of the final resistor R(f) (final dummy resistance layer) of the dummy resistor R(Dmy) is also connected to the buried electrode BE (second connection region BE(2)) through a via electrode VE. That is, one end of the final resistor R(f) of the dummy resistor R(Dmy) and one end of the first resistance layer (resistor R(1)) are both connected to the second connection region BE(2), which constitutes a buried electrode. A first preliminary electrode AX(11) is disposed above the region between the final resistor R(f) and the first resistance layer (resistor R(1)). The first preliminary electrode AX(11) is electrically connected to the second connection region BE(2) through a first via electrode VE11.

[0081] One end of the second resistance layer (resistor R(2)) next to the first is connected to the buried electrode BE(N) through a via electrode VE. Like the other buried electrodes BE, the buried electrode BE(N) connects one end of the adjacent resistor R through the via electrode VE. The buried electrode BE(N) is connected to the second preliminary electrode AX(12) located above it through a second via electrode VE12.

[0082] The first preliminary electrode AX(11) extends along the X-axis direction. The second preliminary electrode AX(12) extends along the X-axis direction. The first preliminary electrode AX(11) and the second preliminary electrode AX(12) are adjacent to each other along the Y-axis direction, with a gap between them. A dielectric constituting a protective film or an insulating layer is located within this gap. Therefore, the first preliminary electrode AX(11) and the second preliminary electrode AX(12) form a capacitor. The thickness of the first preliminary electrode AX(11) is greater than the thickness of the first resistive layer (resistor R(1)). The thickness of the second preliminary electrode AX(12) is greater than the thickness of the second resistive layer (resistor R(2)). The thickness of each of the preliminary electrodes is greater than the thickness of the respective resistive layers. If the thickness of the preliminary electrodes is too thin, sufficient capacitance for transmitting AC cannot be obtained.

[0083] The multiple resistors R in the high resistance section are connected in series between an input electrode that applies a high voltage (HV) and an output electrode that becomes a low voltage (LV).

[0084] The second preliminary electrode AX(12) extends along the X-axis direction. The third preliminary electrode AX(13) extends along the X-axis direction. The second preliminary electrode AX(12) and the third preliminary electrode AX(13) are adjacent to each other along the Y-axis direction, with a gap between them. A dielectric constituting a protective film or insulating layer is located in this gap. Therefore, the second preliminary electrode AX(12) and the third preliminary electrode AX(13) form a capacitor.

[0085] Similarly, the third preliminary electrode AX(13) extends along the X-axis direction. The fourth preliminary electrode AX(14) extends along the X-axis direction. The third preliminary electrode AX(13) and the fourth preliminary electrode AX(14) are adjacent to each other along the Y-axis direction, with a gap between them. A dielectric constituting a protective film or insulating layer is located within this gap. Therefore, the third preliminary electrode AX(13) and the fourth preliminary electrode AX(14) form a capacitor.

[0086] Similarly, the fourth preliminary electrode AX(14) extends along the X-axis direction. The fifth preliminary electrode AX(15) extends along the X-axis direction. The fourth preliminary electrode AX(14) and the fifth preliminary electrode AX(15) are adjacent to each other along the Y-axis direction, with a gap between them. A dielectric constituting a protective film or an insulating layer is located in this gap. Therefore, the fourth preliminary electrode AX(14) and the fifth preliminary electrode AX(15) form a capacitor.

[0087] The first preliminary electrode AX(11) is connected to the buried electrode immediately below through a first via electrode VE11. The second preliminary electrode AX(12) is connected to the buried electrode BE immediately below through a second via electrode VE12. The third preliminary electrode AX(13) is connected to the buried electrode BE immediately below through a third via electrode VE13. The fourth preliminary electrode AX(14) is connected to the buried electrode BE immediately below through a fourth via electrode VE14. The fifth preliminary electrode AX(15) is connected to the buried electrode BE immediately below through a fifth via electrode VE15.

[0088] Similarly, the first preliminary electrode AX(21), the second preliminary electrode AX(22), the third preliminary electrode AX(23), the fourth preliminary electrode AX(24), and the fifth preliminary electrode AX(25) located at the opposite end of each resistance layer are connected to the buried electrodes BE directly below them via the first via electrode VE21, the second via electrode VE22, the third via electrode VE23, the fourth via electrode VE24, and the fifth via electrode VE25, respectively. Each buried electrode BE connects one end of the n-th resistance layer and one end of the n+1-th resistance layer (n is a natural number, illustratively an odd number).

[0089] 9A and 9B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 8 taken along the arrow AA (FIG. 9A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 9B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 9C).

[0090] As shown in FIGS. 9(A) to 9(C), the resistor chip includes a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate 1, and a protective film 4 provided on the insulating layer 2.

[0091] The structures of the insulating layer 2 and the protective film 4 are the same as those shown in FIG.

[0092] The buried electrodes BE (including BE(1) to BE(3) and BE(N)) are formed on the lower dielectric layer 2A. L An upper dielectric layer 2A is formed on the H The upper dielectric layer 2A is located within the H can have multiple dielectric layers (insulating layers), and the upper dielectric layer 2A H A resistor R (resistance layer) is formed on a specific dielectric layer in the upper dielectric layer 2A, and the buried electrode BE and the resistor R are connected by a via electrode VE. Also, as shown in FIG. 9(B), the lower surface of the first preliminary electrode AX (11) is H 9C, the lower surface of the second preliminary electrode AX(12) is connected to the buried electrode BE(2) at the bottom through the first via electrode VE11 passing through the upper dielectric layer 2A. HThe auxiliary electrodes are connected to the lower buried electrode BE(N) through a second via electrode VE12 passing through the auxiliary electrodes. The auxiliary electrodes are adjacent to each other along the Y-axis direction, and a protective film is interposed between them. The capacitance between the auxiliary electrodes can be changed by changing the dielectric constant of this protective film. The capacitance of the capacitor between the auxiliary electrodes depends on the size of the gap between them, the opposing area of ​​the auxiliary electrodes, and the dielectric constant of the dielectric between them. The range of the gap between the auxiliary electrodes can be set to satisfy the exemplary capacitance range of the capacitor described above.

[0093] FIG. 10 is a perspective view of an end structure including a spare electrode and a resistive layer.

[0094] The length X of the first preliminary electrode AX(11) along the longitudinal direction (X-axis direction) R is 100 μm or more and 300 μm or less, and the length X of the second preliminary electrode AX(12) along the longitudinal direction (X-axis direction) R Similarly, the length X of the Nth preliminary electrode AX along the X-axis direction is 100 μm or more and 300 μm or less. R is 100 μm or more and 300 μm or less (N=1, 2, 3, etc.). The dimension Z of the Nth spare electrode AX along the Z-axis is R The dimension Y of the Nth preliminary electrode AX along the Y-axis is 1 μm or more and 3 μm or less. R Since it does not affect the capacitance of the capacitor, it can be changed depending on the width of the adjacent resistive layer. The gap Y in the Y-axis direction between the Nth auxiliary electrode AX and the N+1th auxiliary electrode AX S is 1 μm or more and 3 μm or less. The dielectric material located between the preliminary electrodes can be silicon oxide or silicon nitride, but is not limited to these. The capacitance of the capacitor that can be set under these conditions is 1 fF or more. From the viewpoint of rapid transmission of potential and charge, it is more preferable that the capacitance of the capacitor is 10 fF or more.

[0095] The connections in this example will be described in detail. The dummy resistance layer (final dummy resistance layer R(f)) is disposed adjacent to the first resistance layer (first resistor R(1)) on the opposite side from the second resistance layer (second resistor R(2)), and one end is electrically connected to the first buried electrode BE. The third resistance layer (third resistor R(3)) is disposed adjacent to the second resistance layer (second resistor R(2)) on the opposite side from the first resistance layer (first resistor R(1)), and one end is electrically connected to the second buried electrode BE. The high voltage potential applied to the final dummy resistance layer R(f) is transmitted to the buried electrode BE located below the second via electrode VE12 via the first via electrode VE11 and the capacitor formed by the first preliminary electrode AX(11) and the second preliminary electrode AX(12), and then transmitted to the second resistance layer (second resistor R(2)) and the third resistance layer (third resistor R(3)) connected to it via the via electrode VE. Similarly, the third via electrode VE13 connects the third preliminary electrode AX(13) and the buried wiring BE. The fourth via electrode VE14 connects the fourth preliminary electrode AX(14) and the buried wiring BE.

[0096] FIG. 11 is a plan view of a resistor including a high resistance portion.

[0097] In the resistor of this example, the dimension of the preliminary electrodes in the X-axis direction is larger than that of the resistor shown in Fig. 8, and they protrude outward in the X-axis direction of the resistor. In other words, all the preliminary electrodes (AX(11) to AX(15), AX(21) to AX(25)) have areas that protrude outward from the first high resistance portion RP (or the second high resistance portion RN) so as not to overlap with the resistor R (resistance layer) in plan view. The other structures of the resistor of this example are the same as those of the resistor shown in Fig. 8.

[0098] That is, in the semiconductor chip of the present disclosure, in a plan view, the first preliminary electrode AX(11) extends from a position directly above the first buried electrode (BE) in a direction opposite to the first direction (the direction from the end of each resistor R (resistive layer) toward the center), and the second preliminary electrode AX(12) extends from a position directly above the second buried electrode (BE) in a direction opposite to the first direction. In this structure, the capacitance of the capacitor formed by the preliminary electrodes can be increased.

[0099] 12A and 12B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 11 taken along the arrow AA (FIG. 12A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 12B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 12C).

[0100] As shown in FIGS. 12(A) to 12(C), the resistor chip includes a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate 1, and a protective film 4 provided on the insulating layer 2.

[0101] The structures of the insulating layer 2 and the protective film 4 are the same as those shown in FIG. 9, and only the dimension of the preliminary electrode in the X-axis direction is different.

[0102] In the structure of this example, as shown in FIG. 12(B), the lower surface of the first preliminary electrode AX(11) is H The first preliminary electrode AX(11) is connected to the buried electrode BE(2) below through a first via electrode VE11 passing through the first preliminary electrode AX(11). The first preliminary electrode AX(11) extends from the position of the first via electrode VE11 not only in the negative direction of the X axis but also in the positive direction (the direction opposite to the first direction toward the center).

[0103] The lower surface of the first preliminary electrode AX (21) on the opposite side is the upper dielectric layer 2A. H The first preliminary electrode AX (21) on the opposite side extends from the position of the via electrode not only in the positive direction of the X axis but also in the negative direction of the X axis (the direction opposite to the first direction toward the center).

[0104] As shown in FIG. 12(C), the lower surface of the second preliminary electrode AX(12) is H The second preliminary electrode AX(12) is connected to the buried electrode BE(N) at the bottom via a second via electrode VE12 passing through the interior of the second preliminary electrode AX(12). The second preliminary electrode AX(12) extends not only in the negative direction of the X axis but also in the positive direction of the X axis (the direction opposite to the first direction toward the center).

[0105] The auxiliary electrodes are adjacent to each other along the Y-axis direction, with a protective film interposed between them. The capacitance between the auxiliary electrodes can be changed by changing the dielectric constant of this protective film. The capacitance of the capacitor between the auxiliary electrodes depends on the size of the gap between them, the opposing area of ​​the auxiliary electrodes, and the dielectric constant of the dielectric between them. The range of the gap between the auxiliary electrodes can be set to satisfy the exemplary capacitance range of the capacitor described above.

[0106] FIG. 13 is a plan view of a resistor including a high resistance portion.

[0107] In the resistor of this example, the dimension of the preliminary electrodes in the X-axis direction is smaller than that of the resistor shown in FIG. 11, and the preliminary electrodes extend only outside the resistor in the X-axis direction. In other words, all the preliminary electrodes (AX(11) to AX(15), AX(21) to AX(25)) have an area that extends outside the first high resistance section RP (or the second high resistance section RN) so as not to overlap with each resistor R (resistance layer) in a plan view, but basically do not extend into the area inside the high resistance section. Of course, in the area where the via electrodes are provided in the preliminary electrodes (a dimension that is several times or less the width of each resistor R (resistance layer) in the Y-axis direction), the preliminary electrodes slightly overlap the resistor R. The other structure of the resistor of this example is the same as that of the resistor shown in FIG. 11.

[0108] That is, in the semiconductor chip of the present disclosure, in a plan view, the first preliminary electrode AX(11) extends from a position directly above the first buried electrode BE(2) in a direction opposite to the first direction (the direction from the end toward the center of each resistor R (resistance layer)). The second preliminary electrode AX(12) extends from a position directly above the second buried electrode BE(N) in a direction opposite to the first direction. In this structure, the capacitor formed by the preliminary electrodes can be freely designed without being restricted by the design of the resistance region.

[0109] 14A and 14B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 13 taken along the arrow AA (FIG. 14A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 14B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 14C).

[0110] The structures of the insulating layer 2 and the protective film 4 are the same as those shown in FIG. 12, and only the dimensions of the preliminary electrodes in the X-axis direction are different.

[0111] In the structure of this example, as shown in FIG. 14(B), the lower surface of the first preliminary electrode AX(11) is H The first preliminary electrode AX(11) is connected to the lower buried electrode BE(2) through the first via electrode VE11 passing through the first preliminary electrode AX(11). The first preliminary electrode AX(11) extends only in the positive direction of the X axis (the direction opposite to the first direction toward the center) from the position of the first via electrode VE11.

[0112] The lower surface of the first preliminary electrode AX (21) on the opposite side is the upper dielectric layer 2A. H The first preliminary electrode AX (21) on the opposite side extends only in the negative direction of the X axis (the direction opposite to the first direction toward the center) from the position of the via electrode.

[0113] As shown in FIG. 14(C), the lower surface of the second preliminary electrode AX(12) is H The second preliminary electrode AX(12) is connected to the buried electrode BE(N) at the bottom via a second via electrode VE12 passing through the interior of the second preliminary electrode AX(12). The second preliminary electrode AX(12) extends only in the positive direction of the X axis (the direction opposite to the first direction toward the center).

[0114] The auxiliary electrodes are adjacent to each other along the Y-axis direction, with a protective film interposed between them. The capacitance between the auxiliary electrodes can be changed by changing the dielectric constant of this protective film. The capacitance of the capacitor between the auxiliary electrodes depends on the size of the gap between them, the opposing area of ​​the auxiliary electrodes, and the dielectric constant of the dielectric between them. The range of the gap between the auxiliary electrodes can be set to satisfy the exemplary capacitance range of the capacitor described above.

[0115] The above-mentioned preliminary electrodes are disposed above each resistor R (resistive layer), but they may be formed at a position deeper than the resistor R, for example, by deforming a buried electrode.

[0116] FIG. 15 is a plan view of a resistor including a high resistance portion.

[0117] In the resistor of this example, instead of the preliminary electrode formed above the resistive layer, the shape of the buried electrode BE is modified in the same manner as the preliminary electrode, as compared with the resistor shown in Fig. 13. In the example shown in the figure, the width of the preliminary electrode AX in the Y-axis direction is set slightly wider than that shown in Fig. 13, but this is not limitative.

[0118] In this structure, the preliminary electrodes and via electrodes for connecting the preliminary electrodes to the buried electrodes shown in FIG. 13 are removed, and instead, each buried electrode BE is extended along the X-axis direction. In other words, the regions of the extended parts of the buried electrodes BE are preliminary electrodes AX. The preliminary electrodes (AX(11) to AX(15), AX(21) to AX(25)) as the extended regions of the buried electrodes BE are regions that protrude outside the first high resistance portion RP (or the second high resistance portion RN) in plan view. A capacitor is formed between the preliminary electrodes adjacent in the Y-axis direction, similar to the structure shown in FIG. 13.

[0119] In the resistor chip of the present disclosure, the first preliminary electrode AX(11) is a first extension of the first buried electrode BE(2) that is continuous with the first buried electrode BE(2) and extends in the direction opposite to the first direction (the direction from the end of the resistor R (resistive layer) toward the center). The second preliminary electrode AX(12) is a second extension of the second buried electrode BE(N) that is continuous with the second buried electrode BE(N) and extends in the direction opposite to the first direction. Similarly, each preliminary electrode is continuous with the corresponding buried electrode BE and is an extension of the buried electrode BE that extends in the direction opposite to the first direction. These preliminary electrodes may also extend in the first direction. This structure reduces the number of elements constituting the component, resulting in excellent productivity and enabling a reduction in the thickness dimension.

[0120] 16A and 16B are diagrams showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 15 along the arrow AA (FIG. 16A), along the arrow BB (FIG. 16B), and along the arrow CC (FIG. 16C).

[0121] The structures of the insulating layer 2 and the protective film 4 are the same as those shown in FIG. 14, except that the preliminary electrodes are formed as buried electrodes.

[0122] In the structure of this example, as shown in FIG. 16(B), the first preliminary electrode AX(11) is H The first preliminary electrode AX(11) is formed within the via electrode VE, but is continuous with the buried electrode BE(2). The buried electrodes constituting the preliminary electrodes in this structure are thicker to obtain the capacitance of the capacitor. The first preliminary electrode AX(11) extends in the positive direction of the X-axis (the opposite direction to the first direction toward the center) from the position of the via electrode VE that connects the resistor R and the buried electrode BE(2).

[0123] The first preliminary electrode AX (21) connected to the buried electrode BE on the opposite side in FIG. 16(B) is H The first preliminary electrode AX (21) is formed within the via electrode VE, but is continuous with the buried electrode BE. This first preliminary electrode AX (21) extends in the negative direction of the X axis (the opposite direction to the first direction toward the center) from the position of the via electrode VE that connects the resistor R and the buried electrode BE.

[0124] As shown in FIG. 16(C), the second preliminary electrode AX(12) is formed on the upper dielectric layer 2A. H The second preliminary electrode AX(12) is formed within the buried electrode BE(N) but is continuous with the buried electrode BE(N). The second preliminary electrode AX(12) extends in the positive direction of the X-axis (the opposite direction to the first direction toward the center).

[0125] The auxiliary electrodes are adjacent to each other along the Y-axis direction, with an insulating layer 2 interposed between them. The capacitance between the auxiliary electrodes can be changed by changing the dielectric constant of this insulating layer 2. The capacitance of the capacitor between the auxiliary electrodes depends on the size of the gap between them, the opposing area of ​​the auxiliary electrodes, and the dielectric constant of the dielectric between them. The range of the gap between the auxiliary electrodes can be set to satisfy the exemplary capacitance range of the capacitor described above.

[0126] FIG. 17 is a perspective view of an end structure including a preliminary electrode that also serves as a buried electrode and a resistive layer.

[0127] The first preliminary electrode AX(11), which is an extension region of the embedded electrode BE, extends along the X-axis direction. The length X of the first preliminary electrode AX(11) along the X-axis direction (longitudinal direction) R The length X of the second preliminary electrode AX(12) along the X-axis direction (longitudinal direction) is 100 μm or more and 300 μm or less. R Similarly, the length X of the Nth preliminary electrode AX along the X-axis direction is 100 μm or more and 300 μm or less. R is 100 μm or more and 300 μm or less (N=1, 2, 3, etc.). The dimension Z of the Nth spare electrode AX along the Z-axis is R The dimension Y of the Nth preliminary electrode AX along the Y-axis is 1 μm or more and 3 μm or less. R Since it does not affect the capacitance of the capacitor, it can be changed depending on the width of the adjacent resistive layer. The gap Y in the Y-axis direction between the Nth auxiliary electrode AX and the N+1th auxiliary electrode AX S is 1 μm or more and 3 μm or less. The dielectric material located between the preliminary electrodes can be silicon oxide or silicon nitride, but is not limited to these. The capacitance of the capacitor that can be set under these conditions is 1 fF or more. From the viewpoint of rapid transmission of potential and charge, it is more preferable that the capacitance of the capacitor is 10 fF or more.

[0128] In the above-described structure, each resistor R (resistive layer) may be divided into multiple parts, and the multiple partial resistors may be electrically connected by buried electrodes, etc. Also, by modifying the structure of the buried electrodes themselves that connect the partial resistors, it is possible to use the modified buried electrodes as spare electrodes.

[0129] FIG. 18 is a plan view of a resistor including a high resistance portion.

[0130] The resistor (first high resistance portion RP or second high resistance portion RN) in this example is obtained by dividing one resistor in one line described above into a plurality of resistors, and includes a plurality of partial resistors in one row.

[0131] That is, the resistor of this example includes a plurality of first partial resistors R that are separated into three parts and arranged within a first line (any one line along the X-axis) in a plan view. For example, a total of three first partial resistors R are included within a first line including the first partial resistor R(1). Within the first line, a first preliminary electrode AX(11) extending along the first line and a first preliminary electrode AX(21) on the opposite side adjacent to the first preliminary electrode in the X-axis direction are arranged. The first preliminary electrode AX(11) connects the first partial resistor R(1) to the first partial resistor R adjacent to the first partial resistor R in the X-axis direction and located at the center in the X-axis direction. The first preliminary electrode AX(21) on the opposite side connects the first partial resistor R located at the center in the X-axis direction to the first partial resistor R adjacent to the first partial resistor R in the X-axis direction and located on the negative side in the X-axis direction.

[0132] Similarly, the resistor of this example includes a plurality of second partial resistors R separated into three parts within a second line (a line adjacent to any one line along the X-axis) adjacent to the first line in a plan view. For example, a total of three second partial resistors R are included within the second line including the second partial resistor R(2). Within the second line, a second preliminary electrode AX(12) extending along the second line and a second preliminary electrode AX(22) on the opposite side adjacent to the second preliminary electrode in the X-axis direction are arranged. The second preliminary electrode AX(12) connects the second partial resistor R(2) to the second partial resistor R adjacent to the second partial resistor R in the X-axis direction and located at the center in the X-axis direction. The second preliminary electrode AX(22) on the opposite side connects the second partial resistor R located at the center in the X-axis direction to the second partial resistor R adjacent to the second partial resistor R in the X-axis direction and located on the negative side in the X-axis direction.

[0133] The first preliminary electrode AX(11) in the first line and the second preliminary electrode AX(12) in the second line form a capacitor. Similarly, the first preliminary electrode AX(21) on the opposite side of the first line and the second preliminary electrode AX(22) on the opposite side of the second line form a capacitor. The function of the capacitor is the same as that of the capacitor described above, that is, to suppress a sudden increase in potential difference between resistors adjacent in the Y-axis direction. Note that the potential and charge transmission performance of this capacitor may be delayed depending on the resistance values ​​of the first partial resistor R(1) and the second partial resistor R(2), but basically, it functions to suppress potential difference in the same way as above.

[0134] The length of the first preliminary electrode AX(11) along its longitudinal direction (direction of the first line: X-axis) is 100 μm or more and 300 μm or less, and the length of the second preliminary electrode AX(12) along its longitudinal direction (direction of the second line: X-axis) is 100 μm or more and 300 μm or less, and the capacitance of the capacitor therebetween can be 1 fF or more. From the viewpoint of rapid transmission of potential and charge, the capacitance of this capacitor is preferably 10 fF or more.

[0135] Similarly, the length of the first preliminary electrode AX (21) on the opposite side along its longitudinal direction (the direction of the first line: the X-axis) is 100 μm or more and 300 μm or less, and the length of the second preliminary electrode AX (22) on the opposite side along its longitudinal direction (the direction of the second line: the X-axis) is 100 μm or more and 300 μm or less, and the capacitance of the capacitor therebetween can be 1 fF or more. From the viewpoint of rapid transmission of potential and charge, the capacitance of this capacitor is preferably 10 fF or more. Note that the shape of the preliminary electrodes as embedded electrodes for connection can be determined by referring to FIG. 17, and the values ​​in that figure can be used.

[0136] The combined capacitance of the capacitor group formed by all the spare electrodes in the first and second lines may also satisfy the above range.

[0137] The plurality of first partial resistors R in the first line are electrically connected to the plurality of second partial resistors R in the second line via the buried electrodes BE and via electrodes VE located on the negative side of the X-axis. The plurality of partial resistors R in the second line are electrically connected to the plurality of partial resistors R in the third line via the buried electrodes BE and via electrodes VE located on the positive side of the X-axis. The relationship between the buried electrodes BE and the via electrodes VE is as described above, and the via electrodes VE connect the lower surface of each resistor R (resistive layer) to the upper surface of the buried electrodes BE. This connection structure is repeated for the fourth line and thereafter.

[0138] The thickness of each preliminary electrode (thickness in the Z-axis direction) is greater than the thickness of the partial resistor. That is, the thickness of the first preliminary electrode AX(11) is greater than the thickness of the first partial resistor R(1). The thickness of the second preliminary electrode AX(12) is greater than the thickness of the second partial resistor R(2).

[0139] The first preliminary electrode AX(11) is a buried electrode buried at a position deeper than the first partial resistor R(1), and the second preliminary electrode AX(12) is a buried electrode buried at a position deeper than the second partial resistor R(2). The first preliminary electrode AX(21) on the opposite side, the second preliminary electrode AX(12) on the opposite side, and the other preliminary electrodes are also buried at a position deeper than the resistor R (resistive layer). By forming a capacitor using buried electrodes, the number of elements required for the part can be reduced, improving productivity and also making it possible to thin the thickness of the resistor chip.

[0140] The above-mentioned preliminary electrodes can also be disposed on the resistor R (resistive layer) via via electrodes.

[0141] 19A and 19B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 18 taken along the arrow AA (FIG. 19A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 19B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 19C).

[0142] The structures of the insulating layer 2 and the protective film 4 are the same as those shown in Fig. 16, but differ from the structure shown in Fig. 16 in that divided resistors R are used and connected by their spare electrodes. This semiconductor chip comprises an insulating layer 2 formed on a semiconductor substrate 1 and a resistor embedded in the insulating layer 2.

[0143] In the structure of this example, as shown in Figure 16(B), which is a cross section on the first line, one end of the first partial resistor R(1) on the right side is connected to the buried electrode BE(2) through the via electrode VE, and the other end is connected to the first preliminary electrode AX(11) through the via electrode VE. One end of the first partial resistor R in the center is connected to the first preliminary electrode AX(11) through the via electrode VE, and the other end is connected to the first preliminary electrode AX(21) on the opposite side through the via electrode VE. One end of the first partial resistor R on the left side is connected to the first preliminary electrode AX(21) on the opposite side through the via electrode VE, and the other end is connected to the buried electrode BE on the opposite side through the via electrode VE.

[0144] As shown in Figure 16(C), which is located slightly more positive on the Y-axis than the cross section on the second line, one end of the second partial resistor R(2) on the right side is connected to the buried electrode BE(N) through the via electrode VE, and the other end is connected to the second preliminary electrode AX(12) through the via electrode VE. One end of the second partial resistor R in the center is connected to the second preliminary electrode AX(12) through the via electrode VE, and the other end is connected to the second preliminary electrode AX(22) on the opposite side through the via electrode VE. One end of the second partial resistor R on the left side is connected to the second preliminary electrode AX(22) on the opposite side through the via electrode VE, and the other end is connected to the buried electrode BE on the opposite side through the via electrode VE.

[0145] The auxiliary electrodes are adjacent to each other along the Y-axis direction, with an insulating layer 2 interposed between them. The capacitance between the auxiliary electrodes can be changed by changing the dielectric constant of this insulating layer 2. The capacitance of the capacitor between the auxiliary electrodes depends on the size of the gap between them, the opposing area of ​​the auxiliary electrodes, and the dielectric constant of the dielectric between them. The range of the gap between the auxiliary electrodes can be set to satisfy the exemplary capacitance range of the capacitor described above.

[0146] FIG. 20 is a plan view of an example resistor chip.

[0147] This resistor chip corresponds to the circuit diagram in FIG. 3(A). The resistor chip 10 is constructed by forming an insulating layer on a semiconductor substrate and embedding a resistor in the insulating layer. The resistor chip 10 has a rectangular planar shape and includes a first side surface 10A, a second side surface 10B, a third side surface 10C, and a fourth side surface 10D. A ring-shaped conductor 1R can be embedded in the insulating layer along these sides. The ring-shaped conductor 1R can be constructed of a metal material (e.g., copper). However, if necessary, a ring-shaped conductor made of another material (e.g., a resistive material CrSi) can be provided above or below the metal material and electrically connected by a via electrode (e.g., tungsten). The ring-shaped conductor can contribute to improving waterproofness and electrical stability.

[0148] In this example, in a plan view, the first electrode E1, dummy resistor R (Dmy), first high resistance section RP, first low resistance section RPS, second low resistance section RNS, second high resistance section RN, dummy resistor R (Dmy), and second electrode E2 are aligned in one direction. The first output electrode EP is electrically connected to the buried electrode between the first high resistance section RP and the first low resistance section RPS. The second output electrode EN is electrically connected to the buried electrode between the second high resistance section RN and the second low resistance section RNS. The reference electrode EG is electrically connected to the buried electrode between the first low resistance section RPS and the second low resistance section RNS.

[0149] Another example of a resistor chip is also conceivable.

[0150] For example, several structures are possible for a resistor chip corresponding to the circuit diagram in FIG. 3(B). The structure of another example of a resistor chip will be described with reference to the circuit diagram in FIG. 3(B) and the resistor chip structure described above. This resistor chip, like the resistor chip 10 shown in FIG. 20, is configured by forming an insulating layer on a semiconductor substrate and embedding a resistor in the insulating layer. The resistor chip 10 has a rectangular planar shape and includes a first side surface 10A, a second side surface 10B, a third side surface 10C, and a fourth side surface 10D. It is also possible to embed an annular conductor 1R in the insulating layer along these sides. The structure of the annular conductor 1R is as described above.

[0151] In another example of a resistor chip, in a plan view, the elements shown in FIG. 3B, i.e., the first electrode E1, dummy resistor R(Dmy), high resistance section RP2, dummy resistor R(Dmy), dummy resistor R(Dmy), high resistance section RN2, dummy resistor R(Dmy), and second electrode E2, are aligned along one direction. Also, in a plan view, the high resistance section RP1 and dummy resistor R(Dmy) are aligned next to the first electrode E1 in a direction perpendicular to the above-mentioned one direction. The dummy resistor R(Dmy), high resistance section RP1, dummy resistor R(Dmy), first low resistance section RPS, second low resistance section RNS, dummy resistor R(Dmy), high resistance section RN1, and dummy resistor R(Dmy) are aligned along one direction. One end of the low-voltage side of the high resistance section RP2 is connected to the first output electrode EP. One end on the low voltage side of the high resistance section RN2 is connected to the second output electrode EN.

[0152] One end on the low-voltage side of the first low-resistance unit RPS is electrically connected to the first reference electrode EG1, via an intermediate electrode if necessary. One end on the low-voltage side of the second low-resistance unit RNS is electrically connected to the second reference electrode EG2. The first reference electrode EG1 and the second reference electrode EG2 can also be shorted within the resistor chip or an external amplifier chip and used as the reference electrode EG.

[0153] The electrical connection of the circuit elements of another example of a resistor chip is as shown in Figure 3(B), but the arrangement of the circuit elements is not limited to the above arrangement example and various modifications are possible.

[0154] 21A, 21B, and 21C are plan views of a low resistance portion for voltage detection.

[0155] The first low resistance section RPS (or the second low resistance section RNS) is made up of a plurality of linear resistors R E Each resistor R EA via electrode VE is provided below the end of the resistor, and is physically and electrically connected to the buried electrode BE located below the via electrode VE. The number of linear resistors may be three or more, or may be less than three.

[0156] In the example shown in FIG. 21(A), three linear resistors R E The linear resistor R E and one end of the second row of linear resistors R E The first end of the linear resistor R in the second row is connected to the first end of the linear resistor R in the second row through a via electrode VE and a buried electrode BE. E and the other end of the third row linear resistor R E The other end of the via electrode VE is connected to the other end of the buried electrode BE through a via electrode VE and a buried electrode BE.

[0157] In the example shown in FIG. 21(B), the linear resistor in FIG. 21(A) is divided into two in each row, and a plurality of linear resistors R E Therefore, there are a total of six linear resistors R E In each row, a pair of adjacent linear resistors R E The opposing ends of the electrodes are connected via a via electrode VE and a buried electrode BE.

[0158] In the example shown in FIG. 21(C), all the linear resistors R E One end of each of the linear resistors R is connected to the other end of each of the linear resistors R through a via electrode VE and a common buried electrode BE. E The other ends of the resistors are connected through a via electrode VE and a common buried electrode BE. In this example, the combined resistance value can be reduced more than that of the resistor shown in FIG.

[0159] The cross-sectional structure of the low resistance section (RPS, RNS) for detection can be the same as that of the high resistance section (RP, RN) except for the planar shape. E The via electrodes VE and the buried electrodes BE (buried wiring) are buried in an insulating layer formed on a semiconductor substrate.

[0160] The materials of each element will be explained.

[0161] The semiconductor substrate 1 may have conductivity. For example, the impurity concentration of the semiconductor substrate 1 may be 5×10 13 (cm -3 ) or more 5 x 10 14 (cm -3 The thickness of the semiconductor substrate 1 may be 50 μm or more and 800 μm or less. The material of the semiconductor substrate 1 may be silicon (Si), but it is also possible to use a compound semiconductor such as SiC or SiGe.

[0162] The material of the resistive layer (wire resistor) constituting the resistor R is a resistive material with a higher resistivity than polysilicon. Specifically, the material of the resistor (resistive layer) is a material containing chromium (Cr) and silicon (Si), such as CrSi, CrSiC, or CrSiN. Other materials can also be used. Specifically, the material of the resistive layer constituting the resistor can include at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, TaN, and TiN. The resistive layer constituting the resistor can be formed using a sputtering method using a target containing a resistive material. Depending on the type of material of the resistor R, a plating method can also be used. The material of the resistor R may be composed of a single resistive material or a combination of multiple resistive materials. The thickness Rd of each resistive layer constituting the resistor R can be 1 nm≦Rd≦5 nm. When the thickness Rd is equal to or less than the upper limit, the resistance value can be sufficiently high, and when the thickness Rd is equal to or greater than the lower limit, the durability and strength of the resistive layer can be maintained.

[0163] The first electrode E1, the second electrode E2, and the buried electrodes (buried wiring) can be made of metal materials such as Al (aluminum) or Cu (copper).The various via electrodes can be made of high-melting-point metals such as tungsten (W), but other electrode materials can also be used. (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0164] [A1] A semiconductor device comprising an insulating layer 2 formed on a semiconductor substrate 1, and resistors (first high resistance portion RP, second high resistance portion RN) embedded in the insulating layer 2, the resistors comprising a first resistance layer (resistor R(1)), a first buried electrode (BE(2)) electrically connected to one end of the first resistance layer (resistor R(1)), a second resistance layer (resistor R(2)) disposed adjacent to the first resistance layer (resistor R(1)) and electrically connected to the other end of the first resistance layer (resistor R(1)), and a second buried electrode (BE(N)) electrically connected to one end of the second resistance layer (resistor R(2)), a first preliminary electrode AX(11) extending along the longitudinal direction (X-axis direction) of the first resistive layer (resistor R(1)), electrically connected to the first buried electrode (BE(2)), and having a thickness greater than that of the first resistive layer (resistor R(1)); and a second preliminary electrode AX(12) extending along the longitudinal direction, electrically connected to the second buried electrode (BE(N)), having a thickness greater than that of the second resistive layer (resistor R(2)), adjacent to the first preliminary electrode AX(11), and constituting a capacitor (C11) together with the first preliminary electrode AX(11).

[0165] [A2] The semiconductor device according to [A1], wherein the length of the first preliminary electrode AX(11) along the longitudinal direction (X-axis direction) is 100 μm or more and 300 μm or less, the length of the second preliminary electrode AX(12) along the longitudinal direction (X-axis direction) is 100 μm or more and 300 μm or less, and the capacitance of the capacitor (C11, etc.) is 1 fF or more.

[0166] [A3] The semiconductor device according to [A1], wherein the length of the first preliminary electrode AX(11) along the longitudinal direction (X-axis direction) is 100 μm or more and 300 μm or less, the length of the second preliminary electrode AX(12) along the longitudinal direction (X-axis direction) is 100 μm or more and 300 μm or less, and the capacitance of the capacitor (C11, etc.) is 10 fF or more.

[0167] [A4] The semiconductor device described in [A1], wherein the direction from the end of the first resistance layer (resistor R(1)) in the longitudinal direction (X-axis direction) toward the center is defined as a first direction, and in plan view, the first preliminary electrode AX(11) extends along the first direction from a position directly above the first embedded electrode BE(2), and the second preliminary electrode AX(12) extends along the first direction from a position directly above the second embedded electrode BE(N) (FIGS. 5 and 8).

[0168] [A5] In a plan view, the first preliminary electrode AX(11) extends from a position directly above the first buried electrode BE(2) in the direction opposite to the first direction, and the second preliminary electrode AX(12) extends from a position directly above the second buried electrode BE(N) in the direction opposite to the first direction (FIG. 11), in the semiconductor device described in [A4].

[0169] [A6] The direction from the longitudinal end of the first resistance layer toward the center is defined as a first direction, and in plan view, the first preliminary electrode AX(11) extends from a position directly above the first embedded electrode BE(2) in a direction opposite to the first direction, and the second preliminary electrode AX(12) extends from a position directly above the second embedded electrode BE(N) in a direction opposite to the first direction (FIG. 13).

[0170] [A7] The semiconductor device described in [A1], wherein the first preliminary electrode AX(11) is a first extension (AX) of the first buried electrode (BE(2)) that is continuous with the first buried electrode (BE(2)) and extends along a direction opposite to the first direction, and the second preliminary electrode AX(12) is a second extension (AX) of the second buried electrode BE(N) that is continuous with the second buried electrode BE(N) and extends along a direction opposite to the first direction.

[0171] [A8] The semiconductor device described in [A1] includes: a dummy resistance layer (final dummy resistance layer R(f)) arranged adjacent to the first resistance layer (first resistor R(1)) on the opposite side to the second resistance layer (second resistor R(2)), one end of which is electrically connected to the first buried electrode BE(2); and a third resistance layer (third resistor R(3)) arranged adjacent to the second resistance layer (second resistor R(2)) on the opposite side to the first resistance layer (first resistor R(1)), one end of which is electrically connected to the second buried electrode BE(N) (Figures 10, 5, 8, 11, 13, 15).

[0172] [A9] A semiconductor device comprising an insulating layer 2 formed on a semiconductor substrate 1 and a resistor embedded in the insulating layer 2, wherein the resistor (first high resistance portion RP, second high resistance portion RN) has a thickness greater than that of the first partial resistors (R), a first preliminary electrode AX (11) extending along the first line, a second preliminary electrode AX (12) adjacent to the first line in plan view, and a plurality of first partial resistors (R) arranged separately in a first line in plan view, the first partial resistors (R) being electrically connected to each other. A semiconductor device comprising: a plurality of second partial resistors (R) arranged separately within a line; and a second preliminary electrode AX (12) electrically connecting the plurality of second partial resistors (R), having a thickness greater than that of the second partial resistors (R), and extending along the second line, wherein the first partial resistor (R) is electrically connected to the second partial resistor (R), and the first preliminary electrode AX (11) and the second preliminary electrode AX (12) form a capacitor (C11) (Figures 18 and 19).

[0173] [A10] The semiconductor device according to [A9], wherein the length of the first preliminary electrode AX(11) along the longitudinal direction (X-axis) is 100 μm or more and 300 μm or less, the length of the second preliminary electrode AX(12) along the longitudinal direction is 100 μm or more and 300 μm or less, and the capacitance of the capacitor C11 is 1 fF or more (FIGS. 18, 19, 17).

[0174] [A11] The semiconductor device according to [A9], wherein the length of the first preliminary electrode AX(11) along the longitudinal direction is 100 μm or more and 300 μm or less, the length of the second preliminary electrode AX(12) along the longitudinal direction is 100 μm or more and 300 μm or less, and the capacitance of the capacitor C11 is 10 fF or more (FIGS. 18, 19, 17).

[0175] [A12] The first preliminary electrode AX(11) is a buried electrode buried at a position deeper than the first partial resistor (R(1)), and the second preliminary electrode AX(12) is a buried electrode buried at a position deeper than the second partial resistor (R(2)) (Figures 18 and 19), in the semiconductor device described in [A9].

[0176] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0177] 1...Semiconductor substrate 1R...Ring conductor 2...Insulating layer 2A...First dielectric layer 2A H ,2A L ...dielectric layer 2B: Second dielectric layer 4...Protective film 4A…First protective film 4B…Second protective film 4C…Third protective film 10...Resistor chip (semiconductor device) 10A...First side 10B…Second side 10C…Third side 10D…4th side 10a…1st inner lead 10b…Second inner lead 10c…3rd inner lead 10d…4th inner lead 10e…5th Inner Lead 10f...6th inner lead 10g...7th inner lead 10h…8th inner lead 10i…9th inner lead 20...Amplifier chip (semiconductor device) 30…cases 100...Semiconductor package 110...First die pad 120...Second die pad 200...battery AX...Spare electrode AX(11)...First spare electrode AX(21)...First spare electrode AX(12)...Second spare electrode AX(22)...Second spare electrode AX(13)...Third spare electrode AX(23)...Third spare electrode AX(14)...4th spare electrode AX(24)...4th spare electrode AX(15)...5th spare electrode AX(25)...5th spare electrode BE...buried electrode BE(1)...Buried electrode (first connection region) BE(2)...Buried electrode (second connection area) BE(3)...Buried electrode (third connection region) BE(N)...Buried electrode C10: Resistor circuit (voltage divider circuit) C20: Voltage detection circuit C11...Capacitor D1...Concave E1…1st electrode E2…Second electrode EG…Reference electrode EG1...1st reference electrode EG2…Second reference electrode EP…1st output electrode EN: Second output electrode GND: Ground potential HV(+)...First input terminal HV(-)...Second input terminal INN: Second input terminal INP...First input terminal N1: First node N2: Second node Na...3rd node Nb...4th node Nc...5th node Nd, Ne, Nf, Ng, Nh...nodes R…Resistor (resistance layer, partial resistor) R(1)…Resistor (resistance layer, partial resistor) R(2)…Resistor (resistance layer, partial resistor) R(3)…Resistor (resistance layer) R(4)…Resistor (resistance layer) R(5)…Resistor (resistance layer) R(6)…Resistor (resistance layer) R(7)…Resistor (resistance layer) R(8)…Resistor (resistance layer) R(9)…Resistor (resistance layer) R(10)…Resistor (resistance layer) R(Dmy)...Dummy resistor (resistive layer) R(f)...Final resistor (final dummy resistor layer) R E …Each resistor (linear resistor) RP…1st high resistance part (1st resistor) RN...Second high resistance section (second resistor) RPS...1st low resistance section RNS…Second low resistance section RN1,RN2,RP1,RP2…High resistance part VC…Reference terminal Vcc: power supply voltage VE: Via electrode VE11, VE21...First via electrode VE12, VE22...Second via electrode VE13, VE23...Third via electrode VE14, VE24...Fourth via electrode VE15, VE25...5th via electrode Vout: Output voltage Y R ,Z R …size Y S …gap

Claims

1. an insulating layer formed on a semiconductor substrate; a resistor embedded within the insulating layer; Equipped with The resistor is a first resistive layer; a first buried electrode electrically connected to one end of the first resistive layer; a second resistive layer disposed adjacent to the first resistive layer and electrically connected to the other end of the first resistive layer; a second buried electrode electrically connected to one end of the second resistive layer; a first preliminary electrode extending along the longitudinal direction of the first resistance layer in a plan view, electrically connected to the first buried electrode, and having a thickness greater than a thickness of the first resistance layer; a second preliminary electrode extending along the longitudinal direction, electrically connected to the second buried electrode, having a thickness greater than that of the second resistive layer, adjacent to the first preliminary electrode, and constituting a capacitor together with the first preliminary electrode; A semiconductor device comprising:

2. The length of the first preliminary electrode along the longitudinal direction is 100 μm or more and 300 μm or less, The length of the second preliminary electrode along the longitudinal direction is 100 μm or more and 300 μm or less, The capacitance of the capacitor is 1 fF or more. The semiconductor device according to claim 1 .

3. The length of the first preliminary electrode along the longitudinal direction is 100 μm or more and 300 μm or less, The length of the second preliminary electrode along the longitudinal direction is 100 μm or more and 300 μm or less, The capacitance of the capacitor is 10 fF or more. The semiconductor device according to claim 1 .

4. a direction from an end portion of the first resistance layer toward the center in the longitudinal direction is defined as a first direction; In plan view, the first preliminary electrode extends along the first direction from a position directly above the first buried electrode, the second preliminary electrode extends along the first direction from a position directly above the second buried electrode; The semiconductor device according to claim 1 .

5. In plan view, the first preliminary electrode extends from a position directly above the first buried electrode in a direction opposite to the first direction, the second preliminary electrode extends from a position directly above the second buried electrode in a direction opposite to the first direction; The semiconductor device according to claim 4 .

6. a direction from an end portion of the first resistance layer toward the center in the longitudinal direction is defined as a first direction; In plan view, the first preliminary electrode extends from a position directly above the first buried electrode along a direction opposite to the first direction, the second preliminary electrode extends from a position directly above the second buried electrode in a direction opposite to the first direction; The semiconductor device according to claim 1 .

7. a direction from an end portion of the first resistance layer toward the center in the longitudinal direction is defined as a first direction; the first preliminary electrode is a first extension of the first buried electrode that is continuous with the first buried electrode and extends in a direction opposite to the first direction, the second preliminary electrode is a second extension of the second buried electrode that is continuous with the second buried electrode and extends in a direction opposite to the first direction; The semiconductor device according to claim 1 .

8. a dummy resistance layer disposed adjacent to the first resistance layer on the opposite side to the second resistance layer, one end of which is electrically connected to the first buried electrode; a third resistive layer disposed adjacent to the second resistive layer on the opposite side to the first resistive layer, one end of which is electrically connected to the second buried electrode; Equipped with The semiconductor device according to claim 1 .

9. an insulating layer formed on a semiconductor substrate; a resistor embedded within the insulating layer; Equipped with The resistor is Within the first line in plan view, a plurality of first partial resistors arranged separately; a first preliminary electrode electrically connecting the plurality of first partial resistors, having a thickness greater than a thickness of the first partial resistors, and extending along the first line; In a second line adjacent to the first line in a plan view, a plurality of second partial resistors arranged separately; a second preliminary electrode electrically connecting the second partial resistors, having a thickness greater than a thickness of the second partial resistors, and extending along the second line; Equipped with the first partial resistor is electrically connected to the second partial resistor; The first preliminary electrode and the second preliminary electrode form a capacitor. Semiconductor device.

10. The length of the first preliminary electrode along the longitudinal direction is 100 μm or more and 300 μm or less, The length of the second preliminary electrode along the longitudinal direction is 100 μm or more and 300 μm or less, The capacitance of the capacitor is 1 fF or more. The semiconductor device according to claim 9 .

11. The length of the first preliminary electrode along the longitudinal direction is 100 μm or more and 300 μm or less, The length of the second preliminary electrode along the longitudinal direction is 100 μm or more and 300 μm or less, The capacitance of the capacitor is 10 fF or more. The semiconductor device according to claim 9 .

12. the first preliminary electrode is a buried electrode buried at a position deeper than the first partial resistor, the second preliminary electrode is a buried electrode buried at a position deeper than the second partial resistor; The semiconductor device according to claim 9 .

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