Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device in which the variation in threshold voltage can be suppressed, and a manufacturing method for the same.SOLUTION: A semiconductor device in an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a metal layer, and a second electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The gate electrode faces the second semiconductor region through a gate insulating layer in a second direction perpendicular to a first direction from the first electrode to the first semiconductor region. The metal layer is provided on the gate electrode through a first insulating layer and includes one or more selected from the group consisting of titanium, lanthanum, and vanadium. The second electrode is provided on the metal layer through a second insulating layer and is electrically connected to the second and third semiconductor regions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices such as metal-oxide-semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion. Semiconductor devices can be switched to an on state by applying a voltage greater than a threshold voltage to the gate electrode. It is desirable for the threshold voltage of semiconductor devices to have small fluctuations. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-48335 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of suppressing fluctuations in threshold voltage and a method for manufacturing the same. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a metal layer, and a second electrode. The first semiconductor region is provided on the first electrode and electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The metal layer is provided on the gate electrode via a first insulating layer and contains one or more elements selected from the group consisting of titanium, lanthanum, and vanadium. The second electrode is provided on the metal layer via a second insulating layer and electrically connected to the second semiconductor region and the third semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view of a part of the semiconductor device according to the embodiment. [Figure 3] 3(a) and 3(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 4] 4(a) and 4(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] 5(a) and 5(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a perspective cross-sectional view showing a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already described are designated by the same reference numerals, and detailed description will be omitted as appropriate. In the following description, n + , n - and p + The notation "p" indicates the relative level of impurity concentration in each conductivity type. That is, notations with "+" indicate a relatively higher impurity concentration than notations with neither "+" nor "-" and notations with "-" indicate a relatively lower impurity concentration than notations with neither. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] FIG. 1 is a perspective cross-sectional view showing a semiconductor device according to an embodiment. As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes n - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + source region 3 (third semiconductor region), p + Shape contact area 4, n + The semiconductor device 100 is a MOSFET, and includes a drain region 5, a conductive portion 11, a gate electrode 12, a gate insulating layer 12a, a metal layer 13, a first insulating portion 21, a second insulating portion 22, a first insulating layer 31, a second insulating layer 32, a drain electrode 41 (first electrode), and a source electrode 42 (second electrode).

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. -The direction toward the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction. - The direction toward the drift region 1 is called "up" and the opposite direction is called "down." These directions are the direction of the drain electrode 41 and the n - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0010] The drain electrode 41 is provided at the bottom of the semiconductor device 100. + The drain region 5 is provided on the drain electrode 41 and is electrically connected to the drain electrode 41. - The drift region 1 is n + The n-type drain region 5 is provided on the n-type drain region 5. - The n-type impurity concentration in the n-type drift region 1 is + The n-type impurity concentration in the n-type drain region 5 is lower than that in the n-type drain region 5 .

[0011] The p-type base region 2 is - The n-type drift region 1 is provided on the n-type drift region 1. + Shape source region 3 and p + The p-type contact region 4 is provided on the p-type base region 2. + The n-type impurity concentration in the n-type source region 3 is - The n-type impurity concentration in the n-type drift region 1 is higher than that in the p-type drift region 2. + The p-type impurity concentration in the p-type contact region 4 is higher than the p-type impurity concentration in the p-type base region 2.

[0012] The conductive portion 11 is - The gate electrode 12 is provided in the n-type drift region 1 via a first insulating portion 21. The gate electrode 12 is provided on the conductive portion 11 via a second insulating portion 22. The gate electrode 12 faces the p-type base region 2 in the X direction via a gate insulating layer 12a. The gate electrode 12 is connected to the n-type base region 2 via the gate insulating layer 12a. - A part of the drift region 1 and n +It may also face a part of the source region 3 .

[0013] The metal layer 13 is provided on the gate electrode 12 via a first insulating layer 31. The source electrode 42 is provided on the metal layer 13 via a second insulating layer 32. The source electrode 42 is connected to the p-type base region 2 and the n-type base region 3. + a p-type base region 2 and an n-type source region 3; + The source region 3 is electrically connected to the source region 3 .

[0014] 1, the source electrode 42 may include a contact portion C. The contact portion C is connected to a part of the p-type base region 2 and the n-type base region 3 in the X direction. + Shape source region 3 and line, p + The contact portion C is located on the p-type contact region 4. + Shape source region 3, and p + The contact region 4 is in contact with the substrate.

[0015] An example of the material of each component will be described. n - p-type drift region 1, p-type base region 2, n + Shape source region 3, p + contact region 4, and n +The drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The conductive portion 11 and the gate electrode 12 include a conductive material such as polysilicon. The metal layer 13 includes one or more elements selected from the group consisting of titanium (Ti), lanthanum (La), and vanadium (V). The metal layer 13 may also include one or more compounds selected from the group consisting of titanium, lanthanum, and vanadium. Examples of such compounds include TiFe. Preferably, the metal layer 13 is composed solely of titanium. The gate insulating layer 12a, the first insulating portion 21, the second insulating portion 22, the first insulating layer 31, and the second insulating layer 32 include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 41 and the source electrode 42 include metals such as titanium, aluminum, and copper.

[0016] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 41 relative to the source electrode 42, a voltage equal to or greater than the threshold is applied to the gate electrode 12. This forms a channel (inversion layer) in the p-type base region 2, turning the semiconductor device 100 on. Electrons flow through the channel from the source electrode 42 to the drain electrode 41. When the voltage applied to the gate electrode 12 becomes lower than the threshold, the channel in the p-type base region 2 disappears, turning the semiconductor device 100 off.

[0017] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 41 increases relative to the source electrode 42. The potential of the conductive portion 11 is substantially the same as the potential of the source electrode 42. The n-type ... - The potential difference between the drift region 1 and the conductive portion 11 causes the first insulating portion 21 and the n - From the interface with the drift region 1, -The depletion layer spreads toward the n-type drift region 1. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the breakdown voltage of the semiconductor device 100 can be increased while maintaining the breakdown voltage. - The n-type impurity concentration in the n-type drift region 1 can be increased, and the on-resistance of the semiconductor device 100 can be reduced.

[0018] FIG. 2 is an enlarged cross-sectional view of a part of the semiconductor device according to the embodiment. 2, the source electrode 42 may include multiple metal layers. In the example shown in FIG. 2, the source electrode 42 includes a titanium layer 42a, a titanium nitride layer 42b, a tungsten layer 42c, and an aluminum copper layer 42d. The titanium layer 42a is connected to the p-type base region 2, the n-type base region 3, and the n-type base region 4. + Shape source region 3, and p + The titanium layer 42a is in contact with the contact region 4. A titanium nitride layer 42b is provided on the titanium layer 42a. A tungsten layer 42c is provided on the titanium nitride layer 42b. An aluminum copper layer 42d is provided on the tungsten layer 42c.

[0019] A distance D1 in the Z direction between the gate electrode 12 and the metal layer 13 is shorter than a distance D2 between the metal layer 13 and the source electrode 42. The distance D1 corresponds to the thickness of the first insulating layer 31. The distance D2 corresponds to the thickness of the second insulating layer 32.

[0020] As shown in FIG. 1, the p-type base region 2, n + Shape source region 3, p + A plurality of n-type contact regions 4, conductive portions 11, gate electrodes 12, and contact portions C are provided in the X direction. For example, a pair of n-type contact regions 4, conductive portions 11, gate electrodes 12, and contact portions C are provided on one p-type base region 2. + A pair of n-type source regions 3 are provided in the X direction. + The gate electrode 12 is located between the p-type base region 2 and the pair of n-type source regions 3. + Shape source region 3, and p + The pairs of contact regions 4 are alternately arranged in the X direction.

[0021] Each p-type base region 2, each n + Shape source area 3, each p + The contact region 4, the conductive portions 11, the gate electrodes 12, and the contact portions C extend in the Y direction and are arranged in a stripe pattern. The ends of the conductive portions 11 in the Y direction are pulled upward and contact the source electrodes 42. As a result, the conductive portions 11 are electrically connected to the source electrodes 42.

[0022] 3(a), 3(b), 4(a), 4(b), 5(a), and 5(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. First, n - Shape drift region 1 and n + A semiconductor substrate including a n-type drain region 5 is prepared. - A plurality of openings OP1 are formed in the upper surface of the drift region 1. As shown in FIG. 3(a), inside the openings OP1, a conductive portion 11, a gate electrode 12, a gate insulating layer 12a, a first insulating portion 21, and a second insulating portion 22 are formed. - Shape drift region 1, n + A structure ST including a drain region 5, a conductive portion 11, a gate electrode 12, a gate insulating layer 12a, a first insulating portion 21, and a second insulating portion 22 is prepared.

[0023] n located between the openings OP1 - P-type impurities and n-type impurities are ion-implanted sequentially into a part of the n-type drift region 1. As a result, as shown in FIG. - A p-type base region 2 and an n-type drift region 1 are formed on the p-type base region 2. + A source region 3 is formed.

[0024] A first insulating layer 31 is formed on the upper surface of the gate electrode 12 by thermal oxidation. As shown in FIG. 4(a), a metal layer 13a containing titanium is formed on the first insulating layer 31 by chemical vapor deposition (CVD). The upper surface of the metal layer 13a is recessed by reactive ion etching (RIE). As a result, a metal layer 13 is formed on each gate electrode 12 as shown in FIG. 4(b).

[0025] The second insulating layer 32 is formed on the metal layer 13 by CVD. A part of the second insulating layer 32, n + A part of the p-type source region 3 and the p-type base region 2 are removed to form a plurality of openings OP2. P-type impurities are ion-implanted into the p-type base region 2 through the openings OP2. As a result, as shown in FIG. + A contact region 4 is formed.

[0026] A titanium layer 42a to a tungsten layer 42c are sequentially formed by CVD along the upper surface of the second insulating layer 32 and the inner surface of the opening OP2. An aluminum copper layer 42d is formed by sputtering. This completes the source electrode 42 including the titanium layer 42a to the aluminum copper layer 42d. + The n-type drain region 5 is then grown to a predetermined thickness. + The back surface of the drain region 5 is ground. As shown in FIG. 5(b), + A drain electrode 41 is formed by sputtering on the back surface of the drain region 5. Through the above steps, the semiconductor device 100 according to the embodiment is manufactured.

[0027] After the drain electrode 41 and the source electrode 42 are formed, the semiconductor device 100 is heat-treated in a hydrogen atmosphere. - the interface between the p-type drift region 1 and the first insulating portion 21, the interface between the p-type base region 2 and the gate insulating layer 12a, + Dangling bonds of silicon present at the interface between the source region 3 and the gate insulating layer 12a, for example, are terminated by hydrogen. By terminating the dangling bonds, it is possible to prevent unintended impurities from bonding to the dangling bonds and affecting the characteristics of the semiconductor device 100.

[0028] The advantages of the embodiment will be described. The hydrogen present at the interface described above can be desorbed by voltage during operation of the semiconductor device 100. When hydrogen is desorbed, dangling bonds of silicon are generated, and traps for holes are formed. When holes are trapped, the threshold voltage for turning on the semiconductor device 100 fluctuates. In addition, unintended impurities may bond with the dangling bonds, causing fluctuations in the characteristics of the semiconductor device 100.

[0029] To address this issue, the semiconductor device 100 according to the embodiment includes a metal layer 13. The metal layer 13 is provided on the gate electrode 12 and includes one or more elements selected from the group consisting of titanium, lanthanum, and vanadium. Titanium, lanthanum, and vanadium are all highly susceptible to hydrogen absorption. When the metal layer 13 is provided, hydrogen absorbed by titanium diffuses from the metal layer 13. Therefore, even if hydrogen is desorbed to generate dangling bonds of silicon, hydrogen diffused from the metal layer 13 is supplied to the dangling bonds. For example, the dangling bonds are terminated by the supplied hydrogen. Therefore, according to the embodiment, it is possible to suppress fluctuations in threshold voltage caused by hydrogen desorption.

[0030] The metal layer 13 is preferably separated from the gate electrode 12 by the first insulating layer 31. If the metal layer 13 is in contact with the gate electrode 12, the metal contained in the metal layer 13 may react with the silicon of the gate electrode 12 to form a silicide. The amount of hydrogen absorbed by a silicide is smaller than the amount of hydrogen absorbed by a metal alone. Therefore, in order to suppress the threshold fluctuation, it is effective to separate the metal layer 13 from the gate electrode 12 and suppress the silicidation of the metal layer 13.

[0031] A contact may be provided between a part of the gate electrode 12 and a part of the metal layer 13, and the gate electrode 12 and the metal layer 13 may be electrically connected. However, more preferably, the metal layer 13 is electrically isolated from the gate electrode 12. When the metal layer 13 is electrically connected to the gate electrode 12, the capacitance C between the gate electrode 12 and the source electrode 42 is smaller than when the metal layer 13 is not provided. GSEven when the metal layer 13 is provided, the metal layer 13 and the gate electrode 12 are electrically isolated from each other, so that the capacitance C GS The increase in the amount of oxygen can be suppressed.

[0032] The metal layer 13 may be connected to a potential different from the potential of the gate electrode 12 and the potential of the source electrode 42. Preferably, the potential of the metal layer 13 is floating. By making the potential of the metal layer 13 floating, the structure of the semiconductor device 100 can be simplified.

[0033] The metal layer 13 is preferably located near the interface between the p-type base region 2 and the gate insulating layer 12a. By locating the metal layer 13 near this interface, hydrogen diffused from the metal layer 13 is more easily supplied to the interface. For example, as shown in FIG. 2, the distance D1 between the gate electrode 12 and the metal layer 13 is shorter than the distance D2 between the metal layer 13 and the source electrode 42. This allows the metal layer 13 to be located closer to the interface between the p-type base region 2 and the gate insulating layer 12a. As a result, the threshold voltage fluctuation caused by hydrogen desorption can be further suppressed. For example, the distance D1 is preferably 10 nm or more and 100 nm or less, and more preferably 30 nm or more and 80 nm or less.

[0034] The thickness of the metal layer 13 is arbitrary as long as it can absorb a sufficient amount of hydrogen. For example, the thickness of the metal layer 13 is preferably 8 nm or more and 180 nm or less, and more preferably 8 nm or more and 150 nm or less.

[0035] The top end of the metal layer 13 is n + It is preferable that the metal layer 13 is located below the upper end of the p-type source region 3. If the metal layer 13 is located above the p-type base region 2, the second insulating layer 32 and the source electrode 42 will be located higher by the thickness of the metal layer 13. For example, in the step shown in FIG. 5(a), it may be difficult to form the opening OP2. + By being located below the upper end of the source region 3, the manufacturing of the semiconductor device 100 becomes easier. +By bringing the metal layer 13 closer to the gate electrode 12 so as to be positioned below the upper end of the source region 3, fluctuations in the threshold voltage caused by desorption of hydrogen can be effectively suppressed.

[0036] 2, the source electrode 42 preferably includes a titanium layer 42a. The titanium layer 42a can also absorb hydrogen. By supplying hydrogen to the dangling bonds of silicon from both the metal layer 13 and the titanium layer 42a, fluctuations in the threshold voltage of the semiconductor device 100 can be further suppressed.

[0037] Of the metals titanium, lanthanum, and vanadium, titanium is most preferable for use in the metal layer 13. This is because titanium absorbs hydrogen more easily than lanthanum and vanadium.

[0038] 1, the source electrode 42 preferably includes a contact portion C. By providing the contact portion C, the p-type base region 2 (p + The contact area between the contact region 4) and the source electrode 42, and the n + This allows the contact area between the source region 3 and the source electrode 42 to be increased.

[0039] (Variation) FIG. 6 is a perspective cross-sectional view showing a semiconductor device according to a modified example of the embodiment. As shown in FIG. 6, a semiconductor device 110 according to a modification has n - p-type drift region 1, p-type base region 2, n + Shape source region 3, p + Shape contact area 4, n + The semiconductor device 110 includes a drain region 5, a gate electrode 12, a gate insulating layer 12a, a metal layer 13, a first insulating layer 31, a second insulating layer 32, a drain electrode 41, and a source electrode 42. The semiconductor device 110 differs from the semiconductor device 100 in that it does not include a conductive portion 11.

[0040] The gate electrode 12 is n -The gate electrode 12 is provided in the p-type drift region 1 via a gate insulating layer 12a. The gate electrode 12 faces the p-type base region 2 in the X direction via the gate insulating layer 12a.

[0041] It is desirable to provide the conductive portion 11 in order to improve the withstand voltage or reduce the on-resistance of the semiconductor device 100. However, if the conductive portion 11 can be omitted from the viewpoint of the withstand voltage or the on-resistance, the conductive portion 11 may be omitted as in the semiconductor device 110.

[0042] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a metal layer provided on the gate electrode via a first insulating layer, the metal layer including one or more selected from the group consisting of titanium, lanthanum, and vanadium; a second electrode provided on the metal layer via a second insulating layer and electrically connected to the second semiconductor region and the third semiconductor region; A semiconductor device comprising: (Feature 2) 2. The semiconductor device according to claim 1, wherein the metal layer is electrically isolated from the gate electrode and the second electrode. (Feature 3) 3. The semiconductor device according to claim 1, wherein the metal layer has a floating potential. (Feature 4) The semiconductor device according to any one of features 1 to 3, wherein the distance in the first direction between the gate electrode and the metal layer is shorter than the distance in the first direction between the metal layer and the second electrode. (Feature 5) 5. The semiconductor device according to any one of Features 1 to 4, wherein an upper end of the metal layer is located lower than an upper end of the third semiconductor region. (Feature 6) 6. The semiconductor device according to any one of Features 1 to 5, wherein the second electrode includes a titanium layer in contact with the second semiconductor region and the third semiconductor region. (Feature 7) 7. The semiconductor device according to any one of Features 1 to 6, wherein the metal layer contains titanium. (Feature 8) a conductive portion provided in the first semiconductor region via a first insulating portion; 8. The semiconductor device according to any one of Features 1 to 7, wherein the gate electrode is provided on the conductive portion via a second insulating portion. (Feature 9) a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; forming a metal layer containing one or more elements selected from the group consisting of titanium, lanthanum, and vanadium on the gate electrode via a first insulating layer, for a structure comprising the above; forming a second insulating layer on the metal layer; forming an electrode on the second insulating layer.

[0043] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0044] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0045] 1:n - 1: p-type drift region; 2: p-type base region; 3: n-type + Shape source area, 4:p + Shape contact area, 5:n + Drain region, 11: conductive portion, 12: gate electrode, 12a: gate insulating layer, 13, 13a: metal layer, 21: first insulating portion, 22: second insulating portion, 31: first insulating layer, 32: second insulating layer, 41: drain electrode, 42: source electrode, 42a: titanium layer, 42b: titanium nitride layer, 42c: tungsten layer, 42d: aluminum copper layer, 100, 110: semiconductor device, C: contact portion, D1, D2: distance, OP1, OP2: opening, ST: structure

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a metal layer provided on the gate electrode via a first insulating layer, the metal layer including one or more elements selected from the group consisting of titanium, lanthanum, and vanadium; a second electrode provided on the metal layer via a second insulating layer, the second electrode being electrically connected to the second semiconductor region and the third semiconductor region; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the metal layer is electrically isolated from the gate electrode and the second electrode.

3. 2. The semiconductor device according to claim 1, wherein the metal layer is at a floating potential.

4. 4. The semiconductor device according to claim 1, wherein the distance in the first direction between the gate electrode and the metal layer is shorter than the distance in the first direction between the metal layer and the second electrode.

5. 4. The semiconductor device according to claim 1, wherein an upper end of said metal layer is located lower than an upper end of said third semiconductor region.

6. 4. The semiconductor device according to claim 1, wherein said second electrode includes a titanium layer in contact with said second semiconductor region and said third semiconductor region.

7. 4. The semiconductor device according to claim 1, wherein said metal layer contains titanium.

8. a conductive portion provided in the first semiconductor region via a first insulating portion; 4. The semiconductor device according to claim 1, wherein the gate electrode is provided on the conductive portion via a second insulating portion.

9. a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; forming a metal layer containing one or more elements selected from the group consisting of titanium, lanthanum, and vanadium on the gate electrode via a first insulating layer, for a structure including the above; forming a second insulating layer on the metal layer; forming an electrode on the second insulating layer.

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