Shift register for digital filter and method for reading or writing for shift register of digital filter

Abstract

To provide a shift register for a digital filter capable of simultaneously outputting data at a plurality of time points.SOLUTION: The shift register for a digital filter includes: a plurality of RAMs (#1 to #N); a write control unit (110) configured to write one input data item to the same write address of the plurality of RAMs (#1 to #N) and increment the write address each time one data item is written; and a read control unit (120) configured to control the plurality of RAMs so that data are simultaneously read from mutually different addresses.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to shift registers for digital filters. [Background technology]

[0002] A digital filter must simultaneously acquire and process multiple delayed signal data at a given time. A configuration consisting of multiple delay elements is called a shift register. The method described in Patent Document 1 implements the shift register function using RAM within an LSI (Large Scale Integrated Circuit) to reduce the number of flip-flops used within the LSI. Generally, a single RAM has a large capacity and can hold data not only at a given time but also at multiple times, effectively reducing the number of flip-flops used. Storing data in RAM and outputting data from RAM requires write and read control via address specification, and each write and read requires one clock (processing unit time). Therefore, a minimum of two clocks is required from data input to data output. Furthermore, the number of data that can be written and read is limited to one per time. The method described in Patent Document 1 controls the write and read times of input signal data to RAM, delaying the data by a specific time before outputting it. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2001-520429 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the method described in Patent Document 1 is applied to a shift register of a digital filter, only one piece of data can be acquired at one time, and data at multiple times cannot be output simultaneously.

[0005] Therefore, an object of the present disclosure is to provide a shift register of a digital filter that can simultaneously output data at multiple times. [Means for solving the problem]

[0006] The shift register of the digital filter of the present disclosure includes a plurality of RAMs, a write control unit that simultaneously writes one input data item to the same write address of the plurality of RAMs and increments the write address each time one data item is written, and a read control unit that controls the plurality of RAMs so that data is simultaneously read from different addresses. [Effects of the Invention]

[0007] According to the shift register of the digital filter of the present disclosure, data is simultaneously read from different addresses of a plurality of RAMs, so that data at a plurality of times can be simultaneously output. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is an overall configuration diagram of a shift register of the digital filter according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of a write control unit 110. [Figure 3] 10 is a flowchart showing a procedure for setting a write address. [Figure 4] 10 is a flowchart showing a procedure for issuing a write instruction. [Figure 5] FIG. 2 is a diagram showing an example in which input data is stored in RAMs #1 to #N. [Figure 6] FIG. 2 is a diagram showing the configuration of a read control unit 120. [Figure 7] 10 is a flowchart showing a procedure for setting a read address. [Figure 8] 10 is a flowchart showing a procedure for issuing a read instruction. [Figure 9] FIG. 10 is a diagram showing an example in which data stored in RAM#1 to RAM#N is output. [Figure 10] 10 is a timing chart showing an example in which input data is delayed and output; [Figure 11] FIG. 2 is a diagram showing the configuration of a reset control unit 130. [Figure 12] 10 is a flowchart showing a procedure for recording a written address. [Figure 13] 10 is a flowchart showing a procedure for generating an initial value mask signal. [Figure 14] 10 is a flowchart showing a procedure for initial value mask control. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. Embodiment 1 1 is a diagram showing the overall configuration of a shift register of a digital filter according to the first embodiment. The shift register of the digital filter has a configuration capable of simultaneously acquiring input data at multiple times. The shift register of the digital filter includes a storage unit 100, a write control unit 110, a read control unit 120, a reset control unit 130, and an initial value mask control unit 140.

[0010] The storage unit 100 stores and outputs input data. The storage unit 100 includes a first RAM (RAM #1) 102(1), a second RAM (RAM #2) 102(2), and an Nth RAM (RAM #N) 102(N). The write control unit 110 controls the writing of input data to the storage unit 100 . The read control unit 120 controls the reading of data stored in the storage unit 100 .

[0011] The reset control unit 130 executes reset control while the reset is enabled and until data is written to the storage unit 100 .

[0012] The initial value mask control unit 140 outputs an initial value as output data in response to the reset control of the reset control unit 130.

[0013] The storage unit 100 includes RAMs equal to the number of data items that need to be acquired simultaneously. In FIG. 1, the storage unit 100 includes N RAMs, RAM #1 to RAM #N, where N is 3 or greater. Input data is stored in each RAM under the control of the write control unit 110. The data stored in each RAM is output with a required amount of delay added under the control of the read control unit 120. The amount of delay is added by changing the read address of each RAM and the timing of the read instruction.

[0014] Generally, data stored in RAM cannot be immediately initialized by a reset. Therefore, in this embodiment, instead of initializing the data stored in RAM#1 to RAM#N, output data is replaced with an initial value under the control of reset control unit 130 and initial value mask control unit 140. In this way, initialization by reset is realized.

[0015] The write control unit 110 writes one input data item to the same write address in multiple RAMs RAM#1 to RAM#N, and increments the write address each time it writes one data item. If write enable is disabled, the write control unit 110 does not increment the write address and keeps the original value. If reset is enabled, the write control unit 110 returns the write address to its initial value.

[0016] FIG. 2 is a diagram showing the configuration of the write control unit 110. As shown in FIG. The write control unit 110 comprises a write address setting unit 200 and a write instruction unit 210 . The write address setting unit 200 sets write addresses in RAM #1 to RAM #N that store input data.

[0017] FIG. 3 is a flowchart showing the procedure for setting a write address. In step S101, if the reset is valid, the process proceeds to step S102, and if the reset is invalid, the process proceeds to step S103.

[0018] In step S102, the write address setting unit 200 resets the write address to its initial value. This is because when the reset is enabled, the written address recorded in the written address recording unit 400 (described later) is cleared, and therefore the write address controlled by the write control unit 110 is also reset to its initial value to ensure consistency.

[0019] In step S103, if the write enable is enabled, the process proceeds to step S104, whereas if the write enable is disabled, the process proceeds to step S107.

[0020] In step S104, the write address setting section 200 increments the write address in order to write the input data in order from the initial value of the addresses of RAM#1 to RAM#N.

[0021] In step S105, if the write address exceeds the end of the addresses of RAM#1 to RAM#N, the process proceeds to step S106, and if the write address does not exceed the end of the addresses of RAM#1 to RAM#N, the process proceeds to step S107.

[0022] In step S106, the write address setting section 200 resets the write address to the initial value, thereby making it possible to cope with the case where input data is input continuously.

[0023] In step S107, the write address setting unit 200 sets write addresses in RAM# to RAM#N. The same write address is set in the N RAMs, RAM#1 to RAM#N.

[0024] In step S103, if the write enable is disabled, the write address setting unit 200 does not increment the write address but keeps the original value. This allows the shift register function to be realized not only for data that is continuously input, but also for data that is intermittently input together with the write enable.

[0025] The write instruction unit 210 issues a write instruction to store input data in RAM #1 to RAM #N. FIG. 4 is a flowchart showing the procedure for issuing a write instruction. In step S201, if the write enable is valid, the process proceeds to step S202, and if the write enable is invalid, the process proceeds to step S203.

[0026] In step S203, the write instruction unit 210 disables the write instruction for RAM #1 to RAM #N. As a result, the input data is not stored in RAM #1 to RAM #N. The write address setting unit 200 holds the write address when the write enable is disabled. To prevent the stored data at the held address from being overwritten with the input data, the input data is written to RAM #1 to RAM #N only when the write enable is enabled.

[0027] In step S202, the write instruction unit 210 sets the write instructions for RAM #1 to RAM #N to valid, and as a result, the input data is stored in RAM #1 to RAM #N.

[0028] When the write enable is enabled, the write control unit 110 sets a write instruction to be enabled for the same write address in RAM #1 to RAM #N. Since the input data to each RAM is the same, the same input data is stored in all RAM #1 to RAM #N that make up the storage unit 100 at the same time. The input data stored in each RAM is stored without any gaps, even if it is temporally continuous input data. FIG. 5 is a diagram showing an example in which input data is stored in RAM#1 to RAM#N.

[0029] First, the write addresses of RAM#1 to RAM#N are set to the initial value "0", and input data D(nt-7T) is stored in the set write addresses.

[0030] Next, after the time of the clock cycle T has elapsed, the write address of RAM#1 to RAM#N is incremented to "1", and the input data D(nt-6T) is stored in the set write address.

[0031] Furthermore, after the time of the clock cycle T has elapsed, the write addresses of RAM#1 to RAM#N are incremented to "2", and the input data D(nt-5T) is stored in the set write addresses.

[0032] Furthermore, after the time of the clock cycle T has elapsed, the write addresses of RAM#1 to RAM#N are incremented to "3", and the input data D(nt-4T) is stored in the set write addresses.

[0033] When input data D(nT-4T) is input, the data stored in RAM#1 to RAM#N are all the same.

[0034] As shown in FIG. 5, the input data D(nT-7T), D(nT-6T), D(nT-5T), and D(nT-4T) are input consecutively in time, and are all stored without any gaps.

[0035] Even in the case of data that is input intermittently, the write address setting section 200 and the write instruction section 210 allow the input data to be stored in RAM #1 to RAM #N without any loss.

[0036] The read control unit 120 controls so that data is read simultaneously from different addresses in the plurality of RAMs #1 to #N. The read control unit 120 sets the read addresses of the plurality of RAMs #1 to #N to a plurality of consecutive addresses. When read enable is enabled, the read control unit 120 sets read instructions to be enabled for the plurality of RAMs #1 to #N one by one in order at regular intervals. When reset is enabled, the read control unit 120 returns the read addresses of the plurality of RAMs #1 to #N to their initial values.

[0037] FIG. 6 is a diagram showing the configuration of the read control unit 120. As shown in FIG. The read control unit 120 may include a setting unit 300 and an instruction unit 310 . The setting unit 300 sets read addresses of RAM#1 to RAM#N to acquire stored data from RAM#1 to RAM#N that constitute the memory unit 100. The setting unit 300 includes a first read address setting unit 302(1), a second read address setting unit 302(2), ..., an Nth read address setting unit 302(N). The i-th read address setting unit 302(i) sets the read address (i) of RAM#i.

[0038] FIG. 7 is a flowchart showing the procedure for setting a read address. In step S301, if the reset is valid, the process proceeds to step S302, and if the reset is invalid, the process proceeds to step S303.

[0039] In step S302, the ith read address setting unit 302(i) returns the read address (i) to its initial value. For example, the ith read address setting unit 302(i) returns the read address (i) of RAM #i to "0", where i = 1 to N. This is to ensure consistency in the comparison between the written address and the read address performed by the initial value mask signal generating unit 410, which will be described later, when the reset is enabled. If only the written address is returned to its initial value, the comparison with the read address will no longer be performed correctly, so the read address (i) is also returned to its initial value to ensure consistency.

[0040] In step S303, if the read enable is enabled, the process proceeds to step S304, whereas if the read enable is disabled, the process proceeds to step S308.

[0041] In step S304, the first read address setting unit 302(1) increments the read address (1) of RAM#1 to sequentially read the stored data starting from the initial value of the address of RAM#1.

[0042] In step S305, the i-th read address setting unit 302(i) adjusts the read address (i) of RAM#i according to the read address (1) of RAM#1, where i=2 to N.

[0043] For example, the i-th read address setting unit 302(i) subtracts (i-1) from the read address (1) of RAM #1 and sets the address as the read address (i) of RAM #i. For example, if the read address (1) of RAM #1 is "2," the second read address setting unit 302(2) sets the read address (2) of RAM #2 to "1," and the third read address setting unit 302(3) sets the read address (3) of RAM #3 to "0." This results in a difference in output data between RAM #1 to RAM #N. By adjusting the difference in output data and the output timing by the instruction unit 310, it is possible to simultaneously obtain data at multiple times, which is necessary for the shift register function.

[0044] In step S306, if the read address (i) exceeds the end of the addresses in RAM #i, the process proceeds to step S307, and if the read address (i) does not exceed the end of the addresses in RAM #i, the process proceeds to step S308, where i = 1 to N.

[0045] In step S307, the i-th read address setting unit 302(i) resets the read address (i) of RAM#i to its initial value, where i = 1 to N. By resetting the address to its initial value, it is possible to deal with cases where stored data is continuously output.

[0046] In step S308, the i-th read address setting unit 302(i) sets a read address (i) in RAM#i, where i=1 to N.

[0047] In step S303, if the read enable is disabled, the first read address setting unit 302(1) does not increment the read address (1) but keeps the original value. This allows the shift register function to be realized not only for a shift register function that continuously outputs data stored in RAM, but also for a digital filter that processes data intermittently. Since the shift register function can be realized by adjusting the read control, there is no need to increase the number of RAMs.

[0048] The instruction unit 310 issues a read instruction to each RAM constituting the storage unit 100 in order to acquire stored data from each RAM.

[0049] The instruction unit 310 includes a first read instruction unit 312(1), a second read instruction unit 312(2), ..., an Nth read instruction unit 312(N). The ith read instruction unit 312(i) issues a read instruction to output data stored in RAM #i. FIG. 8 is a flowchart showing the procedure for issuing a read instruction.

[0050] In step S401, if the read enable is enabled, the process proceeds to step S402, whereas if the read enable is disabled, the process proceeds to step S405.

[0051] In step S402, the ith read instruction unit 312(i) waits for a delay amount corresponding to RAM#i, where i=2 to N. For example, the ith read instruction unit 312(i) waits for (i-1) clock cycles T. This allows the setting unit 300 to issue a read instruction at a timing corresponding to the read address adjusted. In step S403, if the waiting is completed, the process proceeds to step S404.

[0052] In step S404, the i-th read instruction unit 312(i) sets the read instruction for RAM#i to valid, where i=1 to N.

[0053] In step S405, the ith read instruction unit 312(i) disables the read instruction for RAM #i, where i = 1 to N. This prevents stored data from being read from RAM #i. The setting unit 300 retains the read address even when read enable is disabled. The read instruction is not issued so as not to repeatedly output the stored data at the retained address and affect subsequent circuits.

[0054] FIG. 9 is a diagram showing an example in which data stored in RAM#1 to RAM#N is output. The read control unit 120 reads data stored in RAM #1 to RAM #N. Unlike write control, read control controls each RAM separately. The data stored in each RAM is the same, but the output data read from each RAM at the same time is different due to adjustments to the read address and the timing of the read instruction. Because the output data from each RAM is different, multiple delayed data are output, which functions similarly to a shift register.

[0055] After the clock cycle T has elapsed, the read instruction for RAM #1 becomes valid. After the clock cycle T has elapsed, the read instruction for RAM #2 becomes valid. After the clock cycle T has elapsed, the read instruction for RAM #3 becomes valid.

[0056] After three clock cycles T have elapsed, the read data from RAM#1 is D(nT-5T), the read data from RAM#2 is D(nT-6T), and the read data from RAM#N is D(nT-7T). This provides a continuous delay of three clock cycles and allows output data to be obtained from the three RAMs at the same time. FIG. 10 is a timing chart showing an example in which input data is delayed and output.

[0057] In FIG. 10, for convenience of explanation, the storage unit 100 is assumed to include three RAMs: RAM #1, RAM #2, and RAM #3.

[0058] The write instruction S20 for RAM#1, the write instruction S90 for RAM#2, and the write instruction S160 for RAM#3 are issued at the same timing.

[0059] The write address S30 of RAM#1, the write address S100 of RAM#2, and the write address S170 of RAM#3 are the same at any time.

[0060] On the other hand, continuous delays can be achieved by adjusting the timing of validating the read instruction S60 for RAM #1, the read instruction S130 for RAM #2, and the read instruction S200 for RAM #3. For example, as shown in Figure 10, it is possible to obtain the same output data with continuous delays at the same time.

[0061] By shifting the initial timing at which the RAM#1 read instruction S60, RAM#2 read instruction S130, and RAM#3 read instruction S200 become effective by one clock (T), three pieces of output data with consecutive delays are obtained at the same time from section 5 onwards.

[0062] For example, in section 5, RAM#1 output data S80, RAM#2 output data S150, and RAM#3 output data S220 are D(nT-7T), D(nT-6T), and D(nT-5T), respectively. Continuous delays at the same time can be achieved.

[0063] If the data to be input to the shift register of the digital filter is intermittently input, it is possible to store all of the input data in RAM and then read and process it sequentially. However, this increases the processing time (latency) required to store the input data in RAM. According to this embodiment, after the input data is stored in RAM, the read control unit 120 can immediately obtain the output data, thereby suppressing latency.

[0064] The initial value mask control unit 140 masks the output data of RAM#1 to RAM#N by replacing the output data of RAM#1 to RAM#N with an initial value when reset is enabled.

[0065] When an address of RAM#1 to RAM#N to which no input data has been written is specified as a read address, the initial value mask control unit 140 masks the output data of RAM#1 to RAM#N by replacing the output data of RAM#1 to RAM#N with an initial value. This is because the data stored in the RAM is not initialized by a reset.

[0066] FIG. 11 is a diagram showing the configuration of reset control unit 130. As shown in FIG. The reset control unit 130 includes a written address recording unit 400 and an initial value mask signal generating unit 410 . The written address recording unit 400 records the written addresses set in RAM#1 to RAM#N.

[0067] FIG. 12 is a flowchart showing the procedure for recording written addresses. In step S501, if the reset is valid, the process proceeds to step S504, and if the reset is invalid, the process proceeds to step S502.

[0068] In step S 502 , the written address recording unit 400 acquires a write address from the write control unit 110 .

[0069] In step S503, the written address recording unit 400 records the acquired write address as a written address.

[0070] In step S504, the written address recording unit 400 clears the recorded written addresses, thereby bringing about a state in which input data has not been written even once to RAM#1 to RAM#N.

[0071] The initial value mask signal generation unit 410 acquires the written address from the written address recording unit 400 and also acquires the read address from the read control unit 120, and notifies the initial value mask control unit 140 whether the initial value mask signal is valid or invalid.

[0072] FIG. 13 is a flowchart showing the procedure for generating the initial value mask signal. In step S601, if the reset is valid, the process proceeds to step S606, and if the reset is invalid, the process proceeds to step S602.

[0073] In step S 602 , the initial value mask signal generation unit 410 acquires the written address from the written address recording unit 400 .

[0074] In step S 603 , the initial value mask signal generation unit 410 acquires a read address from the read control unit 120 .

[0075] In step S604, if the read address is included in the written addresses, the process proceeds to step S605, whereas if the read address is not included in the written addresses, the process proceeds to step S606.

[0076] In step S605, the initial value mask signal generation unit 410 sets the initial value mask signal for the initial value mask control unit 140 to invalid.

[0077] In step S606, the initial value mask signal generation unit 410 sets the initial value mask signal to valid. The initial value mask signal becomes valid when input data has not been written to RAM#1 to RAM#N and a location where an undefined value or a value before reset is stored is specified as the read address. Furthermore, when reset is valid, the initial value mask signal becomes valid regardless of the written address and read address.

[0078] The initial value mask control unit 140 switches between replacing the output data of RAM#1 to RAM#N with an initial value and masking it, or outputting the output data of RAM#1 to RAM#N as is, based on the state of the initial value mask signal generated by the reset control unit 130. When the initial value mask signal is valid, the initial value mask control unit 140 masks the output data of RAM#1 to RAM#N with the initial value.

[0079] FIG. 14 is a flowchart showing the procedure for initial value mask control. In step S701, if the initial value mask signal is valid, the process proceeds to step S703, and if the initial value mask signal is invalid, the process proceeds to step S702.

[0080] In step S703, the initial value mask control unit 140 outputs the value designated as the initial value as the output delay data of RAM#1 to RAM#N.

[0081] In step S702, the initial value mask control unit 140 outputs the data of RAM#1 to RAN#N as output delay data.

[0082] To initialize the data stored in RAM#1 to RAM#N by resetting, all of the data stored in RAM#1 to RAM#N must be written (overwritten) with initial values, which takes a considerable amount of time. In this embodiment, an initial value mask signal is used to mask the output data of RAM#1 to RAM#N with an initial value, thereby achieving a function equivalent to a reset. The time required for this process is only the time required to compare the written address with the read address and to generate the initial value mask signal, so in this embodiment, the reset function can be achieved in a short time.

[0083] In a system in which RAM is implemented, immediately after startup, the RAM is not initialized and an undefined value is stored as stored data. If a read instruction is given to the RAM in this state, an undefined value may be output, which may result in malfunction. In this embodiment, since the written address is not recorded until input data is written to RAM #1 to RAM #N, the initial value mask signal is valid regardless of which read address is the target of a read instruction. As a result, even if an undefined value is output from RAM #1 to RAM #N, the initial value mask control unit 140 replaces the undefined value with an initial value, so the undefined value is not processed.

[0084] According to this embodiment, output data to which successive delay amounts have been added can be acquired simultaneously at the same time, as shown in the operation example of the timing chart in Fig. 10. Therefore, successively input data can be processed successively.

[0085] Even when data is input intermittently rather than continuously, the shift register function can be realized without changing the number of RAMs by adjusting the read address using the setting unit 300. Also, when input data is intermittent but data is output continuously, the shift register function can be realized without changing the number of RAMs.

[0086] When continuously input data is thinned out and processed intermittently, this can be achieved by adjusting the read address using the setting unit 300. Also, since there only need to be RAM#1 to RAM#N for the number of data that need to be acquired simultaneously at the same time, RAM can be used efficiently.

[0087] If a configuration is used in which the output data of a RAM is input to a subsequent RAM, one clock (processing unit time) is required for each write and read, making it impossible to impart a continuous delay amount. To impart a continuous delay amount, for example, two or more similar configurations must be used, increasing the number of RAMs used. The configuration of this embodiment makes it possible to impart a continuous delay amount as output data, thereby reducing the number of RAMs used.

[0088] When input data is input intermittently, it is possible to temporarily store the input data in RAM and then sequentially read it to perform data acquisition processing, but this increases the latency until the data acquisition processing starts.In this embodiment, the data acquisition processing can be performed immediately after the input data is input, so the latency can be reduced.

[0089] The output data of the RAM can be immediately set to the initial value when the reset is enabled by the initial value masking process of the output data of the RAM by the reset control unit 130 and the initial value mask control unit 140. When input data needs to be processed immediately after initialization by reset, if the reset takes time, a period of time will occur during which processing cannot be performed. However, in this embodiment, initialization is performed immediately, so processing can be performed continuously.

[0090] If a read command is issued to the RAM immediately after startup while an undefined value is stored in the RAM, the undefined value may be output, which may result in malfunction. In this embodiment, even if an undefined value is output, the reset control unit 130 and the initial value mask control unit 140 replace the output with an initial value and mask it, so that the undefined value is not processed and malfunction can be prevented.

[0091] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0092] 100 memory unit, 110 write control unit, 120 read control unit, 130 reset control unit, 140 initial value mask control unit, 200 write address setting unit, 210 write instruction unit, 300 setting unit, 302(1) first read address setting unit, 302(2) second read address setting unit, 302(N) Nth read address setting unit, 310 instruction unit, 312(1) first read instruction unit, 312(2) second read instruction unit, 312(N) Nth read instruction unit, 400 written address recording unit, 410 initial value mask signal generation unit.

Claims

1. A plurality of RAMs; a write control unit that simultaneously writes one input data item to the same write address of the plurality of RAMs and increments the write address each time the one data item is written; a read control unit that sets a certain read address among a plurality of read addresses respectively corresponding to the plurality of RAMs as a reference address and sets other read addresses based on a relative relationship with the reference address, thereby controlling so that data is simultaneously read from different addresses of the plurality of RAMs; Digital filter shift register.

2. the read control unit increases the number of RAMs to which read instructions are to be issued in stages over time, among the plurality of RAMs; 2. The shift register of the digital filter according to claim 1.

3. When the data is not input, the write enable signal is invalid. The light control unit If the write enable signal is invalid, the write address is not incremented but is maintained at its original value; When the write enable signal becomes valid next time, the write address is incremented and the data is written to the plurality of RAMs.

3. A shift register for a digital filter according to claim 1.

4. the read control unit resets the read address to an initial value when the read address exceeds a maximum address in the address areas of the plurality of RAMs; 4. The shift register of the digital filter according to claim 1.

5. the write control unit resets the write address to an initial value when the write address exceeds a maximum address in the address areas of the plurality of RAMs; 5. A shift register for a digital filter according to claim 1.

6. the write control unit includes a write instruction unit that determines the timing at which a write should be performed based on a write enable signal; 6. A shift register for a digital filter according to claim 1.

7. the read control unit holds the read address when the read enable signal is invalid and does not issue a read instruction; 7. A shift register for a digital filter according to claim 1.

8. One input data is simultaneously written to the same write address of a plurality of RAMs, and the write address is incremented each time the one data is written; Among a plurality of read addresses corresponding to the plurality of RAMs, one read address is set as a reference address, and other read addresses are set based on a relative relationship with the reference address, thereby simultaneously reading data from different addresses of the plurality of RAMs. A method for reading and writing a shift register in a digital filter.

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