Processing system

Abstract

To appropriately reduce the cost and time required for a chip-on-wafer manufacturing process.SOLUTION: A processing system for processing chips comprises a chip placement device that picks up chips and arranges them on a suction surface of a first electrostatic carrier. The chip placement device includes: a placement carrier holding section that holds the first electrostatic carrier; control terminals disposed on the suction surface side for independently controlling a holding state of each of the plurality of chips on the suction surface; and a power supply section that applies a voltage to the first electrostatic carrier held by the placement carrier holding section from a side opposite to the suction surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to processing systems. [Background technology]

[0002] Patent Document 1 discloses a chip-on-wafer (CoW) bonding method for mounting chips on a wafer. In this chip-on-wafer bonding method, before multiple chips are bonded to corresponding bonding portions of a substrate, the bonding surfaces of the chips are subjected to surface activation treatment and hydrophilization treatment, and the multiple chips are temporarily bonded to the substrate with water interposed therebetween. Note that the water interposed on the bonding surfaces is removed all at once by heating during the actual bonding.

[0003] Patent Document 2 discloses a reinforcing material for a thin plate material such as a silicon wafer. This reinforcing material has a reinforcing material body equipped with a thin plate-shaped electrostatic holding portion having an electrode portion embedded inside an electrical insulating layer. By applying a high voltage to the electrode portion and supplying an electric charge of the opposite polarity to the voltage applied to the electrode portion to the object to be reinforced, the electrostatic holding portion exerts an adhesive force to attract the object to be reinforced, causing the reinforcing material body to function as a reinforcing material. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6337400 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-099674 Summary of the Invention [Problem to be solved by the invention]

[0005] The techniques of the present disclosure significantly reduce the cost and time required for the chip-on-wafer manufacturing process. [Means for solving the problem]

[0006] One aspect of the present disclosure is a processing system for processing chips, comprising a chip placement device that picks up the chips and places them in a row on an adsorption surface of a first electrostatic carrier, the chip placement device comprising: a placement carrier holding unit that holds the first electrostatic carrier; a control terminal that is placed on the adsorption surface side and that independently controls the holding state of each of the multiple chips on the adsorption surface; and a power supply unit that applies voltage to the first electrostatic carrier held by the placement carrier holding unit from the side opposite the adsorption surface. [Effects of the Invention]

[0007] According to the present disclosure, the cost and time required for the chip-on-wafer manufacturing process can be appropriately reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is an explanatory diagram showing an outline of the configuration of a chip attached to a dicing sheet. [Figure 2] 1 is a cross-sectional view showing an outline of the configuration of an electrostatic carrier according to the present embodiment. [Figure 3] 1 is a cross-sectional view showing an outline of the configuration of a wafer to which a chip is bonded. [Figure 4] 1 is a plan view showing an outline of the configuration of a processing system according to an embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view showing an outline of the configuration of a chip placement device. [Figure 6] FIG. 2 is a cross-sectional view showing an outline of the configuration of a transfer device. [Figure 7] FIG. 2 is a cross-sectional view showing an outline of the configuration of a joining device. [Figure 8] FIG. 1 is a flow chart showing main steps of a chip-on-wafer manufacturing process according to the present embodiment. [Figure 9] 1A to 1C are explanatory side views showing some steps in the chip-on-wafer manufacturing process according to the present embodiment. [Figure 10] 1A to 1C are explanatory side views showing some steps in the chip-on-wafer manufacturing process according to the present embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing an outline of the configuration of an electrostatic carrier according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] In recent years, in the manufacturing process of semiconductor devices, in response to demands for even higher performance and higher density of devices, the chip-on-wafer (CoW) manufacturing process has been studied as a method of three-dimensional packaging technology. Chip-on-wafer manufacturing is carried out, for example, by the method described in Patent Document 1.

[0010] However, in this chip-on-wafer manufacturing process, prior to actual mounting of semiconductor chips (hereinafter referred to as "chips") on a semiconductor substrate (hereinafter referred to as "wafer"), it is necessary to temporarily position each of the multiple chips on the wafer. As disclosed in Patent Document 1, this temporary positioning of the chips requires a series of processes, including surface activation and hydrophilization of the bonding surface, for each of the multiple chips, which leaves room for improvement in terms of cost and man-hours.

[0011] As a result of intensive research, the inventors have found that the application of an electrostatic holding mechanism may enable a significant reduction in the cost and man-hours required for the chip-on-wafer manufacturing process. Specifically, instead of temporarily bonding multiple chips onto a wafer in the chip-on-wafer manufacturing process, a carrier substrate (hereinafter referred to as an "electrostatic carrier (ESW)") with an attraction and holding function using electrostatic (Coulomb) force is used, and the multiple chips are held onto the electrostatic carrier by electrostatic attraction. Patent Document 2 discloses an electrostatic reinforcing device that holds and reinforces thin plate materials such as silicon wafers, but does not describe holding multiple chips on a carrier wafer by electrostatic adsorption in this manner and then actually mounting the chips on a wafer to be mounted.

[0012] The technology disclosed herein has been developed in consideration of the above circumstances, and appropriately reduces the cost and time required for the chip-on-wafer manufacturing process. Hereinafter, a processing system and a processing method according to the present embodiment will be described with reference to the drawings. Note that in this specification and the drawings, elements having substantially the same functional configuration are designated by the same reference numerals, and redundant description will be omitted.

[0013] In a processing system 10 according to this embodiment, which will be described later, a plurality of chips C that are aligned and attached to the adhesive surface of a dicing tape T, which will be described later, are placed on an electrostatic carrier Cw, which will be described later, and the plurality of chips C on the electrostatic carrier Cw are then bonded to a wafer W to be mounted (chip-on-wafer manufacturing process). Hereinafter, the surface of each of the plurality of chips C on which a device layer D, which will be described later, is formed is referred to as the front surface Ca, and the surface that is attached to the dicing tape T, opposite the front surface Ca, is referred to as the back surface Cb.

[0014] As shown in FIG. 1, a silicon layer Si is formed on the back surface Cb side of the chip C, and a device layer D including a plurality of devices is formed on the silicon layer Si. The back surface Cb side of the chip C is then attached to the dicing tape T as described above. In other words, the device layer D of the chip C is attached to the dicing tape T via the silicon layer Si. In addition, a protective film (not shown) is formed on the front surface Ca side of the chip C to protect the device layer D in a series of chip-on-wafer manufacturing processes described below. The dicing tape T is fixed to a dicing frame F as shown in FIG. 1 when being transported in a processing system 10 described later.

[0015] The electrostatic carrier Cw has an upper surface that serves as an adsorption surface for electrostatically adsorbing and holding multiple chips C. As shown in Fig. 2, the electrostatic carrier Cw includes, inside an electrically insulating main body 1, multiple adsorption electrodes 2, adsorption control terminals 3 for controlling the adsorption and holding of the chips C by the adsorption electrodes 2, and a capacitor 4 for storing electric charge by applying a DC voltage.

[0016] The main body 1 has a disk shape that is substantially the same as the wafer W on which the chips C are mounted, and is made of an electrically insulating material such as ceramic as described above.

[0017] Each chucking electrode 2 is configured to have a size corresponding to one chip C to be held. The chucking electrodes 2 are arranged side by side inside the main body 1 so as to correspond, in plan view, to the bonding positions of the chips C (mounting positions of the chips C) on the mounting surface of the chips C of the wafer W within the chucking surface of the electrostatic carrier Cw.

[0018] The suction control terminal 3 is disposed inside the main body 1 on the suction surface side of the chip C. The suction control terminal 3 is electrically connected to each of the plurality of suction electrodes 2 inside the main body 1, as shown in FIG. The suction control terminal 3 is configured to be able to communicate with the chip placement device 60, transfer device 100, bonding device 140, or control device 150 of the processing system 10, which will be described later, and is configured to be able to apply an suction voltage independently to each of the multiple suction electrodes 2 based on signals received from these devices. In the electrostatic carrier Cw, the chip C can be attracted and held on the suction surface by Coulomb force generated by applying a voltage to the suction electrode 2 via the suction control terminal 3 in this manner.

[0019] The capacitor 4 as a power storage member accumulates electric charge therein by applying voltage from the chip placement device 60, the transfer device 100, or the bonding device 140 of the processing system 10, which will be described later. The electric charge accumulated in the capacitor 4 is discharged toward each of the attraction electrodes 2 via the above-mentioned attraction control terminals 3, and is used to attract and hold or peel the chips C on the electrostatic carrier Cw.

[0020] The wafer W on which the chip C is mounted is a semiconductor wafer such as a silicon substrate or a glass substrate used in the manufacturing process of semiconductor devices, and as shown in Figure 3, a device layer Dw containing multiple devices is formed on the surface Wa side, which is the mounting surface of the chip C. The device layer Dw is diced into pieces having substantially the same size as the chips C to be mounted, as shown in Fig. 3. In other words, each of the diced device layers Dw on the mounting surface of the wafer W becomes a bonding position of the chip C on the wafer W (a mounting position of the chip C). A protective film Pw is formed on the front surface Wa of the wafer W, and the thickness of the protective film Pw is approximately the same as the thickness of the device layer Dw. In other words, on the front surface Wa of the wafer W, there are formed portions where the diced device layers Dw are exposed and portions where the protective film Pw is exposed between the device layers Dw.

[0021] The wafer W is bonded to the chip C in a bonding device 140 of the processing system 10, which will be described later, and various pre-processing steps for bonding are performed on the front surface Wa of the wafer W before it is loaded into the bonding device 140. More specifically, the front surface Wa of the wafer W loaded into the processing system 10 has been previously subjected to a series of pre-processing steps including surface activation and hydrophilization in one or more pre-processing devices disposed outside the processing system 10.

[0022] 4, the processing system 10 has a configuration in which a load / unload station 11 and a processing station 12 are integrally connected. In the load / unload station 11, for example, FOUPs Ff and Fw, each capable of accommodating a plurality of dicing frames F and a plurality of wafers W, and a FOUP Fc, each capable of accommodating a first electrostatic carrier Cw1 and a second electrostatic carrier Cw2, are loaded and unloaded, respectively, between the outside and the processing station 11. The processing station 12 is equipped with various processing devices for implementing a series of chip-on-wafer manufacturing processes, which will be described later.

[0023] The loading / unloading station 11 is provided with a FOUP mounting table 20. In the illustrated example, a plurality of FOUPs, for example, three FOUPs Ff, Fw, and Fc, are placed on the FOUP mounting table 20, aligned in a line in the Y-axis direction. Note that the number and arrangement of FOUPs Ff, Fw, and Fc placed on the FOUP mounting table 20 are not limited to those in this embodiment and can be determined arbitrarily.

[0024] A transfer device 30 is provided adjacent to the FOUP mounting table 20 on the positive side of the X-axis. The transfer device 30 is configured to be movable on a transfer path 31 extending in the Y-axis direction. The transfer device 30 also has, for example, two transfer arms 32, 32 that hold and transfer a dicing frame F, a wafer W, and an electrostatic carrier Cw (hereinafter, these may be collectively referred to as the "dicing frame F, etc."). Each transfer arm 32 is configured to be movable horizontally, vertically, around a horizontal axis, and around a vertical axis. Note that the configuration of the transfer arm 32 is not limited to this embodiment and may have any configuration. The transfer device 30 is also configured to be able to transfer the dicing frame F, etc. to the FOUPs Ff, Fw, and Fc on the FOUP mounting table 20 and to a transition device 40, which will be described later.

[0025] In the carry-in / out station 11, a transition device 40 for transferring the dicing frame F and the like to and from the processing station 12 is provided adjacent to the transfer device 30 on the positive side of the X-axis of the transfer device 30.

[0026] The processing station 12 is provided with a transport device 50, a chip placement device 60, a protective film forming device 70, a processing device 80, a protective film removing device 90, a transfer device 100, a second protective film forming device 110, a planarization device 120, a second protective film removing device 130, and a bonding device 140. The number and arrangement of these various processing devices are not limited to those in this embodiment, and can be determined as desired.

[0027] The transfer device 50 is provided on the positive side of the transition device 40 in the X-axis direction. The transfer device 50 is configured to be movable on a transfer path 51 extending in the X-axis direction. The transfer device 50 also has, for example, two transfer arms 52, 52 that hold and transfer a dicing frame F or the like. Each transfer arm 52 is configured to be movable horizontally, vertically, around a horizontal axis, and around a vertical axis, and is configured to be able to transfer a dicing frame F or the like to the transition device 40 in the carry-in / out station 11 and various processing devices in the processing station 12.

[0028] In the chip placement device 60, a plurality of chips C attached to a dicing tape T are arranged on the attraction surface of a first electrostatic carrier Cw1, which serves as a relay member when mounting the chips C on a wafer W.

[0029] As shown in Fig. 5, a pickup area 60a, an arrange area 60b, and a delivery area 60c are formed inside the chip placement device 60. In the pickup area 60a, the chip C is picked up from the dicing frame F. In the arrange area 60b, the chip C is placed on the first electrostatic carrier Cw1. In the delivery area 60c, the chip C is delivered between the pickup area 60a and the arrange area 60b.

[0030] In the pickup area 60a, a first holding portion 61, a push-up portion 62, and a first collet 63 are provided.

[0031] The first holding part 61 has a holding surface for the dicing frame F on its upper surface, and holds the dicing frame F transported by the transport device 50 with the multiple chips C attached to the dicing tape T facing upward.

[0032] The push-up portion 62 is disposed below the first holding portion 61, and selectively pushes up one chip C from among the plurality of chips C on the dicing tape T from below to raise it up.

[0033] The first collet 63 is disposed above the first holding part 61, holds from above one chip C pushed up by the push-up part 62, and transports the held chip C between the pickup area 60a and the delivery area 60c. In one example, the first collet 63 is configured to be rotatable around a horizontal axis, and can invert the top and bottom surfaces of the held chip C as shown in the figure.

[0034] In the arrangement area 60b, a second holding unit 64, a second collet 65, a power supply unit 66, a communication unit 67, and an alignment mechanism 68 are provided.

[0035] The second holding part 64 as a carrier holding part for placement has a holding surface for the first electrostatic carrier Cw1 on its upper surface, and holds the first electrostatic carrier Cw1 transported by the transport device 50 with the adsorption surface of the chip C facing upward.

[0036] The second collet 65 is disposed above the second holding part 64, holds the chip C held by the first collet 63 from above, and transports the held chip C between the arrangement area 60b and the delivery area 60c.

[0037] In one example, the power supply unit 66 is disposed inside the second holder 64, and applies a voltage to the first electrostatic carrier Cw1 on the second holder 64. In the chip placement device 60, the chip C is attracted and held on the attracting surface of the first electrostatic carrier Cw1 by the Coulomb force generated thereby. The location of the power supply unit 66 is not limited to this, and it may be located outside the second holding unit 64 as long as it can apply an appropriate voltage to the first electrostatic carriers Cw1.

[0038] The communication unit 67 communicates with the attraction control terminal 3 provided inside the first electrostatic carrier Cw1 and transmits a hold control signal for the chip C to the first electrostatic carrier Cw1. The attraction control terminal 3 applies a voltage from the power supply unit 66 to each of the plurality of attraction electrodes 2 independently based on the received hold control signal, thereby independently controlling the hold state of each of the plurality of chips C on the attraction surface. Note that communication between the communication unit 67 and the attraction control terminal 3 may be performed by wire or wirelessly.

[0039] The alignment mechanism 68 aligns the first electrostatic carrier Cw1 held by the second holder 64 with the chip C held by the second collet 65. More specifically, it aligns one chip C held by the second collet 65 with the chucking and holding position of the chip C on the chucking surface of the first electrostatic carrier Cw1, i.e., the position corresponding to the chucking electrode 2 within the chucking surface of the first electrostatic carrier Cw1. The alignment mechanism 68 can also detect whether the chip C is properly positioned on the attraction surface of the first electrostatic carrier Cw1. More specifically, the alignment mechanism 68 can align the position of the chip C actually positioned on the attraction surface of the first electrostatic carrier Cw1 with the position corresponding to the attraction electrode 2 on the attraction surface of the first electrostatic carrier Cw1. The alignment mechanism 68 may include, for example, a camera, a sensor, or the like.

[0040] In the protective film forming device 70, a protective film P1 (first protective film) is formed on the attracting surface side of the first electrostatic carrier Cw1 after the arrangement of the plurality of chips C. The protective film forming device 70 may have any configuration.

[0041] The processing device 80 grinds the back surface Cb of the chip C on the attraction surface of the first electrostatic carrier Cw1, more specifically, the silicon layer Si, to thin the silicon layer Si and flatten the back surface Cb. The configuration of the processing device 80 is arbitrary.

[0042] The protective film removing device 90 removes the protective film P1 remaining on the attracting surface side of the first electrostatic carrier Cw1 after the grinding process in the processing device 80. The protective film removing device 90 may have any configuration.

[0043] In the transfer device 100, the chip C, whose front surface Ca side is adsorbed and held by the first electrostatic carrier Cw1, is transferred (transferred) so that the back surface Cb side is adsorbed and held by the second electrostatic carrier Cw2, thereby inverting the front and back surfaces of the chip C.

[0044] As shown in FIG. 6, the transfer device 100 includes a holding unit 101, a transport unit 102, an alignment mechanism 103, a first power supply unit 104, a second power supply unit 105, and a communication unit .

[0045] The holding unit 101, which serves as the first transfer carrier holding unit, has a holding surface for the first electrostatic carrier Cw1 on its upper surface, and holds the first electrostatic carrier Cw1 transported by the transport device 50 with the multiple chips C adsorbed and held on the adsorption surface facing upward.

[0046] The transport unit 102, which serves as a second transfer carrier holding unit, has the holding surface of the second electrostatic carrier Cw2 on its lower surface, and holds the second electrostatic carrier Cw2 transported by the transport device 50 with the adsorption surface of the chip C facing downward. In one example, the transport unit 102 is configured to be rotatable around a horizontal axis, and can invert the top and bottom surfaces of the adsorbed and held chips C.

[0047] The alignment mechanism 103 aligns the first electrostatic carrier Cw1 held by the holder 101 with the second electrostatic carrier Cw2 held by the transport unit 102. More specifically, it aligns the multiple chips C held by the first electrostatic carrier Cw1 with the suction-holding positions of the chips C on the suction surface of the second electrostatic carrier Cw2, i.e., the positions corresponding to the suction electrodes 2 within the suction surface of the second electrostatic carrier Cw2. The alignment mechanism 103 may include, for example, a camera, a sensor, etc.

[0048] In one example, the first power supply unit 104 is disposed inside the holder 101 and applies a negative voltage to the first electrostatic carrier Cw1 on the holder 101. In the transfer device 100, by applying a negative voltage to the adsorption electrode 2 of the first electrostatic carrier Cw1 in this manner, the chip C on the adsorption surface is detached from the first electrostatic carrier Cw1. The location of the first power supply unit 104 is not limited to this, and it may be located outside the holding unit 101 as long as it can apply an appropriate voltage to the first electrostatic carrier Cw1.

[0049] In one example, the second power supply unit 105 is disposed inside the transport unit 102 and applies a voltage to the second electrostatic carrier Cw2 on the transport unit 102. In the transfer device 100, the Coulomb force generated thereby attracts and holds the chip C onto the attraction surface of the second electrostatic carrier Cw2. The location of the second power supply unit 105 is not limited to this, and it may be located outside the transport unit 102 as long as it can apply an appropriate voltage to the second electrostatic carriers Cw2.

[0050] The communication unit 106 communicates with the attraction control terminals 3 arranged inside the first electrostatic carrier Cw1 and the second electrostatic carrier Cw2, and transmits hold control signals for the chips C to these electrostatic carriers Cw. In the first electrostatic carrier Cw1, a negative voltage from the first power supply unit 104 is applied to the plurality of attraction electrodes 2 in a batch based on the hold control signal received by the attraction control terminal 3, thereby controlling the hold state of the plurality of chips C on the attraction surface. In the second electrostatic carrier Cw2, a voltage from the second power supply unit 105 is applied to the plurality of attraction electrodes 2 in a batch based on the hold control signal received by the attraction control terminal 3, thereby controlling the hold state of the plurality of chips C on the attraction surface. Note that communication between the communication unit 106 and the attraction control terminal 3 may be performed by wire or wirelessly.

[0051] 2, the first electrostatic carrier Cw1 and the second electrostatic carrier Cw2 each have a plurality of attraction electrodes 2 arranged in correspondence with the bonding positions of the chips C (mounting positions of the chips C) on the mounting surface of the chips C of the wafer W. In other words, the first electrostatic carrier Cw1 and the second electrostatic carrier Cw2 each have a plurality of attraction electrodes 2 arranged in the same arrangement. Therefore, the transfer device 100 can transfer a plurality of chips C held by the first electrostatic carrier Cw1 to the second electrostatic carrier Cw2 all at once. As described above, the transfer device 100 can transfer multiple chips C all at once. However, if, for example, it is desired to transfer only some of the chips C, or if it is not desired to transfer only some of the chips C, the application of voltage to each of the multiple suction electrodes 2 can be independently controlled by the suction control terminal 3, thereby independently controlling the holding state of each of the multiple chips C on the suction surface.

[0052] In the illustrated example, the first power supply unit 104 that applies a voltage to the first electrostatic carriers Cw1 and the second power supply unit 105 that applies a voltage to the second electrostatic carriers Cw2 are arranged independently, but if a single power supply unit can appropriately apply a voltage to both the first electrostatic carriers Cw1 and the second electrostatic carriers Cw2, the single power supply unit may control the application of voltage to both the first electrostatic carriers Cw1 and the second electrostatic carriers Cw2.

[0053] In addition, in the illustrated example, the holding unit 101 holds the first electrostatic carrier Cw1 and the transport unit 102 holds the second electrostatic carrier Cw2, but it is also possible to have the holding unit 101 hold the second electrostatic carrier Cw2 and the transport unit 102 hold the first electrostatic carrier Cw1.

[0054] Furthermore, although the holding unit 101 is fixedly disposed on the bottom side of the transfer device 100 in the illustrated example, the holding unit 101 may also be fixedly disposed on the top side of the transfer device 100. In other words, in the transfer device 100, the holding unit 101 may hold the first electrostatic carrier Cw1 with the multiple chips C attracted and held on the attraction surface facing downward, and further, the transport unit 102 may hold the second electrostatic carrier Cw2 with the attracting surface of the chips C facing upward.

[0055] The second protective film forming device 110 forms a protective film P2 (second protective film) on the attracting surface side of the second electrostatic carrier Cw2 that attracts and holds the plurality of chips C. The protective film P2 (second protective film) is used to prevent contamination of the attracting surface of the second electrostatic carrier Cw2 in a later process. The second protective film forming device 110 may have any configuration.

[0056] In this embodiment, the protective film forming apparatus 70 for forming the protective film P1 and the second protective film forming apparatus 110 for forming the protective film P2 are arranged independently, but the protective film P1 and the protective film P2 may be formed in the same apparatus. That is, in the processing system 10, the configuration of either the protective film forming apparatus 70 or the second protective film forming apparatus 110 may be omitted.

[0057] In the planarization device 120, the surface Ca of the chip C, which is the surface to be bonded to the wafer W in a subsequent process, is planarized, and the protective film (not shown) formed on the surface Ca side is removed. The planarization device 120 may have any configuration.

[0058] The second protective film removing device 130 removes the protective film P2 remaining on the attracting surface side of the second electrostatic carrier Cw2 after the planarization process in the planarizing device 120. The second protective film removing device 130 may have any configuration.

[0059] In this embodiment, the protective film removal device 90 for removing the protective film P1 and the second protective film removal device 130 for removing the protective film P2 are arranged independently, but the protective film P1 and the protective film P2 may be removed in the same device. That is, in the processing system 10, the configuration of either the protective film removal device 90 or the second protective film removal device 130 may be omitted.

[0060] In the bonding device 140, the plurality of chips C attracted and held by the second electrostatic carriers Cw2 are bonded to bonding positions on the mounting surface of the wafer W on which the chips C are to be mounted.

[0061] As shown in FIG. 7, the bonding device 140 includes a holding unit 141, a transport unit 142, an alignment mechanism 143, a power supply unit 144, and a communication unit 145.

[0062] The holding portion 141, which serves as a bonding carrier holding portion, has a holding surface for the second electrostatic carrier Cw2 on its upper surface, and holds the second electrostatic carrier Cw2 transported by the transport device 50 with the multiple chips C adsorbed and held on the adsorption surface facing upward.

[0063] The transfer unit 142 as a substrate holder has a holding surface for a wafer W on which chips C are to be mounted on the underside, and holds the wafer W transferred by the transfer device 50 with the mounting surface for chips C facing downward. In one example, the transfer unit 142 is configured to be rotatable around a horizontal axis, and can invert the top and bottom surfaces of the held wafer W.

[0064] The alignment mechanism 143 aligns the second electrostatic carrier Cw2 held by the holder 141 with the wafer W held by the transport unit 142. More specifically, it aligns the multiple chips C attracted and held by the second electrostatic carrier Cw2 with the bonding positions of the chips C on the mounting surface of the wafer W, i.e., with positions corresponding to the diced device layers Dw on the surface Wa of the wafer W. The alignment mechanism 143 may include, for example, a camera, a sensor, etc.

[0065] In one example, the power supply unit 144 is disposed inside the holder 141 and applies a negative voltage to the second electrostatic carrier Cw2 on the holder 141. In the bonding device 140, by applying a negative voltage to the attraction electrode 2 of the second electrostatic carrier Cw2 in this manner, the chip C on the attraction surface is detached from the second electrostatic carrier Cw2. The location of the power supply unit 144 is not limited to this, and it may be located outside the holding unit 141 as long as it can apply an appropriate voltage to the second electrostatic carriers Cw2.

[0066] The communication unit 145 communicates with the attraction control terminal 3 arranged inside the second electrostatic carrier Cw2 and transmits a hold control signal for the chip C to the second electrostatic carrier Cw2. The attraction control terminal 3 applies a voltage from the power supply unit 144 to each of the plurality of attraction electrodes 2 independently based on the received hold control signal, thereby independently controlling the hold state of each of the plurality of chips C on the attraction surface. Note that communication between the communication unit 145 and the attraction control terminal 3 may be performed by wire or wirelessly.

[0067] In the illustrated example, the second electrostatic carrier Cw2 is held by the holder 141 and the wafer W is held by the transport unit 142, but the wafer W may be held by the holder 141 and the second electrostatic carrier Cw2 may be held by the transport unit 142. In this case, the power supply unit 144 may be disposed inside the transport unit 142.

[0068] Furthermore, in the illustrated example, the holder 141 is fixed to the bottom surface of the bonding device 140, but the holder 141 may be fixed to the top surface of the bonding device 140. In other words, in the bonding device 140, the holder 141 may hold the second electrostatic carriers Cw2 with the plurality of chips C attracted and held on the attraction surface facing downward, and further, the transport unit 142 may hold the wafer W with the mounting surfaces of the chips C facing upward.

[0069] The processing system 10 described above is provided with a control device 150. The control device 150 is, for example, a computer equipped with a CPU, a memory, etc., and has a program storage unit (not shown). The program storage unit stores a program for controlling the chip-on-wafer manufacturing process in the processing system 10. Note that the program may be recorded on a computer-readable storage medium H and installed into the control device 150 from the storage medium H. Furthermore, the storage medium H may be temporary or non-temporary.

[0070] Next, a chip-on-wafer manufacturing process performed in the processing system 10 configured as described above will be described. Fig. 8 is a flow chart showing the main steps of the chip-on-wafer manufacturing process. Figs. 9 and 10 are explanatory side views schematically showing some steps of the chip-on-wafer manufacturing process.

[0071] First, FOUPs Ff and Fw, each containing a plurality of dicing frames F and wafers W, and FOUP Fc, containing first electrostatic carriers Cw1 and second electrostatic carriers Cw2, are placed on the FOUP placement table 20 of the carry-in / out station 11. 9(a), a dicing tape T with multiple chips C attached thereto is fixed to a dicing frame F housed in a hoop Ff. The multiple chips C have their back surfaces Cb attached to the dicing tape T. Moreover, the front surface Wa of the wafer W accommodated in the FOUP Fw has been subjected to pretreatment for bonding with the chip C described above.

[0072] Next, the transfer device 30 removes the dicing frame F from the FOUP Ff and transfers it to the transition device 40. The dicing frame F transferred to the transition device 40 is then transferred to the chip placement device 60 by the transfer device 50. Simultaneously with this, or subsequently, the first electrostatic carrier Cw1 from the FOUP Fc is transferred to the chip placement device 60.

[0073] In the chip placement device 60, the chip C, whose back surface Cb is attached to the adhesive surface of the dicing tape T, is placed in a position corresponding to the adsorption electrode 2 on the adsorption surface of the first electrostatic carrier Cw1 so that the back surface Cb is facing up, as shown in Figure 9(b), and is adsorbed and held (step St1 in Figure 8). An example of the operation of placing the chip C on the first electrostatic carrier Cw1 in the chip placement device 60 will be described below.

[0074] First, one chip C is selectively pushed up from below (the rear surface Cb side) using the push-up portion 62 from among a plurality of chips C attached to the dicing tape T, and is raised. Next, the surface Ca of the pushed-up chip C is held from above by the first collet 63. Next, the first collet 63 is rotated around the horizontal axis, thereby inverting the front and back surfaces of the chip C. In other words, the first collet 63 is placed in a state in which the chip C faces upward. Next, the back surface Cb of the chip C held by the first collet 63 is held from above by the second collet 65, and further, the hold of the front surface Ca side of the chip C by the first collet 63 is released. In other words, the chip C is transferred from the first collet 63 to the second collet 65. Next, the second collet 65 holding the chip C is moved to a position on the attraction surface of the first electrostatic carrier Cw1 corresponding to one of the attraction electrodes 2. The alignment between the second collet 65 and the attraction electrode 2 is appropriately performed using an alignment mechanism 68. Next, a voltage is applied from the power supply unit 66 to one of the adsorption electrodes 2 via the adsorption control terminal 3, and the generated Coulomb force adsorbs and holds the chip C on the adsorption surface of the first electrostatic carrier Cw1. After that, the second collet 65 releases the back surface Cb side of the chip C. Finally, an alignment mechanism 68 is used to detect whether or not the chip C has been properly placed on one of the adsorption electrodes 2. If it is determined as a result of the detection that the chip C has been properly placed, the operation of placing the next chip C on the dicing tape T is started. On the other hand, if it is determined that the chip C has not been properly placed, the placed chip C is re-held by the second collet 65, and the chip C is re-placed on one of the adsorption electrodes 2.

[0075] The operation of placing the chips C on the first electrostatic carrier Cw1 according to one embodiment is performed as described above. The operation of placing the chips C is performed independently and continuously for each of the multiple chips C attached to the dicing tape T.

[0076] In the above example, after the chip C is placed on the attraction surface of the first electrostatic carrier Cw1, a voltage is applied to one of the attraction electrodes 2 to attract the chip C, but the timing of applying the voltage to the attraction electrode 2 is not limited to this. That is, for example, a voltage may be applied to the attraction electrode 2 in advance before the chip C is placed on the attraction surface, or a voltage may be applied to the attraction electrode 2 simultaneously with the placement of the chip C on the attraction surface. However, if a voltage is applied to the chucking electrode 2 when no chip C is placed on the chucking surface, particles may be attracted to the chucking surface and adhere thereto due to the generated Coulomb force. In view of this, it is preferable to apply a voltage to the chucking electrode 2 after the chip C is placed on the chucking surface or simultaneously with the placement of the chip C on the chucking surface.

[0077] In the above example, the application of voltage to one of the plurality of chucking electrodes 2 is independently controlled to chucking and hold the chips C one by one on the chucking surface of the first electrostatic carrier Cw1, but the application of voltage to the plurality of chucking electrodes 2 may be collectively controlled. That is, for example, before the chips C are transported by the collet, a voltage may be applied to all of the chucking electrodes 2 in advance, or a voltage may be applied to all of the chucking electrodes 2 after all of the chips C have been placed on the chucking surface. However, as described above, if a voltage is applied to an attraction electrode 2 on which no chip C is placed, there is a risk that particles will adhere to the attraction surface due to the generated Coulomb force. In view of this, it is preferable to apply a voltage to the attraction electrode 2 after the placement of the chip C on the attraction surface has been completed. It is also more preferable to independently control the application of voltage to each attraction electrode 2.

[0078] Next, the first electrostatic carrier Cw1 that adsorbs and holds the plurality of chips C is transported by the transport device 50 to the protective film forming device 70. In the protective film forming device 70, as shown in FIG. 9(c), a protective film P1 is formed to prevent contamination of the adsorption surface of the first electrostatic carrier Cw1 in the subsequent processing device 80 (step St2 in FIG. 8). The method for forming the protective film P1 is arbitrary, but in one example, the protective film forming device 70 can form the protective film P1 by a so-called spin-on coating method, in which a liquid coating material is supplied onto the attraction surface while rotating the first electrostatic carrier Cw1.

[0079] Next, the first electrostatic carriers Cw1 are transported by the transport device 50 to the processing device 80. In the processing device 80, as shown in Fig. 9(d), the back surface Cb side of the chip C attracted and held by the first electrostatic carriers Cw1 is ground to thin the silicon layer Si of the chip C and flatten the back surface Cb side (step St3 in Fig. 8).

[0080] Next, the first electrostatic carriers Cw1 are transported by the transport device 50 to the protective film removing device 90. As shown in FIG. 9(e), the protective film removing device 90 removes the protective film P1 remaining on the attraction surface of the first electrostatic carriers Cw1 after the silicon layer Si is thinned (step St4 in FIG. 8). The method for removing the protective film P1 is arbitrary, but in one example, the protective film removal device 90 can remove the protective film P1 by so-called spin etching, in which an etching chemical solution is supplied to the attraction surface while rotating the first electrostatic carrier Cw1.

[0081] Next, the first electrostatic carriers Cw1 are transported to the transfer device 100 by the transport device 50. Simultaneously or subsequently, the second electrostatic carriers Cw2 in the FOUP Fc are transported to the transfer device 100.

[0082] In the transfer device 100, as shown in Fig. 9(f), a plurality of chips C whose front surface Ca is adsorbed and held by the first electrostatic carrier Cw1 are held whose back surface Cb is adsorbed and held by the second electrostatic carrier Cw2. In other words, the chips C are transferred from the first electrostatic carrier Cw1 to the second electrostatic carrier Cw2, thereby inverting the front and back surfaces (the surfaces being held) of the chips C (step St5 in Fig. 8). An example of the operation of transferring the chip C in the transfer device 100 will be described below.

[0083] First, the first electrostatic carrier Cw1 that attracts and holds the plurality of chips C is placed on the holder 101 with the attracting surface facing upward, that is, with the plurality of chips C facing upward. Next, the transport unit 102 holding the second electrostatic carrier Cw2 is placed above the first electrostatic carrier Cw1. The second electrostatic carrier Cw2 is held by the transport unit 102 with the attracting surface of the chip C facing downward. At this time, the second electrostatic carrier Cw2 held by the transport unit 102 is aligned by the alignment mechanism 103 so that each of the multiple attracting electrodes 2 on the attracting surface of the second electrostatic carrier Cw2 corresponds to the positions of the multiple chips C on the first electrostatic carrier Cw1. Next, a voltage is applied collectively to the plurality of attraction electrodes 2 of the second electrostatic carrier Cw2 via the attraction control terminal 3 from the second power supply unit 105, and the generated Coulomb force attracts and holds the back surface Cb side of the chip C on the attraction surface of the second electrostatic carrier Cw2. Following this, a negative voltage is applied collectively to the plurality of attraction electrodes 2 of the first electrostatic carrier Cw1 via the attraction control terminal 3 from the first power supply unit 104, and thereby the front surface Ca side of the chip C is peeled off from the first electrostatic carrier Cw1. 10(a), the transport unit 102 is rotated around the horizontal axis, thereby inverting the second electrostatic carriers Cw2. In other words, the chips C are placed in a state where they face upward.

[0084] The above is the process of transferring the chip C according to one embodiment. After the chip C is peeled off, the first electrostatic carrier Cw1 is transported by the transport device 50 to the transition device 40, and then further transported by the transport device 30 to the FOUP Fc on the FOUP mounting table 20.

[0085] In the above example, the transfer of multiple chips C from the adsorption surface of the first electrostatic carrier Cw1 to the adsorption surface of the second electrostatic carrier Cw2 was performed all at once, but as described above, the application of voltage to each of the multiple adsorption electrodes 2 may be independently controlled, so that the transfer of at least some of the multiple chips C can be independently controlled.

[0086] Furthermore, as described above, the first electrostatic carrier Cw1 that attracts and holds the multiple chips C may be held with its attracting surface facing downward, i.e., with the multiple chips C facing downward, and the second electrostatic carrier Cw2 may be disposed below the first electrostatic carrier Cw1. In other words, the vertical arrangement of the first electrostatic carrier Cw1 and the second electrostatic carrier Cw2 is not limited to the example shown in the figure, and they may be held and transported upside down.

[0087] Next, the second electrostatic carrier Cw2 that attracts and holds the plurality of chips C is transported to the second protective film forming device 110 by the transport device 50. In the second protective film forming apparatus 110, as shown in FIG. 10(b), a protective film P2 is formed to prevent contamination of the attraction surface of the second electrostatic carriers Cw2 in the subsequent planarization apparatus 120 (step St6 in FIG. 8). The method for forming the protective film P2 is arbitrary, but in one example, the protective film P2 can be formed by the same method as the protective film P1. That is, in one example, in the second protective film forming device 110, the protective film P2 can be formed by a so-called spin-on coating method in which a liquid coating material is supplied onto the attraction surface while rotating the second electrostatic carrier Cw2.

[0088] Next, the second electrostatic carriers Cw2 are transported by the transport device 50 to the flattening device 120. 10(c), the planarization device 120 polishes and planarizes the surface Ca side of the chip C, which will be bonded to the wafer W in a later process (step St7 in FIG. 8). At this time, the above-mentioned protective film (not shown) formed on the surface Ca side of the chip C is also removed. The method for planarizing the surface Ca of the chip C is arbitrary, but in one example, the planarization device 120 may planarize the surface Ca of the chip C by a CMP (Chemical Mechanical Polishing) process.

[0089] Next, the second electrostatic carriers Cw2 are transported by the transport device 50 to the second protective film removing device 130. As shown in FIG. 10(d), the second protective film removing device 130 removes the protective film P2 remaining on the attracting surface of the second electrostatic carrier Cw2 after the planarization process in the planarization device 120 (step St8 in FIG. 8). The protective film P2 may be removed by any method, but in one example, the protective film P2 may be removed by the same method as the protective film P1. That is, in one example, the second protective film removal device 130 may remove the protective film P2 by so-called spin etching, in which an etching chemical solution is supplied to the attraction surface of the second electrostatic carrier Cw2.

[0090] Next, the second electrostatic carriers Cw2 are transported to the bonding device 140 by the transport device 50. Simultaneously with this, or subsequently, the wafers W in the FOUP Fw are transported to the bonding device 140.

[0091] In the bonding device 140, as shown in FIG. 10(e), multiple chips C on the second electrostatic carrier Cw2 are overlapped with the mounting surface (pre-treated surface Wa) of the wafer W on which the chips C are to be mounted, and then pressed from above and below to bond the chips C to the wafer W (so-called fusion bonding) (step St9 in FIG. 8). An example of the operation of bonding the chip C to the wafer W in the bonding device 140 will be described below.

[0092] First, the second electrostatic carrier Cw2 that attracts and holds the plurality of chips C is placed on the holder 141 with the attracting surface facing upward, that is, with the plurality of chips C facing upward. Next, the transfer unit 142 holding the wafer W is placed above the second electrostatic carrier Cw2. The wafer W is held by the transfer unit 142 with its front surface Wa, which is the mounting surface for the pre-processed chips C, facing downward. At this time, the wafer W held by the transfer unit 142 is aligned by an alignment mechanism 143 so that each of the diced device layers Dw on the mounting surface of the wafer W corresponds to the positions of the multiple chips C on the second electrostatic carrier Cw2. Next, the chip C on the second electrostatic carrier Cw2 held by the holding part 141 and the device layer Dw on the wafer W held by the transport part 142 are pressed from above and below to bond the chip C and the device layer Dw. Next, a negative voltage is applied collectively to the plurality of adsorption electrodes 2 of the second electrostatic carrier Cw2 from the power supply unit 144 via the adsorption control terminal 3, thereby peeling the back surface Cb side of the chip C from the second electrostatic carrier Cw2. 10(f), the transfer part 142 is rotated around the horizontal axis, thereby inverting the front and back surfaces of the wafer W. In other words, the mounting surface of the wafer W to which the multiple chips C are bonded faces upward.

[0093] The bonding operation of the chip C to the wafer W according to the embodiment is performed as described above.

[0094] As described above, the second electrostatic carrier Cw2 that attracts and holds the plurality of chips C may be held with its attracting surface facing downward, i.e., with the plurality of chips C facing downward, and the wafer W may be placed below the second electrostatic carrier Cw2. In other words, the vertical arrangement of the second electrostatic carrier Cw2 and the wafer W is not limited to the example shown in the figure, and they may be held and transported upside down.

[0095] Thereafter, the wafer W on which the chips C are mounted is transferred by the transfer device 50 to the transition device 40, and thereafter, is further transferred by the transfer device 30 to the FOUP Fw of the FOUP mounting table 20. Similarly, the second electrostatic carrier Cw2 after the chip C has been peeled off is transported by the transport device 50 to the transition device 40, and then further transported by the transport device 30 to the FOUP Fc of the FOUP mounting stage 20. In this way, a series of chip-on-wafer manufacturing processes in the processing system 10 is completed.

[0096] According to the above embodiment, during a series of chip-on-wafer manufacturing processes, instead of temporarily bonding (temporarily placing) the chip C to be mounted on the wafer W to a carrier wafer and then transporting and processing it as in the conventional method, the chip C is electrostatically adsorbed to an electrostatic carrier Cw and then transported and processed.

[0097] In conventional chip-on-wafer manufacturing processes, when temporarily placing chips C on a carrier wafer, a series of processes including surface activation and hydrophilization had to be performed on each of the multiple chips C as described above, and temporarily placing chips C on a carrier wafer required a great deal of cost and time. Furthermore, when the temporarily placed chip C is to be separated from the carrier wafer, a so-called debonding process is required, and the separation of the chip C from the carrier wafer also requires a great deal of cost and time.

[0098] In this regard, in the present embodiment, the electrostatic carrier Cw used in place of the carrier wafer can control the attraction, retention, and detachment of the chip C on the attraction surface simply by controlling the application of voltage to the electrostatic carrier Cw, thereby significantly reducing the cost and time required for the chip-on-wafer manufacturing process compared to conventional methods.

[0099] Furthermore, according to this embodiment, when attracting and holding the chips C to and separating them from the electrostatic carrier Cw, it is not necessary to perform a series of processes including surface activation and hydrophilization, or a debonding process, as in the conventional method. As a result, the attracting surface of the electrostatic carrier Cw is not worn out when attracting and holding the chips C to and separating them from the electrostatic carrier Cw, and it is not necessary to replace the carrier wafer as in the conventional method, and the same electrostatic carrier Cw can be reused repeatedly in the chip-on-wafer manufacturing process.

[0100] 2, in the electrostatic carrier Cw according to this embodiment, the chucking electrodes 2 for chucking and holding the chips C are arranged side by side on the chucking surface, with sizes corresponding to the sizes of the chips C to be held. This allows the application of voltage to each of the multiple chucking electrodes 2 to be controlled independently via the chucking control terminals 3, and as a result, the chucking state of each of the multiple chips C can be controlled individually. That is, even if a defect occurs in only some of the chips C on the chucking surface, it is easy to independently peel off only the defective chips C from the electrostatic carrier Cw.

[0101] Furthermore, as described above, the electrostatic carrier Cw according to this embodiment is configured to have substantially the same shape as the wafer W on which the chips C are mounted. In other words, the electrostatic carrier Cw according to this embodiment is configured to have substantially the same wafer shape. This makes it possible to handle the electrostatic carrier Cw in the processing system 10 in the same manner as the carrier wafer used in the conventional chip-on-wafer manufacturing process. In other words, the technology according to the present disclosure can be introduced into an existing processing system 10 without requiring major system modifications.

[0102] Furthermore, by configuring the electrostatic carrier Cw to have approximately the same shape as the wafer W on which the chip C is to be mounted, the alignment of the wafer W and the electrostatic carrier Cw within the bonding device 140, i.e., the alignment of the device layer Dw and the chip C, can be easily performed using a method similar to that used conventionally.

[0103] Furthermore, according to this embodiment, in the electrostatic carrier Cw, a terminal (adsorption control terminal 3) for controlling bonding and peeling is arranged on the same surface as the adsorption surface of the chip C. As described above, the attraction control terminal 3 of the electrostatic carrier Cw transmits and receives a holding control signal via wire or wirelessly to and from the communication units provided in the various processing devices. In this case, particularly when sending and receiving information to and from the communication unit via a wire, if the attraction control terminal 3 is located on the side of the electrostatic carrier Cw opposite the surface that attracts the chip C (the side held by the holding unit), grooves and holes for routing the wiring will be required in the holding unit that holds the electrostatic carrier Cw, requiring major modifications to the existing processing equipment.Furthermore, if grooves and holes for routing the wiring are formed in the holding unit in this way, it may become difficult for the holding unit to attract and hold the electrostatic carrier Cw. In this regard, by arranging the adsorption control terminal 3 on the same surface as the adsorption surface of the chip C as described above, the technology disclosed herein can be applied with only minor improvements to an existing processing device, and the electrostatic carrier Cw can also be appropriately adsorbed and held by the holding part.

[0104] However, the structure of the electrostatic carrier Cw is not limited to the example shown in FIG. 2, and the attraction control terminal 3 may be arranged on the holding surface side of the holding portion of the electrostatic carrier Cw, or on the side surface (near the radially outer end).

[0105] In the above example, the attraction control terminal 3 is disposed inside the electrostatic carrier Cw, but the terminal for controlling the application of the attraction voltage to the attraction electrode 2 may be disposed outside the electrostatic carrier Cw, for example, inside the holding portion. Specifically, as shown in FIG. 11, the adsorption control unit 200 may be disposed inside a holding unit (second holding unit 64, holding unit 101, 141) provided in various processing devices, and a holding control signal may be transmitted and received by connecting a terminal disposed on the side of the third electrostatic carrier Cw3 opposite to the adsorption surface, i.e., on the contact surface side with the holding unit, to a terminal disposed on the upper surface side of the holding unit, as shown in the figure.

[0106] As described above, the attraction and holding of chips C by the second electrostatic carrier Cw2 in the transfer device 100 and the peeling of chips C by the second electrostatic carrier Cw2 in the bonding device 140 can both be performed on multiple chips C at once. In other words, unlike the attraction and holding of chips C by the first electrostatic carrier Cw1 in the chip placement device 60, the second electrostatic carrier Cw2 does not necessarily have to independently attract, hold, and peel at least some of the multiple chips C. In view of this, the second electrostatic carrier Cw2 does not necessarily have to be configured so that the application of voltage to each of the multiple attraction electrodes 2 can be independently controlled.

[0107] In the above embodiment, the first electrostatic carrier Cw1 holds the front surface Ca side of the chip C and grinds the back surface Cb side (steps St2 to St4), and then the second electrostatic carrier Cw2 holds the back surface Cb side of the chip C and flattens the front surface Ca side (steps St6 to St8), but the order of steps in the processing system 10 is not limited to this. That is, for example, the first electrostatic carrier Cw1 may hold the back surface Cb side of the chip C and flatten the front surface Ca side (steps St6 to St8), and then the second electrostatic carrier Cw2 may hold the front surface Ca side of the chip C and grind the back surface Cb side (steps St2 to St4). However, in this case, since the front surface Ca side of the chip C is bonded to the wafer W, it becomes necessary to additionally invert the chip C prior to the bonding process (step St9) in the bonding device 140. In view of this, it is desirable to perform grinding of the back surface Cb side (step St3) prior to planarization of the front surface Ca side (step St7). Furthermore, as described above, in the planarization process of the front surface Ca in step St7, a protective film (not shown) formed on the front surface Ca is removed. Therefore, if the planarization of the front surface Ca (step St7) is performed prior to the grinding of the back surface Cb (step St3) and the protective film is removed, there is a risk that a layer will be damaged on the front surface Ca when the second electrostatic carriers Cw2 hold the front surface Ca. In view of this, it is desirable to perform the grinding of the back surface Cb (step St3) prior to the planarization of the front surface Ca (step St7).

[0108] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive, and the above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims.

[0109] For example, in the above embodiment, the chip placement device 60, the transfer device 100, and the bonding device 140 are arranged in the same processing system 10, but these chip placement device 60, the transfer device 100, and the bonding device 140 may be arranged in different processing systems. In other words, a first processing system for placing the chips C on the dicing frame F on the first electrostatic carrier Cw1, a second processing system for transferring the chips C from the first electrostatic carrier Cw1 to the second electrostatic carrier Cw2, and a third processing system for bonding the chips C on the second electrostatic carrier Cw2 to the wafer W may each be configured independently. [Explanation of symbols]

[0110] 10 Processing System 60 Chip placement device 64 Second holding part 66 Power supply section C-chip Cw1 First electrostatic carrier W wafer

Claims

1. A processing system for processing chips, comprising: a first transfer carrier holding unit that holds the first electrostatic carrier; a transfer device including a second transfer carrier holding unit that holds a second electrostatic carrier so as to face the first electrostatic carrier held by the first transfer carrier holding unit, The transfer device is a plurality of chips whose first surfaces are attracted and held by the first electrostatic carrier are transferred collectively to the second electrostatic carrier so that the second surfaces of the plurality of chips are attracted and held by the second electrostatic carrier; Processing system.

2. The transfer device comprises: a first power supply unit that collectively applies a first voltage for peeling off the plurality of chips to the plurality of first chucking electrodes of the first electrostatic carrier held by the first transfer carrier holding unit; 2. The processing system according to claim 1, further comprising: a second power supply unit that collectively applies a second voltage for attracting the plurality of chips to the plurality of second attraction electrodes of the second electrostatic carrier held by the second transfer carrier holding unit.

3. The transfer device includes a communication unit, the first transfer carrier holding unit has a first suction control terminal therein; the second transfer carrier holding unit has a second suction control terminal therein; The communication unit transmitting a first holding control signal to the first attraction control terminal to control application of the first voltage from the first power supply unit; The processing system according to claim 2 , wherein application of the second voltage from the second power supply unit is controlled by transmitting a second holding control signal to the second attraction control terminal.

4. A processing system as described in claim 2, comprising an alignment mechanism that aligns the positions of the plurality of chips held by the plurality of first adsorption electrodes of the first electrostatic carrier with positions corresponding to the plurality of second adsorption electrodes of the second electrostatic carrier.

5. A protective film forming device that forms a first protective film on the adsorption surface side of the first electrostatic carrier that holds the plurality of chips; a processing device that grinds the surfaces of the plurality of chips that are not held by the first electrostatic carrier; 5. The processing system according to claim 1, further comprising: a protective film removing device that removes the first protective film remaining on the attracting surface side of the first electrostatic carrier after the grinding process.

6. A processing system described in any one of claims 1 to 4, wherein in the transfer device, the second transfer carrier holding unit is configured to be rotatable around a horizontal axis.

7. A bonding device that mounts the plurality of chips held by the second electrostatic carrier on a substrate, The joining device is a bonding carrier holding portion that holds the second electrostatic carrier; a substrate holding unit that holds a substrate on which the plurality of chips are to be mounted, so as to face the second electrostatic carrier held by the bonding carrier holding unit, The processing system according to any one of claims 1 to 4, wherein the plurality of chips, the second surfaces of which are adsorbed and held by the second electrostatic carrier, are collectively mounted on the substrate so that the first surfaces of the plurality of chips are bonded to the substrate.

8. The joining device is 8. The processing system according to claim 7, further comprising a third power supply unit that collectively applies a third voltage for peeling off the plurality of chips to the plurality of second attraction electrodes of the second electrostatic carrier held by the bonding carrier holding unit.

9. The joining device includes a communication unit, the bonding carrier holding portion has a third suction control terminal therein, The communication unit The processing system according to claim 8 , wherein application of the third voltage from the third power supply unit is controlled by transmitting a third holding control signal to the third attraction control terminal.

10. A processing method for processing chips using a processing system, comprising: The processing system includes: a first transfer carrier holding unit that holds the first electrostatic carrier; a transfer device including a second transfer carrier holding unit that holds a second electrostatic carrier so as to face the first electrostatic carrier held by the first transfer carrier holding unit, The processing method comprises: transferring the plurality of chips, the first surfaces of which are attracted and held by the first electrostatic carrier, to the second electrostatic carrier in a batch so that the second surfaces of the plurality of chips are attracted and held by the second electrostatic carrier; Processing method.

11. Applying a first voltage to multiple first adsorption electrodes of the first electrostatic carrier held in the first transfer carrier holding portion at the same time, the first voltage being used to peel off the multiple chips; 11. The processing method according to claim 10, further comprising: simultaneously applying a second voltage for attracting the plurality of chips to a plurality of second attracting electrodes of the second electrostatic carrier held by the second transfer carrier holding unit.

12. The transfer device includes a communication unit, the first transfer carrier holding unit has a first suction control terminal therein; the second transfer carrier holding unit has a second suction control terminal therein; The processing method comprises: transmitting a first holding control signal to the first attraction control terminal to control application of the first voltage from the first power supply unit; 12. The processing method according to claim 11, further comprising: controlling application of the second voltage from the second power supply unit by transmitting a second holding control signal to the second attraction control terminal.

13. A processing method as described in claim 11, comprising aligning the positions of the plurality of chips held by the plurality of first adsorption electrodes of the first electrostatic carrier with positions corresponding to the plurality of second adsorption electrodes of the second electrostatic carrier.

14. Forming a first protective film on an adsorption surface side of the first electrostatic carrier holding the plurality of chips; grinding the surfaces of the chips that are not held by the first electrostatic carrier; The processing method according to any one of claims 10 to 13, further comprising removing the first protective film remaining on the attracting surface side of the first electrostatic carrier after the grinding process.

15. A processing method described in any one of claims 10 to 13, comprising rotating the second transfer carrier holding portion around a horizontal axis to invert the top and bottom surfaces of the multiple chips.

16. The processing system, a bonding device that mounts the plurality of chips held by the second electrostatic carrier on a substrate; The joining device is a bonding carrier holding portion that holds the second electrostatic carrier; a substrate holding unit that holds a substrate on which the plurality of chips are to be mounted, so as to face the second electrostatic carrier held by the bonding carrier holding unit, The processing method comprises: The processing method according to any one of claims 10 to 13, further comprising collectively mounting the plurality of chips, the second surfaces of which are attracted and held by the second electrostatic carrier, on the substrate so that the first surfaces of the plurality of chips are joined.

17. A processing method as described in claim 16, comprising collectively applying a third voltage to multiple second adsorption electrodes of the second electrostatic carrier held in the bonding carrier holding portion, the third voltage peeling off the multiple chips.

18. The joining device includes a communication unit, the bonding carrier holding portion has a third suction control terminal therein, 18. The processing method according to claim 17, further comprising controlling application of the third voltage from the third power supply unit by transmitting a third holding control signal to the third attraction control terminal.

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