Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device that can reduce its on-resistance, and a method for manufacturing the same.SOLUTION: A semiconductor device according to an embodiment comprises a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a conductive part, a gate electrode, and a second electrode. The first semiconductor region includes the first portion. The second semiconductor region is provided above the first portion. The gate electrode faces the first portion with a gate insulating layer therebetween in a second direction. The second electrode includes a first electrode portion arranged side by side with the first portion and the second semiconductor region in the second direction, and a second electrode portion provided above the gate electrode with an insulating layer therebetween. The first portion is located between the first electrode portion and the gate electrode. The second semiconductor region is located between the first electrode portion and the second electrode portion. The second electrode is electrically connected to the conductive part and contains one or more selected from the group consisting of platinum, cobalt, and nickel.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices such as metal-oxide-semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion, etc. It is desirable for semiconductor devices to have a low on-resistance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2008-536316 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of reducing the on-resistance and a method for manufacturing the same. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a conductive portion, a gate electrode, and a second electrode. The first semiconductor region includes a first portion and is provided on the first electrode. The second semiconductor region is provided on the first portion and has a higher impurity concentration of the first conductivity type than the first semiconductor region. The conductive portion is provided in the first semiconductor region via a first insulating portion. The gate electrode is provided on the conductive portion via a second insulating portion. The gate electrode faces the first portion via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The second electrode includes a first electrode portion aligned with the first portion and the second semiconductor region in the second direction, and a second electrode portion provided on the gate electrode via an insulating layer. The first portion is located between the first electrode portion and the gate electrode. The second semiconductor region is located between the first electrode portion and the second electrode portion. The second electrode is electrically connected to the conductive portion and includes one or more selected from the group consisting of platinum, cobalt, and nickel. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view of a part of FIG. [Figure 3] 3(a) and 3(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4(a) and 4(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5(a) and 5(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a semiconductor device according to a reference example. [Figure 7] FIG. 7 is a perspective cross-sectional view showing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already described are designated by the same reference numerals, and detailed description will be omitted as appropriate. In the following description, n + The notation n indicates the relative level of impurity concentration in each conductivity type. + indicates that the concentration of n-type impurities is relatively higher than that of n. Each embodiment described below may be implemented by inverting the conductivity type of each semiconductor region to p-type.

[0008] (First embodiment) FIG. 1 is a perspective cross-sectional view showing a semiconductor device according to a first embodiment. As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes an n-type (first conductivity type) drift region 1 (first semiconductor region), an n + source region 2 (second semiconductor region), n + The semiconductor device 100 is a MOSFET, and includes a drain region 3, a conductive portion 11, a gate electrode 12, a gate insulating layer 12a, a first insulating portion 21, a second insulating portion 22, an insulating layer 30, a drain electrode 41 (first electrode), and a source electrode 42 (second electrode).

[0009] In the description of the embodiment, an XYZ Cartesian coordinate system is used. The direction from the drain electrode 41 toward the n-type drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction. For the sake of explanation, the direction from the drain electrode 41 toward the n-type drift region 1 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the drain electrode 41 and the n-type drift region 1 and are unrelated to the direction of gravity.

[0010] The drain electrode 41 is provided at the bottom of the semiconductor device 100. + The n-type drain region 3 is provided on the drain electrode 41 and is electrically connected to the drain electrode 41. The n-type drift region 1 is + The n-type impurity concentration in the n-type drift region 1 is n + The n-type impurity concentration in the n-type drain region 3 is lower than that in the n-type drift region 1. The n-type drift region 1 includes a first portion 1a. + The source region 2 is provided on the first portion 1a. + The n-type impurity concentration in the n-type source region 2 is higher than the n-type impurity concentration in the n-type drift region 1.

[0011] The conductive portion 11 is provided in the n-type drift region 1 via a first insulating portion 21. The gate electrode 12 is provided on the conductive portion 11 via a second insulating portion 22. The gate electrode 12 faces the first portion 1a in the X direction via a gate insulating layer 12a. The gate electrode 12 is connected to the n-type drift region 1 via the gate insulating layer 12a. + The insulating layer 30 may face a part of the source region 2. The insulating layer 30 is provided on the gate electrode 12.

[0012] The source electrode 42 is connected to the n-type drift region 1, + The source electrode 42 is provided on the source region 2 and the insulating layer 30. The source electrode 42 includes a first electrode portion 42a and a second electrode portion 42b. The first electrode portion 42a is separated from the first portion 1a and the second portion 1b in the X direction. + The second electrode portion 42b is aligned with the source region 2. The second electrode portion 42b is located on the insulating layer 30. The first portion 1a is located between the first electrode portion 42a and the gate electrode 12 in the X direction. + The source region 2 is located between the first electrode portion 42a and the second electrode portion 42b in the X direction.

[0013] The source electrode 42 is connected to the n-type drift region 1 and the n + The n-type source region 2 is in contact with the n-type drift region 1 and the n-type+ The gate electrode 12 and the source electrode 42 are electrically connected to the source region 2. The gate electrode 12 and the source electrode 42 are electrically isolated from each other by an insulating layer 30.

[0014] FIG. 2 is an enlarged cross-sectional view of a part of FIG. 2, the insulating layer 30 may include a first insulating portion 31 and a second insulating portion 32. The second insulating portion 32 is located n away from the first insulating portion 31 in the X direction. + The second insulating portion 32 is located between the source region 2 and the second insulating portion 31. The thickness T2 of the second insulating portion 32 in the Z direction is smaller than the thickness T1 of the first insulating portion 31 in the Z direction. Therefore, the upper surface of the second insulating portion 32 is located lower than the upper surface of the first insulating portion 31.

[0015] The width of the first portion 1a and n + The width of the source region 2 may be gradually narrowed in the Z direction. + The width W2 of the source region 2 is narrower than the width W1 of the first portion 1a. The width is the length in the X direction.

[0016] As shown in FIG. 1, the first portion 1a, n + A plurality of each of the source region 2, the conductive portion 11, the gate electrode 12, the first electrode portion 42a, and the second electrode portion 42b are provided in the X direction. For example, a pair of first portions 1a spaced apart in the X direction is located between a pair of gate electrodes 12 spaced apart in the X direction. Also, a pair of n-type electrode portions 11 spaced apart in the X direction is located between a pair of second electrode portions 42b spaced apart in the X direction. + The first electrode portion 42a is located between the pair of first portions 1a and the pair of n-type source regions 2. + Located between the source regions 2.

[0017] Each 1st part 1a, each n +The source region 2, the conductive portions 11, the gate electrodes 12, the first electrode portions 42a, and the second electrode portions 42b extend in the Y direction and are arranged in a stripe pattern. The ends of the conductive portions 11 in the Y direction are pulled upward and contact the source electrodes 42. The conductive portions 11 are electrically connected to the source electrodes 42.

[0018] An example of the material of each component will be described. n-type drift region 1, n + shaped source region 2, and n + The n-type drain region 3 contains single crystal silicon as a semiconductor material. + shaped source region 2, and n + The n-type drain region 3 contains arsenic, phosphorus, or antimony as an n-type impurity. The conductive portion 11 and the gate electrode 12 contain a conductive material such as polysilicon. The gate insulating layer 12a, the first insulating portion 21, the second insulating portion 22, and the insulating layer 30 contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 41 contains a metal such as aluminum. The source electrode 42 contains one or more selected from the group consisting of platinum, nickel, and cobalt. For example, a Schottky junction is formed between the n-type drift region 1 and the first electrode portion 42a.

[0019] The operation of the semiconductor device 100 will now be described. A depletion layer spreads from the interface between the n-type drift region 1 and the source electrode 42 to the n-type drift region 1. This spread of the depletion layer depletes the first portion 1a. At this time, no current flows between the drain electrode 41 and the source electrode 42, and the semiconductor device 100 is in an off state. When a voltage exceeding the threshold is applied to the gate electrode 12, a channel (inversion layer) is formed in the first portion 1a near the gate insulating layer 12a. Electrons pass through the channel and are depleted into the n + Shape source region 2 to n + The electrons flow toward the drain region 3. This causes the semiconductor device 100 to turn on.

[0020] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 41 increases relative to the source electrode 42. The potential of the conductive portion 11 is substantially the same as the potential of the source electrode 42. Due to the potential difference between the n-type drift region 1 electrically connected to the drain electrode 41 and the conductive portion 11, a depletion layer spreads from the interface between the first insulating portion 21 and the n-type drift region 1 toward the n-type drift region 1. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the n-type impurity concentration in the n-type drift region 1 can be increased while maintaining the breakdown voltage of the semiconductor device 100, thereby reducing the on-resistance of the semiconductor device 100.

[0021] 3(a), 3(b), 4(a), 4(b), 5(a), and 5(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. First, n-type drift region 1 and n + A semiconductor substrate Sub including an n-type drain region 3 is prepared. A plurality of openings are formed in the upper surface of the n-type drift region 1 by a known method. As shown in FIG. 3(a), a conductive portion 11, a gate electrode 12, a gate insulating layer 12a, a first insulating portion 21, a second insulating portion 22, and an insulating layer 30 are formed inside the openings. As a result, the n-type drift region 1, n + A structure ST is provided, which includes a drain region 3, a conductive portion 11, a gate electrode 12, a first insulating portion 21, a second insulating portion 22, an insulating layer 30, and a gate insulating layer 12a.

[0022] A portion of the n-type drift region 1 that is distant from the gate insulating layer 12a in the X direction is removed by reactive ion etching (RIE). As a result, an opening OP is formed in the upper surface of the n-type drift region 1, as shown in FIG. 3(b). A first portion 1a and a second portion 1b located on the first portion 1a remain in the upper portion of the n-type drift region 1. At this time, the upper surface of the insulating layer 30 is located higher than the upper surface of the n-type drift region 1 (the upper surface of the second portion 1b).

[0023] As shown in FIG. 4(a), the upper surface of the insulating layer 30 is recessed by wet etching. At this time, etching also progresses laterally at the ends of the insulating layer 30 in the X direction. As a result, the thickness of the ends of the insulating layer 30 in the X direction becomes smaller than the thickness of the central portion. This forms a first insulating portion 31 and a second insulating portion 32 in the insulating layer 30.

[0024] N-type impurities are ion-implanted into the second portion 1b. The n-type impurities are implanted from a direction tilted with respect to the Z direction. As a result, more n-type impurities are implanted into the second portion 1b than into the first portion 1a. By activating the n-type impurities through heat treatment, as shown in FIG. 4(b), n-type impurities are implanted on the first portion 1a. + A source region 2 is formed.

[0025] By sputtering, n-type drift regions 1 and n + A source electrode 42 is formed on the source region 2 and the insulating layer 30. + The n-type drain region 3 is then grown to a predetermined thickness. + The bottom surface of the n-type drain region 3 is ground. As shown in FIG. 5(b), the ground n-type drain region 3 is + A drain electrode 41 is formed on the back surface of the drain region 3. Through the above steps, the semiconductor device 100 according to the first embodiment is manufactured.

[0026] FIG. 6 is a cross-sectional view showing a semiconductor device according to a reference example. In the semiconductor device 100r shown in FIG. 6, the upper surface of the insulating layer 30 is + The source electrode 42 is located above the source region 2. The source electrode 42 does not include the second electrode portion 42b. + One side of the source region 2 is in contact with the first electrode portion 42a, and + The other side of the source region 2 is in contact with the insulating layer 30 .

[0027] The advantages of the first embodiment will be described with reference to Fig. 6. In the semiconductor device 100 or 100r, it is desirable that the electrical resistance (on-resistance) in the on-state is small. The on-resistance is determined by the n-type impurity concentration in the n-type drift region 1, the channel density, the n + It depends on the electrical resistance (contact resistance) between the source region 2 and the source electrode 42. Note that the "channel density" refers to the number of channels formed per unit area in the XY plane.

[0028] To increase the channel density, it is desirable to have a small cell pitch. The cell pitch is expressed, for example, as the distance between the center of one gate electrode 12 in the X direction and the center of another adjacent gate electrode 12 in the X direction. Also, n + In order to reduce the contact resistance between the source region 2 and the source electrode 42, + It is desirable that the contact area between the source region 2 and the source electrode 42 is large. + In order to increase the contact area between the source region 2 and the source electrode 42, n + The size of the source region 2 needs to be increased. However, + If the size of the source region 2 increases, the cell pitch increases and the channel density may decrease. For this reason, it is not easy to reduce the contact resistance while maintaining the cell pitch in the semiconductor device 100r.

[0029] In the semiconductor device 100 according to the first embodiment, n + The source region 2 is located between the first electrode portion 42a and the second electrode portion 42b. + The source region 2 is in contact with both the first electrode portion 42a and the second electrode portion 42b. Therefore, the semiconductor device 100 has a n-type +This increases the contact area between the source region 2 and the source electrode 42. For example, the contact resistance can be further reduced while suppressing an increase in the cell pitch. Alternatively, the cell pitch can be further reduced while suppressing an increase in the contact resistance. In either case, the on-resistance of the semiconductor device 100 can be reduced.

[0030] In addition, in the manufacture of the semiconductor device 100, n + When forming the n-type source region 2, as shown in FIG. 4(b), n-type impurities are ion-implanted into both side surfaces of the second portion 1b. + When forming the n-type source region 2, the n-type impurity is ion-implanted only into one side surface of the second portion 1b. + The n-type impurity implanted into the n-type source region 2 is increased, and n + This can further increase the n-type impurity concentration in the n-type source region 2. As a result, the on-resistance of the semiconductor device 100 can be further reduced.

[0031] 2, the insulating layer 30 preferably includes a first insulating portion 31 and a second insulating portion 32. The thickness T2 of the second insulating portion 32 is smaller than the thickness T1 of the first insulating portion 31. Since the thickness T2 is small and the upper surface of the second insulating portion 32 is located lower than the upper surface of the first insulating portion 31, + This allows the contact area between the source region 2 and the second electrode portion 42b to be further increased.

[0032] Also, n + The width W2 of the source region 2 is preferably narrower than the width W1 of the first portion 1a. + The amount of n-type impurities contained per unit volume of the n-type source region 2 is large. + This allows the concentration of n-type impurities in the n-type source region 2 to be further increased, thereby further reducing the on-resistance of the semiconductor device 100.

[0033] (Second embodiment) FIG. 7 is a perspective cross-sectional view showing a semiconductor device according to the second embodiment. As shown in FIG. 7, the semiconductor device 200 according to the second embodiment includes an n-type drift region 1, an n-type + Shape source region 2, n + The semiconductor device 200 includes a drain region 3, a gate electrode 12, a gate insulating layer 12a, an insulating layer 30, a drain electrode 41, and a source electrode 42. The semiconductor device 200 differs from the semiconductor device 100 in that the conductive portion 11 is not included.

[0034] The gate electrode 12 is provided via a gate insulating layer 12a in the n-type drift region 1. The gate electrode 12 faces the first portion 1a in the X direction via the gate insulating layer 12a.

[0035] n-type drift region 1, n + shaped source region 2, and n + The n-type drain region 3 includes silicon carbide or gallium nitride as a semiconductor material. The source electrode 42 includes one or more selected from the group consisting of platinum and nickel. For example, a Schottky junction is formed between the n-type drift region 1 and the first electrode portion 42a. The operation of the semiconductor device 200 is substantially similar to that of the semiconductor device 100.

[0036] When each semiconductor region contains a compound semiconductor such as silicon carbide or gallium nitride, the breakdown voltage of the semiconductor device 200 can be improved and the on-resistance can be reduced compared to when each semiconductor region contains single crystal silicon. Therefore, even if the conductive portion 11 is omitted, a sufficient breakdown voltage or on-resistance can be obtained.

[0037] Furthermore, in the first embodiment, in order to improve the breakdown voltage or reduce the on-resistance of the semiconductor device 100, it is desirable that the semiconductor device 100 include the conductive portion 11. However, if the conductive portion 11 can be omitted from the viewpoint of the breakdown voltage or the on-resistance, the conductive portion 11 may be omitted.

[0038] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type including a first portion and provided on the first electrode; a second semiconductor region provided on the first portion and having a higher impurity concentration of the first conductivity type than the first semiconductor region; a conductive portion provided in the first semiconductor region via a first insulating portion; a gate electrode provided on the conductive portion via a second insulating portion, the gate electrode facing the first portion via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a second electrode including a first electrode portion aligned with the first portion and the second semiconductor region in the second direction, and a second electrode portion provided on the gate electrode via an insulating layer, wherein the first portion is located between the first electrode portion and the gate electrode, and the second semiconductor region is located between the first electrode portion and the second electrode portion, the second electrode being electrically connected to the conductive portion and including one or more selected from the group consisting of platinum, cobalt, and nickel; A semiconductor device comprising: (Feature 2) the insulating layer includes a first insulating portion and a second insulating portion located between the first insulating portion and the second semiconductor region in the first direction; 2. The semiconductor device according to feature 1, wherein the thickness of the second insulating portion in the first direction is smaller than the thickness of the first insulating portion in the first direction. (Feature 3) 3. The semiconductor device according to feature 1 or 2, wherein the length of the upper portion of the second semiconductor region in the second direction is shorter than the length of the lower portion of the second semiconductor region in the second direction. (Feature 4) a pair of the first portions spaced apart from each other in the second direction; a pair of the second semiconductor regions is provided on each of the pair of first portions; 4. The semiconductor device according to any one of features 1 to 3, wherein the first electrode portion is located between the pair of first portions and between the pair of second semiconductor regions. (Feature 5) A first electrode; a first semiconductor region of a first conductivity type including a first portion and provided on the first electrode; a second semiconductor region provided on the first portion and having a higher impurity concentration of the first conductivity type than the first semiconductor region; a gate electrode facing the first portion via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a second electrode including a first electrode portion aligned with the first portion and the second semiconductor region in the second direction, and a second electrode portion provided on the gate electrode via an insulating layer, wherein the first portion is located between the first electrode portion and the gate electrode, and the second semiconductor region is located between the first electrode portion and the second electrode portion; A semiconductor device comprising: (Feature 6) 6. The semiconductor device according to feature 5, wherein a Schottky junction is formed between the first semiconductor region and the first electrode portion. (Feature 7) the first semiconductor region and the second semiconductor region include silicon carbide or gallium nitride; 7. The semiconductor device according to feature 5 or 6, wherein the second electrode includes one or more selected from the group consisting of platinum and nickel. (Feature 8) a first semiconductor region of a first conductivity type including a first portion and a second portion provided on the first portion; a conductive portion provided in the first semiconductor region via a first insulating portion; a gate electrode provided on the conductive portion via a second insulating portion, the gate electrode facing the first portion via a gate insulating layer in a second direction perpendicular to a first direction from the conductive portion toward the gate electrode; an insulating layer provided on the gate electrode and aligned with the second portion in the second direction; removing a portion of the first semiconductor region away from the gate insulating layer in the second direction so as to leave the first portion and the second portion, a top surface of the insulating layer is recessed to expose a side surface of the second portion; A method for manufacturing a semiconductor device, comprising forming an electrode containing one or more selected from the group consisting of platinum, cobalt, and nickel on the first semiconductor region and the insulating layer. (Feature 9) 9. The method for manufacturing a semiconductor device according to Feature 8, wherein after exposing the side surface of the second portion, and before forming the electrode, an impurity of the first conductivity type is ion-implanted into the second portion to form a second semiconductor region having a higher impurity concentration of the first conductivity type than the first semiconductor region. (Feature 10) After the upper surface of the insulating layer is recessed, the insulating layer includes a first insulating portion and a second insulating portion located between the first insulating portion and the second semiconductor region in the first direction; 10. The method for manufacturing a semiconductor device according to Feature 9, wherein the thickness of the second insulating portion in the first direction is smaller than the thickness of the first insulating portion in the first direction.

[0039] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0040] Each of the embodiments described above may be implemented by inverting the n-type of the semiconductor region to p-type.

[0041] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0042] 1: n-type drift region, 1a: first portion, 1b: second portion, 2: n + Shape source area, 3:n + Drain region, 11: conductive portion, 12: gate electrode, 12a: gate insulating layer, 21: first insulating portion, 22: second insulating portion, 30: insulating layer, 31: first insulating portion, 32: second insulating portion, 41: drain electrode, 42: source electrode, 42a: first electrode portion, 42b: second electrode portion, 100, 100r, 200: semiconductor device, OP: opening, ST: structure, Sub: semiconductor substrate, T1, T2: thickness, W1, W2: width

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first portion; a second semiconductor region of the first conductivity type provided on the first portion and having a higher impurity concentration of the first conductivity type than the first semiconductor region; a conductive portion provided in the first semiconductor region via a first insulating portion; a gate electrode provided on the conductive portion via a second insulating portion, the gate electrode facing the first portion via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a second electrode including a first electrode portion aligned with the first portion and the second semiconductor region in the second direction, and a second electrode portion provided on the gate electrode via an insulating layer, wherein the first portion is located between the first electrode portion and the gate electrode, and the second semiconductor region is located between the first electrode portion and the second electrode portion, the second electrode being electrically connected to the conductive portion and including one or more selected from the group consisting of platinum, cobalt, and nickel; A semiconductor device comprising:

2. the insulating layer includes a first insulating portion and a second insulating portion located between the first insulating portion and the second semiconductor region in the first direction; The semiconductor device according to claim 1 , wherein the thickness of said second insulating portion in said first direction is smaller than the thickness of said first insulating portion in said first direction.

3. The semiconductor device according to claim 1 , wherein a length of an upper portion of said second semiconductor region in said second direction is shorter than a length of a lower portion of said second semiconductor region in said second direction.

4. a pair of the first portions spaced apart from each other in the second direction; a pair of the second semiconductor regions is provided on each of the pair of first portions; 4. The semiconductor device according to claim 1, wherein the first electrode portion is located between the pair of first portions and between the pair of second semiconductor regions.

5. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first portion; a second semiconductor region of the first conductivity type provided on the first portion and having a higher impurity concentration of the first conductivity type than the first semiconductor region; a gate electrode facing the first portion via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a second electrode including a first electrode portion aligned with the first portion and the second semiconductor region in the second direction, and a second electrode portion provided on the gate electrode via an insulating layer, wherein the first portion is located between the first electrode portion and the gate electrode, and the second semiconductor region is located between the first electrode portion and the second electrode portion; A semiconductor device comprising:

6. 6. The semiconductor device according to claim 5, wherein a Schottky junction is formed between said first semiconductor region and said first electrode portion.

7. the first semiconductor region and the second semiconductor region include silicon carbide or gallium nitride; 7. The semiconductor device according to claim 5, wherein the second electrode includes at least one selected from the group consisting of platinum and nickel.

8. a first semiconductor region of a first conductivity type including a first portion and a second portion provided on the first portion; a conductive portion provided in the first semiconductor region via a first insulating portion; a gate electrode provided on the conductive portion via a second insulating portion, the gate electrode facing the first portion via a gate insulating layer in a second direction perpendicular to a first direction from the conductive portion toward the gate electrode; an insulating layer provided on the gate electrode and aligned with the second portion in the second direction; removing a portion of the first semiconductor region away from the gate insulating layer in the second direction so as to leave the first portion and the second portion, a top surface of the insulating layer is recessed to expose a side surface of the second portion; A method for manufacturing a semiconductor device, further comprising forming an electrode containing one or more elements selected from the group consisting of platinum, cobalt, and nickel on the first semiconductor region and the insulating layer.

9. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising the steps of: exposing a side surface of the second portion; ion-implanting an impurity of a first conductivity type into the second portion; and forming a second semiconductor region of the first conductivity type having a higher impurity concentration of the first conductivity type than the first semiconductor region.

10. After the upper surface of the insulating layer is recessed, the insulating layer includes a first insulating portion and a second insulating portion located between the first insulating portion and the second semiconductor region in the first direction; 10. The method for manufacturing a semiconductor device according to claim 9, wherein the thickness of the second insulating portion in the first direction is smaller than the thickness of the first insulating portion in the first direction.

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