Switching control circuit and power supply circuit

Abstract

To suppress deviation of phase difference even when a rectified voltage fluctuates during interleaving operation.SOLUTION: A switching control circuit controls a first circuit including a first transistor that controls a first inductor current, a second circuit including a second transistor that controls a second inductor current, and switching of the first and second transistors. The switching control circuit includes: a first drive circuit that turns on the first transistor after the first inductor current becomes a first value and turns off the first transistor when a first period according to an output voltage elapses; an output circuit that outputs a signal indicating a half cycle of a switching cycle of the first transistor; and a second drive circuit that turns on the second transistor based on the signal indicating the half cycle after the first transistor is turned on and the second inductor current becomes a second value and turns off the second transistor when a second period according to the output voltage elapses.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a switching control circuit and a power supply circuit. [Background technology]

[0002] A typical power factor correction circuit (hereinafter referred to as a PFC circuit) that operates in critical current mode improves the power factor by making the waveform of the peak value of the inductor current flowing through the inductor similar to the rectified voltage obtained by rectifying an AC voltage. Also, a power factor correction circuit may include multiple (e.g., two systems) boost chopper circuits (e.g., Patent Documents 1 to 23). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-037532 [Patent Document 2] Japanese Patent Publication No. 2020-129865 [Patent Document 3] Japanese Patent Publication No. 2020-039235 [Patent Document 4] Japanese Patent Application Laid-Open No. 2017-070193 [Patent Document 5] Japanese Patent Application Laid-Open No. 2015-019558 [Patent Document 6] Japanese Patent Application Laid-Open No. 2014-155240 [Patent Document 7] Japanese Patent Application Laid-Open No. 2011-030311 [Patent Document 8] Japanese Patent Application Laid-Open No. 2011-030310 [Patent Document 9] Japanese Patent Application Laid-Open No. 2010-130896 [Patent Document 10] Japanese Patent Application Laid-Open No. 2010-035271 [Patent Document 11] Japanese Patent Application Laid-Open No. 2010-035270 [Patent Document 12] Japanese Patent Application Laid-Open No. 2007-181342 [Patent Document 13] Japanese Patent Application Laid-Open No. 2007-181252 [Patent Document 14] Japanese Patent Application Laid-Open No. 2007-043875 [Patent Document 15] Japanese Patent Application Laid-Open No. 2007-043807 [Patent Document 16] Japanese Patent Application Laid-Open No. 2007-043787 [Patent Document 17] Japanese Patent Application Laid-Open No. 2007-043786 [Patent Document 18] Japanese Patent Application Laid-Open No. 2007-028753 [Patent Document 19] Japanese Patent Application Laid-Open No. 2007-028729 [Patent Document 20] Japanese Patent Application Laid-Open No. 2007-020252 [Patent Document 21] Japanese Patent Application Laid-Open No. 2007-014139 [Patent Document 22] Japanese Patent Application Laid-Open No. 2005-045996 [Patent Document 23] Japanese Patent Application Laid-Open No. 2005-045995 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in a PFC circuit, two boost chopper circuits may be operated in parallel (hereinafter also referred to as interleaved operation as appropriate).

[0005] However, when two boost chopper circuits are operated in parallel, for example, if fluctuations occur in the output of the full-wave rectifier circuit, the switching cycles of the two transistors constituting the two boost chopper circuits may be disrupted, causing the phase difference between the on-timings of the two transistors constituting the two boost chopper circuits to deviate from a predetermined phase difference (for example, 180°).

[0006] The present invention has been made in consideration of the above-mentioned conventional problems, and aims to provide a switching control circuit that suppresses deviations in phase difference even when the rectified voltage fluctuates during interleaving operation. [Means for solving the problem]

[0007] a first driver circuit that turns on the first transistor after the first inductor current reaches a first value, and turns off the first transistor after a first period corresponding to the output voltage has elapsed; an output circuit that outputs a signal indicating a half cycle of a switching period of the first transistor; and a second driver circuit that turns on the second transistor based on the signal indicating the half cycle since the first transistor was turned on and on the fact that the second inductor current has reached a second value, and turns off the second transistor after a second period corresponding to the output voltage has elapsed.

[0008] A second aspect of the present invention for solving the above-mentioned problems is a power supply circuit that generates an output voltage of a target level from an AC voltage, the power supply circuit comprising: a first circuit including a first inductor to which a voltage corresponding to the AC voltage is applied and a first transistor that controls a first inductor current flowing through the first inductor; a second circuit including a second inductor to which a voltage corresponding to the AC voltage is applied and a second transistor that controls a second inductor current flowing through the second inductor; output terminals to which outputs of the first and second circuits and a load are connected; and a switch that controls switching of the first and second transistors of the power supply circuit that generates an output voltage at the output terminal. a first drive circuit that turns on the first transistor after the first inductor current reaches a first value, and turns off the first transistor after a first period corresponding to the output voltage has elapsed; an output circuit that outputs a signal indicating a half period of the switching period of the first transistor; and a second drive circuit that turns on the second transistor based on the signal indicating the half period after the first transistor is turned on and that the second inductor current has reached a second value, and turns off the second transistor after a second period corresponding to the output voltage has elapsed. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a switching control circuit that suppresses deviation of the phase difference even when the rectified voltage fluctuates during interleaving operation. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating an example of an AC-DC converter 10. FIG. [Figure 2A] FIG. 2 is a diagram illustrating an example of an input line filter 20. [Figure 2B] FIG. 2 is a diagram illustrating an example of an input line filter 20 that takes into account parasitic components. [Figure 3] FIG. 2 is a diagram illustrating an example of a power factor correction IC 25. [Figure 4]FIG. 2 is a diagram illustrating an example of a switching control circuit 203a. [Figure 5] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 203a. [Figure 6] 2A to 2C are diagrams showing main waveforms of the AC-DC converter 10. [Figure 7] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 203a. [Figure 8] FIG. 10 is a diagram showing an example of a flowchart of the operation of a switching control circuit 203a. [Figure 9] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 203a. [Figure 10] FIG. 10 is a diagram showing an example of a flowchart of the operation of a switching control circuit 203a. [Figure 11] FIG. 10 is a diagram illustrating an example of a switching control circuit 203b. [Figure 12] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 203b. [Figure 13] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 203b. [Figure 14] FIG. 10 is a diagram showing an example of a flowchart of the operation of a switching control circuit 203b. [Figure 15] FIG. 10 is a diagram illustrating an example of a switching control circuit 203c. [Figure 16] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 203c. [Figure 17] FIG. 10 is a diagram showing an example of a flowchart of the operation of a switching control circuit 203c. [Figure 18] FIG. 10 is a diagram illustrating an example of a switching control circuit 203d. [Figure 19] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 203d. [Figure 20] FIG. 10 is a diagram illustrating an example of the operation of a switching control circuit 203d. [Figure 21] FIG. 10 is a diagram showing an example of a flowchart of the operation of a switching control circuit 203d.

Best Mode for Carrying Out the Invention

[0011] From the descriptions in this specification and the accompanying drawings, at least the following matters become clear. Hereinafter, the "circuit" in this embodiment includes not only analog circuits and wired logic type logic circuits, but also functional blocks (or means) included in a DSP (Digital Signal Processor), a microcomputer, etc. that can execute digital arithmetic processing.

[0012] Hereinafter, preferred embodiments of the present invention will be described while referring to the drawings. The same or equivalent components, members, etc. shown in each drawing are denoted by the same reference numerals, and redundant explanations will be omitted as appropriate.

[0013] =====This Embodiment===== <<<Outline of AC-DC Converter 10>>> FIG. 1 is a diagram showing the configuration of an AC-DC converter 10 according to an embodiment of the present invention. The AC-DC converter 10 is a boost-type PFC circuit that generates an output voltage Vout at a target level from the AC voltage Vac of a commercial power supply to an output terminal VOUTP. Further, the AC-DC converter 10 outputs the output voltage Vout to the load 11 via the output terminal VOUTP. Note that the output terminal VOUTN is grounded.

[0014] The AC-DC converter 10 includes an input line filter 20, a full-wave rectifier circuit 21, capacitors 22, 23, coils La, Lb, diodes 24a, 24b, a power factor correction IC 25, NMOS transistors 26a, 26b, capacitors 27a, 27b, 28a, 28b, and resistors 30, 31. Note that the AC-DC converter 10 corresponds to a "power supply circuit".

[0015] The input line filter 20 attenuates both noise from the AC power supply (e.g., nodes N1 and N2) and noise from the AC-DC converter 10 (e.g., nodes N3 and N4). An AC voltage Vac is applied to nodes N1 and N2 of the input line filter 20. The input line filter 20 then applies the AC voltage Vac, with noise attenuated, to nodes N3 and N4.

[0016] 2A, the input line filter 20 includes capacitors 100 and 102 and a common mode coil 101. With this configuration, the input line filter 20 can attenuate both so-called common mode noise and differential noise.

[0017] Specifically, the input line filter 20 attenuates common mode noise using a common mode coil 101. On the other hand, the input line filter 20 attenuates differential noise from the AC power supply side using a capacitor 100, and attenuates differential noise from the AC-DC converter 10 side using a capacitor 102.

[0018] However, as shown in FIG. 2B, the actual common mode coil 101 has a stray inductance Le as a parasitic component. This stray inductance Le, together with the capacitor 100 or 102, forms an LC resonant circuit. If resonance occurs between the stray inductance Le and the capacitor 102, the voltage between the nodes N3 and N4 will fluctuate with a period corresponding to the resonant frequency. As a result, the output voltage of the full-wave rectifier circuit 21 (described later) will fluctuate.

[0019] The full-wave rectifier circuit 21 in Figure 1 full-wave rectifies a predetermined input AC voltage Vac and outputs it as an input voltage Vrec to the capacitor 22 and the coils La and Lb. The AC voltage Vac has an effective value of 100 to 240 V and a frequency of 50 to 60 Hz, for example. Hereinafter, in this embodiment, the voltage is basically the potential difference with respect to a reference point (GND in the figure), but the AC voltage Vac refers to the voltage between terminals.

[0020] Capacitor 22 smoothes the input voltage Vrec, and capacitor 23 is an element into which the output voltages of the two boost chopper circuits are charged. Coil La, diode 24a, and NMOS transistor 26a, together with capacitor 23, form a "first system boost chopper circuit." Coil Lb, diode 24b, and NMOS transistor 26b, together with capacitor 23, form a "second system boost chopper circuit." Therefore, the charging voltage of capacitor 23 becomes the DC output voltage Vout. The first system boost chopper circuit corresponds to the "first circuit," and the second system boost chopper circuit corresponds to the "second circuit."

[0021] When the inductor current ILa flows in the direction of the arrow in the coil La, the flow direction of the inductor current ILa is the positive direction, and when the inductor current ILa flows in the opposite direction to the arrow, the flow direction of the inductor current ILa is the negative direction. Note that the coil La corresponds to the "first inductor."

[0022] When the inductor current ILb flows in the direction of the arrow in the coil Lb, the direction of the inductor current ILb is positive, and when the inductor current ILb flows in the opposite direction to the arrow, the direction of the inductor current ILb is negative. Note that the coil Lb corresponds to a "second inductor."

[0023] The power factor correction IC 25 is an integrated circuit that controls the switching of the NMOS transistors 26a and 26b so that the output voltage Vout reaches a target level (e.g., 400 V) while improving the input power factor of the AC-DC converter 10. Specifically, the power factor correction IC 25 drives the NMOS transistor 26a based on the inductor current ILa flowing through the coil La and the output voltage Vout. The inductor current ILa corresponds to the "first inductor current."

[0024] Furthermore, the power factor correction IC 25 drives the NMOS transistor 26b based on the inductor current ILb flowing through the coil Lb and the on-period of the NMOS transistor 26a. The power factor correction IC 25 is provided with terminals ZCDa, ZCDb, FB, OUTa, and OUTb, which will be described in detail later. In this embodiment, for convenience, terminals other than the terminal ZCDa and the like of the power factor correction IC 25 (for example, a ground terminal) are omitted. Furthermore, the inductor current ILb corresponds to a "second inductor current."

[0025] The NMOS transistors 26a and 26b are power transistors for controlling the power to the load 11 of the AC-DC converter 10. In this embodiment, the NMOS transistors 26a and 26b are N-type MOS (Metal Oxide Semiconductor) transistors, but are not limited to this and may be other switching elements such as bipolar transistors. The gate electrode of the NMOS transistor 26a is connected to the terminal OUTa, and the gate electrode of the NMOS transistor 26b is connected to the terminal OUTb. The NMOS transistor 26a corresponds to a "first transistor," and the NMOS transistor 26b corresponds to a "second transistor."

[0026] The capacitors 27a and 28a are elements for detecting that the current value of the inductor current ILa flowing through the coil La becomes almost zero (hereinafter, for convenience, "almost zero" will be simply referred to as "zero") after the NMOS transistor 26a is turned off. Specifically, the capacitors 27a and 28a are connected in series and in parallel with the NMOS transistor 26a between the source and drain of the NMOS transistor 26a. Note that "almost zero" corresponds to a "first value."

[0027] For example, when the NMOS transistor 26a is turned off, the voltage Vswa, which is the drain voltage of the NMOS transistor 26a, rises. Then, when the inductor current ILa stops flowing, the voltage Vswa drops. The capacitors 27a and 28a function as a voltage divider circuit that divides the voltage Vswa, so the voltage Vzcda at the connection point between the capacitors 27a and 28a corresponds to the voltage Vswa. Therefore, the power factor correction IC 25 can detect the timing at which the inductor current ILa becomes zero by detecting the voltage Vzcda. The voltage Vzcda is applied to the terminal ZCDa of the power factor correction IC 25. When the current value of the inductor current ILa becomes zero, the voltage Vzcda becomes the reference voltage Vref1.

[0028] Similarly, capacitors 27b and 28b are elements for detecting that the current value of inductor current ILb flowing through coil Lb becomes zero after NMOS transistor 26b is turned off. Specifically, capacitors 27b and 28b are connected in series and in parallel with NMOS transistor 26b between the source and drain of NMOS transistor 26b. Note that "almost zero" corresponds to "second value."

[0029] For example, when the NMOS transistor 26b is turned off, the voltage Vswb, which is the drain voltage of the NMOS transistor 26b, rises. Then, when the inductor current ILb stops flowing, the voltage Vswb drops. The capacitors 27b and 28b function as a voltage divider circuit that divides the voltage Vswb, so the voltage Vzcdb at the connection point between the capacitors 27b and 28b corresponds to the voltage Vswb. Therefore, the power factor correction IC 25 can detect the timing at which the inductor current ILb becomes zero by detecting the voltage Vzcdb. The voltage Vzcdb is applied to the terminal ZCDb of the power factor correction IC 25. When the current value of the inductor current ILb becomes zero, the voltage Vzcdb becomes equal to the reference voltage Vref1.

[0030] The resistors 30 and 31 form a voltage divider circuit that divides the output voltage Vout and generates a feedback voltage Vfb used to switch the NMOS transistors 26a and 26b. The feedback voltage Vfb generated at the node to which the resistors 30 and 31 are connected is applied to the terminal FB.

[0031] <<<About the Power Factor Correction IC25>>> ==Configuration of Power Factor Correction IC25== 3 is a diagram showing an example of the power factor correction IC 25. The power factor correction IC 25 includes analog-to-digital converters (ADCs) 200 to 202, a switching control circuit 203, and buffer circuits 204 and 205. The switching control circuit 203 is formed of a digital circuit.

[0032] The AD converter 200 converts the voltage Vzcda into a digital value, the AD converter 201 converts the voltage Vzcdb into a digital value, and the AD converter 202 converts the feedback voltage Vfb into a digital value.

[0033] The switching control circuit 203 is a circuit that outputs drive signals Vqa and Vqb for driving the NMOS transistors 26a and 26b based on the feedback voltage Vfb and voltages Vzcda and Vzcdb corresponding to the inductor currents ILa and ILb, respectively. The switching control circuit 203 is a digital circuit configured with wired logic circuits that perform various calculations, and is configured to include, for example, logic gates, flip-flops, and memories. However, the switching control circuit 203 may also be a DSP (Digital Signal Processor) or a microcomputer. Details of the switching control circuit 203 will be described later.

[0034] The buffer circuit 204 is a drive circuit that drives the NMOS transistor 26a based on the drive signal Vqa. Specifically, the buffer circuit 204 turns on the NMOS transistor 26a when the drive signal Vqa goes high (hereinafter referred to as "H" level), and turns off the NMOS transistor 26a when the drive signal Vqa goes low (hereinafter referred to as "L" level).

[0035] Similarly, the buffer circuit 205 is a drive circuit that drives the NMOS transistor 26b based on the drive signal Vqb. Specifically, the buffer circuit 205 turns on the NMOS transistor 26b when the drive signal Vqb goes high, and turns off the NMOS transistor 26b when the drive signal Vqb goes low.

[0036] ==Configuration of Switching Control Circuit 203a== 4 shows an example of a switching control circuit 203a which is an embodiment of the switching control circuit 203. The switching control circuit 203a outputs drive signals Vqa and Vqb based on inductor currents ILa and ILb and feedback voltage Vfb.

[0037] Specifically, when the load 11 is in a light load state, the switching control circuit 203a operates the boost chopper circuit of the first system and switches on the NMOS transistor 26a. On the other hand, when the load 11 is in a heavy load state, the switching control circuit 203a operates the boost chopper circuits of the first and second systems and switches on the NMOS transistors 26a and 26b.

[0038] A light load on the load 11 means, for example, a state in which the current flowing through the load 11 is smaller than a predetermined value, and a heavy load on the load 11 means, for example, a state in which the current steadily flowing through the load 11 is larger than a predetermined value.

[0039] Although details will be described later, in this embodiment, when the load 11 becomes heavy and the ON period during which the NMOS transistor 26a is turned on becomes longer than the predetermined period Ta, the two boost chopper circuits are operated. On the other hand, when the load 11 becomes light and the ON period during which the NMOS transistors 26a and 26b are turned on becomes shorter than the predetermined period Tb while the two boost chopper circuits are operating, only the first boost chopper circuit is operated.

[0040] The switching control circuit 203 a includes an on-period output circuit 300 , detection circuits 301 and 303 , a first drive circuit 302 , an output circuit 304 , and a second drive circuit 305 .

[0041] The on-period output circuit 300 is a circuit that outputs the on-periods Vy and Vz of the NMOS transistors 26a and 26b based on the feedback voltage Vfb.

[0042] The on-period output circuit 300 includes an error amplifier circuit (ERR) 400, a PI control circuit (PI) 401, a decision circuit 402, a switch 403, and a multiplication circuit 404. The "on-period" is, for example, a digital value indicating a voltage.

[0043] The error amplifier circuit 400 calculates an error E1, which is the difference between a reference voltage Vref0, which is the reference for a target level of output voltage Vout (for example, 400 V), and the feedback voltage Vfb. The feedback voltage Vfb is a digital value converted from the feedback voltage Vfb by the AD converter 202.

[0044] The PI control circuit 401 calculates the integral value of the error E1, and outputs the on-period Vx for matching the level of the feedback voltage Vfb with the level of the reference voltage Vref0 based on the integral value.

[0045] The decision circuit 402 determines whether the on-period Vx is equal to or longer than a predetermined period Ta. Then, based on the decision, the decision circuit 402 determines whether the on-period output circuit 300 should output the on-period Vy or Vz. Specifically, when the on-period Vx is shorter than the predetermined period Ta, the decision circuit 402 controls the switch 403 so that the on-period output circuit 300 outputs the on-period Vx as the on-period Vy. In other words, the decision circuit 402 controls the switch 403 so that the PI control circuit 401 and the first drive circuit 302 are connected. In this case, the AC-DC converter 10 operates using only the boost chopper circuit of the first system.

[0046] On the other hand, when the on-period Vx is, for example, equal to or greater than the predetermined period Ta, the decision circuit 402 controls the switch 403 to connect the PI control circuit 401 and the multiplication circuit 404. In this embodiment, the multiplication circuit 404 multiplies the input on-period Vx by 0.5 and outputs an on-period Vz that is half the on-period Vx. Note that when the PI control circuit 401 and the first drive circuit 302 are connected, the multiplication circuit 404 outputs an on-period Vz of "0."

[0047] Therefore, when the on-period Vx is shorter than the predetermined period Ta, the first drive circuit 302 turns on the NMOS transistor 26a during the on-period Vy (=Vx), and only the boost chopper circuit of the first system operates. On the other hand, when the on-period Vx is longer than the predetermined period Ta, the first drive circuit 302 and the second drive circuit 305 turn on the NMOS transistors 26a and 26b during the on-period Vz (=Vx / 2). Therefore, the AC-DC converter 10 operates using the boost chopper circuits of the first and second systems.

[0048] The detection circuit 301 detects whether the inductor current ILa has decreased to approximately zero. Specifically, when the voltage value of the voltage Vzcda corresponding to the inductor current ILa becomes equal to the reference voltage Vref1, the detection circuit 301 outputs an “H” level signal DETa indicating that the inductor current ILa has decreased to approximately zero.

[0049] ===First driving circuit 302=== The first drive circuit 302 drives the NMOS transistor 26a based on the drive signal Vqa that corresponds to the input on-periods Vy and Vz. Specifically, when the inductor current ILa decreases and becomes almost zero and the detection circuit 301 outputs an "H" level signal DETa, the first drive circuit 302 outputs the drive signal Vqa that turns on the NMOS transistor 26a.

[0050] Thereafter, if the on-period Vx is shorter than the predetermined period Ta, the first drive circuit 302 outputs the drive signal Vqa that turns off the NMOS transistor 26a after the on-period Vy has elapsed.

[0051] On the other hand, when the on-period Vx is equal to or longer than the predetermined period Ta, the first drive circuit 302 outputs a drive signal Vqa that turns off the NMOS transistor 26a when the on-period Vz has elapsed since the NMOS transistor 26a was turned on. The on-period Vy or Vz used in the first drive circuit 302 corresponds to the "first period."

[0052] The detection circuit 303 detects whether the inductor current ILb decreases to approximately zero and the voltage value of the voltage Vzcdb corresponding to the inductor current ILb becomes the reference voltage Vref1. Specifically, when the voltage value of the voltage Vzcdb corresponding to the inductor current ILb becomes the reference voltage Vref1, the detection circuit 303 outputs an “H” level signal DETb.

[0053] ===Output circuit 304=== The output circuit 304 outputs the timing of a half cycle Th of the switching cycle of the NMOS transistor 26a. Specifically, when the first drive circuit 302 outputs an "H" level drive signal Vqa, the output circuit 304 starts measuring the switching cycle of the NMOS transistor 26a. Then, when the first drive circuit 302 outputs an "H" level drive signal Vqa again, the output circuit 304 calculates the half cycle Th of the switching cycle of the NMOS transistor 26a and outputs an "H" level signal HALF_T for a predetermined period Thalf that includes the timing of the half cycle Th. Note that the predetermined period Thalf is a period that is determined in advance and corresponds to a "predetermined period."

[0054] ===Second driving circuit 305=== The second drive circuit 305 drives the NMOS transistor 26b based on the drive signal Vqb that corresponds to the input on-period Vz. Specifically, when the on-period Vx is shorter than a predetermined period Ta, the second drive circuit 305 outputs the drive signal Vqb that turns off the NMOS transistor 26b.

[0055] On the other hand, when the on-period Vx is equal to or longer than the predetermined period Ta, the second drive circuit 305 outputs a drive signal Vqb that turns on the NMOS transistor 26b when the inductor current ILb decreases to approximately zero while the output circuit 304 outputs an “H” level signal HALF_T and the detection circuit 303 outputs an “H” level signal DETb.

[0056] After that, when the on-period Vz has elapsed, the second drive circuit 305 outputs the drive signal Vqb that turns off the NMOS transistor 26b. The on-period Vz used by the second drive circuit 305 corresponds to the "second period."

[0057] ==Operation using only the first boost chopper circuit== 5 is a diagram showing an example of the operation of the switching control circuit 203a when only the boost chopper circuit of the first system operates. In this case, the on-period output circuit 300 outputs the on-period Vy, which is the on-period Vx corresponding to the feedback voltage Vfb, and the second drive circuit 305 outputs the drive signal Vq2 that turns off the NMOS transistor 26b.

[0058] Therefore, the following describes the operation of the AC-DC converter 10 when it generates an output voltage Vout at a target level from a predetermined AC voltage Vac and supplies power to a certain load. At the same time, the following also describes the operation of the first drive circuit 302 when it outputs a drive signal Vqa that drives the NMOS transistor 26a based on the on-period Vy.

[0059] First, at time t0, the inductor current ILa decreases and becomes zero, and the detection circuit 301 changes the signal DETa to the "H" level. Then, when the signal DETa becomes the "H" level, the first drive circuit 302 outputs the "H" level signal Vqa.

[0060] When the drive signal Vqa goes to the "H" level, the NMOS transistor 26a turns on, and the inductor current ILa increases.

[0061] Furthermore, when the drive signal Vqa becomes "H" level and the on-period Vy has elapsed, the first drive circuit 302 outputs the drive signal Vqa at "L" level, as shown at time t1, to turn off the NMOS transistor 26a. As a result, the inductor current ILa gradually decreases. At time t2, the inductor current ILa decreases and becomes zero, and the operation at time t0 is repeated.

[0062] When the AC-DC converter 10 generates an output voltage Vout of a target level from a predetermined AC voltage Vac, the capacitance of the capacitor 23 is sufficiently large, and the feedback voltage Vfb is substantially constant within a period of about one cycle of Vac. As a result, the on-period Vy output from the on-period output circuit 300 also becomes substantially constant, and the period during which the NMOS transistor 26a is on (for example, the period from time t0 to t1) also becomes substantially constant.

[0063] Furthermore, when the NMOS transistor 26a is turned on, if the level of the voltage Vrec obtained by rectifying the AC voltage Vac increases, the current value of the inductor current ILa also increases. As a result, as shown in FIG. 6, the waveform of the peak value of the inductor current ILa becomes similar to the waveform of the voltage Vrec.

[0064] Furthermore, if the peak value of the inductor current ILa when the NMOS transistor 26a turns off increases, the time it takes for the inductor current ILa to reach zero when the NMOS transistor 26a turns off increases. Therefore, when the level of the voltage Vrec is low, the switching frequency of the NMOS transistor 26a increases, and when the level of the voltage Vrec is high, the switching frequency of the NMOS transistor 26a decreases.

[0065] ==Operation by boost chopper circuits of the first and second systems== Fig. 7 is a diagram showing an example of the operation of the switching control circuit 203a. In Fig. 7, the operation of the switching control circuit 203a when transitioning from a state in which only the boost chopper circuit of the first system is operating to a state in which the boost chopper circuits of the first and second systems are operating will be described.

[0066] It is assumed that, before time t10, the feedback voltage Vfb is a voltage at which the PI control circuit 401 outputs an on-period Vx shorter than the predetermined period Ta, and then outputs an on-period Vx of the predetermined period Ta. It is also assumed that the on-period output circuit 300 outputs an on-period Vy that changes from a period shorter than the predetermined period Ta to the predetermined period Ta. Therefore, the on-period output circuit 300 causes the second drive circuit 305 to turn off the NMOS transistor 26b and stop switching. It is also assumed that, before time t10, the switching control circuit 203a operates only with the first-system boost chopper circuit, as described in FIG. 5. It is also assumed that the operations of steps S10 to S12 in FIG. 8 are always performed, and that, before time t10, the decision circuit 402 determines that the on-period Vx is shorter than the predetermined period Ta (NO in step S13 in FIG. 8).

[0067] At time t10, when the drive signal Vqa changes to the "L" level, the on-period Vx becomes equal to or longer than the predetermined period Ta (YES in step S13 of FIG. 8), so the decision circuit 402 outputs the "H" level signal SW. As a result, the decision circuit 402 causes the switch 403 to connect the PI control circuit 401 and the multiplication circuit 404.

[0068] Then, the multiplication circuit 404 calculates the on-period Vz by multiplying the on-period Vx by 0.5 (i.e., Ta / 2) (step S15 in FIG. 8). Since the inductor current ILb is zero, the second drive circuit 305 outputs a drive signal Vqb that turns on the NMOS transistor 26b. When the NMOS transistor 26b is turned on, the inductor current ILb starts to increase. That is, the AC-DC converter 10 operates using the first and second boost chopper circuits (step S16 in FIG. 8).

[0069] At time t11, when the on-period of the NMOS transistor 26b reaches the on-period Vz of Ta / 2, the second drive circuit 305 outputs the drive signal Vqb to turn off the NMOS transistor 26b. After that, the inductor current ILb starts to decrease. Also, at time t11, when the inductor current ILa becomes zero, the first drive circuit 302 outputs the drive signal Vqa to turn on the NMOS transistor 26a.

[0070] At time t12 when the inductor current ILb decreases to zero, the second drive circuit 305 outputs the drive signal Vqb that turns on the NMOS transistor 26b. After that, the second drive circuit 305 repeats the same operation.

[0071] At time t13 when the on-period of the NMOS transistor 26a becomes the on-period Vz of "50", the first drive circuit 302 outputs the drive signal Vqa that turns off the NMOS transistor 26a. After that, the inductor current ILa starts to decrease.

[0072] At time t14 when the inductor current ILa becomes zero, the first drive circuit 302 outputs the drive signal Vqa that turns on the NMOS transistor 26a. After that, the first drive circuit 302 repeats the same operation.

[0073] In this way, when the on-period Vx is shorter than the predetermined period Ta, the switching control circuit 203a drives only the NMOS transistor 26a for the on-period Vy, which is the on-period Vx based on the feedback voltage Vfb. On the other hand, when the on-period Vx is longer than the predetermined period Ta, the switching control circuit 203a drives the NMOS transistors 26a and 26b for the on-period Vz, which is half the on-period Vx.

[0074] The above describes the operation when the AC-DC converter 10 transitions to interleaved operation. If the frequencies of the drive signals Vqa and Vqb differ even slightly, it will be impossible to turn on the NMOS transistors 26a and 26b with a predetermined phase relationship (i.e., a 180° phase difference between the timings at which the NMOS transistors 26a and 26b turn on) so that the two boost chopper circuits perform interleaved operation.

[0075] In particular, if the switching frequencies of the drive signals Vqa and Vqb differ slightly, this difference in frequency may produce a low-frequency component known as a beat frequency, which may cause resonance in the input line filter 20. Furthermore, if the input line filter 20 enters a resonant state, the full-wave rectified voltage Vrec may fluctuate, which may cause slight differences in the frequencies of the drive signals Vqa and Vqb.

[0076] ==Operation of Switching Control Circuit 203a== 9 is a diagram showing an example of the operation of the switching control circuit 203a. Note that the period from time t20 to t22 shows the operation when the first timing at which the inductor current ILb becomes zero coincides with the half-cycle Th. On the other hand, the period from time t23 onwards shows the operation when the first timing at which the inductor current ILb becomes zero deviates from the half-cycle Th. In this case, the rectified voltage Vrec decreases. Also, it is assumed that the NMOS transistors 26a and 26b operate during an on-period Vz during which they are on for half the switching period.

[0077] The NMOS transistor 26a is turned on before time t20, and is turned off at time t20 after the on-period Vz has elapsed, causing the voltage Vzcda to become higher than the reference voltage Vref1, and the inductor current ILa to start decreasing.

[0078] On the other hand, the NMOS transistor 26b is turned off before time t20, and the inductor current ILb decreases and becomes zero. Therefore, the detection circuit 303 outputs an “H” level signal DETb. Time t20 is the timing when the half cycle Th begins, and the output circuit 304 outputs an “H” level signal HALF_T (step S20 in FIG. 10). Since the inductor current ILb becomes zero (YES in step S21 in FIG. 10), the second drive circuit 305 outputs a drive signal Vqb that turns on the NMOS transistor 26b (step S22 in FIG. 10). Then, the voltage Vzcdb becomes lower than the reference voltage Vref1, and the inductor current ILb begins to increase. Note that the period during which the output circuit 304 outputs an “H” level signal HALF_T shown in FIG. 9 and subsequent figures is merely an example. The period may start so that the timing when the half cycle Th begins is in the middle, or the period before the half cycle Th may be longer than the period after the half cycle Th.

[0079] At time t21, when the on-period Vz has elapsed since time t20, the NMOS transistor 26b is turned off, and the inductor current ILb begins to decrease. The decreased inductor current ILa then becomes zero, and the detection circuit 301 outputs an "H" level signal DETa, causing the first drive circuit 302 to output a drive signal Vqa that turns on the NMOS transistor 26a. The same operation is repeated from time t22 onwards.

[0080] In this way, when the inductor current ILb becomes zero while the output circuit 304 is outputting the "H" level signal HALF_T, the second drive circuit 305 outputs the drive signal Vqb that turns on the NMOS transistor 26b. Therefore, the phase difference between the timings at which the NMOS transistors 26a and 26b are turned on tends to be constant.

[0081] Furthermore, although the case where the rectified voltage Vrec fluctuates low has been described here, if the rectified voltage Vrec fluctuates high, the timing at which the inductor current ILb becomes zero may be delayed relative to the period during which the signal HALF_T is at the “H” level, and may occur during the period during which the signal HALF_T is at the “L” level.

[0082] In this case, if the number of times n that the NMOS transistor 26b could not be turned on is less than the predetermined number of times N (NO in step S23 in FIG. 10), the second drive circuit 305 waits until the output circuit 304 outputs the signal HALF_T at the “H” level (step S20 in FIG. 10). On the other hand, if the number of times n that the NMOS transistor 26b could not be turned on is the predetermined number of times N (YES in step S23 in FIG. 10), the second drive circuit 305 turns on the NMOS transistor 26b at the timing when the output circuit 304 next outputs the signal HALF_T (step S24 in FIG. 10).

[0083] The above describes a case where the timing when the inductor current ILb becomes zero for the first time falls within the period when the output circuit 304 is outputting the "H" level signal HALF_T. Below, we will describe a case where the timing when the inductor current ILb becomes zero for the second or subsequent time falls within the period when the output circuit 304 is outputting the "H" level signal HALF_T.

[0084] Before time t23, the NMOS transistor 26b is turned off, and at time t23, when the inductor current ILb first becomes zero, the detection circuit 303 outputs an "H" level signal DETb. However, time t23 is not the timing of a half period Th, and the output circuit 304 outputs an "L" level signal HALF_T, so the second drive circuit 305 does not output the drive signal Vqb that turns on the NMOS transistor 26b (steps S23 and S24 in FIG. 10).

[0085] At time t24 when the inductor current ILb becomes zero for the second time, the detection circuit 303 outputs the signal DETb of "H" level. Furthermore, time t24 is the timing of the half period Th, and the output circuit 304 outputs the signal HALF_T of "H" level, so the second drive circuit 305 outputs the drive signal Vqb that turns on the NMOS transistor 26b (steps S21 and S22 in FIG. 10).

[0086] At time t25, when the on-period Vz has elapsed since time t24, the second drive circuit 305 outputs the drive signal Vqb that turns off the NMOS transistor 26b. After that, the inductor current ILb starts to decrease. Note that the same operation is repeated from time t26 onwards.

[0087] In this way, even if the inductor current ILb becomes zero while the output circuit 304 is outputting the "L" level signal HALF_T, the second drive circuit 305 does not output the drive signal Vqb that turns on the NMOS transistor 26b. Thereafter, when the inductor current ILb becomes zero while the output circuit 304 is outputting the "H" level signal HALF_T, the second drive circuit 305 outputs the drive signal Vqb that turns on the NMOS transistor 26b. Therefore, the phase difference between the timings at which the NMOS transistors 26a and 26b are turned on tends to be constant. This makes it possible to provide a switching control circuit that suppresses deviations in the phase difference even when the rectified voltage fluctuates during interleaving operation.

[0088] == Variations == ==Configuration of Switching Control Circuit 203b== 11 shows an example of a switching control circuit 203b, which is one embodiment of the switching control circuit 203. When the difference between the phase difference in the switching timing of the drive signals Vqa and Vqb and the half cycle Th becomes equal to or greater than a predetermined value, the switching control circuit 203b turns on the NMOS transistor 26b in the half cycle Th.

[0089] The switching control circuit 203b includes an on-period output circuit 300, detection circuits 301, 303, and 306, a first drive circuit 302, an output circuit 304, and a second drive circuit 305.

[0090] The detection circuit 306 detects the difference between the phase difference of the switching of the NMOS transistors 26a and 26b and the half-cycle Th. Specifically, the detection circuit 306 counts the phase difference from when the NMOS transistor 26a is switched to when the NMOS transistor 26b is switched based on the drive signals Vqa and Vqb, and detects whether the difference ΔT between the phase difference and the half-cycle Th is greater than a predetermined value T0. If the detection circuit 306 detects that the difference ΔT between the phase difference and the half-cycle Th is greater than the predetermined value T0, it continues counting. If the count value, i.e., the number of times n1, is greater than the predetermined number N1, the detection circuit 306 outputs a signal DIFF to the second drive circuit 305 to turn on the NMOS transistor 26b at the timing of the half-cycle Th after the NMOS transistor 26a is turned on. The detection circuit 306 then resets the number n1. The detection circuit 306 corresponds to a "detection circuit," and the signal DIFF corresponds to a "detection result."

[0091] Furthermore, the second drive circuit 305 turns on the NMOS transistor 26b when a half cycle Th has elapsed since the NMOS transistor 26a was turned on, based on the signal DIFF that is output when the difference ΔT is greater than a predetermined value T0. In this modification, the phase difference is the difference in the timing at which the NMOS transistors 26a and 26b are switched on, but it can also be the difference in the timing at which the NMOS transistors 26a and 26b are turned on. In this case, the phase difference can be detected more accurately.

[0092] The timing at which the NMOS transistor 26a is switched corresponds to the "first timing," and the timing at which the NMOS transistor 26b is switched corresponds to the "second timing." The phase difference corresponds to the "first difference," and the difference ΔT corresponds to the "second difference." The predetermined value T0 corresponds to the "first predetermined value."

[0093] ===Operation of the switching control circuit 203b when the difference ΔT is less than the predetermined value T0=== 12 is a diagram showing an example of the operation of the switching control circuit 203b. Note that the period from time t30 to t32 shows the operation when the NMOS transistor 26b is turned on at the timing when a half cycle Th has elapsed since the NMOS transistor 26a was turned on. Also, it is assumed that the NMOS transistors 26a and 26b are operating in an on-period Vz during which they are on for half the switching cycle.

[0094] At time t30, the inductor current ILa decreases to zero, and the detection circuit 301 outputs a high-level signal DETa, causing the first drive circuit 302 to turn on the NMOS transistor 26a. As a result, the voltage Vzcda becomes lower than the reference voltage Vref1, and the inductor current ILa begins to increase. Meanwhile, the NMOS transistor 26b was turned on before time t30, so the inductor current ILb increases and the on-period Vz has elapsed, causing the second drive circuit 305 to turn off the NMOS transistor 26b.

[0095] At time t31, an on-period Vz has elapsed since the NMOS transistor 26a was turned on, and the first drive circuit 302 turns off the NMOS transistor 26a. Meanwhile, while the inductor current ILb is decreasing and the output circuit 304 is outputting the signal HALF_T at an "H" level, the detection circuit 303 outputs the signal DETb at an "H" level, and the second drive circuit 305 turns on the NMOS transistor 26b (steps S20, S21, and S22 in FIG. 14). As a result, the voltage Vzcdb becomes lower than the reference voltage Vref1, and the inductor current ILb begins to increase.

[0096] Here, the period from when the NMOS transistor 26a turns on to when the NMOS transistor 26b turns on is defined as period P1, and half the period Th is defined as period P2. When operating as described in FIG. 12, the periods P1 and P2 are equal, and the detection circuit 306 calculates the difference ΔT to be "0" (step S30 in FIG. 14). Then, because the difference ΔT is smaller than the predetermined value T0, the detection circuit 306 does not output the "H" level signal DIFF (NO in step S31 in FIG. 14).

[0097] The second driving circuit 305 does not turn on the NMOS transistor 26b in the half period Th. Note that the same operation is repeated from time t32 onwards.

[0098] ===Operation of the switching control circuit 203b when the difference ΔT is equal to or greater than the predetermined value T0=== 13 is a diagram illustrating an example of the operation of the switching control circuit 203b. The diagram illustrates the operation when the initial timing at which the inductor current ILb becomes zero is shifted from the half-cycle Th. In the case of FIG. 13, the rectified voltage Vrec is assumed to decrease due to fluctuations.

[0099] At time t40, the output circuit 304 outputs the "H" level signal HALF_T, the inductor current ILb becomes zero, and the detection circuit 303 outputs the "H" level signal DETb, so that the second drive circuit 305 turns on the NMOS transistor 26b (steps S20, S21, and S22 in FIG. 14). As a result, the voltage Vzcdb becomes lower than the reference voltage Vref1, and the inductor current ILb starts to increase.

[0100] At time t41, the inductor current ILa becomes zero and the detection circuit 301 outputs the signal DETa at the "H" level, and the first drive circuit 302 turns on the NMOS transistor 26a.

[0101] At time t42, when the on-period Vz has elapsed since time t40, the second drive circuit 305 turns off the NMOS transistor 26b, so that the voltage Vzcdb becomes higher than the reference voltage Vref1, and the inductor current ILb starts to decrease.

[0102] At time t43, when the on-period Vz has elapsed since time t41, the first drive circuit 302 turns off the NMOS transistor 26a. As a result, the voltage Vzcda becomes higher than the reference voltage Vref1, and the inductor current ILa begins to decrease. The inductor current ILb then becomes zero for the first time after the NMOS transistor 26b is turned on. Therefore, the detection circuit 303 outputs an "H" level signal DETb, but because the output circuit 304 outputs an "L" level signal HALF_T, the second drive circuit 305 does not turn on the NMOS transistor 26b (NO in step S23 in FIG. 14).

[0103] At time t44, the output circuit 304 outputs the signal HALF_T at the "H" level (step S20 in FIG. 14).

[0104] At time t45 when the inductor current ILb becomes zero for the second time, the output circuit 304 outputs the signal HALF_T at the “H” level, and the detection circuit 303 outputs the signal DETb at the “H” level, so the second drive circuit 305 turns on the NMOS transistor 26b (steps S21 and S22 in FIG. 14).

[0105] In this case, because period P2 is shorter than period P1, detection circuit 306 calculates difference ΔT (step S30 in FIG. 14) and detects that difference ΔT is greater than predetermined value T0 (YES in step S31 in FIG. 14). Then, detection circuit 306 counts the number of times n1 that difference ΔT is greater than predetermined value T0 (step S32 in FIG. 14), and when the number of times n1 becomes greater than predetermined value N1 ("0" in the case of the operation in FIG. 13) (step S33 in FIG. 14), detection circuit 306 outputs signal DIFF at an "H" level. Note that predetermined value N1 corresponds to a "second predetermined value."

[0106] At time t46, the inductor current ILa becomes zero and the detection circuit 301 outputs the signal DETa at the "H" level, and the first drive circuit 302 turns on the NMOS transistor 26a.

[0107] At time t47, when the on-period Vz has elapsed since time t45, the second drive circuit 305 turns off the NMOS transistor 26b, so that the voltage Vzcdb becomes higher than the reference voltage Vref1, and the inductor current ILb starts to decrease.

[0108] At time t48, when the output circuit 304 outputs the signal HALF_T at "H" level, the second drive circuit 305 turns on the NMOS transistor 26b.

[0109] In this way, when the periods P1 and P2 are not equal, the detection circuit 306 outputs a high-level signal DIFF because the difference ΔT between the phase difference between the switching of the NMOS transistors 26a and 26b and the half period Th is greater than the predetermined value T0. Then, the second drive circuit 305 turns on the NMOS transistor 26b during the half period Th.

[0110] In this operation, when the difference ΔT becomes larger than a predetermined value T0, the NMOS transistor 26b is turned on in half a period Th, so that the phase difference between the timings at which the NMOS transistors 26a and 26b are turned on tends to be constant.

[0111] ==Configuration of Switching Control Circuit 203c== 15 shows an example of a switching control circuit 203c that is an embodiment of the switching control circuit 203. When the number of times that the inductor currents ILa and ILb become zero reaches a set value M, the switching control circuit 203c turns on each of the NMOS transistors 26a and 26b.

[0112] The switching control circuit 203c includes an on-period output circuit 300, detection circuits 301 and 303, a first drive circuit 302, an output circuit 304, a second drive circuit 305, counters 307 and 308, a setting circuit 309, and a memory circuit 310.

[0113] The counter 307 counts the number of times the inductor current ILa becomes zero. Specifically, the counter 307 counts the number of times the detection circuit 301 outputs the "H" level signal DETa. When the count value of the counter 307 reaches a set value M, the first drive circuit 302 turns on the NMOS transistor 26a. The counter 307 corresponds to a "first counter."

[0114] The counter 308 counts the number of times the inductor current ILb becomes zero. Specifically, the counter 308 counts the number of times the detection circuit 303 outputs an "H" level signal DETb. Note that the second drive circuit 305 turns on the NMOS transistor 26b when the count value of the counter 308 reaches a set value M. Note that the counter 308 corresponds to a "second counter."

[0115] The setting circuit 309 sets the set value M based on a predetermined switching frequency and a predetermined set value of the NMOS transistors 26a and 26b. Specifically, the setting circuit 309 sets in advance, in the storage circuit 310, the predetermined set value PreSET, which determines how many times the inductor currents ILa and ILb must become zero before the NMOS transistors 26a and 26b are turned on. Then, the setting circuit 309 updates the set value M in the storage circuit 310 based on the predetermined switching frequency, which is the predetermined maximum frequency of the NMOS transistors 26a and 26b.

[0116] More specifically, the setting circuit 309 detects the switching period of the NMOS transistors 26a and 26b based on the drive signals Vqa and Vqb, and then updates the setting value M in the storage circuit 310 based on the predetermined setting value PreSET so that the switching frequency does not exceed a predetermined switching frequency.

[0117] The memory circuit 310 stores information indicating the set value M.

[0118] ===Operation of the switching control circuit 203c when the inductor currents ILa and ILb become zero a predetermined number of times=== 16 is a diagram showing an example of the operation of the switching control circuit 203c. Note that the period from time t50 to t54 shows the operation when the NMOS transistors 26a and 26b are turned on when the inductor currents ILa and ILb become zero twice (i.e., the predetermined value M is set to "2"). On the other hand, the period from time t55 onwards shows the operation when the timing at which the inductor current ILb becomes zero twice does not coincide with the half cycle Th. In this case, the rectified voltage Vrec decreases.

[0119] The NMOS transistor 26a is turned on before time t50, and is turned off at time t50 after the on-period Vz has elapsed. As a result, the voltage Vzcda becomes higher than the reference voltage Vref1, and the inductor current ILa begins to decrease. In addition, the output circuit 304 outputs the signal HALF_T at an “H” level (step S20 in FIG. 17).

[0120] On the other hand, the NMOS transistor 26b is turned off before time t50, and the inductor current ILb decreases and reaches zero for the second time. Therefore, the detection circuit 303 outputs a signal DETb of “H” level. The counter 308 then counts the number of times the inductor current ILb reaches zero twice, and the count value of the counter 308 matches the set value M (step S40 in FIG. 17). Furthermore, time t50 is the timing of the half period Th, and the output circuit 304 outputs a signal HALF_T of “H” level (YES in step S21 in FIG. 17). Therefore, the second drive circuit 305 outputs a drive signal Vqb that turns on the NMOS transistor 26b (step S22 in FIG. 17). The voltage Vzcdb then becomes lower than the reference voltage Vref1, and the inductor current ILb begins to increase.

[0121] At time t51, the inductor current ILa first becomes zero. Therefore, the detection circuit 301 outputs an "H" level signal DETa. Then, the counter 307 counts the number of times the inductor current ILa becomes zero by one. Since the count value of the counter 307 does not match the set value M, the first drive circuit 302 does not turn on the NMOS transistor 26a.

[0122] At time t52, when the on-period Vz has elapsed since time t50, the NMOS transistor 26b is turned off, and the inductor current ILb begins to decrease. Meanwhile, the inductor current ILa decreases and reaches zero for the second time. Therefore, the detection circuit 301 outputs an "H" level signal DETa. Then, the counter 307 counts the number of times the inductor current ILa reaches zero twice, and the count value of the counter 307 matches the set value M. Therefore, the first drive circuit 302 turns on the NMOS transistor 26a.

[0123] At time t53, the inductor current ILb first becomes zero. Therefore, the detection circuit 303 outputs an "H" level signal DETb. Then, the counter 308 counts the number of times the inductor current ILb becomes zero by one. Since the count value of the counter 308 does not match the set value M, the second drive circuit 305 does not turn on the NMOS transistor 26b (step S40 in FIG. 17). Then, the same operation is repeated from time t54 onwards.

[0124] In this way, when the inductor current ILb becomes zero for the second time while the output circuit 304 is outputting the "H" level signal HALF_T, the second drive circuit 305 outputs the drive signal Vqb that turns on the NMOS transistor 26b. Therefore, the phase difference between the timings at which the NMOS transistors 26a and 26b are turned on tends to be constant.

[0125] Furthermore, although the case where the rectified voltage Vrec fluctuates low has been described here, if the rectified voltage Vrec fluctuates high, the timing at which the count value of the counter 308 matches the set value M may be delayed relative to the period during which the signal HALF_T is at the "H" level, and may occur during the period during which the signal HALF_T is at the "L" level. In other words, when the output circuit 304 is outputting the signal HALF_T at the "L" level, the count value of the counter 308 matches the set value M (NO in step S21 of FIG. 17).

[0126] In this case, if the number of times the NMOS transistor 26b could not be turned on is less than the predetermined number N (NO in step S23 in FIG. 17), the second drive circuit 305 waits until the output circuit 304 outputs the signal HALF_T at the “H” level (step S20 in FIG. 17). On the other hand, if the number of times the NMOS transistor 26b could not be turned on reaches the predetermined number N (YES in step S23 in FIG. 17), the second drive circuit 305 turns on the NMOS transistor 26b at the timing when the output circuit 304 next outputs the signal HALF_T (step S24 in FIG. 17).

[0127] The above describes the case where, when the output circuit 304 outputs the signal HALF_T at "H" level, the count value of the counter 308 matches the set value M. Below, we will describe the case where, when the output circuit 304 outputs the signal HALF_T at "L" level, the count value of the counter 308 matches the set value M.

[0128] Before time t55, the NMOS transistor 26b is turned off, and at time t55 when the inductor current ILb first becomes zero, the detection circuit 303 outputs an "H" level signal DETb. Then, although the counter 308 counts the number of times the inductor current ILb becomes zero by one, the count value of the counter 308 does not match the set value M (NO in step S40 in FIG. 17). Therefore, the second drive circuit 305 does not output the drive signal Vqb that turns on the NMOS transistor 26b.

[0129] At time t56 when the inductor current ILb becomes zero for the second time, the detection circuit 303 outputs a signal DETb of "H" level. Then, the counter 308 counts the number of times the inductor current ILb becomes zero twice, and the count value of the counter 308 matches the set value M (YES in step S40 in FIG. 17). However, because the output circuit 304 outputs the signal HALF_T of "L" level, the second drive circuit 305 does not output a drive signal Vqb that turns on the NMOS transistor 26b (NO in steps S21 and S23 in FIG. 17).

[0130] At time t57 when the inductor current ILb reaches zero for the third time, the detection circuit 303 outputs an "H" level signal DETb. The counter 308 then counts three times the number of times the inductor current ILb reaches zero, and the count value of the counter 308 becomes greater than the set value M. Since the output circuit 304 outputs an "H" level signal HALF_T, the second drive circuit 305 outputs a drive signal Vqb that turns on the NMOS transistor 26b (YES in step S21, S22 in FIG. 17).

[0131] At time t58, the inductor current ILa first becomes zero. Therefore, the detection circuit 301 outputs an "H" level signal DETa. Then, the counter 307 counts the number of times the inductor current ILa becomes zero by one. Since the count value of the counter 307 does not match the set value M, the first drive circuit 302 does not turn on the NMOS transistor 26a.

[0132] At time t59, when the on-period Vz has elapsed since time t57, the second drive circuit 305 outputs the drive signal Vqb that turns off the NMOS transistor 26b. After that, the inductor current ILb starts to decrease. Note that the same operation is repeated from time t60 onwards.

[0133] In this way, even if the counter 308 counts the number of times that the inductor current ILb reaches zero, which corresponds to the set value M, if the output circuit 304 is outputting the "L" level signal HALF_T, the second drive circuit 305 does not output the drive signal Vqb that turns on the NMOS transistor 26b. Thereafter, if the inductor current ILb reaches zero while the output circuit 304 is outputting the "H" level signal HALF_T, the second drive circuit 305 outputs the drive signal Vqb that turns on the NMOS transistor 26b. Therefore, the phase difference between the timing at which the NMOS transistors 26a and 26b are turned on tends to be constant.

[0134] ==Configuration of Switching Control Circuit 203d== 18 shows an example of a switching control circuit 203d, which is an embodiment of the switching control circuit 203. When the difference between the phase difference of the switching timing and the half cycle Th becomes equal to or greater than a predetermined value, the switching control circuit 203d turns on the NMOS transistor 26b in the half cycle Th, and when the number of times that the inductor currents ILa and ILb become zero reaches a set value M, the switching control circuit 203d turns on each of the NMOS transistors 26a and 26b.

[0135] The switching control circuit 203c includes an on-period output circuit 300, detection circuits 301, 303, and 306, a first drive circuit 302, an output circuit 304, a second drive circuit 305, counters 307 and 308, a setting circuit 309, and a memory circuit 310.

[0136] ===Operation of the switching control circuit 203d when the difference ΔT is less than the predetermined value T0 and the inductor currents ILa and ILb become zero a predetermined number of times=== 19 is a diagram illustrating an example of the operation of the switching control circuit 203d. It is assumed that the NMOS transistors 26a and 26b are operating during an ON period Vz during which they are turned on for half the switching period. It is also assumed that the set value M is set to "2."

[0137] The NMOS transistor 26a is turned off before time t70, and at time t70, when the inductor current ILa reaches zero for the second time, the NMOS transistor 26a is turned on. As a result, the voltage Vzcda becomes lower than the reference voltage Vref1, and the inductor current ILa begins to increase. Then, the NMOS transistor 26b is turned on before time t70, and the on-period Vz elapses, so the NMOS transistor 26b is turned off. Then, the inductor current ILb begins to decrease.

[0138] At time t71, the inductor current ILb decreases and becomes zero for the first time. Therefore, the detection circuit 303 outputs an "H" level signal DETb. Then, the counter 308 counts the number of times the inductor current ILb becomes zero once, and the count value of the counter 308 does not match the set value M (NO in step S40 in FIG. 21). Therefore, the second drive circuit 305 does not output the drive signal Vqb that turns on the NMOS transistor 26b.

[0139] At time t72, the inductor current ILb decreases and becomes zero for the second time. Therefore, the detection circuit 303 outputs a high-level signal DETb. The counter 308 counts the number of times the inductor current ILb becomes zero twice, and the count value of the counter 308 matches the set value M (YES in step S40 of FIG. 21). Time t72 is the timing of the half period Th, and the output circuit 304 outputs a high-level signal HALF_T (YES in steps S20 and S21 of FIG. 21). Therefore, the second drive circuit 305 turns on the NMOS transistor 26b (step S22 of FIG. 21). The voltage Vzcdb becomes lower than the reference voltage Vref1, and the inductor current ILb begins to increase. The detection circuit 306 calculates the difference ΔT (step S30 of FIG. 21), and the difference ΔT is smaller than the predetermined value T0 (NO in step S31 of FIG. 21).

[0140] Meanwhile, since the on-period Vz has elapsed since time t70, the first drive circuit 302 outputs the drive signal Vqa that turns off the NMOS transistor 26a. Then, the voltage Vzcda becomes higher than the reference voltage Vref1, and the inductor current ILa starts to decrease.

[0141] At time t73, the inductor current ILa becomes zero for the first time after the NMOS transistor 26a is turned on. Therefore, the detection circuit 301 outputs an "H" level signal DETa. Then, the counter 307 counts the number of times the inductor current ILa becomes zero by one. Since the count value of the counter 307 does not match the set value M, the first drive circuit 302 does not turn on the NMOS transistor 26a.

[0142] At time t74, when the on-period Vz has elapsed since time t72, the NMOS transistor 26b is turned off, and the inductor current ILb begins to decrease. Meanwhile, the inductor current ILa decreases and reaches zero for the second time. This causes the detection circuit 301 to output an "H" level signal DETa. The counter 307 then counts the number of times the inductor current ILa reaches zero twice, and the count value of the counter 307 matches the set value M. This causes the first drive circuit 302 to turn on the NMOS transistor 26a. Similar operations are then repeated.

[0143] ===Operation of the switching control circuit 203d when the difference ΔT is equal to or greater than a predetermined value T0 and the inductor currents ILa and ILb become zero a predetermined number of times=== 20 is a diagram showing an example of the operation of the switching control circuit 203d, where the set value M is set to "2."

[0144] At time t80, the inductor current ILb becomes zero for the second time. Therefore, the detection circuit 303 outputs an “H” level signal DETb. Then, the counter 308 counts the number of times the inductor current ILb becomes zero twice, and the count value of the counter 308 matches the set value M (YES in step S40 of FIG. 21). Furthermore, because the output circuit 304 outputs an “H” level signal HALF_T (YES in steps S20 and S21 of FIG. 21), the second drive circuit 305 turns on the NMOS transistor 26b (step S22 of FIG. 21). Therefore, the voltage Vzcdb becomes lower than the reference voltage Vref1, and the inductor current ILb begins to increase. Furthermore, the inductor current ILa becomes zero for the first time after the NMOS transistor 26a is turned on. Therefore, the detection circuit 301 outputs an “H” level signal DETa. Then, the counter 307 counts the number of times the inductor current ILa becomes zero by one, and since the count value of the counter 307 does not match the set value M, the first drive circuit 302 does not turn on the NMOS transistor 26a.

[0145] At time t81, the inductor current ILa becomes zero for the second time, and the detection circuit 301 outputs the signal DETa at the "H" level, and the first drive circuit 302 turns on the NMOS transistor 26a.

[0146] At time t82, when the on-period Vz has elapsed since time t80, the second drive circuit 305 turns off the NMOS transistor 26b, so that the voltage Vzcdb becomes higher than the reference voltage Vref1, and the inductor current ILb starts to decrease.

[0147] At time t83, when the on-period Vz has elapsed since time t81, the first drive circuit 302 turns off the NMOS transistor 26a. As a result, the voltage Vzcda becomes higher than the reference voltage Vref1, and the inductor current ILa begins to decrease. The inductor current ILb then becomes zero for the first time after the NMOS transistor 26b is turned on. As a result, the detection circuit 303 outputs a signal DETb of an “H” level. The counter 308 then counts the number of times the inductor current ILb becomes zero once, and the count value of the counter 308 does not match the set value M (NO in step S40 in FIG. 21). Furthermore, because the output circuit 304 outputs a signal HALF_T of an “L” level, the second drive circuit 305 does not turn on the NMOS transistor 26b.

[0148] At time t84, the output circuit 304 outputs the signal HALF_T at the "H" level.

[0149] At time t85, when the inductor current ILb reaches zero for the second time, the detection circuit 303 outputs an “H” level signal DETb. The counter 308 then counts the number of times the inductor current ILb reaches zero twice, and the count value of the counter 308 matches the set value M (YES in step S40 in FIG. 21). Furthermore, because the output circuit 304 outputs an “H” level signal HALF_T (YES in steps S30 and S32 in FIG. 20), the second drive circuit 305 turns on the NMOS transistor 26b (step S33 in FIG. 20). Furthermore, the inductor current ILa reaches zero for the first time after the NMOS transistor 26a is turned on. Therefore, the detection circuit 301 outputs an “H” level signal DETa. Then, the counter 307 counts the number of times the inductor current ILa becomes zero by one, and since the count value of the counter 307 does not match the set value M, the first drive circuit 302 does not turn on the NMOS transistor 26a.

[0150] In this case, since period P2 is shorter than period P1, detection circuit 306 calculates difference ΔT (step S30 in FIG. 21) and detects that difference ΔT is greater than predetermined value T0 (YES in step S31 in FIG. 21). Furthermore, detection circuit 306 counts number of times n1, and since number of times n1 is greater than predetermined number of times N1 ("0" in the case of the operation in FIG. 20) (YES in step S33 in FIG. 21), it outputs signal DIFF at "H" level.

[0151] At time t86, the inductor current ILa becomes zero for the second time after the NMOS transistor 26a is turned on. Therefore, the detection circuit 301 outputs an "H" level signal DETa. Then, the counter 307 counts the number of times the inductor current ILa becomes zero twice, and the count value of the counter 307 matches the set value M. Therefore, the first drive circuit 302 turns on the NMOS transistor 26a.

[0152] At time t87, when the on-period Vz has elapsed since time t85, the second drive circuit 305 turns off the NMOS transistor 26b, so that the voltage Vzcdb becomes higher than the reference voltage Vref1, and the inductor current ILb starts to decrease.

[0153] At time t88, when the output circuit 304 outputs the signal HALF_T at "H" level, the second drive circuit 305 turns on the NMOS transistor 26b (step S24 in FIG. 21).

[0154] In this way, when the periods P1 and P2 are not equal, the detection circuit 306 outputs a high-level signal DIFF because the difference ΔT between the phase difference between the switching of the NMOS transistors 26a and 26b and the half period Th is greater than the predetermined value T0. Then, the second drive circuit 305 turns on the NMOS transistor 26b during the half period Th.

[0155] In this operation, when the difference ΔT becomes larger than a predetermined value T0, the NMOS transistor 26b is turned on in half a period Th, so that the phase difference between the timings at which the NMOS transistors 26a and 26b are turned on tends to be constant.

[0156] ===Summary=== The AC-DC converter 10 of this embodiment has been described above. The switching control circuit 203a includes a first drive circuit 302, an output circuit 304, and a second drive circuit 305. The second drive circuit 305 turns on the NMOS transistor 26b based on the signal HALF_T from the output circuit 304 and the fact that the inductor current ILb has become zero. This makes it possible to provide a switching control circuit that suppresses deviations in phase difference even when the rectified voltage fluctuates during interleaved operation.

[0157] Furthermore, when the inductor current ILb becomes zero while the output circuit 304 is outputting the "H" level signal HALF_T, the second drive circuit 305 turns on the NMOS transistor 26b, thereby suppressing a shift in the phase difference caused by an early drop in the inductor current ILb due to a drop caused by fluctuations in the rectified voltage Vrec.

[0158] The switching control circuit 203b also includes a detection circuit 306. When the difference ΔT is greater than a predetermined value T0, the second drive circuit 305 turns on the NMOS transistor 26b when the output circuit 304 outputs a high-level signal HALF_T. That is, as the difference ΔT increases, the phase difference also increases. Therefore, the NMOS transistor 26b is turned on at the timing of a half cycle to suppress the phase difference. This makes it possible to compensate for fluctuations in the switching cycle that accompany a decrease in the rectified voltage Vrec.

[0159] Furthermore, the detection circuit 306 counts the number of times ΔT exceeds a predetermined value T0, and when the count value exceeds a predetermined value T1, the second drive circuit 305 turns on the NMOS transistor 26b when the output circuit 304 outputs an "H" level signal HALF_T. This corrects the phase difference when ΔT continues to exceed the predetermined value T0, thereby improving the stability of the operation of the AC-DC converter 10.

[0160] The switching control circuit 203c also includes counters 307 and 308 and a memory circuit 310. The first drive circuit 302 and the second drive circuit 305 perform a bottom skip operation in which they turn on the NMOS transistors 26a and 26b after the voltages corresponding to the inductor currents ILa and ILb reach their minimum values, or bottoms, the same number of times. This suppresses harmonic distortion in the input current caused by an increase in the switching frequency of the NMOS transistors 26a and 26b.

[0161] The switching control circuit 203c also includes a setting circuit 309. This allows the switching control circuit 203c to flexibly set the number of bottoms based on the switching period as well, with the predetermined set value PreSET set by the user as the minimum value.

[0162] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0163] 10 AC-DC converter 11 Load 20 Input Line Filter 21 Full wave rectifier circuit 22,23 Capacitor 24a, 24b Diodes 25 Power Factor Correction IC 26a, 26b Transistors 27a, 28a, 27b, 28b, 100, 102 capacitors 30,31 Resistance 101 Common mode coil 200, 201, 202 AD converters 203, 203a, 203b, 203c, 203d Switching control circuit 204,205 Buffer circuit 300 ON period output circuit 301, 303, 306 Detection circuit 302 First drive circuit 304 Output circuit 305 Second drive circuit 307,308 counters 309 Setting Circuit 310 Memory circuit 400 Error amplifier circuit 401 PI control circuit 402 Decision Circuit 403 Switch 404 Multiplication Circuit

Claims

1. a switching control circuit for controlling switching of the first and second transistors of a power supply circuit that generates an output voltage at the output terminal that is at a target level from the AC voltage, the power supply circuit including: a first circuit including a first inductor to which a voltage corresponding to the AC voltage is applied and a first transistor that controls a first inductor current flowing through the first inductor; a second circuit including a second inductor to which a voltage corresponding to the AC voltage is applied and a second transistor that controls a second inductor current flowing through the second inductor; and an output terminal to which outputs of the first and second circuits and a load are connected; a first drive circuit that turns on the first transistor after the first inductor current reaches a first value, and turns off the first transistor after a first period corresponding to the output voltage has elapsed; an output circuit that outputs a signal indicating a half period of the switching period of the first transistor; a second drive circuit that turns on the second transistor based on a signal indicating the half cycle since the first transistor was turned on and based on the second inductor current reaching a second value, and turns off the second transistor when a second period corresponding to the output voltage has elapsed; A switching control circuit comprising:

2. 2. The switching control circuit according to claim 1, The second drive circuit is when the second inductor current reaches the second value within a predetermined period determined by the timing of the half cycle after the first transistor is turned on, the second transistor is turned on; Switching control circuit.

3. 3. The switching control circuit according to claim 2, a detection circuit that detects whether a second difference between a first difference between a first timing at which the first transistor is switched and a second timing at which the second transistor is switched and the half period is greater than a first predetermined value; The second drive circuit is turning on the second transistor when the first transistor is turned on and the first half cycle begins based on a detection result indicating that the second difference is greater than the first predetermined value; Switching control circuit.

4. 4. The switching control circuit according to claim 3, The detection circuit Counting the number of times the second difference is greater than the first predetermined value; The second drive circuit is When the count value of the detection circuit becomes larger than a second predetermined value, the second transistor is turned on at the half cycle after the first transistor is turned on. Switching control circuit.

5. The switching control circuit according to any one of claims 2 to 4, a first counter that counts the number of times the first inductor current reaches the first value; a second counter that counts the number of times the second inductor current reaches the second value; a memory circuit for storing information indicating the set value; Equipped with The first drive circuit When the count value of the first counter reaches the set value, the first transistor is turned on; The second drive circuit is When the count value of the second counter reaches the set value within the predetermined period, the second transistor is turned on. Switching control circuit.

6. 6. The switching control circuit according to claim 5, a setting circuit for setting the set value based on a predetermined switching frequency and a predetermined set value of the first and second transistors; A switching control circuit comprising:

7. 2. The switching control circuit according to claim 1, The second period is equal to the first period. Switching control circuit.

8. A power supply circuit that generates an output voltage of a target level from an AC voltage, a first circuit including a first inductor to which a voltage corresponding to the AC voltage is applied, and a first transistor that controls a first inductor current flowing through the first inductor; a second circuit including a second inductor to which a voltage corresponding to the AC voltage is applied, and a second transistor that controls a second inductor current flowing through the second inductor; an output terminal to which the outputs of the first and second circuits and a load are connected; a switching control circuit that controls switching of the first and second transistors of a power supply circuit that generates an output voltage at the output terminal; Including, The switching control circuit a first drive circuit that turns on the first transistor after the first inductor current reaches a first value, and turns off the first transistor after a first period corresponding to the output voltage has elapsed; an output circuit that outputs a signal indicating a half period of the switching period of the first transistor; a second drive circuit that turns on the second transistor based on a signal indicating the half cycle since the first transistor was turned on and based on the second inductor current reaching a second value, and turns off the second transistor when a second period corresponding to the output voltage has elapsed; A power supply circuit comprising:

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