Semiconductor device

Abstract

To provide a technique for suppressing a decrease in breakdown voltage in a semiconductor device including a super-junction layer and a plurality of guard ring regions at a terminal portion.SOLUTION: A plurality of guard ring regions 40 include a first guard ring region 42 including at least an outermost guard ring region 40, and a second guard ring region 44 including a guard ring region 40 disposed on the inner circumferential side of the first guard ring region 42. The first guard ring region 42 is spaced apart from a p-type column 13a of a super-junction layer 13, and the second guard ring region 44 is in contact with the p-type column 13a of the super-junction layer 13.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] The semiconductor substrate of the semiconductor device has an active portion and a termination portion located around the active portion. A gate structure is provided in the active portion, and a termination breakdown structure is provided in the termination portion. Patent Document 1 discloses a semiconductor device that includes a super junction layer (hereinafter sometimes referred to as an "SJ layer") and multiple guard ring regions as the termination breakdown structure of the termination portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2012-533167 Summary of the Invention [Problem to be solved by the invention]

[0004] The SJ layer and guard ring region are spaced apart in the thickness direction of the semiconductor substrate, with a drift region between them. For example, if the impurity concentration in the drift region is increased to reduce on-resistance, the electric field will concentrate at the pn junction between the guard ring region and the drift region, raising concerns about a decrease in the breakdown voltage of the semiconductor device. This specification provides a technology for suppressing a decrease in breakdown voltage in a semiconductor device that has a superjunction layer and multiple guard ring regions in the termination area. [Means for solving the problem]

[0005] The semiconductor device disclosed herein includes a semiconductor substrate (10) having an active section (10A) and a termination section (10B) located around the active section. The termination section may include a lower drift region (12) of a first conductivity type, a superjunction layer (13) provided on the lower drift region and including first conductivity type columns (13b) and second conductivity type columns (13a) alternately arranged in at least one direction, an upper drift region (14) of the first conductivity type provided on the superjunction layer, and multiple guard ring regions (40) of a second conductivity type surrounded by the upper drift region and extending around the active section. The multiple guard ring regions may include a first guard ring region (42) including at least the outermost guard ring region, and a second guard ring region (44) including guard ring regions located more inward than the first guard ring region. The first guard ring region is spaced apart from the second conductivity type columns of the superjunction layer. The second guard ring region contacts the second conductivity type column of the superjunction layer.

[0006] In the semiconductor device, the second guard ring region located on the inner side of the multiple guard ring regions is formed deep enough to contact the second conductivity-type columns of the superjunction layer. This reduces electric field concentration at the p-n junction between the second guard ring region and the upper drift region. If all guard ring regions were formed deep enough to contact the second conductivity-type columns of the superjunction layer, the outermost guard ring region would not be depleted when a low voltage is applied to the semiconductor substrate, raising concerns about electric field concentration at the p-n junction between the side surface of the outermost guard ring region and the upper drift region. In the semiconductor device, the first guard ring region including the outermost guard ring region is formed away from the second conductivity-type columns of the superjunction layer and has a floating potential. This reduces electric field concentration at the p-n junction between the side surface of the outermost guard ring region and the upper drift region. In this way, the semiconductor device reduces electric field concentration throughout the multiple guard ring regions, thereby suppressing a decrease in breakdown voltage. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram showing the positional relationship between an active portion and a termination portion defined in a semiconductor substrate when the semiconductor substrate is viewed in plan; [Figure 2] 2 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment, and is a diagram schematically showing a cross-sectional view corresponding to line II-II in FIG. 1. [Figure 3] FIG. 2 is a schematic perspective view of a main part of an active portion of a semiconductor layer. [Figure 4] 2 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment, and is a diagram schematically showing a cross-sectional view corresponding to line II-II in FIG. 1. [Figure 5] 1. FIG. 5 is a cross-sectional view of a main part of a semiconductor device according to a third embodiment, and is a diagram schematically showing a cross-sectional view corresponding to line II-II in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, a semiconductor device to which the technology disclosed in this specification is applied will be described with reference to the drawings. In the following drawings, for the purpose of clarity of illustration, only some of the common components may be designated by reference numerals. Furthermore, the common components in each embodiment are designated by the same reference numerals, and their description will be omitted.

[0009] (First embodiment) As shown in FIGS. 1 to 3, the semiconductor device 1 is a type of power device called a MOSFET, and is formed using a semiconductor substrate 10. The material of the semiconductor substrate 10 is not particularly limited, but may be, for example, a wide band gap semiconductor. The wide band gap semiconductor is not particularly limited, but examples thereof include silicon carbide (SiC) and nitride semiconductors. The semiconductor device 1 may also be a type of power device called an IGBT.

[0010] 1, when viewed from a direction perpendicular to the main surface of the semiconductor substrate 10 (hereinafter referred to as "when viewed in a plan view"), the semiconductor substrate 10 has an active portion 10A and a termination portion 10B. The active portion 10A is a region defined inside the semiconductor substrate 10, and is a region in which a switching structure is formed, as described below. The termination portion 10B is a region defined outside the semiconductor substrate 10, i.e., around the active portion 10A, and is a region in which a termination breakdown structure is formed, as described below.

[0011] As shown in FIGS. 2 and 3 , the semiconductor device 1 includes a semiconductor substrate 10, a drain electrode 22, a source electrode 24, and multiple trench gates 30. The semiconductor substrate 10 includes a drain region 11, a lower drift region 12, a superjunction layer 13 (hereinafter sometimes referred to as the “SJ layer 13”), an upper drift region 14, a deep P region 15, a body region 16, a contact region 17, and a source region 18. The active portion 10A includes multiple trench gates 30, and is a region through which current flows between the drain electrode 22 and the source electrode 24 when the semiconductor device 1 is turned on. The termination portion 10B includes multiple guard ring regions 40, and is a region that causes a depletion layer to extend outward when the semiconductor device 1 is turned off. In this example, the active portion 10A and the termination portion 10B are separated by the periphery of the body region 16.

[0012] The drain electrode 22 is provided to cover the lower surface of the semiconductor substrate 10. The drain electrode 22 is disposed in both the active portion 10A and the terminal portion 10B, and is in contact with the entire lower surface of the semiconductor substrate 10.

[0013] The source electrode 24 is provided to cover the upper surface of the semiconductor substrate 10. The source electrode 24 is disposed over substantially the entire active portion 10A and is in contact with the upper surface of the semiconductor substrate 10 exposed through an opening in an interlayer insulating film formed on the upper surface of the semiconductor substrate 10.

[0014] The drain region 11 is an n-type region containing a high concentration of n-type impurities. The drain region 11 is provided in both the active portion 10A and the termination portion 10B, and is disposed in a position exposed on the lower surface of the semiconductor substrate 10. The drain region 11 is in ohmic contact with the drain electrode 22.

[0015] The lower drift region 12 is provided on the drain region 11 and is an n-type region with a lower n-type impurity concentration than the drain region 11. Note that other semiconductor regions may be provided between the lower drift region 12 and the drain region 11. The lower drift region 12 is provided in both the active section 10A and the termination section 10B. The lower drift region 12 may be formed by growing crystals from the surface of the drain region 11 using, for example, a crystal growth technique. The lower drift region 12, together with the upper drift region 14 described below, is referred to as the drift region.

[0016] The SJ layer 13 is provided on the lower drift region 12 and has multiple p-type columns 13a and multiple n-type columns 13b. Note that other semiconductor regions may be provided between the SJ layer 13 and the lower drift region 12. Each of the multiple p-type columns 13a is a p-type region containing p-type impurities. Each of the multiple n-type columns 13b is an n-type region containing n-type impurities. The SJ layer 13 is provided in both the active section 10A and the termination section 10B. A peripheral edge 13S of the SJ layer 13 does not reach the side surface of the semiconductor substrate 10. The side surface constituting the peripheral edge 13S of the SJ layer 13 is in contact with the drift region. An n-type field stop region (not shown) fixed to the drain potential is formed at a position exposed on the upper surface of the semiconductor substrate 10 outside the peripheral edge 13S of the SJ layer 13.

[0017] Each of the multiple p-type columns 13a and each of the multiple n-type columns 13b extends in at least one direction (the y direction in this example, which is perpendicular to the longitudinal direction of the trench gate 30) when the semiconductor substrate 10 is viewed in a plan view. The p-type columns 13a and the n-type columns 13b are alternately arranged in a direction parallel to the longitudinal direction of the trench gate 30 (the x direction in this example). The widths and impurity concentrations of the p-type columns 13a and the n-type columns 13b are adjusted to achieve charge balance. The multiple p-type columns 13a and the multiple n-type columns 13b may be formed by introducing p-type impurities into a portion of the lower drift region 12 using, for example, ion implantation technology.

[0018] The upper drift region 14 is provided on the SJ layer 13 and is an n-type region containing n-type impurities. Note that other semiconductor regions may be provided between the upper drift region 14 and the SJ layer 13. The upper drift region 14 is provided in both the active section 10A and the termination section 10B. The n-type impurity concentration in the upper drift region 14 may be the same as or higher than the n-type impurity concentration in the lower drift region 12. The n-type impurity concentration in the upper drift region 14 may be different or the same in the active section 10A and the termination section 10B. In this example, the n-type impurity concentration in the upper drift region 14 is higher than the n-type impurity concentration in the lower drift region 12 and is the same in the active section 10A and the termination section 10B. If the n-type impurity concentration in the upper drift region 14 is higher than that in the lower drift region 12, the on-resistance of the semiconductor device 1 decreases. If the n-type impurity concentration in the upper drift region 14 is the same in the active section 10A and the termination section 10B, the upper drift region 14 can be formed in each of the active section 10A and the termination section 10B simultaneously in the same process. The upper drift region 14 contacts the bottom surface and lower portions of the side surfaces of the trench gate 30. The upper drift region 14 also contacts the n-type columns 13b of the SJ layer 13. The upper drift region 14 may be formed by, for example, growing an epitaxial layer from the top surface of the SJ layer 13 using a crystal growth technique, and then introducing n-type impurities into at least a portion of the epitaxial layer using an ion implantation technique.

[0019] The deep P region 15 is a p-type region containing p-type impurities. The deep P region 15 is provided in the active portion 10A and penetrates the upper drift region 14. The upper end of the deep P region 15 contacts the body region 16 or the contact region 17, and the lower end of the deep P region 15 contacts the p-type column 13a of the SJ layer 13. This fixes the potential of the p-type column 13a of the SJ layer 13 to the source potential. The deep P region 15 extends along at least one direction (the x-direction in this example, which is parallel to the longitudinal direction of the trench gate 30) when the semiconductor substrate 10 is viewed from above. The deep P region 15 may be formed by introducing p-type impurities into a portion of the upper drift region 14 using, for example, ion implantation technology.

[0020] The body region 16 is a p-type region containing p-type impurities. The body region 16 is provided in the active portion 10A and is arranged on the upper drift region 14. Note that another semiconductor region may be provided between the body region 16 and the upper drift region 14. The body region 16 contacts a side surface of the trench gate 30 and separates the upper drift region 14 from the source region 18. The body region 16 may be formed by introducing p-type impurities into a portion of the upper drift region 14 using, for example, ion implantation technology.

[0021] The contact region 17 is provided in contact with the body region 16 and is a p-type region that contains a higher concentration of p-type impurities than the body region 16. The contact region 17 is provided in the active portion 10A and is arranged at a position exposed on the upper surface of the semiconductor substrate 10. The contact region 17 is exposed from an opening in an interlayer insulating film formed on the upper surface of the semiconductor substrate 10 and is in ohmic contact with the source electrode 24. The contact region 17 may be formed by introducing p-type impurities into a part of the upper drift region 14 using, for example, ion implantation technology.

[0022] The source region 18 is provided on the body region 16 and is an n-type region containing a high concentration of n-type impurities. Note that another semiconductor region may be provided between the source region 18 and the body region 16. The source region 18 is provided in the active portion 10A and is located at a position exposed on the upper surface of the semiconductor substrate 10. The source region 18 is exposed from an opening in an interlayer insulating film formed on the upper surface of the semiconductor substrate 10 and is in ohmic contact with the source electrode 24. The source region 18 contacts an upper portion of the side surface of the trench gate 30. The source region 18 may be formed by introducing n-type impurities into a portion of the upper drift region 14 using, for example, ion implantation technology.

[0023] Each of the trench gates 30 is provided in the active portion 10A and extends from the upper surface of the semiconductor substrate 10 through the source region 18 and the body region 16 to reach the upper drift region 14. When the semiconductor substrate 10 is viewed from above, each of the trench gates 30 extends along at least one direction (the x direction in this example). The trench gates 30 are repeatedly arranged at intervals along a direction perpendicular to the longitudinal direction (the y direction in this example). Thus, when the semiconductor substrate 10 is viewed from above, the trench gates 30 are arranged in a stripe pattern. Note that the stripe pattern is just an example, and the trench gates 30 may be arranged in other layouts. Each of the trench gates 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the upper drift region 14, the body region 16, and the source region 18 by the gate insulating film 34 and from the source electrode 24 by the interlayer insulating film.

[0024] In this way, in the active portion 10A, a switching structure is formed by the drain electrode 22, the drain region 11, the lower drift region 12, the SJ layer 13, the upper drift region 14, the deep P region 15, the body region 16, the contact region 17, the source region 18, the source electrode 24, and the trench gate 30.

[0025] As shown in FIG. 2 , the semiconductor substrate 10 further includes multiple guard ring regions 40 in the termination portion 10B. While seven guard ring regions 40 are illustrated in this example, the number is not particularly limited. Each of the multiple guard ring regions 40 is surrounded by the upper drift region 14 and is a p-type region containing p-type impurities. Each of the multiple guard ring regions 40 is located at a position exposed on the upper surface of the semiconductor substrate 10 and extends around the active portion 10A along the termination portion 10B. When the semiconductor substrate 10 is viewed from above, the guard ring regions 40 are repeatedly arranged at intervals along the inner / outer direction (the direction connecting the center of the active portion 10A and the termination portion 10B). A portion of the upper drift region 14 is located between adjacent guard ring regions 40. The multiple guard ring regions 40 may be formed by introducing p-type impurities into a portion of the upper drift region 14 using, for example, ion implantation technology. The multiple guard ring regions 40 are an example of a termination breakdown voltage structure.

[0026] The plurality of guard ring regions 40 includes a plurality of first guard ring regions 42 and a plurality of second guard ring regions 44 formed shallower than the plurality of first guard ring regions 42 .

[0027] The multiple first guard ring regions 42 include at least the outermost guard ring region 40. In this example, the two outermost guard ring regions 40 belong to the first guard ring region 42, but the number is not particularly limited. Each of the multiple first guard ring regions 42 is separated from the p-type column 13a of the SJ layer 13 and has a floating potential. The impurity concentration and dimensions of each of the multiple first guard ring regions 42 are designed appropriately depending on the electrical characteristics desired for the semiconductor device 1.

[0028] The second guard ring regions 44 include one or more guard ring regions 40 arranged more inward than the first guard ring region 42. Each of the second guard ring regions 44 is in contact with a p-type column 13a of the SJ layer 13, and its potential is fixed to the source potential. The impurity concentration and dimensions of each of the second guard ring regions 44 are designed appropriately depending on the electrical characteristics desired for the semiconductor device 1.

[0029] Next, the operation of the semiconductor device 1 will be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 32 while a voltage is applied between the drain and source such that the drain electrode 22 has a higher potential than the source electrode 24, a channel is formed in the body region 16 in an area adjacent to the gate insulating film 34. Electrons supplied from the source region 18 flow into the upper drift region 14 through this channel. The electrons that flow into the upper drift region 14 then flow into the drain region 11 via the n-type columns 13b of the SJ layer 13 and the lower drift region 12. This establishes conduction between the drain electrode 22 and the source electrode 24, turning the semiconductor device 1 on.

[0030] When a voltage less than the gate threshold voltage is applied to the gate electrode 32, the channel disappears, turning off the semiconductor device 1. When the semiconductor device 1 is turned off, the p-type columns 13a and n-type columns 13b of the SJ layer 13 are depleted, thereby mitigating the electric field concentration in the termination portion 10B.

[0031] To understand the characteristics of the semiconductor device 1 of this embodiment, consider a comparative example in which none of the multiple guard ring regions 40 reaches the p-type columns 13a of the SJ layer 13. In this comparative example, if the impurity concentration of the upper drift region 14 is increased to reduce the on-resistance, for example, an electric field will concentrate at the pn junction between the guard ring regions 40 and the upper drift region 14, raising concerns about a decrease in the breakdown voltage of the semiconductor device.

[0032] In contrast, in the semiconductor device 1 of this embodiment, the second guard ring region 44, which is located on the inner side of the multiple guard ring regions 40, is formed deep enough to contact the p-type columns 13a of the SJ layer 13. This promotes depletion of the second guard ring region 44 and the upper drift region 14, and reduces electric field concentration at the p-n junction between the second guard ring region 44 and the upper drift region 14. If all guard ring regions 40 were formed deep enough to contact the p-type columns 13a of the SJ layer 13, the outermost guard ring region 40 would not be depleted when a small voltage is applied to the semiconductor substrate 10, raising concerns about electric field concentration at the p-n junction between the side surface of the outermost guard ring region 40 and the upper drift region 14. In the semiconductor device 1 of this embodiment, the first guard ring region 42, which includes the outermost guard ring region 40, is formed away from the p-type columns 13a of the SJ layer 13 and is at a floating potential. This reduces electric field concentration at the pn junction between the side surface of the outermost guard ring region 40 and the upper drift region 14. In this way, in the semiconductor device 1 of this embodiment, electric field concentration is reduced across the entirety of the multiple guard ring regions 40, thereby suppressing a decrease in breakdown voltage.

[0033] (Second embodiment) 4, in the semiconductor device 2 of the second embodiment, each of the multiple second guard ring regions 44 has an upper guard ring portion 44a and a lower guard ring portion 44b. The upper guard ring portion 44a is formed in the same depth range as the first guard ring region 42. The lower guard ring portion 44b is formed at least in the depth range between the upper guard ring portion 44a and the p-type column 13a of the SJ layer 13. In this embodiment, the upper guard ring portion 44a of the second guard ring region 44 and the first guard ring region 42 can be formed simultaneously in the same process. This reduces the manufacturing cost of the semiconductor device 2.

[0034] Furthermore, in the semiconductor device 2 of the second embodiment, the upper guard ring portion 44a of the second guard ring region 44 and the first guard ring region 42 are formed in the same depth range as the contact region 17. This allows the upper guard ring portion 44a of the second guard ring region 44, the first guard ring region 42, and the contact region 17 to be formed simultaneously in the same process. Furthermore, the lower guard ring portion 44b of the second guard ring region 44 and the deep P region 15 are formed in the same depth range. This allows the lower guard ring portion 44b of the second guard ring region 44 and the deep P region 15 to be formed simultaneously in the same process. This allows the manufacturing cost of the semiconductor device 2 to be reduced.

[0035] (Third embodiment) As shown in FIG. 5 , in the semiconductor device 3 of the third embodiment, the upper end of the lower guard ring portion 44b overlaps the lower end of the upper guard ring portion 44a in the second guard ring region 44. Furthermore, the lower guard ring portion 44b and the upper guard ring portion 44a are offset in the inward / outward direction connecting the active portion 10A and the termination portion 10B. Therefore, at the overlapping portion between the lower guard ring portion 44b and the upper guard ring portion 44a, the distance between the side surface of the lower guard ring portion 44b and the side surface of the upper guard ring portion 44a is shortened. This configuration allows the minimum spacing between the lower guard ring portion 44b and the upper guard ring portion 44a to be smaller than the minimum processing dimension. As a result, even if the concentration of n-type impurities in the upper drift region 14 is high, the depletion layer can be effectively developed from the inner periphery toward the outer periphery when the semiconductor device 1 is turned off. In this way, the structure of the multiple guard ring regions 40 included in the semiconductor device 3 is a particularly useful structure when the concentration of n-type impurities in the upper drift region 14 is high.

[0036] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness either alone or in various combinations.

[0037] (Aspect 1) A semiconductor device (1, 2, 3) comprising a semiconductor substrate (10) having an active portion (10A) and a termination portion (10B) located around the active portion, The terminal end is a lower drift region (12) of the first conductivity type; a superjunction layer (13) provided on the lower drift region, in which first conductivity type columns (13b) and second conductivity type columns (13a) are alternately and repeatedly formed in at least one direction; an upper drift region (14) of a first conductivity type provided on the superjunction layer; a plurality of guard ring regions (40) of a second conductivity type that are surrounded by the upper drift region and extend around the active region, The plurality of guard ring regions include: a first guard ring region (42) including at least the outermost guard ring region; a second guard ring region (44) including a guard ring region disposed on the inner circumferential side of the first guard ring region, the first guard ring region is spaced apart from the second conductivity type columns of the superjunction layer; the second guard ring region is in contact with the second conductivity type column of the superjunction layer.

[0038] (Aspect 2) The second guard ring region is an upper guard ring portion (44a) formed in the same depth range as the first guard ring region; The semiconductor device of aspect 1, further comprising: a lower guard ring portion (44b) formed at least in a depth range between the upper guard ring portion and the second conductivity type column of the superjunction layer.

[0039] (Aspect 3) the impurity concentration of the upper drift region is higher than the impurity concentration of the lower drift region, an upper end of the lower guard ring portion and a lower end of the upper guard ring portion overlap each other; 3. The semiconductor device according to aspect 2, wherein the lower guard ring portion and the upper guard ring portion are offset in an inward / outward direction connecting the active portion and the termination portion.

[0040] (Aspect 4) the lower drift region, the superjunction layer, and the upper drift region are also provided in the active section, 4. The semiconductor device according to aspect 3, wherein the upper drift region of the termination section and the active section have the same impurity concentration.

[0041] (Aspect 5) 5. The semiconductor device according to any one of aspects 1 to 4, wherein the semiconductor substrate is a wide-gap semiconductor.

[0042] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0043] 1, 2, 3: semiconductor device, 10: semiconductor substrate, 10A: active portion, 10B: termination portion, 11: drain region, 12: lower drift region, 13: superjunction layer, 13a: p-type column, 13a: p-column, 13b: n-type column, 14: upper drift region, 15: deep P region, 16: body region, 17: contact region, 18: source region, 22: drain electrode, 24: source electrode, 30: trench gate, 40: guard ring region, 42: first guard ring region, 44: second guard ring region

Claims

1. A semiconductor device (1, 2, 3) comprising a semiconductor substrate (10) having an active portion (10A) and a termination portion (10B) located around the active portion, The terminal end is a lower drift region (12) of a first conductivity type; a superjunction layer (13) provided on the lower drift region, in which first conductivity type columns (13b) and second conductivity type columns (13a) are alternately and repeatedly formed in at least one direction; an upper drift region (14) of a first conductivity type provided on the superjunction layer; a plurality of guard ring regions (40) of a second conductivity type that are surrounded by the upper drift region and extend around the active region, The plurality of guard ring regions include: a first guard ring region (42) including at least the outermost guard ring region; a second guard ring region (44) including a guard ring region disposed on the inner circumferential side of the first guard ring region, the first guard ring region is spaced apart from the second conductivity type columns of the superjunction layer; the second guard ring region is in contact with the second conductivity type column of the super junction layer.

2. The second guard ring region is an upper guard ring portion (44a) formed in the same depth range as the first guard ring region; 2. The semiconductor device according to claim 1, further comprising: a lower guard ring portion (44b) formed at least in a depth range between said upper guard ring portion and said second conductivity type column of said superjunction layer.

3. the impurity concentration of the upper drift region is higher than the impurity concentration of the lower drift region, an upper end of the lower guard ring portion and a lower end of the upper guard ring portion overlap each other; 3. The semiconductor device according to claim 2, wherein said lower guard ring portion and said upper guard ring portion are offset in an inward / outward direction connecting said active portion and said terminal portion.

4. the lower drift region, the superjunction layer, and the upper drift region are also provided in the active section, 4. The semiconductor device according to claim 3, wherein the upper drift region of the termination section and the upper drift region of the active section have the same impurity concentration.

5. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is a wide-gap semiconductor.

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