Fast on-switch protection of cascode switches

Abstract

To provide a fast on-switch protection of a cascode switch 101.SOLUTION: A cascode circuit includes an electrically cascoded depletion type field effect transistor 102 and an enhancement type field effect transistor 103. During on-switching, a protection circuit 104 detects an overcurrent anomaly by observing a plateau of a cascode node voltage. The overcurrent anomaly may be detected in response to the presence of the plateau for longer than a threshold duration.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 129,086, filed December 22, 2020, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to overcurrent protection, and more particularly to fast turn-on protection for cascode switches. [Background technology]

[0003] Electronic devices use electrical power to operate. Due to their high efficiency, small size, and light weight, switching power converters are commonly used to power many modern electronic devices. Traditional wall sockets provide high-voltage alternating current (AC). In a switching power converter, a high-voltage alternating current (AC) input is converted through an energy transfer element to provide a properly regulated direct current (DC) output. A controller for a switching power converter typically provides output regulation by sensing one or more inputs representing one or more output quantities and controlling the output in a closed loop. In operation, switches are used to provide a desired output by varying the duty cycle (typically the ratio of the on-time of the switch to the total switching period), changing the switching frequency, or varying the number of pulses per unit time of the switch in a switching power converter.

[0004] Gallium nitride (GaN) and other wide-bandgap III-nitride-based direct transition semiconductor materials exhibit high breakdown fields and are suitable for high current densities. In this regard, GaN-based semiconductor devices are being actively investigated as replacements for silicon-based semiconductor devices in power and high-frequency applications. For example, GaN HEMTs can offer lower on-resistance with higher breakdown voltages than silicon power field-effect transistors of the same area.

[0005] Power field effect transistors (FETs) can be enhancement-mode or depletion-mode. An enhancement-mode device can refer to a transistor (e.g., a field-effect transistor) that blocks current (i.e., is off) when no gate bias is applied (i.e., when the gate-to-source bias is zero). In contrast, a depletion-mode device can refer to a transistor that passes current (i.e., is on) when the gate-to-source bias is zero. Summary of the Invention

[0006] Non-limiting and non-exhaustive embodiments for fast on-switching protection of cascode switches are described with reference to the following figures, in which like reference numerals in different figures refer to like parts unless otherwise specified: [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1A illustrates a circuit including a cascode switch, a protection circuit, and a driver, according to an embodiment. [Figure 1B] FIG. 1B illustrates a power converter including a cascode switch, a protection circuit, and a driver, according to an embodiment. [Figure 2] FIG. 2 compares the on-switching waveforms for different modes of operation in accordance with the teachings herein. [Figure 3] FIG. 3 shows empirical waveforms according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will understand that the elements in the figures are drawn for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to facilitate a better understanding of the various embodiments of the present disclosure. Furthermore, common but well-understood elements useful or necessary in commercially available embodiments are often not shown in the drawings so as not to obscure the views of these various embodiments of the teachings herein.

[0009] In the following description, numerous specific details are set forth to provide a thorough understanding of the fast-on protection of a cascode switch. However, it will be apparent to those skilled in the art that the specific details may not necessarily be used to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0010] References herein to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with an embodiment or example is included in at least one embodiment of the teachings herein. Thus, the use of the phrases "in one embodiment," "in an embodiment," "an example," or "an example" in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in any suitable combination and / or subcombination in one or more embodiments or examples. Particular features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. Additionally, it is understood that the figures provided herewith are for illustrative purposes to persons skilled in the art, and that the drawings, including waveforms, are not necessarily drawn to scale.

[0011] In the context of this application, when a transistor is in an "off state" or "off," the transistor blocks current and / or does not substantially conduct current. Conversely, when a transistor is in an "on state" or "on," the transistor can substantially conduct current. By way of example, the transistor may comprise an N-channel metal-oxide-semiconductor (NMOS) field effect transistor (FET) in which a high voltage is supported between a first terminal, the drain, and a second terminal, the source.

[0012] As mentioned above, an enhancement mode device may refer to a transistor that blocks current when the control voltage (e.g., gate-to-source voltage) is low (e.g., 0 volts). In many circuit and switching applications, it may be desirable to use an enhancement mode transistor (i.e., an enhancement mode device) to implement a circuit function. For example, in power applications, it is often desirable to use a power transistor as a switch (i.e., a power switch). Ideally, a power transistor may operate as a switch when it blocks current in one state (e.g., a state with zero control voltage) and provides current with low on-resistance and low power losses in a second state (e.g., a state with a non-zero control voltage).

[0013] Furthermore, in the context of this application, a cascode may be constructed from two transistors (e.g., field-effect transistors and / or bipolar junction transistors). When a cascode is configured to operate as an amplifier, it may be referred to as a cascode amplifier. Furthermore, when a cascode is configured to operate as a switch, it may be referred to as a cascode switch. Cascodes may be further classified based on transistor type; for example, a cascode including gallium nitride depletion transistors may be referred to as a GaN cascode, a GaN cascode switch, and / or a GaN cascode amplifier. Alternatively and additionally, a cascode may be referred to as a cascode configuration, a cascode device, and / or a cascode circuit. Furthermore, during operation, a cascode may provide gain (e.g., voltage gain), and the gain of a cascode may be referred to as cascode gain, cascode circuit gain, cascode device gain, etc.

[0014] Modern high-power converters and power converters may use cascode devices, including gallium nitride (GaN) cascode devices (e.g., GaN cascode switches). Examples of modern high-power converters and / or modern power converters that may expose cascode devices (e.g., cascode switches) to abnormal and large currents may include, but are not limited to, power factor correction (PFC) converters, flyback converters, buck converters, and / or boost converters. For example, when used in a PFC converter, the cascode switch (e.g., a GaN cascode switch) may be exposed to very large currents (e.g., 50 amperes) for a short period of time (e.g., 100 nanoseconds) when the PFC inductor shorts out. Alternatively, and additionally, when used in a boost converter, the cascode switch (e.g., a GaN cascode switch) may be exposed to very large currents when the boost diode shorts out.

[0015] Power converters, high-power converters, and their switches (e.g., cascode switches) often require protection when faults and / or overcurrent conditions occur. Traditionally, overcurrents (i.e., overcurrent conditions) can be detected using a protection circuit and / or a detection field-effect transistor (FET). Typically, a leading-edge blanking approach is employed to avoid detecting information (e.g., current information) from the detection FET during the initial transient. During the initial transient, the detection information signal may contain noise with an appreciable amplitude relative to the detection information signal, and further filtering may be required to extract the detection information signal. A power converter using leading-edge blanking may wait for the protection circuit and / or the detection FET to reach a stable operating condition, which may require a longer period to detect an overcurrent operating condition.

[0016] Unfortunately, in modern power converters, an overcurrent condition (i.e., an overcurrent event) can occur rapidly after switching on. For example, an overcurrent can occur rapidly in low on-resistance (i.e., low RDS) devices (e.g., low RDS switches) on a time scale less than the leading-edge blanking period. Thus, an overcurrent in a modern power converter using low on-resistance cascode switches (e.g., GaN cascode switches and / or silicon carbide (SiC) cascode switches) can occur so rapidly that it cannot be detected by conventional protection circuits using leading-edge blanking.

[0017] Therefore, there is a need for a protection circuit that can rapidly detect an overcurrent condition after switching on.

[0018] An apparatus and method for fast on-switching protection of a cascode switch is presented herein. The cascode circuit includes a depletion-mode field-effect transistor and an enhancement-mode field-effect transistor electrically cascode-coupled. During on-switching, the protection circuit detects an overcurrent fault by observing a plateau of the cascode node voltage. The overcurrent fault can be detected in response to the presence of the plateau for longer than a threshold duration.

[0019] 1A shows a circuit 100 including a cascode switch 101, a protection circuit 104, and a driver 110 according to an embodiment. The protection circuit 104 includes a comparator 105, a logic AND gate 106, and a control device 108. The cascode switch 101 may include a depletion-mode field-effect transistor 102 and an enhancement-mode field-effect transistor 103. The depletion-mode field-effect transistor 102 may be a gallium nitride (GaN) depletion-mode field-effect transistor (FET) 102 or a silicon carbide (SiC) depletion-mode field-effect transistor 102. The enhancement-mode field-effect transistor 103 may be a low-voltage field-effect transistor (FET) 103.

[0020] The GaN depletion mode FET 102 includes a GaN source SH, a GaN gate GH, and a GaN drain DH, and the low-voltage FET 103 includes a FET source S, a FET gate G, a FET drain D, and a FET body B. As shown, the GaN depletion mode FET 102 is electrically cascode coupled with the low-voltage FET 103, in which case the GaN source SH is electrically coupled to the FET drain D. Furthermore, the FET body B is electrically coupled to the FET source S, and the GaN gate GH and the FET source S are electrically coupled to ground GND.

[0021] With this configuration (i.e., cascode configuration), cascode switch 101 may beneficially operate as an enhancement type (i.e., operate as a normally-off device) in response to a gate voltage VGS applied to FET gate G. For example, when the gate voltage VGS is less than the threshold voltage of low-voltage FET 103 (e.g., 2 volts), cascode switch 101 may block cascode switch current I, and when the gate voltage VGS is greater than the threshold voltage of low-voltage FET 103, cascode switch 101 may conduct cascode switch current I between GaN drain D and FET source S. Thus, cascode switch 101 may "turn on" when gate voltage VGS transitions (i.e., switches) cascode switch 101 from its off state to its on state.

[0022] As shown, the cascode switch 101 can support a drain voltage VDS between the GaN drain DH and the FET source S. The drain voltage VDS can also be referred to as the drain-to-source voltage VDS of the cascode switch 101 because the FET source S is electrically coupled to ground.

[0023] As described above, protection circuit 104 includes comparator 105, logic AND gate 106, and controller 108. A non-inverting input of comparator 105 may be electrically coupled to FET drain D to compare a cascode (e.g., cascode circuit) node voltage VDL with a threshold voltage HS_TH (e.g., 5 volts) at an inverting input of comparator 105. When the cascode node voltage VDL is higher than the threshold voltage HS_TH, a comparator output voltage VCMP may be asserted high (i.e., a logic high state).

[0024] As further shown, a first input of logical AND gate 106 may be electrically coupled to the output of comparator 105 to receive comparator output voltage VCMP. A second input of logical AND gate 106 may be electrically coupled to the output of controller 108, and an output of logical AND gate 106 may be electrically coupled to an input of controller 108. As shown, logical AND gate 106 provides signal HSOUT as a logical AND function of comparator output voltage VCMP and enable signal ENHS.

[0025] According to the teachings herein, during turn-on (i.e., after application of the gate voltage VGS), the cascode node voltage VDL may exhibit a plateau, and the protection circuit 104 may determine whether an overcurrent condition exists by monitoring the duration of the plateau. For example, as described below in connection with the waveforms of FIG. 2, the controller 108 may assert the enable signal ENHS high after a calibrated and / or specified period of time (e.g., 300 nanoseconds) after application of the gate voltage VGS.

[0026] Thus, the signal HSOUT may indicate the duration for which the comparator output voltage VCMP remains high (i.e., the duration of the plateau in the cascode node voltage VDL). Subsequently, the controller 108 may, in response to the signal HSOUT, identify that the cascode switch current ID is excessive and may take corrective action (e.g., turn off the cascode switch). In one embodiment, the corrective action (e.g., turning off the cascode switch 101) may be taken after each on-switching event during a switching cycle. Alternatively, or additionally, the corrective action may cause the cascode switch 101 to remain off until the controller 108 is recycled.

[0027] Additionally, driver 110 may be electrically coupled between controller 108 and cascode switch 101 to function as a gate driver. As shown, controller 108 provides a driver input voltage VDR to an input (I) of driver 110, which in turn provides a gate voltage VGS to an output (O). For example, driver 110 may buffer (e.g., amplify) the driver input voltage VDR from controller 108 so that the gate voltage VGS is delivered with sufficient boost power to drive the FET gate G.

[0028] Although driver 110 is shown as being external to controller 108, in other embodiments, driver 110 may be internal to controller 108. For example, controller 108 may implement a low impedance driver output port to directly drive FET gate G using gate voltage VGS.

[0029] Similarly, as one skilled in the art will appreciate, protection circuit 104 may be implemented using more or fewer circuit elements. Alternatively, instead of using comparator 105 and / or logical AND gate 106, cascode node voltage VDL may be provided directly to controller 108. Controller 108 may then use analog and / or digital processing to identify the duration of the plateau.

[0030] Although the controller 108 is described above in the context of the protection circuit 104, the controller 108 may further provide a driver input voltage VDR based on additional system variables. For example, as shown in FIG. 1B, the controller 108 may further receive the output voltage VOUT and provide a driver input voltage VDR to regulate the output voltage VOUT.

[0031] 1B shows a power converter 150 including a cascode switch 101, a protection circuit 104, and a driver 110 according to an embodiment. The power converter 150 includes the circuit 100 of FIG. 1A, a bridge rectifier 95, an inductor L1, a diode DB, an output capacitor CB, and a load RL. Alternating current (AC) input power having an AC voltage VAC may be transmitted between input terminals 91 and 93 to the bridge rectifier 95. The bridge rectifier 95 may subsequently rectify the AC input power to provide a rectified input power (i.e., an input power signal including an inductor current IL and an input voltage VIN) relative to ground GND.

[0032] As shown, the controller 108 may provide a driver input voltage VDR such that the gate voltage VGS switches the cascode switch 101 on and off according to a switching cycle. According to switching power supply theory, the controller 108 may be part of a control loop configured to sample and regulate the output voltage VOUT. When the controller 108 switches the cascode switch 101 on and off according to a steady-state switching frequency, the output voltage VOUT may be regulated. For example, the power converter 150 may be configured as a boost-type converter and / or a boost-type converter with power factor correction (PFC).

[0033] According to the teachings herein, the protection circuit 104 can protect the cascode switch 101 whenever the cascode switch 101 is switched on (i.e., turned on by the gate voltage VGS). For example, if the inductor L1 is shorted, this can create an excessive overcurrent condition in the cascode switch 101. As described herein, the protection circuit 104 can quickly (i.e., in about 100 nanoseconds or less) detect the overcurrent by observing the duration of the plateau in the cascode node voltage VDL.

[0034] Alternatively, and additionally, the protection circuit 104 may protect the cascode switch 101 by switching off the cascode switch 101 for a period (e.g., 1 millisecond) longer than a switching cycle (e.g., 10 microseconds). For example, in response to identifying the presence of an overcurrent condition (e.g., a short circuit), the protection circuit 104 may switch off the cascode switch 101 and keep it off until the controller 108 is refreshed. Furthermore, the protection circuit 104 may identify the anomaly (e.g., a short circuit) after measuring the anomaly over several consecutive cycles (e.g., five consecutive switching cycles).

[0035] According to the teachings herein, the threshold voltage HS_TH and threshold duration THS may be empirically determined and / or calibrated to ensure that the protection circuitry distinguishes between normal operating modes from abnormal modes (i.e., overcurrent and / or short circuit conditions).

[0036] On-switching transient behavior of cascode switches

[0037] For example, Figure 2 compares on-switching waveforms 201, 202a-c, 203a-c, 204a-c, 205a-c, 206a-c, 207, and 208c for different operating modes in accordance with the teachings herein. The different operating modes include discontinuous condition mode (DCM), continuous conduction mode (CCM), and an abnormal mode (e.g., a short circuit or overcurrent condition). As shown, waveforms 201, 202a-c, 203a-c, 204a-c, 205a-c, 206a-c, 207, and 208c are plotted as a function of time relative to an on-switching event occurring at time t0. Thus, times t1-t7 may represent temporal events during the on-switching transient of cascode switch 101.

[0038] As shown in FIG. 2, waveform 201 represents the driver input voltage VDR. Waveforms 202a-c represent the gate voltage VGS (i.e., gate-to-source voltage) of low-voltage FET 103 during DCM, CCM, and abnormal modes, respectively. Waveforms 203a-c represent the cascode node voltage VDL during DCM, CCM, and abnormal modes, respectively. Waveforms 204a-c represent the cascode switch current ID during DCM, CCM, and abnormal modes, respectively. Waveforms 205a-c represent the drain-to-source voltage VDS during DCM, CCM, and abnormal modes, respectively. Waveforms 206a-c represent the comparator output voltage VCMP during DCM, CCM, and abnormal modes, respectively. Waveform 207 represents the enable signal ENHS from controller 108, and waveforms 208a-c represent the signal HSOUT during abnormal modes.

[0039] Behavior before switching on at time t0

[0040] As shown by waveform 201, before time t, driver input voltage V may swing low (e.g., swing to 0 volts). At the same time, driver 110 drives FET gate G low so that cascode switch 101 blocks current in its off state. Thus, as shown by waveforms 202a-c, for a period before time t, driver 110 may hold gate voltage V substantially equal to zero.

[0041] Furthermore, the cascode node voltage VDL may have a steady-state value that depends at least in part on the threshold voltage magnitude GaN_VTH (e.g., 10 volts) of the GaN depletion mode FET 102. Thus, over a period of time prior to time t0, the cascode node voltage VDL may maintain a maximum node voltage VDL_MX (e.g., 15 volts) as shown by waveforms 203a-c. Furthermore, in accordance with the teachings herein, the threshold voltage HS_TH may be selected (e.g., calibrated) to indicate an overcurrent condition, and thus the threshold voltage HS_TH may have a value (e.g., 5 volts) that is less than the threshold voltage magnitude GaN_VTH.

[0042] Before time t0, while the cascode switch 101 is operating in the OFF state, the cascode switch current I may be substantially equal to its OFF-state (e.g., leakage) current. Thus, for the period before t0, the cascode switch current I may be substantially equal to zero (e.g., less than 100 microamperes), as shown in waveforms 204a-c.

[0043] At the same time, before time t0, cascode switch 101 can withstand a drain voltage VDS that is determined at least in part based on the breakdown voltage (e.g., 800 volts) of GaN depletion mode FET 102. Thus, before time t0, drain voltage VDS can be at its maximum drain voltage VDS_MX (e.g., 600 volts) as shown in waveforms 205a-c.

[0044] Furthermore, before time t0, while the cascode switch 101 is off, the protection circuit 104 may be in a standby state and / or disabled thanks to the enable signal ENHS. For example, referring to waveforms 203a-c, the cascode node voltage VDL may be higher than the threshold voltage HS_TH. Therefore, the comparator output voltage VCMP may indicate that the cascode node voltage VDL is higher than the threshold voltage HS_TH. Therefore, as shown in waveforms 206a-c, before time t0, the comparator output voltage VCMP is logic high (e.g., 5 volts).

[0045] However, before time t0, controller 108 may swing enable signal ENHS low so that the output of logic AND gate 106 remains low. Thus, as shown in waveform 207 and waveform 208c, enable signal ENHS may swing low (e.g., 0 volts), and therefore signal HSOUT remains low (e.g., 0 volts).

[0046] Behavior at time t0

[0047] At time t0 (e.g., zero nanoseconds), the controller 108 may swing the driver input voltage VDR to initiate switching on (e.g., to begin the process of switching on the cascode switch 101). For example, as shown in waveform 201, the driver input voltage VDR may swing high (e.g., 5 volts) at time t0.

[0048] In accordance with the teachings herein, the threshold duration THS may be a duration that begins simultaneously and / or substantially simultaneously with the initiating on-switch event at time t0. For example, an analog and / or digital timer may begin timing the threshold duration THS beginning at time t0, and the threshold duration THS may have a preselected value (e.g., 250 nanoseconds) based on empirical data and / or calibration.

[0049] In response to the transition in the driver input voltage VDR at time t0, the driver 110 may begin to drive the FET gate G. For example, the gate voltage VGS may begin to ramp (i.e., increase in voltage), as shown in waveforms 202a-c.

[0050] Furthermore, at time t0, low-voltage FET 103 may momentarily remain in its off state. Thus, at time t0, cascode switch 101 may be off. For example, as shown in waveforms 203a-c, cascode node voltage VDL may remain at its maximum node voltage VDL_MX. As shown in waveforms 204a-c, drain current ID may be substantially equal to its cut-off state (e.g., leakage) current, and, according to waveforms 205a-c, drain voltage VDS may remain at the maximum drain voltage VDS_MX.

[0051] Furthermore, at time t0, the cascode node voltage VDL may remain higher than the threshold voltage HS_TH as shown in waveforms 203a-c, and therefore, at time t0, the comparator output voltage VCMP remains at logic high (e.g., 5 volts) as shown in waveforms 206a-c.

[0052] According to the teachings herein, the duration threshold may begin at time t0. Thus, as shown in waveform 207 and waveform 208c, enable signal ENHS may continue to swing low (e.g., 0 volts) so that signal HSOUT remains low (e.g., 0 volts) at time t0.

[0053] Behavior from time t0 to time t1

[0054] As shown by waveform 201, from time t0 to time t1, controller 108 may continue to swing driver input voltage VDR high. Driver 110 then continues to drive FET gate G. Thus, gate voltage VGS may continue to rise (i.e., ramp), and the rate of increase (i.e., the time derivative of gate voltage VGS) may depend at least in part on the capacitance (e.g., gate capacitance) of low-voltage FET 103. Thus, as shown in waveforms 202a-c, gate voltage VGS rises from its low value (e.g., 0 volts) at time t0 (e.g., zero nanoseconds) toward a value VG1 (e.g., 2 volts) at time t1 (e.g., 10 nanoseconds).

[0055] During the period from time t0 to time t1, GaN depletion-mode FET 102 has not yet been switched on, and low-voltage FET 103 has not yet been switched on strongly enough to pull down GaN source SH. Thus, from time t0 to time t1, cascode switch 101 may remain off. For example, as shown in waveforms 203a-c, cascode node voltage VDL remains at its maximum node voltage VDL_MX. As shown in waveforms 204a-c, drain current ID may continue to remain substantially equal to its cut-off state (e.g., leakage) current, and according to waveforms 205a-c, drain voltage VDS remains at the maximum drain voltage VDS_MX.

[0056] Furthermore, as shown in waveforms 203a-c, from time t0 to time t1, the cascode node voltage VDL may remain higher than the threshold voltage HS_TH. Thus, as shown in waveforms 206a-c, from time t0 to time t1, the comparator output voltage VCMP may remain at logic high (e.g., 5 volts). Furthermore, as shown in waveforms 207 and 208c, from time t0 to time t1, the enable signal ENHS may continue to swing low (e.g., 0 volts), and thus the signal HSOUT may remain low (e.g., 0 volts).

[0057] Behavior at time t1

[0058] At time t1 (e.g., 10 nanoseconds), controller 108 may continue to swing driver input voltage VDR high, as shown by waveform 201, causing driver 110 to continue driving FET gate G. Gate voltage VGS may reach a value VG1 (e.g., 2 volts), causing low-voltage FET 103 to provide enough drive to begin pulling down GaN source SH. For example, value VG1 may be a value substantially equal to the threshold voltage of low-voltage FET 103. Furthermore, low-voltage FET 103 may begin to have a higher gain, resulting in an increase in effective gate capacitance (e.g., Miller capacitance).

[0059] Thus, at time t1, the rate of change of the gate voltage V may decrease due in part to an increase in the effective gate capacitance at the FET gate G. Thus, as shown in waveforms 202a-c, the rate of change (i.e., the time derivative) of the gate voltage V decreases.

[0060] Furthermore, at time t1, GaN depletion-mode FET 102 has not yet been switched on, but low-voltage FET 103 may be strong enough to pull down GaN source SH. Thus, as shown in waveforms 203a-c, cascode node voltage VDL may begin to decrease from its maximum node voltage VDL_MX. As shown in waveforms 204a-c, drain current ID may continue to remain substantially equal to its cutoff state (e.g., leakage) current, and waveforms 205a-c show that drain voltage VDS remains at maximum drain voltage VDS_MX.

[0061] Furthermore, as shown in waveforms 203a-c, the cascode node voltage VDL remains above the threshold voltage HS_TH. Thus, at time t1, the comparator output voltage VCMP remains at logic high (e.g., 5 volts), as shown in waveforms 206a-c. Furthermore, the enable signal ENHS may continue to swing low (e.g., 0 volts) so that the signal HSOUT remains low (e.g., 0 volts), as shown in waveforms 207 and 208c.

[0062] Behavior from time t1 to time t2

[0063] From time t1 to time t2, as shown by waveform 201, controller 108 may continue to swing driver input voltage VDR high, and thus driver 110 may continue to drive FET gate G. During the period from time t1 to time t2, GaN depletion mode FET 102 may continue to be off, and low-voltage FET 103 may continue to provide enough drive to begin to pull down GaN source SH. Thus, the rate of change (i.e., time derivative) of gate voltage VGS may continue to be reduced due to the higher gain.

[0064] Therefore, as shown in waveforms 202a-c, the rate of change (i.e., the time derivative) of the gate voltage VGS is reduced so that the gate voltage VGS at time t2 can be substantially equal to the gate voltage VGS at time t1 (i.e., the value VG1 at time t1).

[0065] Furthermore, from time t1 to time t2, GaN depletion mode FET 102 may be off, while low-voltage FET 103 may continue to pull down GaN source SH. Thus, as shown in waveforms 203a-c, cascode node voltage VDL may monotonically decrease from its maximum node voltage VDL_MX at time t1 toward a threshold voltage magnitude GaN_VTH. As shown in waveforms 204a-c, drain current ID may continue to remain substantially equal to its cut-off state (e.g., leakage) current, and drain voltage VDS may remain at a maximum drain voltage VDS_MX, according to waveforms 205a-c.

[0066] As shown in waveforms 203a-c, the cascode node voltage VDL remains above the threshold voltage HS_TH. Thus, as shown in waveforms 206a-c, from time t1 to time t2, the comparator output voltage VCMP remains at logic high (e.g., 5 volts). Furthermore, as shown in waveforms 207 and 208c, the enable signal ENHS may continue to swing low (e.g., 0 volts) so that the signal HSOUT remains low (e.g., 0 volts).

[0067] Behavior at time t2

[0068] At time t2 (e.g., 20 nanoseconds), controller 108 may continue to swing driver input voltage VDR high, as shown by waveform 201. Driver 110 then continues to drive FET gate G so that GaN depletion mode FET 102 begins to switch on. The rate of change of gate voltage VGS remains low, as shown by waveforms 202a-c.

[0069] When GaN depletion mode FET 102 is turned on, cascode switch 101 is turned on. Thus, the rate of change of cascode node voltage VDL can vary, as shown by waveforms 203a-c.

[0070] As shown in waveforms 203a-c, the cascode node voltage VDL may still be greater than the threshold voltage HS_TH. Thus, as shown in waveforms 206a-c, the comparator output voltage VCMP may remain at a logic high (e.g., 5 volts). Furthermore, as shown in waveforms 207 and 208c, the enable signal ENHS may continue to swing low (e.g., 0 volts) so that the signal HSOUT remains low (e.g., 0 volts).

[0071] According to the teachings herein, when the cascode switch 101 is turned on, the transient behavior of the cascode switch 101 may become more mode dependent at time t2.

[0072] DCM behavior after time t2

[0073] During DCM after time t2, the cascode node voltage VDL drops below the threshold voltage HS_TH at time t3 (eg, 100 ns) within the threshold duration THS (eg, 250 ns).

[0074] In DCM, the cascode switch 101 can be switched on quickly and is configured to operate with zero current switching (ZCS).

[0075] After time t2, as shown by waveform 201, controller 108 continues to swing driver input voltage VDR high.

[0076] As shown in waveform 202a, the rate of change of the gate voltage V remains low, and the gate voltage V is slightly higher than the value VG1 until time t4 (e.g., 150 nanoseconds). At time t4, the gate voltage V may rise due, at least in part, to a decrease in the gain of the cascode switch. The decrease in gain may be accompanied by a decrease in capacitance (e.g., Miller capacitance) at the FET gate G. Thus, the gate voltage V rises until it reaches a maximum limit VG2 (e.g., 20 volts).

[0077] As shown in waveform 203a, the cascode node voltage VDL drops to the threshold voltage HS_TH by time t3 (e.g., 100 nanoseconds). As will be described below, and according to semiconductor device physics, the cascode node voltage VDL may reach the threshold voltage HS_TH by time t3 due, at least in part, to the low-voltage FET 103 coming out of saturation.

[0078] As shown in waveform 204a, the cascode switch current I increases and decreases according to the DCM configuration and DCM operating conditions. Compared to waveform 204b (CCM) and waveform 204c (fault mode), waveform 204a exhibits the minimum cascode switch current I as a function of time.

[0079] For example, under DCM operating conditions, the cascode switch current I reaches a limit value before time t3 and decreases toward a minimum value (e.g., about zero amperes) at time t4. At the same time, the low-voltage FET 103 may begin to operate out of saturation according to the following relationship (Equation 1) for the cascode switch current I as a function of the transconductance GM_LVFET and threshold voltage V of the low-voltage FET 103: ID<(VGS-VTH)×GM_LVFET Equation 1 Subsequently, the low-voltage FET 103 may pull the cascode node voltage VDL at a faster rate determined at least in part by the ratio of the cascode switch current ID to the transconductance GM_LVFET (i.e., the ratio ID / GM_LVFET). For example, as shown by waveform 203a, the cascode node voltage VDL decreases at a faster rate after time t2.

[0080] Between time t3 and time t4, as shown in waveform 205a, the drain voltage VDS decreases and reaches its low value (eg, a voltage less than 1 volt).

[0081] As shown in waveform 206a, the comparator output voltage VCMP transitions from high (e.g., 5 volts) to low (e.g., 0 volts) at time t3 in response to the cascode node voltage VDL reaching and / or falling below the threshold voltage HS_TH.

[0082] As shown in waveform 207, the threshold duration THS lasts from time t0 to time t6 (e.g., 250 nanoseconds), at which time the controller 108 may transition (i.e., swing) the enable signal ENHS high (e.g., 5 volts).

[0083] Because the comparator output voltage VCMP swings low at time t3, which is before time t6 and within the threshold duration THS, the logic AND gate 106 maintains the signal HSOUT low (e.g., 0 volts) for the entire period (e.g., from time t0 to time t7 inclusive). In this manner, the protection circuit 104 recognizes DCM as a normal mode in which no faults are present (e.g., no short circuit and / or overcurrent condition is present).

[0084] CCM behavior after time t2

[0085] During CCM after time t2, the cascode node voltage VDL drops below the threshold voltage HS_TH at time t5 (eg, 200 ns) within the threshold duration THS (eg, 250 ns).

[0086] After time t2, as shown by waveform 201, controller 108 continues to swing driver input voltage VDR high.

[0087] As shown in waveform 202b, the rate of change of the gate voltage V remains low, and the gate voltage V is slightly higher than the value VG1 until time t6 (e.g., 250 nanoseconds). At time t6, the gate voltage V may rise due, at least in part, to a decrease in the gain of the cascode switch. The decrease in gain may be accompanied by a decrease in capacitance (e.g., Miller capacitance) at the FET gate G. Thus, the gate voltage V rises until it reaches a maximum limit VG2 (e.g., 20 volts).

[0088] As shown in waveform 203b, the cascode node voltage VDL drops to the threshold voltage HS_TH by time t5 (e.g., 200 nanoseconds). As explained herein and according to semiconductor device physics, the cascode node voltage VDL may reach the threshold voltage HS_TH by time t5 due at least in part to the low-voltage FET 103 coming out of saturation.

[0089] As shown in waveform 204b, the cascode switch current I increases and decreases according to the CCM configuration. The cascode switch current I may rise (i.e., increase) until time t4. In one embodiment, at time t4, an external component, such as a boost diode (e.g., diode DB), may begin to recover, causing the cascode switch current I to decrease. Compared to waveform 204a (DCM) and waveform 204c (abnormal mode), waveform 204b exhibits a larger switch current I than waveform 204a, but waveform 204b exhibits a smaller switch current I than waveform 204c (abnormal mode) for a period after time t4.

[0090] For example, under CCM operating conditions, the cascode switch current I may reach a limit value at time t4 and vary depending on load conditions. At the same time, the low-voltage FET 103 may begin to operate out of saturation according to the above relationship (Equation 1) for the cascode switch current I. Subsequently, the low-voltage FET 103 may pull the cascode node voltage V at a higher rate determined at least in part by the ratio of the cascode switch current I to the transconductance GM_LVFET (i.e., the ratio I / GM_LVFET). For example, after time t4, the cascode node voltage V decreases at a faster rate, as shown by waveform 203b.

[0091] Between time t5 and time t6, as shown in waveform 205b, the drain voltage VDS decreases and reaches its low value (eg, a voltage less than 1 volt).

[0092] As shown in waveform 206b, at time t5, the comparator output voltage VCMP transitions from high (e.g., 5 volts) to low (e.g., 0 volts) in response to the cascode node voltage VDL reaching and / or falling below the threshold voltage HS_TH.

[0093] As shown in waveform 207, the threshold duration THS lasts from time t0 to time t6 (e.g., 250 nanoseconds), at which time the controller 108 may transition (i.e., swing) the enable signal ENHS high (e.g., 5 volts).

[0094] Because the comparator output voltage VCMP swings low at time t5, which is before time t6 and within the threshold duration THS, the logic AND gate 106 maintains the signal HSOUT low (e.g., 0 volts) for the entire period (e.g., from time t0 to time t7 inclusive). In this manner, the protection circuit 104 recognizes CCM as a normal mode in which no faults are present (e.g., no short circuit and / or overcurrent condition is present).

[0095] Abnormal mode behavior after time t2

[0096] During a fault mode (e.g., a short circuit and / or an overcurrent condition) after time t2, the cascode node voltage VDL drops below the threshold voltage HS_TH at time t7 (e.g., 300 ns). As shown, time t7 occurs after a threshold duration THS (e.g., 250 ns).

[0097] After time t2, as shown by waveform 201, controller 108 continues to swing driver input voltage VDR high.

[0098] As shown in waveform 202c, the rate of change of the gate voltage V remains low, and the gate voltage V is slightly above the value VG1. For example, the low-voltage FET 103 may continue to operate in saturation. Therefore, for the entire illustrated period after time t2, the gate voltage V does not reach the maximum limit VG2 (e.g., 20 volts).

[0099] As shown in waveform 203c, the cascode node voltage VDL gradually decreases (i.e., exhibits a plateau) and reaches the threshold voltage HS_TH by time t7 (e.g., 300 nanoseconds). In contrast to operation during DCM and CCM, operation during a fault may gradually decrease due, at least in part, to the low-voltage FET 103 remaining in saturation. The gradual decrease (i.e., plateau) in the cascode node voltage VDL may also be due, at least in part, to gain. As described above with respect to waveform 202c, the low-voltage FET 103 may be operating in its saturation region with high gain. Thus, the plateau may indicate gain and / or high gain, which may be referred to as cascode circuit gain.

[0100] As shown in waveform 204c, the cascode switch current I ramps (i.e., increases) in accordance with the abnormal condition (e.g., a short circuit). Compared to waveform 204a (DCM) and waveform 204b (CCM), waveform 204c exhibits a larger switch current I. For example, as shown in waveform 204c, at time t7, the cascode switch current I may ramp to and / or be greater than 20 amperes due at least in part to the abnormal condition.

[0101] In contrast to CCM and DCM, during fault conditions, the cascode switch current ID increases so that the low-voltage FET 103 continues to operate in saturation. Therefore, the cascode switch current ID may continue to change according to the following relationship (Equation 2): ID=(VGS-VTH)×GM_LVFET Equation 2 Subsequently, the cascode node voltage VDL may gradually decrease according to the following relationship (Equation 3) for the cascode switch current ID as a function of the transconductance GM_GaN of the depletion-mode FET 102: VDL=GaN_VTH-ID / GM_GaN Equation 3

[0102] Therefore, when the transconductance GM_GaN is large, the cascode node voltage VDL may decrease gradually (i.e., have a small slope). Furthermore, during fault conditions, the GaN depletion mode FET 102 may be exposed to high voltages.

[0103] For example, as shown in waveform 205c, the drain voltage VDS remains substantially equal to its maximum drain voltage VDS_MX for the period shown after time t2.

[0104] As shown in waveform 206c, in response to the cascode node voltage VDL reaching and / or falling below the threshold voltage HS_TH, the comparator output voltage VCMP transitions from high (e.g., 5 volts) to low (e.g., 0 volts) at time t7.

[0105] As shown in waveform 207, the threshold duration THS lasts from time t0 to time t6 (e.g., 250 nanoseconds), at which time the controller 108 may transition (i.e., swing) the enable signal ENHS high (e.g., 5 volts).

[0106] Because the comparator output voltage VCMP remains high after time t6 and after the threshold duration THS, the logic AND gate 106 transitions (i.e., swings) the signal HSOUT high (e.g., 5 volts) at time t6. The signal HSOUT remains high until time t7, at which time the comparator output voltage VCMP swings low.

[0107] In this manner, protection circuit 104 recognizes the presence of a fault (e.g., an overcurrent and / or short-circuit condition). During the period from time t6 to time t7 while signal HSOUT is pulled high, controller 108 can use that information to implement corrective action. For example, as shown in FIG. 3 below, controller 108 can immediately turn off cascode switch 101 in response to signal HSOUT transitioning from low to high.

[0108] FIG. 3 illustrates empirical waveforms 301-302 according to an embodiment. Waveform 301 illustrates the cascode node voltage VDL from time TA to time TC, while waveform 302 illustrates the cascode switch current ID from time TA to time TC. Referring to FIG. 2, time TA may correspond to the transition of waveform 201 at time t0, time TB may correspond to time t6, and time TC may correspond to a time after time t6. Furthermore, the threshold duration may begin at time TA and end at time TB, and referring to FIG. 2, time TC may correspond to any time in the interval from time t6 to time t7 while signal HSOUT is asserted high. For example, time TA may be zero nanoseconds (0 ns). time TB may be 250 nanoseconds (250 ns), and time TC may be 255 nanoseconds (255 ns).

[0109] 1B, the overcurrent condition may be at least partially due to a short circuit. For example, inductor L1 may be shorted with a low impedance substantially equal to zero ohms (e.g., a 1 milliohm short). The calibrated value of threshold voltage HS_TH may be approximately 4 volts (e.g., 4.15 volts), and the calibrated value of threshold duration THS may be less than 300 nanoseconds (e.g., 250 nanoseconds).

[0110] Furthermore, as shown in waveforms 301-302, the cascode node voltage VDL may gradually decrease (i.e., exhibit a plateau) during an overcurrent condition (e.g., a short circuit of inductor L1). For example, the cascode node voltage VDL at time TA may be 10 volts, and the cascode node voltage VDL at time TC may be 7 volts. Thus, at time TB after the expiration of the threshold duration THS, the protection circuit 104 may determine that the cascode node voltage VDL is greater than the threshold voltage HS_TH.

[0111] The protection circuit 104 may then take corrective action to protect the cascode switch 101. For example, the drive signal VDR may be quickly pulled low (e.g., within 1 nanosecond) by the controller 108 at time TB. Subsequently, when the cascode switch current I reaches 40 amperes at time TC, the driver 110 may drive the gate voltage VGS low.

[0112] Therefore, according to the teachings herein, the protection circuit 104 can beneficially and rapidly (e.g., within 300 nanoseconds) switch off the cascode switch 101 before the cascode switch current I exceeds its maximum rated current (e.g., a maximum rated current of 50 amperes).

[0113] According to the teachings herein, the protection circuit 104 can observe the cascode node voltage VDL from the cascode switch 101 for the entire period immediately following time t0. Therefore, protection can be achieved quickly and without leading-edge blanking. Furthermore, according to the teachings herein, an abnormal condition can occur when the cascode node voltage exhibits a plateau and gradually decreases as a function of time. For example, waveform 203c can gradually decrease from time t2 to time t7, and therefore waveform 203c can be characterized as exhibiting a plateau between time t2 and time t7.

[0114] Furthermore, according to the teachings herein, the protection circuit 104 may detect an overcurrent condition based on the following relationship (Equation 4) of the cascode node voltage VDL for a period of time after time t0 (ie, the turn-on time t0): VDL ≥ HS_TH for {time: (t0 + THS) ≤ time} Equation 4 Thus, according to the above relationship (Equation 4), if the cascode node voltage VDL is substantially greater than and / or equal to the threshold voltage HS_TH for at least the threshold duration THS, an overcurrent condition may exist.

[0115] In one embodiment, and depending on the semiconductor device operation, the plateau may be the result of gain (e.g., cascode switch gain). For example, during the plateau from time t2, low-voltage FET 103 may be operating in its saturation region (i.e., high-gain, high-transconductance region).

[0116] Furthermore, the protection circuit 104 can determine that the cascode switch 101 is operating in an abnormal (i.e., overcurrent) mode thanks to the comparator 105 and thanks to the threshold duration THS (i.e., the period THS). The threshold duration THS (i.e., the period THS) can be determined, for example, by the controller 108. Furthermore, the comparator 105 can compare the cascode node voltage VDL with a threshold voltage HS_TH. If the comparator 105 remains in a logic high state (e.g., the comparator output voltage VCMP is high) for longer than the period THS, the controller 108 can cause the enable signal ENHS to go logic high (see, for example, waveform 207 at time point t6).

[0117] In one embodiment, the controller may adaptively adjust the threshold duration THS in response to system parameters, for example, the controller may adaptively adjust the threshold duration THS as a function of load.

[0118] In one embodiment, the power converter includes a cascode circuit (e.g., cascode switch 101) and an overcurrent detection circuit (e.g., protection circuit 104). The cascode circuit includes a depletion-mode field-effect transistor 102 and an enhancement-mode field-effect transistor 103 electrically cascode-coupled to provide a cascode node voltage VDL. The overcurrent detection circuit is configured to detect an overcurrent fault condition during turn-on (e.g., see waveform 207 from time t0 to time t6 in FIG. 2). The overcurrent condition occurs during the plateau of the cascode node voltage VDL (i.e., while waveform 203c gradually decreases). As described above, the plateau may indicate the gain of the cascode switch 101. For example, the plateau may indicate that the low-voltage FET 103 is operating in a saturated state.

[0119] In another aspect, a method for detecting an overcurrent in a gallium nitride (GaN) cascode circuit (e.g., cascode switch 101) includes switching on the GaN cascode circuit with a transient step (e.g., waveform 201 at time t0), receiving a cascode node voltage VDL, identifying when the cascode node voltage VDL enters a plateau (e.g., waveform 203c), and indicating an overcurrent fault (e.g., waveforms 207, 208c). For example, the protection circuit 104 and the comparator 105 may determine that the cascode node voltage VDL is slowly decreasing by comparing the cascode node voltage VDL with a reference voltage HS_TH. If this condition exists for longer than a time period THS, an overcurrent condition may exist. Thus, an overcurrent fault is indicated in response to the plateau existing for longer than a threshold duration (i.e., time period THS).

[0120] The protection circuit 104 can detect when the cascode switch 101 enters an abnormal state (e.g., excessive switch current ID) without any limitation on how the abnormality occurs and without any limitation on the power converter configuration. In one configuration, the protection circuit 104 can be used to quickly detect an overcurrent (i.e., an overcurrent of the cascode switch current ID). For example, in a PFC converter, if the PFC inductor shorts out, the cascode switch 101 can be exposed to a very large current (e.g., 50 amperes) for a short period of time (e.g., 100 nanoseconds). Alternatively and additionally, if the boost diode shorts out, the cascode switch 101 (e.g., a GaN cascode switch) used as the main switch in a boost-type converter can be exposed to a very large current.

[0121] In one application, the controller 108 may protect the cascode switch 101 by immediately switching it off in response to identifying an abnormal condition (i.e., an overcurrent condition). For example, when the signal HSOUT is pulled high, the controller 108 may pull the input drive signal VDR low. Alternatively, and additionally, the controller 108 may prevent the cascode switch 101 from switching on until after the controller 108 is recycled. Furthermore, the controller 108 may be programmed to switch the cascode switch 101 off after an overcurrent condition is detected for more than a set number of switching cycles (e.g., five).

[0122] The foregoing description of illustrated examples of the present disclosure, including matters described in the Abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. Specific embodiments and examples of fast-on protection of cascode switches are described herein with reference to the following figures, which are described for illustrative purposes, but various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it will be understood that specific and example voltages, currents, frequencies, power range values, times, and the like are presented for illustrative purposes, and that other values ​​may be used in other embodiments and examples in accordance with the teachings herein.

[0123] While the present invention is defined in the claims, it should be understood that the invention may alternatively be defined by the following examples.

[0124] Example 1: A power converter includes a cascode circuit and an over-current detection circuit. The cascode circuit includes a depletion-mode field-effect transistor and an enhancement-mode field-effect transistor electrically cascode-coupled. The cascode circuit is configured to provide a cascode node voltage. The over-current detection circuit is configured to detect an over-current fault condition during turn-on, the over-current fault condition occurring during a plateau of the cascode node voltage, the plateau indicating an increase in cascode circuit gain.

[0125] Example 2: The power converter of example 1, wherein the over-current detection circuit comprises a comparator.

[0126] Example 3: The power converter of any one of the preceding examples, wherein the over-current detection circuit comprises an AND gate.

[0127] Example 4: The power converter of any one of the preceding examples, wherein the over-current detection circuit comprises a controller.

[0128] Example 5: The power converter of any one of the preceding examples, wherein the depletion mode field effect transistor is a gallium nitride (GaN) depletion mode transistor.

[0129] Example 6: The power converter of any one of the preceding examples, wherein the depletion mode field effect transistor is a silicon carbide (SiC) depletion mode transistor.

[0130] Example 7: The power converter of any one of the preceding examples, wherein the enhancement mode field effect transistor is a low voltage field effect transistor.

[0131] Example 8: A method for detecting an overcurrent in a gallium nitride (GaN) cascode circuit includes switching on the GaN cascode circuit with a transient step, receiving a cascode node voltage indicative of the cascode circuit gain, identifying when the cascode node voltage enters a plateau indicative of an increase in the cascode circuit gain, and indicating an overcurrent fault in response to the plateau existing for more than a threshold duration.

[0132] Example 9: The method of any one of the preceding examples, wherein switching on the GaN cascode circuit includes providing a gate signal to a low-voltage field-effect transistor.

[0133] Example 10: The method of any one of the preceding examples, wherein receiving a cascode node voltage indicative of a cascode circuit gain includes receiving a drain voltage of a low-voltage field-effect transistor.

[0134] Example 11: The method of any one of the preceding examples, wherein identifying when the cascode node voltage enters a plateau indicative of an increase in cascode circuit gain includes comparing a drain voltage of the low-voltage field-effect transistor to a threshold voltage.

[0135] Example 12: Indicating an overcurrent fault in response to the plateau existing for more than a threshold duration includes identifying the threshold duration using a controller. The method of any one of the preceding examples.

[0136] Example 13: A method for rapidly detecting an overcurrent in a power converter includes switching on a cascode switch with a transient step, receiving a cascode node voltage indicative of a cascode circuit gain, identifying when the cascode node voltage enters a plateau indicative of an increase in the cascode circuit gain, and indicating an overcurrent fault in response to the plateau existing for more than a threshold duration.

[0137] Example 14: The method of any one of the preceding examples, wherein the cascode switch comprises a depletion-mode field-effect transistor and an enhancement-mode field-effect transistor electrically cascode-coupled.

[0138] Example 15: The method of any one of the preceding examples, wherein switching on the cascode switch includes providing a gate signal to an enhancement mode field effect transistor.

[0139] Example 16: The method of any one of the preceding examples, wherein receiving a cascode node voltage indicative of a cascode circuit gain includes receiving a drain voltage of an enhancement mode field effect transistor.

[0140] Example 17: The method of any one of the preceding examples, wherein identifying when the cascode node voltage enters a plateau indicating an increase in cascode circuit gain includes comparing an enhancement mode field effect transistor to a threshold voltage.

[0141] Example 18: The method of any one of the preceding examples, wherein the threshold voltage is between 1 volt and 10 volts.

[0142] Example 19: The method of any one of the preceding examples, wherein indicating an overcurrent fault in response to the plateau being present for longer than a threshold duration includes identifying the threshold duration using the controller.

[0143] Example 20: The method of any one of the preceding examples, wherein the threshold duration is between 100 nanoseconds and 300 nanoseconds.

[0144] (Additional note 1) a cascode circuit including a depletion mode field effect transistor and an enhancement mode field effect transistor electrically cascode coupled, the cascode circuit configured to provide a cascode node voltage; An overcurrent detection circuit, comprising: a comparator electrically coupled to the cascode node voltage, the comparator configured to compare the cascode node voltage to a threshold voltage to indicate when the cascode node voltage has entered a plateau; a control device configured to monitor a duration of the plateau in the cascode node voltage during turn-on, wherein the over-current detection circuit is configured to detect an over-current fault condition during turn-on when the duration exceeds a threshold duration; the overcurrent detection circuit, A power converter comprising: (Additional note 2) the overcurrent detection circuit includes an AND gate; 10. The power converter of claim 1. (Additional note 3) The depletion-mode field effect transistor is a gallium nitride (GaN) depletion-mode transistor. 10. The power converter of claim 1. (Additional note 4) The depletion-mode field effect transistor is a silicon carbide (SiC) depletion-mode transistor. 10. The power converter of claim 1. (Additional note 5) The enhancement type field effect transistor is a low voltage field effect transistor. 10. The power converter of claim 1. (Additional note 6) 1. A method for detecting overcurrent in a gallium nitride (GaN) cascode circuit, the method comprising: Switching on the GaN cascode circuit with a transient step by providing a gate signal to a low voltage field effect transistor; receiving a cascode node voltage by receiving a drain voltage of the low voltage field effect transistor; determining when the cascode node voltage enters a plateau by comparing the drain voltage of the low voltage field effect transistor to a threshold voltage; identifying a threshold duration using a controller to indicate an overcurrent fault in response to the plateau existing for longer than the threshold duration; A method comprising: (Additional note 7) the GaN cascode circuit comprises a depletion-mode field-effect transistor electrically cascode-coupled with the low-voltage field-effect transistor; The method described in Appendix 6. (Additional note 8) The low-voltage field-effect transistor is an enhancement-mode field-effect transistor. The method described in Appendix 6. (Additional note 9) the threshold voltage is between 1 volt and 10 volts; The method described in Appendix 6. (Additional note 10) the threshold duration is between 100 nanoseconds and 300 nanoseconds; The method described in Appendix 6.

Claims

1. A method for rapidly detecting an overcurrent in a power converter, said method comprising: turning on a cascode switch including a depletion mode field effect transistor and an enhancement mode field effect transistor cascode-coupled; receiving a cascode node voltage, the cascode node voltage being a voltage at the drain of the enhancement mode field effect transistor and the source of the depletion mode field effect transistor; monitoring the duration of the plateau exhibited by the cascode node voltage; indicating an overcurrent fault in response to the plateau existing for greater than a threshold duration; A method comprising:

2. The method of claim 1, wherein switching on the cascode switch comprises providing a gate signal to the enhancement mode field effect transistor. The method of claim 1.

3. The method of claim 2, wherein determining when the cascode node voltage enters the plateau comprises comparing the cascode node voltage to a threshold voltage. The method of claim 1.

4. The threshold voltage is between 1 volt and 10 volts; the threshold duration is between 100 nanoseconds and 300 nanoseconds; The method of claim 3.

5. Indicating the overcurrent anomaly in response to the plateau existing for longer than the threshold duration includes identifying the threshold duration using a control device. The method of claim 3.

6. The threshold duration is between 100 nanoseconds and 300 nanoseconds. The method of claim 5.

7. The cascode node voltage gradually decreases during the plateau. The method of claim 1.

8. A cascode circuit including a depletion mode field effect transistor and an enhancement mode field effect transistor electrically cascode coupled, the cascode circuit providing a cascode node voltage at the drain of the enhancement mode field effect transistor and the source of the depletion mode field effect transistor; an overcurrent detection circuit configured to detect an overcurrent fault condition during turn-on by monitoring a duration of a plateau of the cascode node voltage and comparing the duration of the plateau to a threshold duration; A power converter comprising:

9. The overcurrent detection circuitry comprising: a comparator coupled to compare the cascode node voltage to a threshold voltage, the threshold voltage being less than a threshold voltage of the depletion mode field effect transistor and indicating an overcurrent condition.

9. The power converter of claim 8.

10. The overcurrent detection circuit, comprising: an AND gate coupled to an output of the comparator and to an enable signal; the enable signal is asserted after the threshold duration has elapsed; 10. The power converter of claim 9.

11. The overcurrent detection circuit, comprising: a controller configured to assert the enable signal high after the threshold duration has elapsed.

11. The power converter of claim 10.

12. The control device configured to adaptively adjust the threshold duration in response to system parameters.

12. The power converter of claim 11.

13. The control device configured to adaptively adjust the threshold duration in response to a load powered by the power converter.

12. The power converter of claim 11.

14. The cascode node voltage gradually decreases during the plateau.

9. The power converter of claim 8.

15. The depletion-mode field-effect transistor according to claim 1, wherein the depletion-mode field-effect transistor is a gallium nitride (GaN) depletion-mode transistor or a silicon carbide (SiC) depletion-mode transistor.

9. The power converter of claim 8.

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