Semiconductor device and grating fin

Abstract

To provide a semiconductor device and a grating fin that can improve the cooling efficiency.SOLUTION: A semiconductor device 1 in an embodiment includes a semiconductor module 10 including a semiconductor chip 11 having a first surface and a second surface, and a grating fin 30 disposed on a second surface side of the semiconductor chip 11. The grating fin 30 includes a first grating body 31 including multiple first rod parts 50 extending in a rod shape in a first direction, in which multiple first groove parts 55 are formed between the adjacent first rod parts 50 by the arrangement of the first rod parts 50 with a space therebetween in an arrangement direction, and a second grating body 32 including multiple second rod parts 60 extending in a rod shape in a second direction, in which multiple second groove parts 65 are formed between the adjacent second rod parts 60 by the arrangement of the second rod parts 60 with a space therebetween in the arrangement direction. The first grating body 31 and the second grating body 32 are stacked in a stacking direction.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices and grid fins. [Background technology]

[0002] Patent Documents 1 to 3 disclose semiconductor devices in which a cooler and a power module are integrated together. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-183058 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-146801 [Patent Document 3] Japanese Patent Application Laid-Open No. 2015-216409 Summary of the Invention [Problem to be solved by the invention]

[0004] Power modules have large heat capacity and consume large amounts of power. Therefore, as power density increases, appropriate cooling and heat dissipation design is essential. It is known that insufficient cooling of a power module can affect its lifespan and reliability. There is a demand for semiconductor devices with a structure that can more easily and efficiently cool a power module.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device comprises a semiconductor module including a semiconductor chip having a first surface and a second surface opposite to the first surface, and a lattice-like fin arranged on the second surface side of the semiconductor chip, wherein the lattice-like fin includes: a first lattice body including a plurality of first rod portions extending in a rod-like manner in a first direction within a first plane, wherein one end of the plurality of first rod portions and the other end opposite the one end are arranged at intervals in an arrangement direction intersecting the first direction within the first plane, thereby forming a plurality of first groove portions between adjacent first rod portions; and a second lattice body including a plurality of second rod portions extending in a rod-like manner in a second direction intersecting the first direction and the arrangement direction within the first plane, wherein one end of the plurality of second rod portions and the other end opposite the one end are arranged at intervals in the arrangement direction, thereby forming a plurality of second groove portions between adjacent second rod portions, and the first lattice body and the second lattice body are stacked in a stacking direction perpendicular to the first plane.

[0007] According to one embodiment, the lattice-shaped fin includes a first lattice body including a plurality of first rod portions extending in a rod-like manner in a first direction within a first plane, wherein one end of the plurality of first rod portions and the other end opposite the one end are arranged at intervals in an arrangement direction intersecting the first direction within the first plane, thereby forming a plurality of first groove portions between adjacent first rod portions; and a second lattice body including a plurality of second rod portions extending in a rod-like manner in a second direction intersecting the first direction and the arrangement direction within the first plane, wherein one end of the plurality of second rod portions and the other end opposite the one end are arranged at intervals in the arrangement direction, thereby forming a plurality of second groove portions between adjacent second rod portions, and the first lattice body and the second lattice body are stacked in a stacking direction perpendicular to the first plane. [Effects of the Invention]

[0008] According to the embodiment, it is possible to provide a semiconductor device and a grid-like fin that can improve cooling efficiency. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view illustrating the configuration of a semiconductor device according to Reference Example 1. [Figure 2] FIG. 10 is a cross-sectional view illustrating the configuration of a semiconductor device according to Reference Example 2. [Figure 3] FIG. 10 is a cross-sectional view illustrating the configuration of a semiconductor device according to Reference Example 3. [Figure 4] FIG. 10 is a cross-sectional view illustrating the configuration of a semiconductor device according to a comparative example. [Figure 5] FIG. 10 is a perspective view illustrating pin fins in a semiconductor device according to a comparative example. [Figure 6] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a comparative example, showing a state in which a coolant jacket is attached. [Figure 7] 10 is a cross-sectional view illustrating a semiconductor module and a cooling top plate in a semiconductor device according to a comparative example. [Figure 8] FIG. 10 is a perspective view illustrating a coolant jacket in a semiconductor device according to a comparative example. [Figure 9] 9 is a cross-sectional view illustrating a coolant jacket in a semiconductor device according to a comparative example, taken along line IX-IX in FIG. 8. FIG. [Figure 10] 10 is a cross-sectional view illustrating the flow of a coolant between a coolant jacket and a cooling top plate in a semiconductor device according to a comparative example. FIG. [Figure 11] 1 is a cross-sectional view illustrating the configuration of a semiconductor device according to a first embodiment. [Figure 12] 2 is a perspective view illustrating a grid-shaped fin in the semiconductor device according to the first embodiment. FIG. [Figure 13] 2 is a plan view illustrating grid-shaped fins in the semiconductor device according to the first embodiment. FIG. [Figure 14] 3 is a plan view illustrating a first grid element included in a grid-shaped fin in the semiconductor device according to the first embodiment. FIG. [Figure 15] 3 is a plan view illustrating a second grid element included in a grid-shaped fin in the semiconductor device according to the first embodiment. FIG. [Figure 16]1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment, showing a state in which a coolant jacket is attached. [Figure 17] 10 is a plan view illustrating grid-shaped fins in a semiconductor device according to a modified example of the first embodiment. FIG. [Figure 18] 10 is a plan view illustrating a first grid element included in a grid-shaped fin in a semiconductor device according to a modified example of the first embodiment. FIG. [Figure 19] 10 is a plan view illustrating a second grid element included in a grid-shaped fin in a semiconductor device according to a modified example of the first embodiment. FIG. [Figure 20] 3 is a cross-sectional view illustrating a grid-shaped fin in which a plurality of first grids and second grids are stacked in the semiconductor device according to the first embodiment. FIG. [Figure 21] 3 is a cross-sectional view illustrating a grid-shaped fin in which a plurality of first grids and second grids are stacked in the semiconductor device according to the first embodiment. FIG. [Figure 22] 1 is a graph illustrating Tjmax when the width of the first rod portion and the second rod portion, the width of the first groove portion and the second groove portion, and the number of first lattices and second lattices are changed in the semiconductor device of embodiment 1, where the horizontal axis indicates the number of first lattices and second lattices, and the vertical axis indicates Tjmax. [Figure 23] 1 is a graph illustrating pressure loss when the width of the first rod portion and the second rod portion, the width of the first groove portion and the second groove portion, and the number of first lattices and second lattices are changed in the semiconductor device of embodiment 1, where the horizontal axis indicates the number of first lattices and second lattices, and the vertical axis indicates pressure loss. [Figure 24] 1 is a graph illustrating the flow path cross-sectional area when the width of the first rod portion and the second rod portion, the width of the first groove portion and the second groove portion, and the number of first lattices and second lattices are changed in the semiconductor device of embodiment 1, where the horizontal axis indicates the number of first lattices and second lattices, and the vertical axis indicates the flow path cross-sectional area. [Figure 25]1 is a graph illustrating the average flow velocity within the lattice when the width of the first rod portion and the second rod portion, the width of the first groove portion and the second groove portion, and the number of first lattice members and second lattice members are changed in the semiconductor device of embodiment 1, where the horizontal axis indicates the number of first lattice members and second lattice members, and the vertical axis indicates the average flow velocity within the lattice. [Figure 26] 1 is a graph illustrating the relationship between pressure loss and Tjmax when the width of the first rod portion and the second rod portion, the width of the first groove portion and the second groove portion, and the number of first lattices and second lattices are changed in the semiconductor device of embodiment 1, where the horizontal axis represents pressure loss and the vertical axis represents Tjmax. [Figure 27] FIG. 10 is a cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment. [Figure 28] FIG. 10 is a cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment. [Figure 29] FIG. 10 is a cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment. [Figure 30] FIG. 10 is a cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Note that in each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0011] First, in <Reference Example 1> to <Reference Example 3>, semiconductor devices according to the Reference Examples will be described, and in <Comparative Example>, a semiconductor device according to a Comparative Example will be described. Then, in <Problems newly discovered by the inventors>, problems newly discovered by the inventors with respect to the semiconductor devices of the Reference Examples and Comparative Examples will be described. Then, in <Embodiment 1> to <Embodiment 2>, semiconductor devices according to Embodiments 1 and 2 will be described in comparison with the Comparative Example. This will make the semiconductor devices according to Embodiments 1 and 2 clearer. Note that Reference Examples 1 to 3, the Comparative Example, and the problems newly discovered by the inventors are also within the technical scope of the embodiments.

[0012] <Reference Example 1> FIG. 1 is a cross-sectional view illustrating the configuration of a semiconductor device 101 according to Reference Example 1. As shown in FIG. 1, the semiconductor device 101 includes a power module 110, an insulating layer 120, a cooler 130, and a molded resin 140. The cooler 130 is attached to the power module 110 via the insulating layer 120. The molded resin 140 covers the power module 110, the insulating layer 120, and the cooler 130. The cooler 130 includes a base portion 131 and a fin portion 132. The width of the base portion 131 of the cooler 130 decreases with increasing distance from the insulating layer 120 (downward in the figure). For example, the base portion 131 has a tapered or stepped shape with increasing distance from the insulating layer 120. This improves adhesion between the cooler 130 and the molded resin 140. Therefore, the semiconductor device 101 can suppress peeling at the interface between the base portion 131 and the molded resin 140, thereby improving cooling performance and reliability.

[0013] <Reference Example 2> FIG. 2 is a cross-sectional view illustrating the configuration of a semiconductor device 201 according to Reference Example 2. As shown in FIG. 2, the semiconductor device 201 includes a power module 210 and a cooler 230. The cooler 230 includes a metal member. The cooler 230 has multiple recesses formed by press working, and fin portions 232 are brazed to the recesses. The semiconductor device 201 does not require processing such as extrusion molding, and is therefore less expensive than processing into a typical pin fin shape. Furthermore, the semiconductor device 201 can have the fin portion 232 and the base portion 231 made of dissimilar metals, and the fin portion 232 can be located at any desired position, thereby improving design flexibility. Furthermore, the semiconductor device 201 can seamlessly bond (including diffusion bonding) the fin portion 232 and the base portion 231 by applying pressure and heat with brazing material.

[0014] <Reference Example 3> FIG. 3 is a cross-sectional view illustrating the configuration of a semiconductor device 301 according to Reference Example 3. As shown in FIG. 3, the semiconductor device 301 includes a cooler 330. The cooler 330 includes a base portion 331 having a coolant inlet 333, and a fin portion 332. A coolant 334 flows from the coolant inlet 333 through the base portion 331 in a fan-shaped manner. The base portion 331 is formed with fin portions 332. The fin portions 332 may be blade fins made of flat plates, round pin-shaped fins with a circular cross section, polygonal square pin-shaped fins, or the like. In the semiconductor device 303, the coolant 334 flows evenly through the base portion 331, thereby achieving even cooling.

[0015] <Comparative Example> FIG. 4 is a cross-sectional view illustrating the configuration of a semiconductor device 401 according to a comparative example. FIG. 5 is a perspective view illustrating pin fins 430 in the semiconductor device 401 according to the comparative example. FIG. 6 is a cross-sectional view illustrating the semiconductor device 401 according to the comparative example, showing a state in which a coolant jacket 40 is attached. FIG. 7 is a cross-sectional view illustrating the semiconductor module 10 and the cooling top plate 20 in the semiconductor device 401 according to the comparative example. FIG. 8 is a perspective view illustrating the coolant jacket 40 in the semiconductor device 401 according to the comparative example. FIG. 9 is a cross-sectional view illustrating the coolant jacket 40 in the semiconductor device 401 according to the comparative example, showing a cross section taken along line XI-XI in FIG. 8. FIG. 10 is a cross-sectional view illustrating the flow of the coolant 46 flowing between the coolant jacket 40 and the cooling top plate 20 in the semiconductor device 401 according to the comparative example.

[0016] As shown in FIGS. 4 to 10 , a semiconductor device 401 of the comparative example includes a semiconductor module 10, a cooling top plate 20, and pin fins 430. The cooling top plate 20 has a heat dissipation function and therefore functions as a heat sink. In other words, the heat sink includes the cooling top plate 20. The semiconductor device 401 may further include a refrigerant jacket 40. Here, for convenience of explanation of the semiconductor device 401, an XYZ Cartesian coordinate system is introduced. For example, the direction perpendicular to the upper surface 21 of the cooling top plate 20 is defined as the Z-axis direction, and two directions perpendicular to the Z-axis direction and perpendicular to each other are defined as the X-axis direction and the Y-axis direction. The +Z-axis direction may be referred to as the upward direction, and the −Z-axis direction may be referred to as the downward direction. Note that the terms upward and downward are used for convenience of explanation of the semiconductor device 401, etc., and do not indicate the directions in which the semiconductor device 401, etc. are actually arranged.

[0017] The semiconductor module 10 includes a semiconductor chip 11. The semiconductor chip 11 may be called a semiconductor element. The semiconductor chip 11 is, for example, a power semiconductor element. The power semiconductor element may include a semiconductor that controls power, such as voltage control or conversion between direct current and alternating current. Note that the semiconductor chip 11 is not limited to a power semiconductor element. The semiconductor chip 11 may be a semiconductor element including a memory IC or a logic IC. The semiconductor chip 11 may include silicon (Si), silicon carbide (SiC), or the like as a material. The semiconductor chip 11 has an upper surface 12 and a lower surface 13. The lower surface 13 is opposite to the upper surface 12. The upper surface 12 may be called a first surface, and the lower surface 13 may be called a second surface.

[0018] In addition to the semiconductor chip 11, the semiconductor module 10 may further include a substrate 14 on which the semiconductor chip 11 is attached. The substrate 14 may include a conductive plate 15, an insulating plate 16, and a heat sink 17. The conductive plate 15, the insulating plate 16, and the heat sink 17 each have a plate-like shape. The conductive plate 15 is disposed on a surface of the insulating plate 16 on the +Z-axis direction side, and the heat sink 17 is disposed on a surface of the insulating plate 16 on the -Z-axis direction side. The substrate 14 has the conductive plate 15, the insulating plate 16, and the heat sink 17 stacked in the Z-axis direction. The conductive plate 15 and the heat sink 17 may be made of a material such as copper (Cu). The insulating plate 16 may be made of a material such as silicon nitride (SiN).

[0019] The heat sink 17 may be called a substrate heat sink. The heat sink 17 may function as a heat sink disposed between the semiconductor chip 11 and the pin fins 430. In that case, the cooling top plate 20 may not be provided. The pin fins 430 are attached to the lower surface of the heat sink 17.

[0020] The semiconductor chip 11 is connected to the +Z-axis direction side of the conductive plate 15 via a bonding material 18. The cooling top plate 20 is joined to the -Z-axis direction side of the heat sink 17 via the bonding material 18. The bonding material 18 includes, for example, solder. The insulating sealing material 19 is formed on the upper surface 21 of the cooling top plate 20 so as to cover the semiconductor module 10.

[0021] The cooling top plate 20 is disposed between the semiconductor module 10 and the pin fins 430. The cooling top plate 20 has a plate-like shape. The pin fins 430 are attached to the lower surface 22 of the cooling top plate 20.

[0022] The pin fins 430 include a plurality of pins 431. The pins 431 extend downward from the lower surface 22 of the cooling top plate 20. The plurality of pins 431 are arranged such that there is a predetermined interval between adjacent pins 431.

[0023] The refrigerant jacket 40 has a recess 42 on its upper surface 41. The refrigerant jacket 40 has, for example, a rectangular parallelepiped shape, and the recess 42 is on its rectangular upper surface 41. Note that the shape of the refrigerant jacket 40 is not limited to a rectangular parallelepiped, as long as the recess 42 is on its upper surface 41. The upper surface 41 of the refrigerant jacket 40 is joined to the lower surface 22 of the cooling top plate 20. In this case, the pin fins 430 are arranged inside the recess 42 of the refrigerant jacket 40.

[0024] The refrigerant jacket 40 is formed with an inlet 43 and an outlet 44 that connect the recess 42 to the outside. For example, the inlet 43 is formed on the +X-axis direction side of the bottom surface 45 of the recess 42. The outlet 44 is formed on the −X-axis direction side of the bottom surface 45 of the recess 42.

[0025] A refrigerant 46 flows into the inlet 43 of the refrigerant jacket 40. The refrigerant 46 includes, for example, cooling water. Note that the refrigerant 46 is not limited to cooling water, and may be a cooling gas, an organic solvent, or the like. The refrigerant 46 flowing in from the inlet 43 fills the recess 42 of the refrigerant jacket 40, which is sealed by the cooling top plate 20. The refrigerant 46 passes between the multiple pins 431 in the recess 42. At this time, the refrigerant 46 exchanges heat with the pins 431. The refrigerant 46 is discharged from the recess 42 of the refrigerant jacket 40 through the outlet 44.

[0026] <New problem discovered by the inventor> The coolers 130 and the like for cooling the power modules 110 and the like in Reference Examples 1 to 3 and the Comparative Example may have a pin fin shape to increase surface area. Pin fins are generally manufactured by forging. Pin fins have a complex structure. Therefore, manufacturing pin fins requires large-scale equipment, which increases manufacturing costs. Furthermore, while copper has a higher thermal conductivity than aluminum and is therefore suitable as a material for coolers 130 and the like, it also has the disadvantage of high deformation resistance and poor workability. This increases the difficulty of designing and manufacturing coolers 130 and the like made of copper. Therefore, the present disclosure proposes a semiconductor device equipped with a cooler having a new fin shape that solves these issues. As a result, the semiconductor device of this embodiment not only simplifies manufacturing but also cools semiconductor chips 11, such as power modules, more efficiently than the structures of Reference Examples 1 to 3 and the Comparative Example.

[0027] <Embodiment 1> Next, a semiconductor device 1 according to embodiment 1 will be described. FIG. 11 is a cross-sectional view illustrating the configuration of the semiconductor device 1 according to embodiment 1. FIG. 12 is a perspective view illustrating the lattice fins 30 in the semiconductor device 1 according to embodiment 1. FIG. 13 is a plan view illustrating the lattice fins 30 in the semiconductor device 1 according to embodiment 1. FIG. 14 is a plan view illustrating the first lattice element 31 included in the lattice fin 30 in the semiconductor device 1 according to embodiment 1. FIG. 15 is a plan view illustrating the second lattice element 32 included in the lattice fin 30 in the semiconductor device 1 according to embodiment 1. FIG. 16 is a cross-sectional view illustrating the semiconductor device 1 according to embodiment 1, showing a state in which the refrigerant jacket 40 is attached.

[0028] 11 to 16, the semiconductor device 1 includes a semiconductor module 10 and a lattice fin 30. The semiconductor device 1 may further include a cooling top plate 20 disposed between the semiconductor module 10 and the lattice fin 30. The semiconductor device 1 may also include a refrigerant jacket 40.

[0029] The lattice fins 30 are arranged on the lower surface 13 side of the semiconductor chip 11. In other words, the lattice fins 30 are arranged on the −Z-axis direction side of the semiconductor module 10. For example, the lattice fins 30 are attached to the lower surface 22 of the cooling top plate 20.

[0030] Similar to the comparative example, the semiconductor module 10 includes a semiconductor chip 11. Similar to the comparative example, the semiconductor module 10 may further include a substrate 14. The substrate 14 is disposed between the semiconductor chip 11 and the lattice-shaped fins 30. The heat sink 17 may function as a heat sink disposed between the semiconductor chip 11 and the lattice-shaped fins 30. In this case, the cooling top plate 20 does not need to be provided. The lattice-shaped fins 30 are attached to the lower surface of the heat sink 17.

[0031] The lattice fins 30 may be made of at least one of copper and aluminum. By including such a material with high thermal conductivity, the lattice fins 30 can improve cooling efficiency and can be easily processed.

[0032] The grid-like fin 30 includes a first grid element 31 and a second grid element 32. The first grid element 31 and the second grid element 32 have a plate-like shape. The plate surfaces of the first grid element 31 and the second grid element 32 face the +Z-axis direction and the -Z-axis direction, respectively. The first grid element 31 and the second grid element 32 are stacked in the Z-axis direction, which is perpendicular to the XY plane. The Z-axis direction in which the first grid element 31 and the second grid element 32 are stacked is sometimes referred to as the stacking direction.

[0033] The first lattice element 31 includes a plurality of first rod portions 50 extending in a rod shape in a first direction in the XY plane. The first direction is a direction inclined toward the X-axis direction and the Y-axis direction. One end 51 of the plurality of first rod portions 50 and the other end 52 opposite the one end 51 are arranged with a gap in the X-axis direction. The direction in which the one ends 51 and the other ends 52 of the plurality of first rod portions 50 are arranged with a gap in between is called the arrangement direction. By arranging the first rod portions 50 in this manner, a plurality of first groove portions 55 are formed between adjacent first rod portions 50. The plurality of first groove portions 55 extend in the first direction. The plurality of first groove portions 55 penetrate in the Z-axis direction.

[0034] The first grid element 31 may include a one-end frame 53 and an other-end frame 54. The one-end frame 53 extends in the arrangement direction and is connected to one ends 51 of the multiple first rod portions 50. The other-end frame 54 extends in the arrangement direction and is connected to the other ends 52 of the multiple first rod portions 50. The one-end frame 53 closes one end of the multiple first grooves 55. The other-end frame 54 closes the other ends of the multiple first grooves 55. The first grid element 31 may be a plate-like element integrally molded to include the multiple first rod portions 50, the one-end frame 53, and the other-end frame 54. Specifically, the first grid element 31 may be formed by punching the multiple first grooves 55 out of a rectangular metal plate extending in the X-axis direction.

[0035] The second lattice element 32 includes a plurality of second rod portions 60 extending in a rod shape in a second direction in the XY plane. The second direction is a direction inclined toward the X-axis direction and the Y-axis direction and intersects with the first direction and the arrangement direction. One end 61 of the plurality of second rod portions 60 and the other end 62 opposite to the one end 61 are arranged at intervals in the X-axis direction, which is the arrangement direction. By arranging the second rod portions 60 in this manner, a plurality of second groove portions 65 are formed between adjacent second rod portions 60. The plurality of second groove portions 65 extend in the second direction. The plurality of second groove portions 65 penetrate in the Z-axis direction.

[0036] The second lattice element 32 may include a one-end frame 63 and an other-end frame 64. The one-end frame 63 extends in the arrangement direction and is connected to one ends 61 of the second rods 60. The other-end frame 64 extends in the arrangement direction and is connected to the other ends 62 of the second rods 60. The one-end frame 63 closes one end of the second grooves 65. The other-end frame 64 closes the other ends of the second grooves 65. The second lattice element 32 may be a plate-like element integrally molded to include the second rods 60, the one-end frame 63, and the other-end frame 64. Specifically, the second lattice element 32 may be formed by punching the second grooves 65 from a rectangular metal plate extending in the X-axis direction.

[0037] Fig. 17 is a plan view illustrating the lattice fin 30a in the semiconductor device 1a according to a modification of embodiment 1. Fig. 18 is a plan view illustrating the first lattice element 31a included in the lattice fin 30a in the semiconductor device 1a according to a modification of embodiment 1. Fig. 19 is a plan view illustrating the second lattice element 32a included in the lattice fin 30a in the semiconductor device 1a according to a modification of embodiment 1.

[0038] 17 to 19, in the semiconductor device 1a of the modified example, the lattice fin 30a includes a first lattice element 31a and a second lattice element 32a. The first lattice element 31a does not include a one-end frame 53 or an other-end frame 54. The second lattice element 32a does not include a one-end frame 63 or an other-end frame 64.

[0039] The first lattice element 31a includes a plurality of first rod portions 50 extending rod-like in the first direction, with one end 51 and the other end 52 of the plurality of first rod portions 50 arranged with a gap in the arrangement direction. A plurality of first groove portions 55 formed between adjacent first rod portions 50 communicate from the end of the first lattice element 31a in the +Y-axis direction to the end in the -Y-axis direction. In other words, one end and the other end of the plurality of first groove portions 55 are not closed but are open.

[0040] The second lattice element 32a includes a plurality of second rod portions 60 extending in a rod-like shape in the second direction, with one end 61 and the other end 62 of the plurality of second rod portions 60 spaced apart in the arrangement direction. A plurality of second groove portions 65 formed between adjacent second rod portions 60 communicate from the end of the second lattice element 32a in the +Y-axis direction to the end in the -Y-axis direction. In other words, one end and the other end of the plurality of second groove portions 65 are open rather than closed. This configuration of the lattice fins 30a increases the contact area of ​​the refrigerant 46. In the following description, the lattice fins 30 may be appropriately replaced with lattice fins 30a.

[0041] The first lattice element 31 may have the same shape as the second lattice element 32 when turned upside down. With this configuration, once the first lattice element 31 is manufactured, it becomes the second lattice element 32 when turned upside down, thereby reducing manufacturing costs. Furthermore, the number of connection points between the first grooves 55 and the second grooves 65 can be made symmetrical with respect to the Y-axis direction, allowing the refrigerant 46 to flow uniformly. The first lattice element 31 may have a different shape from the second lattice element 32 when turned upside down. In this case, the degree of freedom in design can be improved.

[0042] The lattice-shaped fins 30 may be bonded to the cooling top plate 20. Note that, when the heat sink 17 of the substrate 14 functions as a heat sink, the cooling top plate 20 may not be provided, and the lattice-shaped fins 30 may be bonded to the heat sink 17 of the substrate 14. The lattice-shaped fins 30 and the cooling top plate 20 or the heat sink 17 may be metal-bonded. Specifically, the lattice-shaped fins 30 and the cooling top plate 20 or the heat sink 17 may be bonded with a metal containing at least one of solder and sintered silver. The lattice-shaped fins 30 and the cooling top plate 20 or the heat sink 17 may also be directly bonded. The lattice-shaped fins 30 and the cooling top plate 20 or the heat sink 17 may also be directly bonded by diffusion bonding.

[0043] In the lattice fins 30, the first grooves 55 and the second grooves 65 are connected to each other. The refrigerant jacket 40 has recesses 42 that cover the lattice fins 30. For example, the semiconductor device 1 is integrated by joining the upper surface 41 of the refrigerant jacket 40 to the lower surface 22 of the cooling top plate 20. The semiconductor device 1 may also be integrated by screwing the upper surface 41 of the refrigerant jacket 40 to the lower surface 22 of the cooling top plate 20. The thicknesses of the first lattice element 31 and the second lattice element 32 in the stacking direction are each less than half the depth of the recesses 42 of the refrigerant jacket 40 that cover the lattice fins 30. This allows the lattice fins 30 to be accommodated in the recesses 42. The refrigerant 46 that flows in through the inlet 43 of the refrigerant jacket 40 flows through the connected first grooves 55 and second grooves 65 and flows out through the outlet 44.

[0044] 20 and 21 are cross-sectional views illustrating a lattice fin 30 in the semiconductor device 1 according to the first embodiment, in which a plurality of first lattices 31 and a plurality of second lattices 32 are stacked. As shown in FIGS. 20 and 21, the lattice fin 30 includes a plurality of first lattices 31 and a plurality of second lattices 32 stacked in the stacking direction. While two first lattices 31 and two second lattices 32 are stacked in FIGS. 20 and 21, this is not limitative. Three or more first lattices 31 and three or more second lattices 32 may be stacked. Furthermore, the number of first lattices 31 and the number of second lattices 32 do not have to be the same. In this manner, the lattice fin 30 may include at least one of a plurality of first lattices 31 stacked in the stacking direction and a plurality of second lattices 32 stacked in the stacking direction.

[0045] As shown in FIG. 20 , the grid fin 30 may include first grid elements 31 and second grid elements 32 stacked alternately in the stacking direction. Also, as shown in FIG. 21 , the grid fin 30 does not need to have the first grid elements 31 and second grid elements 32 stacked alternately. That is, the grid fin 30 may include at least one of a portion where multiple first grid elements 31 are stacked in contact with each other in the stacking direction and a portion where multiple second grid elements 32 are stacked in contact with each other in the stacking direction. By stacking the same first grid elements 31 and second grid elements 32 in this way, ease of manufacturing can be improved and costs can be reduced. Specifically, for example, punching a metal plate, such as copper, thicker than 1 mm is difficult from a manufacturing perspective. Even if it can be implemented, additional costs, such as deburring, are required. Therefore, by stacking thin, easily punched first grid elements 31 and second grid elements 32 in the same direction to achieve the desired thickness, deburring and other processes can be eliminated, thereby reducing costs.

[0046] The cross section of the first rod portion 50 of the lattice fin 30 perpendicular to the first direction and the cross section of the second rod portion 60 perpendicular to the second direction may be rectangular. This makes it possible to make the shape of the passages communicating with the first groove portions 55 and the second groove portions 65 uniform, thereby improving the flow of the refrigerant 46.

[0047] 22 is a graph illustrating the maximum junction temperature (Tjmax) of the semiconductor chip when the width L of the first rod portion 50 and the second rod portion 60, the width S of the first groove portion 55 and the second groove portion 65, and the number of first lattices 31 and second lattices 32 are changed in the semiconductor device 1 according to embodiment 1, where the horizontal axis represents the number of first lattices 31 and second lattices 32, and the vertical axis represents Tjmax. Fig. 22 also shows Tjmax of a pin fin 430 as a comparative example.

[0048] As shown in Figure 22, Tjmax can be lowered by reducing width L and width S. However, this increases the pressure loss as the flow path becomes more complex. Width L is the width of the first rod portion 50 perpendicular to the first direction and stacking direction, and width of the second rod portion 60 perpendicular to the second direction and stacking direction. Width S is the width of the first groove portion 55 perpendicular to the first direction and stacking direction, and width of the second groove portion 65 perpendicular to the second direction and stacking direction.

[0049] 23 is a graph illustrating pressure loss when the width L of the first rod portion 50 and the second rod portion 60, the width S of the first groove portion 55 and the second groove portion 65, and the number of first lattices 31 and second lattices 32 are changed in the semiconductor device 1 of embodiment 1, where the horizontal axis represents the number of first lattices 31 and second lattices 32, and the vertical axis represents pressure loss. Fig. 23 also shows the pressure loss of pin fin 430 of the comparative example.

[0050] 23, when the width L and width S are between 2.0 mm and 3.0 mm, the pressure loss is minimized when the number of fins is 4. This is presumably because the ease of flow in the thickness direction and horizontal direction of the grid-like fin 30 is reversed.

[0051] Figure 24 is a graph illustrating the flow path cross-sectional area when the width L of the first rod portion 50 and the second rod portion 60, the width S of the first groove portion 55 and the second groove portion 65, and the number of first lattice members 31 and second lattice members 32 are changed in the semiconductor device 1 of embodiment 1, where the horizontal axis indicates the number of first lattice members 31 and second lattice members 32 and the vertical axis indicates the flow path cross-sectional area.

[0052] 25 is a graph illustrating the average flow velocity within the lattice when the width L of the first rod portion 50 and the second rod portion 60, the width S of the first groove portion 55 and the second groove portion 65, and the number of first lattice members 31 and second lattice members 32 are changed in the semiconductor device 1 of embodiment 1, where the horizontal axis represents the number of first lattice members 31 and second lattice members 32, and the vertical axis represents the average flow velocity within the lattice. FIG. 22 also shows the average flow velocity of the pin fin 430 of the comparative example.

[0053] As shown in Figures 24 and 25, the average flow velocity within the grid through the grid-like fins 30 of this embodiment is greater than the average flow velocity through the pin fins 430 of the comparative example. In convective heat transfer, it is believed that thermal conductivity depends on the flow velocity. Therefore, the faster the flow velocity, the greater the thermal conductivity. Since the average flow velocity within the grid-like fins 30 is greater than the average flow velocity through the pin fins 430, cooling efficiency can be improved. Furthermore, as the number of fins increases, the flow path cross-sectional area decreases and the flow path becomes more complex. This reduces the average flow velocity within the grid.

[0054] 26 is a graph illustrating the relationship between pressure loss and Tjmax when the width L of the first rod portions 50 and second rod portions 60, the width S of the first groove portions 55 and second groove portions 65, and the number of first lattices 31 and second lattices 32 are changed in the semiconductor device 1 of embodiment 1, where the horizontal axis represents pressure loss and the vertical axis represents Tjmax. Fig. 26 also shows a relationship K1 between pressure loss and Tjmax in the pin fins 430 of the comparative example, and a relationship K2 between pressure loss and Tjmax when the pressure loss in the pin fins 430 of the comparative example is allowed to increase by up to +10%.

[0055] As shown in Fig. 26, width L and width S of 2.5 mm (4 sheets) show good values. Furthermore, width L and width S of 1.8 mm (2 sheets) and width L and width S of 2.0 mm (2 sheets) also show good values. Considering the results of the pressure loss described above, width L and width S are preferably 1.5 mm to 3.0 mm, and more preferably 1.8 mm to 2.5 mm.

[0056] Next, the effects of this embodiment will be described. The semiconductor device 1 of this embodiment is equipped with lattice fins 30. The lattice fins 30 can easily have a larger surface area than the pin fins 430 of the comparative example. This allows the semiconductor device 1 to improve cooling efficiency.

[0057] In convective heat transfer, the thermal conductivity depends on the flow velocity of the refrigerant 46. Therefore, the faster the flow velocity of the refrigerant 46, the greater the thermal conductivity. The average flow velocity of the refrigerant 46 in the lattice fins 30 of this embodiment is faster than the average flow velocity of the refrigerant 46 in the pin fins 430 of the comparative example, thereby improving cooling efficiency.

[0058] The semiconductor device 1 can be designed more simply and provides more cost-effective cooling than the pin fins 430 of the comparative example. The number of layers of the first lattice element 31 and the second lattice element 32 and the width of the slits of the first grooves 55 and the second grooves 65 can be easily designed, thereby providing three-dimensional flow paths in the thickness direction and horizontal direction. This reduces pressure loss of the coolant 46 and contributes to a longer life and higher reliability of the semiconductor module 10 including the semiconductor chip 11.

[0059] The thickness of each of the first lattice element 31 and the second lattice element 32 in the stacking direction is equal to or less than half the depth of the recess 42 of the refrigerant jacket 40. This allows two or more first lattice elements 31 and two or more second lattice elements 32 to be stacked within the recess 42. This allows the formation of a flow path for the refrigerant 46 that connects the first grooves 55 of the first lattice element 31 and the second grooves 65 of the second lattice element 32.

[0060] The lattice fin 30 does not need to be formed by stacking the first lattice elements 31 and the second lattice elements 32 in alternating directions. Stacking the same first lattice elements 31 and second lattice elements 32 can improve ease of manufacturing and reduce costs.

[0061] <Embodiment 2> Next, a semiconductor device according to embodiment 2 will be described. The semiconductor device of this embodiment differs from embodiment 1 in the configuration in which it is sealed with an insulating sealing material 19. Figs. 27 to 30 are cross-sectional views illustrating the configurations of semiconductor devices 2 to 5 according to embodiment 2.

[0062] As shown in FIG. 27 , the semiconductor device 2 includes a mold containing an insulating sealant 19, an insulating sheet TIM, a cooling top plate 20, and grid-like fins 30. Specifically, the semiconductor device 2 includes a semiconductor module 10a inside the insulating sealant 19. The insulating sealant 19 is disposed on the upper surface 21 of the cooling top plate 20 via the insulating sheet TIM. The insulating sheet TIM includes, for example, a resin sheet. The semiconductor module 10a includes multiple semiconductor chips 11, multiple conductive plates 15, an insulating plate 16, and a heat sink 17. The insulating plate 16 is disposed on the heat sink 17. Two conductive plates 15 are disposed side by side on the insulating plate 16 in the X-axis direction. Two semiconductor chips 11 are stacked on one conductive plate 15, and two semiconductor chips 11 are stacked on the other conductive plate 15.

[0063] As shown in FIG. 28, the semiconductor device 3 includes a mold containing an insulating sealant 19, a cooling top plate 20, and grid-like fins 30. Specifically, the semiconductor device 3 includes a semiconductor module 10b inside the insulating sealant 19. The insulating sealant 19 is disposed on the upper surface 21 of the cooling top plate 20. The semiconductor module 10b includes multiple semiconductor chips 11, multiple conductive plates 15, and an insulating sheet TIM. Two conductive plates 15 are disposed side by side in the X-axis direction on the insulating sheet TIM. The conductive plate 15 may contain copper as a material. Two semiconductor chips 11 are stacked on one conductive plate 15, and two semiconductor chips 11 are stacked on the other conductive plate 15.

[0064] As shown in FIG. 29 , the semiconductor device 4 has an insulating sheet TIM and a cooling top plate 20 integrated into a mold including an insulating sealing material 19. Specifically, the semiconductor device 4 includes a semiconductor module 10c, an insulating sheet TIM, and a cooling top plate 20 inside the insulating sealing material 19. The insulating sheet TIM is disposed on the cooling top plate 20. The semiconductor module 10c is disposed on the insulating sheet TIM. The semiconductor module 10c includes multiple semiconductor chips 11, multiple conductive plates 15, an insulating plate 16, and a heat sink 17. The insulating plate 16 is disposed on the heat sink 17. Two conductive plates 15 are disposed side by side on the insulating plate 16 in the X-axis direction. Two semiconductor chips 11 are stacked on one conductive plate 15, and two semiconductor chips 11 are stacked on the other conductive plate 15.

[0065] 30, the semiconductor device 5 includes a mold containing an insulating sealing material 19, an insulating sheet TIM provided above and below the mold, a cooling top plate 20, and a grid-like fin 30. Specifically, the semiconductor device 5 includes a semiconductor module 10d inside the insulating sealing material 19. On the +Z-axis direction side of the insulating sealing material 19, the insulating sheet TIM, the cooling top plate 20, and the grid-like fin 30 are arranged in this order on the +Z-axis direction side. On the -Z-axis direction side of the insulating sealing material 19, the insulating sheet TIM, the cooling top plate 20, and the grid-like fin 30 are arranged in this order on the -Z-axis direction side.

[0066] On the +Z-axis direction side of the lower insulating sheet TIM, a heat sink 17, an insulating plate 16, and two conductive plates 15 are arranged in this order on the +Z-axis direction side. The two conductive plates 15 are arranged side by side in the X-axis direction on the insulating plate 16. A semiconductor chip 11 is stacked on one of the conductive plates 15, and a semiconductor chip 11 is stacked on the other conductive plate 15.

[0067] Meanwhile, on the -Z-axis direction side of the upper insulating sheet TIM, a heat sink 17, an insulating plate 16, and two conductive plates 15 are arranged in this order on the -Z-axis direction side. The two conductive plates 15 are arranged side by side in the X-axis direction below the insulating plate 16. One conductive plate 15 is joined to the semiconductor chip 11 via a spacer SP, and the other conductive plate 15 is joined to the semiconductor chip 11 via a spacer SP.

[0068] According to the second embodiment, various variations can be made in the arrangement of the components constituting the semiconductor devices 2 to 5. This improves the degree of freedom in design. Other configurations and effects of the second embodiment are described in the first embodiment.

[0069] The disclosure made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the above embodiments, the reference examples, and the comparative examples, and various modifications are possible without departing from the spirit of the disclosure. For example, appropriate combinations of the configurations of Reference Examples 1 to 3, the comparative examples, and the embodiments 1 and 2 are also within the scope of the technical concept of the embodiments. Furthermore, the following configurations are also within the scope of the technical concept of the embodiments.

[0070] (Appendix A1) a semiconductor module including a semiconductor chip having a first surface and a second surface opposite to the first surface; a lattice-shaped fin disposed on a second surface side of the semiconductor chip; Equipped with The grid-like fins are a first grid including a plurality of first rod portions extending in a rod shape in a first direction within a first plane, wherein one end and another end opposite to the one end of the plurality of first rod portions are arranged at intervals in an arrangement direction intersecting the first direction within the first plane, thereby forming a plurality of first groove portions between adjacent first rod portions; a second grid including a plurality of second rod portions extending in a rod shape in a second direction intersecting the first direction and the arrangement direction within the first plane, wherein one end and another end opposite to the one end of the plurality of second rod portions are arranged with a gap in the arrangement direction, thereby forming a plurality of second groove portions between adjacent second rod portions; Including, The first lattice element and the second lattice element are stacked in a stacking direction perpendicular to the first plane. Semiconductor device. (Appendix A2) The grid-like fin and the heat sink are directly bonded to each other. The semiconductor device according to Appendix A1. (Appendix A3) The grid-like fin and the heat sink are directly bonded by diffusion bonding. The semiconductor device according to Appendix A2. (Appendix B1) a first grid including a plurality of first rod portions extending in a rod shape in a first direction within a first plane, wherein one end and another end opposite to the one end of the plurality of first rod portions are arranged at intervals in an arrangement direction intersecting the first direction within the first plane, thereby forming a plurality of first groove portions between adjacent first rod portions; a second grid including a plurality of second rod portions extending in a rod shape in a second direction intersecting the first direction and the arrangement direction within the first plane, wherein one end and another end opposite to the one end of the plurality of second rod portions are arranged with a gap in the arrangement direction, thereby forming a plurality of second groove portions between adjacent second rod portions; and The first lattice element and the second lattice element are stacked in a stacking direction perpendicular to the first plane. Lattice fins. (Appendix B2) a heat sink to which the grid-shaped fins are bonded; a refrigerant jacket having a recessed portion covering the grid-shaped fin and joined to the heat sink; Furthermore, Grid fins as described in Appendix B1. [Explanation of symbols]

[0071] 1, 1a, 2, 3, 4, 5 Semiconductor device 10, 10a, 10b, 10c, 10d Semiconductor modules 11 Semiconductor chips 12 Top side 13 Bottom side 14 PCB 15 Conductive plate 16 Insulating plate 17 Heat sink 18 Bonding material 19 Insulating sealing material 20 Cooling tray 30, 30a Lattice fin 31, 31a 1st grid body 32, 32a 2nd grid body 40 Refrigerant jacket 41 Top side 42 recess 43 Inlet 44 Outlet 45 bottom 46 Refrigerant 50 1st rod part 51 one end 52 other end 53 One end frame 54 Other end frame 55 First groove 60 2nd rod part 61 one end 62 other end 63 One end frame 64 Other end frame 65 Second groove 101, 201, 301 Semiconductor device 110, 210 Power Module 120 insulating layer 130, 230, 330 cooler 131, 231, 331 base 132, 232, 332 Fin section 140 Molding resin 333 Refrigerant inlet 334 Refrigerant 401 Semiconductor devices 430 Pinfin 431 pins

Claims

1. a semiconductor module including a semiconductor chip having a first surface and a second surface opposite to the first surface; a lattice-shaped fin disposed on a second surface side of the semiconductor chip; Equipped with The grid-like fins are a first grid including a plurality of first rod portions extending in a rod shape in a first direction within a first plane, wherein one end and another end opposite to the one end of the plurality of first rod portions are arranged at intervals in an arrangement direction intersecting the first direction within the first plane, thereby forming a plurality of first groove portions between adjacent first rod portions; a second grid including a plurality of second rod portions extending in a rod shape in a second direction intersecting the first direction and the arrangement direction within the first plane, wherein one end and another end opposite to the one end of the plurality of second rod portions are arranged with a gap in the arrangement direction, thereby forming a plurality of second groove portions between adjacent second rod portions; Including, The first lattice element and the second lattice element are stacked in a stacking direction perpendicular to the first plane. Semiconductor device.

2. The semiconductor module further includes a heat sink including a cooling top plate disposed between the semiconductor module and the grid-like fins. The semiconductor device according to claim 1 .

3. the semiconductor module further includes a substrate to which the semiconductor chip is bonded; The substrate is disposed between the semiconductor chip and the grid-like fins. The semiconductor device according to claim 1 .

4. The substrate is A conductive plate; An insulating plate; a substrate heat sink; Including, The semiconductor device according to claim 3 .

5. the substrate heat sink functions as a heat sink disposed between the semiconductor chip and the grid-like fins; The semiconductor device according to claim 4 .

6. The cooling system further includes a refrigerant jacket having a recess covering the lattice fin. The semiconductor device according to claim 1 .

7. The first groove portion and the second groove portion are connected to each other. The semiconductor device according to claim 1 .

8. The first lattice element is A plurality of the first rod portions; a one-end frame connected to the one ends of the plurality of first rod portions and extending in the arrangement direction; an other-end frame connected to the other ends of the plurality of first rod portions and extending in the arrangement direction; It is an integrally molded plate including The second grating body is A plurality of the second rod portions; a one-end frame connected to the one ends of the plurality of second rod portions and extending in the arrangement direction; an other-end frame connected to the other ends of the plurality of second rod portions and extending in the arrangement direction; It is an integrally molded plate-like member including The semiconductor device according to claim 1 .

9. the lattice fin includes at least one of a plurality of the first lattices stacked in the stacking direction and a plurality of the second lattices stacked in the stacking direction, The semiconductor device according to claim 1 .

10. The lattice fin includes the first lattice elements and the second lattice elements stacked alternately in the stacking direction. The semiconductor device according to claim 1 .

11. the grid-like fin includes at least one of a portion where a plurality of the first grid elements are stacked in contact with each other in the stacking direction and a portion where a plurality of the second grid elements are stacked in contact with each other in the stacking direction, The semiconductor device according to claim 1 .

12. a thickness in the stacking direction of the first lattice element and the second lattice element is equal to or less than half a depth of a recess of a refrigerant jacket having a recess covering the lattice fins; The semiconductor device according to claim 1 .

13. The grid-like fin contains at least one of copper and aluminum as a material. The semiconductor device according to claim 1 .

14. The grid-like fins and the heat sink are joined by metal joining. The semiconductor device according to claim 2 .

15. The first lattice has the same shape as the second lattice when turned upside down. The semiconductor device according to claim 1 .

16. The first lattice has a different shape from an inverted shape of the second lattice. The semiconductor device according to claim 1 .

17. A cross section of the first rod portion perpendicular to the first direction and a cross section of the second rod portion perpendicular to the second direction are rectangular. The semiconductor device according to claim 1 .

18. The width of the first rod portion perpendicular to the first direction and the stacking direction and the width of the second rod portion perpendicular to the second direction and the stacking direction are 1.5 mm to 3.0 mm. The semiconductor device according to claim 1 .

19. The width of the first groove portion perpendicular to the first direction and the stacking direction and the width of the second groove portion perpendicular to the second direction and the stacking direction are 1.5 mm to 3.0 mm. The semiconductor device according to claim 1 .

20. a first grid including a plurality of first rod portions extending in a rod shape in a first direction within a first plane, wherein one end and another end opposite to the one end of the plurality of first rod portions are arranged at intervals in an arrangement direction intersecting the first direction within the first plane, thereby forming a plurality of first groove portions between adjacent first rod portions; a second grid including a plurality of second rod portions extending in a rod shape in a second direction intersecting the first direction and the arrangement direction within the first plane, wherein one end and another end opposite to the one end of the plurality of second rod portions are arranged with a gap in the arrangement direction, thereby forming a plurality of second groove portions between adjacent second rod portions; Including, The first lattice element and the second lattice element are stacked in a stacking direction perpendicular to the first plane. Lattice fins.

Images