Display device

Abstract

To provide an electroluminescent display device that can achieve size increase and higher definition simultaneously.SOLUTION: A display device comprises a plurality of pixels and at least one scan line drive circuit. Each of the plurality of pixels includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The scan line drive circuit is electrically connected to the plurality of pixels. Any of the pixel circuits do not overlap the scan line drive circuit. A display area defined as the smallest quadrangle containing all the light-emitting elements partially overlaps the scan line drive circuit. The pixel circuits are arranged in a matrix having a plurality of rows and a plurality of columns. Each of the pixel circuits includes a drive transistor configured to supply current to the light-emitting element, and a switching transistor configured to supply the current from the drive transistor to the light-emitting element. In each of the plurality of pixels, the switching transistor and the light-emitting element are electrically connected to each other via relay wiring.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device having a light-emitting element. [Background technology]

[0002] In the field of flat panel displays, technological development for further increasing the size and narrowing the frame of display devices remains an important issue. For example, Patent Documents 1 and 2 disclose that a display device with a narrow frame can be provided by arranging display elements in the frame area where a drive circuit is provided, where display elements are not usually arranged. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-167403 [Patent Document 2] Japanese Patent Publication No. 2020-12977 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide an electroluminescent display device having a new structure, or an object of one embodiment of the present invention is to provide an electroluminescent display device that can not only have a narrow frame but also achieve a large size and high definition at the same time. [Means for solving the problem]

[0005] One embodiment of the present invention is a display device. The display device includes a plurality of pixels and at least one scanning line driving circuit. Each of the plurality of pixels includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The at least one scanning line driving circuit is electrically connected to the plurality of pixels. None of the pixel circuits overlaps with the at least one scanning line driving circuit. A display area, defined as the smallest rectangle that encompasses all of the light-emitting elements, partially overlaps with the at least one scanning line driving circuit. The pixel circuits are arranged in a matrix having a plurality of rows and a plurality of columns. Each pixel circuit includes a driving transistor configured to supply current to the light-emitting element, and a switching transistor configured to supply the current from the driving transistor to the light-emitting element. In each of the plurality of pixels, the switching transistor and the light-emitting element are electrically connected to each other by a relay wiring. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 2] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 3] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 4] FIG. 2 is a schematic end view of a light-emitting element included in a display device according to an embodiment of the present invention. [Figure 5] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 6] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 7] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 8] 1 is an equivalent circuit diagram of a pixel circuit provided in a pixel of a display device according to an embodiment of the present invention. [Figure 9] FIG. 1 is a schematic top view of a pixel circuit provided in a pixel of a display device according to an embodiment of the present invention. [Figure 10]1 is a schematic end view including a pixel circuit provided in a pixel of a display device according to an embodiment of the present invention. [Figure 11] 1 is a schematic top view showing the positional relationship between pixel circuits and light-emitting elements in a display device according to an embodiment of the present invention. [Figure 12] 1 is a schematic end view including a pixel circuit provided in a pixel of a display device according to an embodiment of the present invention. [Figure 13] 1 is a schematic top view showing the positional relationship between pixel circuits and light-emitting elements in a display device according to an embodiment of the present invention. [Figure 14] 1 is a schematic end view including a pixel circuit provided in a pixel of a display device according to an embodiment of the present invention. [Figure 15] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 16] 1 is a schematic end view including a pixel circuit provided in a pixel of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings, etc. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below.

[0008] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those explained in the previous drawings may be assigned the same reference numerals, and duplicate explanations may be omitted.

[0009] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0010] In this specification and claims, the expression "a structure exposed from another structure" means a state in which a part of a structure is not covered by another structure, and includes a state in which the part not covered by another structure is covered by yet another structure. The state expressed by this expression also includes a state in which a structure is not in contact with another structure.

[0011] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from films formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, these multiple films are defined as existing in the same layer.

[0012] First Embodiment In this embodiment, a configuration of a display device 100 according to one embodiment of the present invention will be described.

[0013] 1.Overall structure FIG. 1 shows a schematic top view of a display device 100 according to one embodiment of the present invention. As shown in FIG. 1, the display device 100 includes a substrate 102 and an opposing substrate (not shown in FIG. 1), and various patterned conductive films, insulating films, and semiconductor films are stacked between the substrate 102 and the opposing substrate. These conductive films, insulating films, and semiconductor films are appropriately combined to form a plurality of electroluminescent elements (hereinafter simply referred to as "light-emitting elements") 210, drive circuits (scanning line drive circuit 110, signal line drive circuit 112) for driving the light-emitting elements 210, and a plurality of terminals (not shown) for receiving signals and power from external circuits. The smallest rectangle that simultaneously encompasses all the light-emitting elements 210 is called the display area, and the area surrounding the display area is called the frame area. Each light-emitting element 210 is one of the components of a pixel, which is the smallest unit that provides color information, and is controlled by a pixel circuit included in the pixel, as described below. These components are described below.

[0014] 2. Substrate and opposing substrate The substrate 102 and the counter substrate 104 (see FIG. 10 , etc., described later) are provided to provide physical strength to the display device 100 and to arrange and protect the light-emitting elements 210, the scanning line driving circuit 110, and the signal line driving circuit 112. The substrate 102 and the counter substrate 104 may be substrates containing inorganic materials such as crystalline semiconductor substrates, glass substrates, and quartz substrates, or may contain polymers such as polyimide, polyamide, and polycarbonate. The substrate 102 and the counter substrate 104 may each be flexible or inflexible. In the former case, the substrate 102 and / or the counter substrate 104 may be flexible enough to allow elastic deformation, or may be highly flexible enough to allow plastic deformation. Light emitted from the light-emitting elements 210 is extracted to the outside through the counter substrate 104. Therefore, at least the counter substrate 104 is configured to transmit visible light. The substrate 102 may be configured to transmit visible light or may be configured to block visible light.

[0015] There are no restrictions on the size of the substrate 102 and the opposing substrate 104. For example, large rectangular amorphous glass substrates, also known as mother glass, can be used as the substrate 102 and the opposing substrate 104. Specifically, a glass substrate called 8th generation mother glass, measuring 2160 mm × 2460 mm, a glass substrate called 9th generation mother glass, measuring 2400 mm × 2800 mm, a glass substrate called 10th generation mother glass, measuring 2880 mm × 3130 mm, or even larger glass substrates may be used. As will be described in detail later, embodiments of the present invention effectively suppress the increase in load on the driving circuitry that accompanies the enlargement of display devices, thereby enabling the provision of high-resolution, large-sized display devices. Therefore, by using the large glass substrates described above, it is possible to provide ultra-large display devices, for example, exceeding 100 inches.

[0016] 3.Drive circuit The scanning line driving circuit 110 and the signal line driving circuit 112 are configured to receive signals supplied from an external circuit, generate control signals for controlling the pixel circuits, and provide power to the pixel circuits along with these control signals. The display device 100 includes at least one scanning line driving circuit 110 together with the signal line driving circuit 112. These driving circuits are arranged along the edge of the substrate 102.

[0017] The scanning line driving circuit 110 is configured with a shift register circuit, a scan driver circuit, a sub-signal line selection circuit, etc., and is formed by appropriately combining a plurality of transistors, capacitive elements, etc. on the substrate 102. There is no restriction on the number of scanning line driving circuits 110. For example, a single scanning line driving circuit 110 may be provided on the substrate 102, or, as shown in FIG. 1, a pair of scanning line driving circuits 110 may be provided on the substrate 102. Alternatively, as shown in FIG. 2, three scanning line driving circuits (here, a first scanning line driving circuit 110-1, a second scanning line driving circuit 110-2, and a third scanning line driving circuit 110-3) may be provided on the substrate 102. In this case, the first scanning line drive circuit 110-1 and the second scanning line drive circuit 110-2 are provided along opposing edges of the substrate 102, and the third scanning line drive circuit 110-3 is disposed between the first scanning line drive circuit 110-1 and the second scanning line drive circuit 110-2. By providing three scanning line drive circuits 110, pixels disposed between the first scanning line drive circuit 110-1 and the second scanning line drive circuit 110-2 can be driven by the first scanning line drive circuit 110-1 and the second scanning line drive circuit 110-2, and pixels disposed between the second scanning line drive circuit 110-2 and the third scanning line drive circuit 110-3 can be driven by the second scanning line drive circuit 110-2 and the third scanning line drive circuit 110-3. In other words, all pixels are divided into multiple blocks, and each scanning line drive circuit 110 can control only the pixels in the corresponding block. This reduces the load on each scanning line driving circuit 110. Although not shown, four or more scanning line driving circuits 110 may be arranged.

[0018] Like the scan line driver circuit 110, the signal line driver circuit 112 is arranged along an edge of the substrate 102 so that its longitudinal direction intersects with the longitudinal direction of the scan line driver circuit 110. Like the scan line driver circuit 110, the signal line driver circuit 112 may also be formed by combining transistors and capacitors provided on the substrate 102, or an integrated circuit may be separately formed using a single crystal semiconductor substrate and mounted on the substrate 102. None of the multiple light-emitting elements 210 may overlap with the signal line driver circuit 112, or a portion of the light-emitting elements 210 may overlap with the signal line driver circuit 112. Alternatively, the signal line driver circuit 112 may not be provided on the substrate 102, but may be arranged on a connector (not shown) such as a flexible printed circuit board that connects the display device 100 to an external circuit.

[0019] 4. Pixels As mentioned above, each pixel includes a pixel circuit and a light emitting element 210 electrically connected thereto.

[0020] 4-1.Light-emitting element (1) Placement As shown in FIGS. 1 and 2, the light-emitting elements 210 of the plurality of pixels are arranged in a matrix having a plurality of rows and a plurality of columns. Here, the column direction is the longitudinal direction of the scanning line drive circuit 110 (i.e., the extension direction of the scanning line drive circuit 110), and the row direction is perpendicular to the longitudinal direction of the scanning line drive circuit 110. As can be seen from FIGS. 1 and 2, some of the plurality of light-emitting elements 210 overlap with the scanning line drive circuit 110, while others do not. That is, some of the display area overlaps with the scanning line drive circuit 110, while others do not. Therefore, the display area, i.e., the plurality of light-emitting elements 210, can be arranged over the entire area between the opposing sides of the substrate 102, regardless of the shape or area of ​​the scanning line drive circuit 110. This arrangement enables the display device 100 to have a narrower frame, thereby reducing the frame area and ensuring a large display area.

[0021] The plurality of light emitting elements 210 are provided at the same pitch across the entire display area. That is, as shown in FIG. 3, the intervals between adjacent light emitting elements 210 in each row are the same, and therefore the pitch P pe The spacing between adjacent light-emitting elements 210 and the pitch of the light-emitting elements 210 are also constant in the column direction. With this arrangement, color information generated by the pixels can be provided uniformly across the entire display area.

[0022] (2) Structure 4 shows a schematic end view of the light-emitting element 210. The light-emitting element 210 includes a pixel electrode 212 and a counter electrode 216 that overlap each other in the vertical direction (the normal direction of the substrate 102), and an electroluminescent layer (hereinafter referred to as an EL layer) 214 containing an organic compound between the pixel electrode 212 and the counter electrode 216. By applying a potential difference between the pixel electrode 212 and the counter electrode 216, carriers injected from the pixel electrode 212 and the counter electrode 216 recombine in the EL layer 214, and the excited state of the organic compound generated at this time returns to the ground state, and the released energy can be obtained as light.

[0023] As described above, since light from the light-emitting element 210 is extracted through the counter substrate 104, the pixel electrode 212 is configured to also function as a reflective electrode that reflects light. For example, the pixel electrode 212 is formed as a laminate of a film containing a highly reflective metal such as silver or aluminum or an alloy thereof and a film of a conductive oxide that transmits visible light, such as indium-tin oxide (ITO) or indium-zinc (IZO), provided thereon. On the other hand, the counter electrode 216 is configured to contain a conductive oxide that transmits visible light. Alternatively, a metal-containing film having a thickness that allows visible light to transmit (e.g., 5 nm to 20 nm) may be used as the counter electrode 216. In the latter case, a film of a conductive oxide that transmits visible light may be further provided on the metal-containing film.

[0024] There are no restrictions on the configuration of the EL layer, and it may be configured by appropriately combining functional layers such as a charge injection layer, a charge transport layer, a light-emitting layer, an exciton blocking layer, and a charge blocking layer.

[0025] 4-2.Pixel circuit (1) Placement Unlike the light-emitting element 210, the pixel circuits that constitute the pixels are provided on the substrate 102 so as not to overlap with the scanning line drive circuit 110 or the signal line drive circuit 112. For example, when the display device 100 has a pair of scanning line drive circuits 110 as shown in FIG. 1, all of the pixel circuits are sandwiched between the pair of scanning line drive circuits 110. When the display device 100 has a first scanning line drive circuit 110-1, a second scanning line drive circuit 110-2, and a third scanning line drive circuit 110-3 as shown in FIG. 2, some of the pixel circuits are sandwiched between the first scanning line drive circuit 110-1 and the second scanning line drive circuit 110-2, and the remaining pixel circuits are sandwiched between the second scanning line drive circuit 110-2 and the third scanning line drive circuit 110-3.

[0026] Like the light-emitting elements 210, the pixel circuits are also arranged in a matrix having multiple rows and multiple columns. The number of rows and columns of the matrix formed by the pixel circuits is the same as those formed by the light-emitting elements 210. However, the area of ​​the area where the pixel circuits are arranged is smaller than the area of ​​the display area where the light-emitting elements 210 are arranged. For this reason, each pixel circuit is configured so that its occupation area is smaller than the occupation area of ​​each light-emitting element 210 (more specifically, the area of ​​the pixel electrode 212 or the area of ​​the surface where the pixel electrode 212 and the EL layer 214 contact). Furthermore, while all pixel circuits are arranged at the same pitch in the column direction, the pixel circuits are arranged at a pitch smaller than that of the light-emitting elements 210 in the row direction. For example, as shown in FIG. 5, when all pixel circuits 130 are arranged at the same pitch P1 in each row, the pitch P1 of the pixel circuits 130 is smaller than the pitch P of the light-emitting elements 210. pe (See Figure 3)

[0027] Alternatively, the arrangement density of the pixel circuits 130 may be varied in each row. For example, as shown in FIG. 6, the pixel circuits 130 may be arranged so that the pitch P2 of the pixel circuits 130 closer to the scanning line driving circuit 110 is smaller than the pitch P3 of the pixel circuits 130 farther from the scanning line driving circuit 110. In this case, in each row, all the pixel circuits 130 are divided into a first pixel circuit group and a second pixel circuit group, each including a plurality of pixel circuits 130. The second pixel circuit group is located closer to the scanning line driving circuit 110 than the first pixel circuit group. In the second pixel circuit group, the pixel circuits 130 are arranged at a pitch P2, and in the first pixel circuit group, the pixel circuits 130 are arranged at a pitch P3 larger than the pitch P2. The pitch P3 is set equal to the pitch P pe may be the same as the pitch P pe 7, when a first pixel circuit group consisting of two pixel circuits 130 adjacent to each other in the row direction with a distance D1 therebetween and a second pixel circuit group consisting of two pixel circuits 130 adjacent to each other in the row direction with a distance D2 therebetween are set, the pixel circuits 130 may be arranged such that the distance D2 of the second pixel circuit group closer to the scanning line driving circuit 110 is smaller than the distance D1 of the first pixel circuit group.

[0028] Alternatively, although not shown, the pixel circuits 130 may be arranged so that in each row, the pitch of the pixel circuits 130 or the distance between adjacent pixel circuits 130 decreases continuously or stepwise as the distance from the scanning line driving circuit 110 decreases. When a plurality of scanning line driving circuits 110 are provided, the pixel circuits 130 are arranged so that the pitch of the pixel circuits 130 is maximum at the midpoint between adjacent scanning line driving circuits 110 and decreases as the distance from the midpoint between the scanning line driving circuits 110 increases in the row direction.

[0029] (2) Structure An example of an equivalent circuit of the pixel circuit 130 is shown in Fig. 8, and a schematic top view of the pixel circuit 130 is shown in Fig. 9. The display device 100 is provided with a plurality of video signal lines 132 and a plurality of current supply lines 136 corresponding to the plurality of columns of the pixel circuits 130, respectively. That is, one video signal line 132 and one current supply line 136 are arranged for each column. A video signal and a power source are supplied from the signal line drive circuit 112 to the pixel circuit 130 via the video signal line 132 and the current supply line 136, respectively. Therefore, the pixel circuit 130 may be configured so that a current supplied via the current supply line 136 based on a video signal supplied via the video signal line 132 is supplied to the light-emitting element 210.

[0030] Specifically, as shown in the equivalent circuit of FIG. 8 , the pixel circuit 130 includes a drive transistor 160, a storage capacitor element 174, a write transistor 164, and a switching transistor 172 for preventing an increase in the write time of a video signal. In addition to these elements, the pixel circuit 130 may also include an emission control transistor 162, an initialization transistor 166, a reset transistor 168, a precharge transistor 170, and the like. The display device 100 is provided with gate lines (emission control gate line 140, reset gate line 142, precharge gate line 144, write gate line 146, switching gate line 148) for controlling the on / off of the various transistors described above, signal lines (precharge signal line 150, reset signal line 152), a common wiring 138 to which a constant potential such as ground potential is supplied, and the like. These gate lines and signal lines extend from the scanning line drive circuit 110 or the signal line drive circuit 112. Each pixel circuit 130 may be provided with various driving elements such as transistors and capacitors in addition to the above-mentioned transistors and storage capacitors 174. The area occupied by the pixel circuit 130 is the area between the current supply line 136 and the video signal line 132 that sandwich the driving element of each pixel 120 in the row direction, and is the area that includes all driving elements in the column direction.

[0031] As shown in FIG. 8 , one terminal of the write transistor 164 is connected to the video signal line 132 and receives a video signal. The other terminal of the write transistor 164 is connected to one terminal of the light-emitting control transistor 162. The other terminal of the light-emitting control transistor 162 is connected to the gate of the drive transistor 160. When the light-emitting control transistor 162 is off, the write transistor 164 is turned on, and the potential of the other terminal reaches the potential of the video signal. Then, by turning the write transistor 164 and the light-emitting control transistor 162 off and on, respectively, the potential of the video signal supplied via the video signal line 132 is supplied to the gate of the drive transistor 160. As a result, a potential corresponding to the video signal is written to the drive transistor 160. The potential of the gate of the drive transistor 160 is maintained by the storage capacitor element 174.

[0032] One terminal of the initialization transistor 166 is connected to the gate of the drive transistor 160 and the other terminal of the light-emitting control transistor 162, and the other terminal is connected to one terminal of the reset transistor 168. The other terminal of the reset transistor 168 is connected to one terminal of the drive transistor 160, and the gate is connected to the reset gate line 142. Therefore, by turning on the reset transistor 168 and the initialization transistor 166 and turning off the light-emitting control transistor 162, the gate potential of the drive transistor 160 can be initialized by the potential supplied from the reset signal line 152.

[0033] One terminal of the drive transistor 160 (the terminal connected to the reset transistor 168) is connected to one terminal of the switching transistor 172 and one terminal (first capacitor electrode) of the storage capacitor element 174, and the other terminal is connected to the current supply line 136. The other terminal of the switching transistor 172 is connected to the light-emitting element 210 via a relay wiring 154 that connects the pixel circuit 130 and the light-emitting element 210. When the drive transistor 160 is on, a current supplied via the current supply line 136 flows through the drive transistor 160. This current is not supplied to the light-emitting element 210 when the switching transistor 172 is off. The switching transistor 172 is configured to be turned on by a potential supplied from a reset gate line 142 connected to its gate after writing to the drive transistor 160 has been performed and a node n branching the drive transistor 160, the reset transistor 168, and the light-emitting element 210 has been sufficiently charged. Therefore, after the potential of the node n is sufficiently charged by writing the video signal, the switching transistor 172 turns on, and the current flowing through the drive transistor 160 is supplied to the light emitting element 210 via the switching transistor 172 and the relay wiring 154.

[0034] One terminal of the precharge transistor 170 is connected to the other electrode (second capacitance electrode) of the storage capacitor element 174, the other terminal of the write transistor 164, and one terminal of the light-emitting control transistor 162, the other terminal is connected to a precharge signal line 150, and the gate is connected to a precharge gate line 144. By providing the precharge transistor 170, the other electrode of the storage capacitor element 174, the other terminal of the write transistor 164, and one terminal of the light-emitting control transistor 162 can be initialized.

[0035] FIG. 10 is a schematic diagram of an end surface taken along the dashed line AA′ in FIG. 9 . As shown in FIG. 10 , each transistor is provided on the substrate 102 directly or via an undercoat 106 of any configuration. The drive transistor 160 shown in FIG. 10 is a so-called top-gate transistor, and includes a semiconductor film 180, a gate insulating film 182, and a gate electrode 184 disposed on the semiconductor film 180 via the gate insulating film 182. There are no restrictions on the structure of the transistors provided in the pixel circuit 130, including the drive transistor 160, and they may be top-gate transistors or bottom-gate transistors. When a top-gate transistor is used, it is preferable to provide an undercoat 106 to prevent impurities from the substrate 102 from penetrating into the semiconductor film 180, as shown in FIG. 10 .

[0036] A first planarization film 186 is provided on the transistor to absorb the irregularities and form a flat surface. On the first planarization film 186, the video signal line 132, the current supply line 136, the first capacitance electrode 188 of the storage capacitance element 174, and wiring 190 connecting the transistors are provided. A capacitance insulating film 192 and a second planarization film 194 are sequentially provided to cover the first capacitance electrode 188. An opening is provided in the second planarization film 194 that overlaps with the first capacitance electrode 188 and exposes the capacitance insulating film 192. A second capacitance electrode 196 is disposed to cover this opening. This completes the storage capacitance element 174. A connection pad 198, located in the same layer as the first capacitance electrode 188, is further provided on the second planarization film 194. The connection pad 198 is connected to the other terminal of the switching transistor 172 and is used to connect the switching transistor 172 to the relay wiring 154. The connection pads 198 are provided within the regions occupied by the pixel circuits 130. A third planarization film 200 is provided on the connection pads 198 and the second capacitor electrodes 196. The third planarization film 200 exposes the connection pads 198 and has openings 158 that function as contact portions between the switching transistors 172 and the relay wiring 154.

[0037] 4-3. Connection between pixel circuit and light-emitting element by relay wiring The relay wiring 154 is formed on the third planarization film 200 so as to cover the opening 158 of the third planarization film 200. The switching transistor 172 and the relay wiring 154 are electrically connected via this opening 158.

[0038] A fourth planarization film 202 is provided on the relay wiring 154. An opening exposing the relay wiring 154 is also provided in the fourth planarization film 202, and a pixel electrode 212 is formed to cover this opening. This connects the relay wiring 154 and the pixel electrode 212, and the relay wiring 154 electrically connects the switching transistor 172 of the pixel circuit 130 and the light-emitting element 210. A partition wall 206 is provided on the opening formed in the fourth planarization film 202 so as to cover the opening and to cover the end of the pixel electrode 212. The partition wall 206 electrically insulates adjacent light-emitting elements 210. An EL layer 214 is provided so as to be in contact with the partition wall 206 and the pixel electrode 212, and a counter electrode 216 is further formed on the EL layer 214. The pixel electrode 212, the EL layer 214, and the counter electrode 216 form a light-emitting element 210. The counter substrate 104 is fixed onto the light emitting element 210 using an adhesive (not shown), thereby protecting the multiple pixels 120, the scanning line driving circuit 110, the signal line driving circuit 112, etc. As an optional configuration, a sealing film 220 may be provided between the light emitting element 210 and the counter substrate 104.

[0039] As described above, the light-emitting element 210 and the pixel circuit 130 are electrically connected to each other by the relay wiring 154. As shown in FIGS. 9 and 10 , one end of the relay wiring 154 is connected to one end of the switching transistor 172 through an opening 158 formed in the pixel circuit 130. Therefore, one end of each relay wiring 154 is located within the corresponding pixel circuit 130. However, as described above, the display area including the light-emitting element 210 is larger than the area in which the pixel circuit 130 is provided. Therefore, depending on the position of the light-emitting element 210, the distance from the pixel circuit 130 to the light-emitting element 210, i.e., the length of the relay wiring 154, varies within the display device 100.

[0040] For example, in pixels 120 that are far from the scanning line driving circuit 110 (when multiple scanning line driving circuits 110 are provided, at the midpoint between adjacent scanning line driving circuits 110 and pixels in the vicinity thereof), the distance between the pixel circuit 130 and the light-emitting element 210 is small, and as shown schematically in FIG. 11, the pixel circuit 130 and the light-emitting element 210 that are electrically connected to each other can overlap. Furthermore, although not shown, the other end of the relay wiring 154 can also be disposed within the pixel circuit 130. Therefore, the relay wiring 154 is short.

[0041] However, the light-emitting elements 210 on or near the scanning line driving circuit 110 may not overlap with the corresponding pixel circuits 130. For this reason, as schematically shown in Fig. 12, the light-emitting elements 210 located at the extreme edge of the display area have the routing wiring 218 and the elements constituting the scanning line driving circuit 110 provided below them, but do not have the pixel circuits 130 provided below them, and the light-emitting elements 210 are connected to relay wiring 154 that extends over the pixel circuits 130 of other pixels 120. As shown in Fig. 13, taking four light-emitting elements 210-1 to 210-4 that overlap with or are located near the scanning line driving circuit 110 as an example, for the light-emitting elements 210-1 to 210-3, one end of the relay wiring 154 overlaps with the light-emitting element 210 or its pixel electrode 212, but the other end does not overlap with the corresponding light-emitting element 210. For this reason, in the first pixel circuit group described above, although the distance between a pixel circuit 130 and its corresponding light-emitting element 210 and the length of the relay wiring 154 connecting them may be the same, the distance between the light-emitting elements 210-1 to 210-4 and the corresponding pixel circuits 130-1 to 130-4 will be different, and the lengths of the relay wiring 154 will also be different. Furthermore, when all pixel circuits 130 are arranged at the same pitch in each row, the length of the relay wiring 154 increases as the distance from the scanning line driving circuit 110 decreases. Even when the arrangement density of the pixel circuits 130 varies in each row, the length of the relay wiring 154 increases as the distance from the scanning line driving circuit 110 decreases, particularly for pixel circuits 130 arranged close to the scanning line driving circuit 110.

[0042] When the length of the relay wiring 154 increases, its constant resistance load (CR load) increases, which results in a delay in charging the node n (see FIG. 8) that branches off the drive transistor 160, reset transistor 168, and light-emitting element 210, and a longer time is required to write to the drive transistor 160. In other words, the time required to maintain the write transistor 164 in the on state becomes longer. This causes a display delay.

[0043] However, as described above, the pixel circuit 130 is provided with the switching transistor 172 between the relay wiring 154 and the driving transistor 160, and the switching transistor 172 is configured to turn on after the potential of the node n is sufficiently charged. Therefore, the gate-source potential V gs is established in the saturation region, the switching transistor 172 is turned on, and therefore a constant current can be supplied to the light-emitting element 210 regardless of the length of the relay wiring 154. As a result, the light-emitting element 210 can emit light at a predetermined luminance. Therefore, even if a wide display area is set on the substrate 102, no display delay occurs. Note that immediately after the switching transistor 172 is turned on, some of the charge flows from the storage capacitor element 174 to the light-emitting element 210 via the relay wiring 154, but because a sufficient amount of current can be supplied to the light-emitting element 210 via the drive transistor 160, this effect can be almost ignored.

[0044] As described above, in the display device 100 according to an embodiment of the present invention, the plurality of light-emitting elements 210 are arranged so as to partially overlap with the scanning line driving circuit 110. This allows for a display device with a narrow frame and an extremely wide display area to be provided. Furthermore, the switching transistor 172 provided between the relay wiring 154 and the driving transistor 160 eliminates the effect of changes in the length of the relay wiring 154 connecting the light-emitting elements 210 and the pixel circuit 130. Furthermore, by providing three or more scanning line driving circuits 110, the plurality of pixels 120 constituting the display area can be divided into multiple blocks, each including pixels 120 arranged in two or more columns, and driven accordingly. Therefore, each scanning line driving circuit 110 can display by controlling only the pixels 120 in the corresponding block, thereby reducing the load on the scanning line driving circuit 110 and preventing signal delays due to this. Due to these features, applying the embodiment of the present invention makes it possible to provide a high-definition, ultra-large display device with a narrow frame.

[0045] Second Embodiment In this embodiment, a modified example of the display device 100 described in the first embodiment will be described. Description of configurations that are the same as or similar to those described in the first embodiment may be omitted.

[0046] In the display device 100 according to the first embodiment, the video signal lines 132 and the current supply lines 136 are located in the same layer. In contrast, in the display device 100 according to the present embodiment, the video signal lines 132 are located in a different layer from the current supply lines 136 in order to reduce the coupling capacitance between the video signal lines 132 and the various gate lines. Specifically, as shown in FIG. 14, which is a schematic end view corresponding to FIG. 10, the video signal lines 132 are located on a fourth planarization film 202. This significantly increases the distance between the video signal lines 132 and the various gate lines, thereby reducing the coupling capacitance therebetween. As a result, the load on the signal line driving circuit 112 is reduced, and signal delays can be prevented. A fifth planarization film 204 is further provided on the video signal lines 132. The pixel electrodes 212 and the relay wirings 154 are connected to each other through openings provided in the fourth planarization film 202 and the fifth planarization film 204 so as to expose the relay wirings 154. Since the relay wiring 154 and the video signal lines 132 are present on different layers, interference between them is prevented, and as a result, the relay wiring 154 can be arranged so as to cross the video signal lines 132 .

[0047] Here, in order to supply a video signal from the video signal line 132 to the write transistor 164, a sub video signal line 134 is provided that exists in a different layer from the video signal line 132. For example, the sub video signal line 134 that exists in the same layer as the current supply line 136 is disposed between the first planarization film 186 and the second planarization film 194. The sub video signal line 134 extends in parallel to the video signal line 132. Although the sub video signal line 134 overlaps with the video signal line 132 in FIG. 14 , the sub video signal line 134 does not necessarily have to overlap with the video signal line 132.

[0048] 15, one video signal line 132 is provided for each column, while multiple sub-video signal lines 134 are provided for each column. In each row, each sub-video signal line 134 is electrically connected to the video signal line 132 via at least one selection transistor 176 and to two or more pixel circuits 130, supplying these pixel circuits 130 with a video signal provided via the video signal line 132. While it is preferable that the number of pixel circuits 130 connected to one sub-video signal line 134 be the same, the number may vary within each column. This configuration allows all of the pixels 120 in each column to be divided into blocks, each including two or more pixels 120.

[0049] The gate of the selection transistor 176 is connected to a selection gate line 156 extending from a sub-signal line selection circuit that constitutes the scanning line drive circuit 110. When the selection transistor 176 is turned on in response to a potential supplied via the selection gate line 156, a video signal is supplied from the video signal line 132 to the sub-video signal line 134 via the selection transistor 176, and as a result, the video signal is supplied to two or more pixel circuits 130 connected to this sub-video signal line 134. Note that a pair of selection transistors 176-1 and 176-2 may be connected to each sub-video signal line 134. In this case, as shown in FIG. 15 , the pair of selection transistors 176-1 and 176-2 are connected to selection gate lines 156-1 and 156-2, respectively, and each sub-video signal line 134 is connected to two or more pixel circuits 130 between the pair of selection transistors 176-1 and 176-2.

[0050] In each column, the selection transistors 176 are configured to be driven sequentially rather than simultaneously. That is, when selection transistors 176 are connected to each sub-video signal line 134, the scanning line drive circuit 110 and the selection transistors 176 are configured so that, in each column, one of the multiple selection transistors 176 is turned on, and when writing to the pixel circuits 130 connected to it is completed, that selection transistor 176 is turned off and the next selection transistor 176 is turned on. When a pair of selection transistors 176-1, 176-2 is connected to one sub-video signal line 134, in each column, the pair of selection transistors 176-1, 176-2 connected to this one sub-video signal line 134 is turned on simultaneously to supply a video signal to this sub-video signal line 134, and then the pair of selection transistors 176-1, 176-2 are turned off simultaneously, and then the pair of selection transistors 176-1, 176-2 connected to the next sub-video signal line 134 is turned on simultaneously. Therefore, in each column, the pixels 120 can be driven in blocks each including two or more pixel circuits 130. This reduces the capacitive coupling that occurs between the sub-video signal line 134 and the various gate lines, thereby reducing the burden on the signal line drive circuit 112 and preventing signal delays and the like.

[0051] 16, which is a schematic end view corresponding to FIG. 10, the relay wiring 154 may be configured with two relay wirings located in different layers. More specifically, the relay wiring 154 may be configured with a first relay wiring 154-1 located on the third planarization film 200 and connected to the switching transistor 172 via a connection pad 198, and a second relay wiring 154-2 located on a fourth planarization film 202 above the first relay wiring 154-1. An opening exposing the first relay wiring 154-1 is provided in the fourth planarization film 202, and the first relay wiring 154-1 and the second relay wiring 154-2 are connected through this opening. The opening in the fourth planarization film 202 (i.e., the connection portion between the first relay wiring 154-1 and the second relay wiring 154-2) may be located inside or outside the pixel circuit 130. In this configuration, the second relay wiring 154-2 is located in the same layer as the video signal line 132, and therefore the second relay wiring 154-2 is arranged so as not to intersect with the video signal line 132. For example, the second relay wiring 154-2 is arranged so as to extend parallel to the video signal line 132 or in a direction not intersecting with the video signal line 132. On the other hand, the first relay wiring 154-1 is located in a different layer from the video signal line 132, and therefore does not interfere with the video signal line 132 even if it intersects with it. Therefore, by using the first relay wiring 154-1, the first relay wiring 154-1 can be extended to the corresponding light-emitting element 210 so as to cross the pixel circuit 130 that is not connected to this first relay wiring 154-1. The second relay wiring 154-2 and the light-emitting element 210 are connected using an opening provided in the fifth planarization film 204.

[0052] Although not shown, when the relay wiring 154 is configured with two relay wirings located in different layers, the video signal line 132 may be located in the same layer as the first relay wiring 154-1. That is, the video signal line 132 may be located between the third planarization film 200 and the fourth planarization film 202. In this case, the first relay wiring 154-1 is located so as to extend parallel to the video signal line 132 or in a direction not intersecting with the video signal line 132. On the other hand, the second relay wiring 154-2 is located in a different layer from the video signal line 132, and therefore does not interfere with the video signal line 132 even if it intersects with it. Therefore, by using the second relay wiring 154-2, the relay wiring 154 can be extended to the corresponding light-emitting element 210 so as to cross the pixel circuit 130 that is not connected to the second relay wiring 154-2.

[0053] Even in the display device 100 according to the modification described in this embodiment, the light-emitting elements 210 can be arranged so that a portion of the display area overlaps with the scanning line driving circuit 110. This allows for a narrower frame and a higher ratio of the display area to the overall area of ​​the display device 100 (e.g., 90% or more). Furthermore, since three or more scanning line driving circuits 110 can be provided, an increase in the load on the scanning line driving circuit 110 due to an increase in the size of the display device 100 is prevented. Furthermore, since the switching transistor 172 is provided in the pixel circuit 130, signal delays due to an increase in the CR load of the relay wiring 154 do not occur. Furthermore, since the video signal lines 132 are arranged at positions away from the various gate lines and video signals can be written sequentially using multiple sub-video signal lines 134 connected to each video signal line 132, capacitive coupling between the video signal lines 132 and the gate lines is reduced. Furthermore, since the pixels 120 can be driven block by block in each column, the load on the signal line driving circuit can also be reduced. In addition to these features, the display device 100 has electroluminescent elements as display elements, which provides high image contrast and color reproducibility, as well as a fast response speed. Because of these features, by applying the embodiments of the present invention, it is possible to provide a high-definition, ultra-large display device that is capable of displaying high-quality images and has a wide display area.

[0054] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0055] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0056] 100: display device, 102: substrate, 104: opposing substrate, 106: undercoat, 110: scanning line driving circuit, 110-1: first scanning line driving circuit, 110-2: second scanning line driving circuit, 110-3: third scanning line driving circuit, 112: signal line driving circuit, 120: pixel, 130: pixel circuit, 130-1: pixel circuit, 130-2: pixel circuit, 130-3: pixel circuit, 130-4: pixel circuit, 132: video signal line, 134: sub-video signal line, 136: Current supply line, 138: common wiring, 140: light emitting control gate line, 142: reset gate line, 144: precharge gate line, 146: write gate line, 148: switching gate line, 150: precharge signal line, 152: reset signal line, 154: relay wiring, 154-1: first relay wiring, 154-2: second relay wiring, 156: select gate line, 156-1: select gate line, 156-2: select gate line, 158: opening, 160: drive transistor transistor, 162: light emission control transistor, 164: write transistor, 166: initialization transistor, 168: reset transistor, 170: precharge transistor, 172: switching transistor, 174: storage capacitor element, 176: selection transistor, 176-1: selection transistor, 176-2: selection transistor, 180: semiconductor film, 182: gate insulating film, 184: gate electrode, 186: first planarization film, 188: First capacitor electrode, 190: wiring, 192: capacitor insulating film, 194: second planarization film, 196: second capacitor electrode, 198: connection pad, 200: third planarization film, 202: fourth planarization film, 204: fifth planarization film, 206: partition wall, 210: light emitting element, 210-1: light emitting element, 210-2: light emitting element, 210-3: light emitting element, 210-4: light emitting element, 212: pixel electrode, 214: EL layer, 216: counter electrode, 218: routing wiring, 220: sealing film

Claims

1. a plurality of pixels, each including a light emitting element and a pixel circuit electrically connected to the light emitting element; at least one scanning line driving circuit electrically connected to the plurality of pixels; none of the pixel circuits overlaps with the at least one scanning line driving circuit; a display area defined as the smallest rectangle that includes all of the light-emitting elements partially overlaps with the at least one scanning line driving circuit; The pixel circuits are arranged in a matrix having a plurality of rows and a plurality of columns, a drive transistor configured to provide current to the light emitting element; and a switching transistor configured to supply the current from the drive transistor to the light emitting element; In each of the plurality of pixels, the switching transistor and the light-emitting element are electrically connected to each other by a relay wiring.

2. the at least one scanning line driving circuit includes a pair of scanning line driving circuits; The display device according to claim 1 , wherein the pair of scanning line driving circuits are arranged to sandwich all of the pixel circuits therebetween.

3. the at least one scanning line driving circuit includes a first scanning line driving circuit, a second scanning line driving circuit, and a third scanning line driving circuit; the first scanning line driving circuit and the second scanning line driving circuit are arranged to sandwich all of the pixel circuits therebetween; 2. The display device according to claim 1, wherein the third scanning line driving circuit is disposed so as to be sandwiched between the first scanning line driving circuit and the second scanning line driving circuit.

4. the at least one scanning line driving circuit extends in a column direction; The display device according to claim 1 , wherein the pixel circuits are arranged at the same pitch in each of the plurality of rows.

5. 5. The display device according to claim 4, wherein in each of the plurality of rows, the length of the relay wiring increases as the distance from the at least one scanning line driving circuit decreases.

6. the at least one scanning line driving circuit extends in a column direction; The display device according to claim 1 , wherein in each of the plurality of rows, the pixel circuits are arranged at a pitch that decreases as the distance from the at least one scanning line driving circuit decreases.

7. 7. The display device according to claim 6, wherein in each of the plurality of rows, the length of the relay wiring increases as the distance from the at least one scanning line driving circuit decreases.

8. the at least one scanning line driving circuit extends in a column direction; In each of the plurality of rows, the pixel circuit a first pixel circuit group consisting of two of the pixel circuits adjacent to each other at a first interval in the row direction; and a second pixel circuit group consisting of two of the pixel circuits adjacent to each other at a second interval in the row direction; the second pixel circuit group is located closer to the at least one scanning line driving circuit than the first pixel circuit group; The display device of claim 1 , wherein the second distance is smaller than the first distance.

9. In the first pixel circuit group, the relay wirings have the same length; 9. The display device according to claim 8, wherein in the second pixel circuit group, the length of the relay wiring increases as the distance from the at least one scanning line driving circuit decreases.

10. The display device according to claim 1 , wherein the relay wiring includes a first relay wiring and a second relay wiring that are present in different layers and are electrically connected to each other.

11. a plurality of video signal lines configured to supply video signals to the pixel circuits; The display device according to claim 10 , wherein the second relay wiring is present in the same layer as the video signal line.

12. The display device according to claim 11 , wherein the second relay wiring extends in a direction parallel to the video signal lines.

13. The display device according to claim 11 , wherein the first relay wiring extends in a direction intersecting with an extension direction of the video signal lines.

14. a planarization film is further provided on the second relay wiring; each of the light-emitting elements of the plurality of pixels has a pixel electrode, an electroluminescent layer on the pixel electrode, and a counter electrode on the electroluminescent layer; The display device according to claim 10 , wherein the second relay wiring and the pixel electrode are electrically connected to each other through an opening provided in the planarization film so as to expose the second relay wiring.

15. a plurality of video signal lines, and further comprising a plurality of sub-video signal lines extending in parallel to the plurality of video signal lines; The plurality of video signal lines are arranged one for each column, Two or more of the plurality of sub-video signal lines are arranged in each column, In each of the plurality of columns, each of the pixel circuits is electrically connected to one of the plurality of sub-video signal lines; The display device according to claim 1 , wherein each of the plurality of sub-video signal lines is electrically connected to the video signal line via at least one selection transistor.

16. The display device according to claim 15 , wherein in each of the plurality of columns, the plurality of sub-video signal lines are located below the video signal lines and overlap the video signal lines.

17. the at least one select transistor includes a pair of select transistors; The display device according to claim 15 , wherein two or more of the pixel circuits are electrically connected to the sub-video signal line between the pair of selection transistors.

18. a plurality of select gate lines extending from the at least one scanning line driving circuit; The display device according to claim 15 , wherein each of the plurality of selection gate lines is connected to a gate of the corresponding one of the at least one selection transistor.

19. further comprising a current supply line arranged in each of the plurality of columns; The display device according to claim 15 , wherein the sub-video signal line is present in the same layer as the current supply line.

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