Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device with improved reliability, and a data storage system including the same.SOLUTION: A semiconductor device includes gate electrodes 130 extending with different lengths along an X direction and including a gate contact region 130P, interlayer insulating layers 120 disposed alternately with the gate electrodes, a contact plug 170 extending in the X direction and a Z direction while penetrating the gate electrode, and contact insulating layers 160 disposed alternately with the interlayer insulating layers, surrounding the contact plug, and including a first contact insulating layer 161 disposed between the gate contact region and the contact plug. Each of the contact plugs includes a vertical extension part 170V and a horizontal extension part 170H extending in a horizontal direction from the vertical extension part and overlapping with the gate contact region and the first contact insulating layer in a perpendicular direction, and a conductive liner extending between the horizontal extension part and the first contact insulating layer from between the horizontal extension part and the gate contact region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In data storage systems requiring data storage, semiconductor devices capable of storing high-capacity data are in demand. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical problems to be solved by the present invention is to provide a semiconductor device and a data storage system including the same with improved reliability.

[0004] However, the object of the present invention is not limited to the above object, and can be variously expanded within the scope of the idea and scope of the present invention. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment of the present invention includes a first semiconductor structure including a substrate, a circuit element on the substrate, and circuit wiring on the circuit element; and a second semiconductor structure disposed on the first semiconductor structure and having first and second regions, the second semiconductor structure including a plate layer, gate electrodes stacked on the plate layer and spaced apart from each other along a direction perpendicular to an upper surface of the plate layer, extending on the second region with different lengths along a first direction intersecting the perpendicular direction, and each including a gate contact region, an interlayer insulating layer alternately arranged with the gate electrodes, a channel structure penetrating the gate electrodes and the interlayer insulating layer in the first region and extending along the perpendicular direction, and a channel structure penetrating the gate electrodes in the second region, contact plugs extending along the vertical direction and electrically connecting the gate electrodes to portions of the circuit wirings, respectively; and contact insulating layers alternately arranged with the interlayer insulating layer, surrounding the contact plugs, and including a first contact insulating layer arranged between the gate contact region and the contact plug, wherein each of the contact plugs may include a vertical extension portion extending along the vertical direction, a horizontal extension portion extending horizontally from the vertical extension portion and overlapping the gate contact region and the first contact insulating layer in the vertical direction, and a conductive liner extending from between the horizontal extension portion and the gate contact region to between the horizontal extension portion and the first contact insulating layer.

[0006] A semiconductor device according to an embodiment of the present invention includes: a stack pattern having a memory cell array region and a staircase region; a stack structure extending on the stack pattern from the memory cell array region to the staircase region, the stack structure including interlayer insulating layers and gate electrodes alternately arranged in a vertical direction, the gate electrodes including gate contact pads arranged in a staircase region; a channel structure extending in a vertical direction through the stack structure in the memory cell array region; contact plugs penetrating the gate electrodes and the interlayer insulating layers in the staircase region; and gate electrodes alternately arranged with the interlayer insulating layers and contact pads. and a contact insulating layer surrounding the contact plug, the contact insulating layer including a first contact insulating layer disposed between the gate contact pad and the contact plug, and a second contact insulating layer alternately disposed with the interlayer insulating layer below the gate contact pad and surrounding the contact plug, each of the contact plugs including a vertical extension extending along the vertical direction and a horizontal extension extending horizontally from the vertical extension to contact the first contact insulating layer and the gate contact pad, respectively, and each height of the first contact insulating layer may be smaller than each height of the second contact insulating layer.

[0007] A data storage system according to an embodiment of the present invention includes a semiconductor memory device including a first semiconductor structure including a circuit element and circuit wiring electrically connected to the circuit element, a second semiconductor structure disposed on one surface of the first semiconductor structure and including a first region and a second region, and an input / output pad electrically connected to the circuit element, and a controller electrically connected to the semiconductor memory device via the input / output pad and controlling the semiconductor memory device, wherein the second semiconductor structure includes a plate layer, gate electrodes stacked on the plate layer at a distance from each other in a direction perpendicular to an upper surface of the plate layer and extending in the second region along a first direction intersecting the perpendicular direction with different lengths, each gate electrode including a gate contact region, interlayer insulating layers alternately arranged with the gate electrodes, channel structures penetrating the gate electrodes and the interlayer insulating layer in the first region and extending along the perpendicular direction, and an upper The gate electrode may include contact plugs that penetrate the gate contact regions of the gate electrodes in the second region, extend along the vertical direction, and electrically connect the gate electrodes to portions of the circuit wirings, respectively; first contact insulating layers that are alternately disposed with the interlayer insulating layer between the gate contact regions and the contact plugs and surround the contact plugs; and second contact insulating layers that are alternately disposed with the interlayer insulating layer below the gate contact regions and surround the contact plugs, each of the contact plugs including a vertical extension that extends along the vertical direction, a horizontal extension that extends horizontally from the vertical extension and overlaps with the first contact insulating layer and the gate contact regions, and a conductive liner that is disposed between the horizontal extension and the gate contact region and between the horizontal extension and the first contact insulating layer. [Effects of the Invention]

[0008] According to an embodiment of the present invention, a semiconductor device and a data storage system including the same may include a gate electrode having a gate contact region and a contact plug connected to the gate contact region, and the gate contact region may be connected to the contact plug through a horizontal extension disposed on an upper surface of the gate contact region. This prevents a decrease in reliability due to deformation of a gate stack region disposed below the gate contact region and a contact insulating layer disposed between the gate stack region and the vertical extension depending on a contact position between the gate contact region and the contact plug. In other words, a semiconductor device and a data storage system having improved reliability may be provided.

[0009] However, the effects of the present invention are not limited to the above-mentioned effects, and can be variously expanded within the scope of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1a] 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention; [Figure 1b] 1b is a cross-sectional view of one embodiment of the semiconductor device of FIG. 1a taken along line II'. [Figure 1c] 1b is a cross-sectional view showing an embodiment of the semiconductor device taken along line II-II' of FIG. 1a. [Figure 2] FIG. 1c is a schematic enlarged view of region A of the semiconductor device of FIG. 1b. [Figure 3a] 3 is an enlarged view showing an embodiment of region B of the semiconductor device of FIG. 2. [Figure 3b] 3b is an enlarged view of one embodiment of region C of the semiconductor device of FIG. 3a. [Figure 4a] 3 is an enlarged view showing another embodiment of region B of the semiconductor device of FIG. 2. FIG. [Figure 4b] 3 is an enlarged view showing another embodiment of region B of the semiconductor device of FIG. 2. FIG. [Figure 4c] 3 is an enlarged view showing another embodiment of region B of the semiconductor device of FIG. 2. FIG. [Figure 5a] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 1b. [Figure 5b] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 1b. [Figure 5c] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 1b. [Figure 5d] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 1b. [Figure 5e] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 1b. [Figure 5f] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 1b. [Figure 6a] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6b] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6c] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6d] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6e] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6f] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6g] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6h] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6i] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 6j] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 3a. [Figure 7a] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4b. [Figure 7b]It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4b. [Figure 7c] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4b. [Figure 8a] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4c. [Figure 8b] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4c. [Figure 8c] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4c. [Figure 8d] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4c. [Figure 8e] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4c. [Figure 8f] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4c. [Figure 8g] It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device of FIG. 4c. [[ID=]] [Figure 9] It is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. [Figure 10] It is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. [Figure 11] It is a drawing schematically showing a data storage system including a semiconductor device according to an embodiment of the present invention. [Figure 12] It is a perspective view schematically showing a data storage system including a semiconductor device according to an embodiment of the present invention. [Figure 13] It is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components on the drawings, and duplicate descriptions of the same components are omitted.

[0012] FIG. 1a is a schematic plan view of a semiconductor device according to an embodiment of the present invention, FIG. 1b is a cross-sectional view showing one embodiment of the semiconductor device of FIG. 1a taken along line II', and FIG. 1c is a cross-sectional view showing one embodiment of the semiconductor device of FIG. 1a taken along line II'.

[0013] 1a to 1c, the semiconductor device 100 may include a peripheral circuit region PERI, which is a first semiconductor structure including a first substrate 201, and a memory cell region CELL, which is a second semiconductor structure including a second substrate 101. The memory cell region CELL may be disposed above the peripheral circuit region PERI. In another example, the memory cell region CELL may be disposed below the peripheral circuit region PERI.

[0014] The peripheral circuit region PERI may include a first substrate 201, source / drain regions 205 in the first substrate 201, an element isolation layer 210, circuit elements 220 arranged on the first substrate 201, circuit contact plugs 270, circuit wiring lines 280, and a peripheral region insulating layer 290.

[0015] The first substrate 201 may have an upper surface extending in a first direction (X direction) and a second direction (Y direction). An active region may be defined in the first substrate 201 by an isolation layer 210. A source / drain region 205 containing impurities may be disposed in a portion of the active region. The first substrate 201 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0016] The circuit elements 220 may include planar transistors. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed in the first substrate 201 on both sides of the circuit gate electrode 225.

[0017] The peripheral region insulating layer 290 may be disposed on the circuit elements 220 on the first substrate 201. The circuit contact plugs 270 may be connected to the source / drain regions 205 through the peripheral region insulating layer 290. In a region not shown, the circuit contact plugs 270 may also be connected to the circuit gate electrodes 225. The circuit wiring lines 280 may be connected to the circuit contact plugs 270 and may be disposed in multiple layers.

[0018] The memory cell region CELL includes a first region R1, a second region R2, and a third region R3, and may include a source structure SS including a second substrate 101, a gate electrode 130 stacked on the source structure SS, interlayer insulating layers 120 stacked alternately with the gate electrode 130, a channel structure CH arranged to penetrate the stacked structure of the gate electrode 130 in the first region R1, first and second isolation regions MS1, MS2 extending through the stacked structure of the gate electrode 130, a contact plug 170 extending through the gate electrode 130 in the second region R2, and a via plug 175 arranged in the third region R3 outside the second substrate 101. The memory cell region CELL may further include a contact insulating layer 160 surrounding the contact plug 170.

[0019] The memory cell region CELL may further include a first horizontal conductive layer 102 on the first region R1, a horizontal insulating layer 110 arranged alongside the first horizontal conductive layer 102 on the second region R2 of the second substrate 101, a second horizontal conductive layer 104 on the first horizontal conductive layer 102 and the horizontal insulating layer 110, a substrate insulating layer 121 penetrating the second substrate 101, an upper isolation region US penetrating a portion of the stacked structure of the gate electrode 130, a dummy channel structure DCH arranged to penetrate the stacked structure of the gate electrode 130 in the second region R2, a cell region insulating layer 190, and a cell wiring line 195.

[0020] The source structure SS may include a second substrate 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104, which are sequentially stacked. The second substrate 101 has a plate shape and may function as at least a part of a common source line of the semiconductor device 100. The second substrate 101 may include a conductive material, for example, a semiconductor material. The second substrate 101 may further include impurities. The second substrate 101 may be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer. In this specification, the source structure SS may be referred to as a plate structure, and the second substrate 101 may be referred to as a plate layer.

[0021] The first and second horizontal conductive layers 102, 104 may be stacked sequentially on the upper surface of the first region R1 of the second substrate 101. The first horizontal conductive layer 102 may not extend onto the upper surface of the second region R2, and the second horizontal conductive layer 104 may extend into the second region R2.

[0022] The first horizontal conductive layer 102 may function as a part of a common source line of the semiconductor device 100, for example, may function as a common source line together with the second substrate 101. The first horizontal conductive layer 102 may be directly connected to the channel layer 140 in the channel structure CH.

[0023] The second horizontal conductive layer 104 may contact the second substrate 101 in a region where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. The second horizontal conductive layer 104 may be folded over an end of the first horizontal conductive layer 102 or the horizontal insulating layer 110 in a portion of its upper portion, and extend onto the second substrate 101.

[0024] The first and second horizontal conductive layers 102, 104 may include a semiconductor material, for example, the first and second horizontal conductive layers 102, 104 may all include polycrystalline silicon. In this case, at least the first horizontal conductive layer 102 may be a doped layer, and the second horizontal conductive layer 104 may be a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 102. However, in an exemplary embodiment, the second horizontal conductive layer 104 may be replaced with an insulating layer.

[0025] The horizontal insulating layer 110 may be disposed on the second substrate 101 at the same level as the first horizontal conductive layer 102. The horizontal insulating layer 110 may include first and second horizontal insulating layers 111 and 112. The horizontal insulating layer 110 may be a layer that remains after a portion of it is replaced by the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100. The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. In one example, the first horizontal insulating layer 111 and the second horizontal insulating layer 112 may include different insulating materials.

[0026] The substrate insulating layer 121 may be disposed to extend in the third direction (Z direction) from the second region R2 and penetrate the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. The substrate insulating layer 121 may be disposed to surround each of the contact plugs 170. This allows the contact plugs 170 connected to different gate electrodes 130 to be electrically isolated from each other. The substrate insulating layer 121 may also be disposed in the third region R3 and to surround each of the through plugs 175.

[0027] The substrate insulating layer 121 may include an insulating material such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0028] The gate electrodes 130 may be stacked vertically spaced apart on the second substrate 101 to form a stacked structure. The gate electrodes 130 may include a lower gate electrode 130L forming a gate of a ground selection transistor, memory gate electrodes 130M forming a plurality of memory cells, and an upper gate electrode 130U forming a gate of a string selection transistor. The number of memory gate electrodes 130M forming memory cells may be determined depending on the capacity of the semiconductor device 100. Depending on the embodiment, the upper and lower gate electrodes 130U and 130L may each be one to four or more and may have the same or different structure as the memory gate electrode 130M. In an exemplary embodiment, the gate electrode 130 may further include a gate electrode 130 forming an erase transistor disposed below the upper gate electrode 130U and / or the lower gate electrode 130L and used for an erase operation using a gate induced drain leakage (GIDL) phenomenon. Furthermore, some of the gate electrodes 130, for example, the memory gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L, may be dummy gate electrodes.

[0029] The gate electrodes 130 may be stacked vertically and spaced apart on the first region R1 and may extend from the first region R1 to the second region R2 at different lengths to form a stepped structure. The gate electrodes 130 may form a stepped structure between the gate electrodes 130 along the first direction (X direction) and may also be arranged to have a stepped structure in the second direction (Y direction). Due to the stepped structure, the lower gate electrode 130 may extend longer than the upper gate electrode 130, be exposed from the interlayer insulating layer 120, and have a region in contact with the contact plug 170. This region may be referred to as a gate contact region 130P. The gate contact region 130P of each gate electrode 130 may be a region including an end portion along the first direction (X direction). The gate contact region 130P may correspond to a portion of the gate electrodes 130 forming the stacked structure in the second region R2 of the second substrate 101. The gate electrode 130 may be connected to the contact plug 170 at the gate contact region 130P.

[0030] The gate electrodes 130 may be separated from each other in the second direction (Y direction) by a first isolation region MS1 ​​extending in the first direction (X direction). The gate electrodes 130 between a pair of first isolation regions MS1 may form one memory block, but the scope of the memory block is not limited thereto. The gate electrodes 130 may include a metal material, such as tungsten (W). Depending on the embodiment, the gate electrodes 130 may include polycrystalline silicon or a metal silicide material.

[0031] The interlayer insulating layers 120 may be disposed between the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layers 120 may be disposed to extend in the first direction (X direction) and spaced apart from each other in a direction perpendicular to the top surface of the second substrate 101. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

[0032] The first and second isolation regions MS1 and MS2 may be disposed to extend along the first direction (X direction) through the gate electrode 130. The first and second isolation regions MS1 and MS2 may be disposed parallel to each other. The first and second isolation regions MS1 and MS2 may be connected to the second substrate 101 by penetrating the entire gate electrode 130 stacked on the second substrate 101. The first isolation region MS1 ​​may extend along the first direction (X direction), and the second isolation region MS2 may extend intermittently between a pair of first isolation regions MS1 or may be disposed in only a portion of the first isolation region MS1. However, in the embodiment, the arrangement order, number, etc. of the first and second isolation regions MS1 and MS2 are not limited to those shown in FIG. 1a. As shown in FIG. 1c, an isolation insulating layer 105 may be disposed in the first and second isolation regions MS1 and MS2.

[0033] As shown in FIGS. 1A and 1C, the upper isolation region US may extend in the first direction (X direction) between the first isolation region MS1 ​​and the second isolation region MS2 in the first region R1. The upper isolation region US may include, for example, the upper gate electrode 130U, to separate a total of three gate electrodes 130 from each other in the second direction (Y direction). However, the number of gate electrodes 130 separated by the upper isolation region US may vary depending on the embodiment. The upper gate electrodes 130U separated by the upper isolation region US may form different string selection lines. An upper isolation insulating layer 103 may be disposed in the upper isolation region US. The upper isolation insulating layer 103 may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0034] 1a, the channel structures CH each form one memory cell string and may be arranged spaced apart from one another in rows and columns in the first region R1. The channel structures CH may be arranged in a checkerboard pattern or in a staggered pattern in one direction. The channel structures CH may have a columnar shape and may have sloped sides that become narrower as they approach the second substrate 101 depending on the aspect ratio.

[0035] 1b, the channel structure CH may include first and second channel portions CH1 and CH2 stacked vertically. Each channel structure CH may have a shape in which a first channel portion CH1 penetrating a lower stack structure of the gate electrode 130 and a second channel portion CH2 penetrating an upper stack structure of the gate electrode 130 are connected to each other, and may have a bent portion due to a difference in width in the connection region. However, depending on the embodiment, the number of channel structures stacked along the third direction (Z direction) may be variously changed.

[0036] 1c, a channel layer 140 may be disposed within the channel structure CH. The channel layer 140 within the channel structure CH may be formed in an annular shape surrounding the inner channel buried insulating layer 147. The channel layer 140 may be connected to the first horizontal conductive layer 102 at a lower portion. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystalline silicon.

[0037] The gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer, which are sequentially stacked from the channel layer 140. The tunneling layer may tunnel charges to the charge storage layer and may include, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In an exemplary embodiment, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130. The channel pad 149 may be disposed only on an upper end of the upper second channel portion CH2. The channel pad 149 may include, for example, doped polycrystalline silicon.

[0038] The channel layer 140, the gate dielectric layer 145, and the channel buried insulating layer 147 may be connected to each other between the first channel portion CH1 and the second channel portion CH2. A relatively thick upper interlayer insulating layer 125 may be disposed between the first channel portion CH1 and the second channel portion CH2, i.e., between the lower stack structure and the upper stack structure. However, the shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may be variously changed depending on the embodiment.

[0039] The dummy channel structures DCH may be arranged spaced apart from one another in rows and columns in the second region R2. The dummy channel structures DCH may be larger than the channel structures CH in a plan view, but are not limited to this. The dummy channel structures DCH may also be arranged in a portion of the first region R1 adjacent to the second region R2. The dummy channel structures DCH may not be electrically connected to an upper wiring structure and may not form a memory cell string in the semiconductor device 100, unlike the channel structures CH.

[0040] The dummy channel structures DCH may have the same or different structure as the channel structures CH. When the dummy channel structures DCH are formed together with the channel structures CH, the dummy channel structures DCH may have the same structure as the channel structures CH. When the dummy channel structures DCH are formed using a part of the process of forming the contact plug 170, the dummy channel structures DCH may have a different structure from the channel structures CH. In this case, for example, the dummy channel structures DCH may have a structure filled with an insulating material such as oxide.

[0041] The contact plugs 170 may penetrate the uppermost gate electrodes 130 and the interlayer insulating layer 120 in the second region R2 and be connected to the gate contact regions 130P of the gate electrodes 130. The contact plugs 170 may be disposed to penetrate at least a portion of the cell region insulating layer 190 and extend toward the gate contact regions 130P to be connected to each of the gate contact regions 130P of the gate electrodes 130.

[0042] The contact plug 170 may be connected to a circuit wiring line 280 in the peripheral circuit region PERI by penetrating the second substrate 101, the second horizontal conductive layer 104, and the horizontal insulating layer 110 under the gate electrode 130. The contact plug 170 may be separated from the second substrate 101, the second horizontal conductive layer 104, and the horizontal insulating layer 110 by a substrate insulating layer 121.

[0043] The contact plug 170 may be surrounded by the substrate insulating layer 121 and electrically isolated from the second substrate 101. In an exemplary embodiment, a region including the lower end of the contact plug 170 may be surrounded by a pad layer 285 on the circuit wiring line 280. However, depending on the embodiment, the contact plug 170 may not extend into the pad layer 285 but may be in contact with the pad layer 285. The pad layer 285 may be a layer for protecting the circuit wiring line 280 during the manufacturing process of the semiconductor device 100 and may include a conductive material, for example, polycrystalline silicon.

[0044] The contact plug 170 may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In an exemplary embodiment, the contact plug 170 may further include a barrier layer (e.g., conductive liner 173 in FIG. 3a) on the sidewall and bottom of the contact hole in which the contact plug 170 is disposed. The barrier layer may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0045] The contact insulating layer 160 may surround the contact plug 170 while being alternately arranged with the interlayer insulating layer 120. The contact insulating layer 160 may include a first contact insulating layer 161 disposed between the gate contact region 130P and the contact plug 170 and surrounding a side surface of the contact plug 170, and a second contact insulating layer 162 disposed below the gate contact region 130P and surrounding a side surface of the contact plug 170. An inner surface of the contact insulating layer 160 may surround the contact plug 170, and an outer surface of the contact insulating layer 160 may be surrounded by the gate electrode 130. The contact insulating layer 160 may physically and electrically connect the contact plug 170 to the gate contact region 130P and electrically isolate the contact plug 170 from the gate electrode 130 below the gate contact region 130P.

[0046] The through plug 175 may be disposed in a third region R3 of the memory cell region CELL, which is an outer region of the second substrate 101, and may extend to the peripheral circuit region PERI by penetrating the cell region insulating layer 190. The through plug 175 may be disposed to connect a cell wiring line 195 of the memory cell region CELL to a circuit wiring line 280 of the peripheral circuit region PERI. The through plug 175 may include a conductive material, such as a metal material such as tungsten (W), copper (Cu), or aluminum (Al). The through plug 175 may be formed in the same process step as the contact plug 170, may include the same material, and may have the same internal structure.

[0047] The cell region insulating layer 190 may be disposed to cover the second substrate 101, the gate electrode 130 on the second substrate 101, and the peripheral region insulating layer 290. The cell region insulating layer 190 may be made of an insulating material and may be made of multiple insulating layers.

[0048] The cell wiring line 195 may constitute an upper wiring structure electrically connected to the memory cells in the memory cell region CELL. The cell wiring line 195 may be connected to the contact plug 170 and the through plug 175, and may be electrically connected to the gate electrode 130 and the channel structure CH. In an exemplary embodiment, the number of contact plugs and wiring lines constituting the upper wiring structure may vary. The cell wiring line 195 may include a metal, such as tungsten (W), copper (Cu), or aluminum (Al).

[0049] In this specification, the first direction (X direction) and the second direction (Y direction) may be perpendicular to each other. The first direction (X direction) and the second direction (Y direction) may be perpendicular to the third direction (Z direction). The horizontal direction may refer to the first direction (X direction) and the second direction (Y direction).

[0050] FIG. 2 is a schematic enlarged view of region A of the semiconductor device of FIG. 1b.

[0051] Referring to FIG. 2, the contact plug 170 may be connected to the gate electrode of the gate electrode 130 through the gate contact region 130P.

[0052] Each gate electrode 130 may include a gate contact region 130P and a gate stack region 130G, which is the remaining region excluding the gate contact region 130P. The gate contact region 130P may be a region of the gate electrode layer that is not covered by other gate electrodes due to a stepped structure. The gate stack region 130G may be a region of the gate electrode layer that is covered by other gate electrodes. The gate contact region 130P may overlap the horizontal extension portion 170H of the contact plug 170 in the third direction (Z direction) and contact a lower surface of the horizontal extension portion 170H.

[0053] The gate electrode 130 may include a first gate electrode portion 130a corresponding to the gate contact region 130P and a second gate electrode portion 130b corresponding to the gate stack region 130G. In this specification, the first gate electrode portion 130a may be referred to as a gate contact pad, and the second gate electrode portion 130b may be referred to as a gate stack structure.

[0054] The contact insulating layer 160 may include a first contact insulating layer 161 disposed between the gate contact region 130P and the vertical extension 170V of the contact plug 170 and a second contact insulating layer 162 disposed between the gate stack region 130G and the vertical extension 170V. The contact plug 170 may be electrically isolated from the second gate electrode portion 130b below the gate contact region 130P by the second contact insulating layer 162.

[0055] The first and second contact insulating layers 161 and 162 may have the same length in the horizontal direction. In one example, the length of the first contact insulating layer 161 in the third direction (Z direction) may be shorter than the length of the second contact insulating layer 162 in the third direction (Z direction). In one example, the top surface of the first contact insulating layer 161 may be disposed at a level lower than the top surface of the gate contact region 130P (or the first gate electrode portion 130a). However, this is not limited thereto, and the top surface of the first contact insulating layer 161 may be disposed at the same level as the top surface of the gate contact region 130P. In one example, the top surface of the second contact insulating layer 162 may be disposed at the same level as the top surface of the gate stack region 130G (or the second gate electrode portion 130b).

[0056] The contact plug 170 may have a shape that extends horizontally toward the gate contact region 130P and the first contact insulating layer 161. In one example, the contact plug 170 may include a vertical extension 170V that extends along the third direction (Z direction) through the gate electrode 130 and the interlayer insulating layer 120, and a horizontal extension 170H that extends horizontally from the vertical extension 170V and contacts an upper surface of the gate contact region 130P and an upper surface of the first contact insulating layer 161. In one example, the horizontal extension 170H is arranged along the periphery of the vertical extension 170V, the side and top surfaces of the horizontal extension 170H may be covered by the cell region insulating layer 190, and the bottom surface of the horizontal extension 170H may be covered by the first gate electrode portion 130a and the first contact insulating layer 161.

[0057] 3a is an enlarged view of an embodiment of region B of the semiconductor device of FIG. 2, and FIG. 3b is an enlarged view of an embodiment of region C of the semiconductor device of FIG. 3a.

[0058] 3a and 3b, the semiconductor device 100a may include a contact plug 170, first and second gate electrode portions 130a and 130b, and first and second contact insulating layers 161 and 162.

[0059] The contact plug 170 may include a vertical extension 170V penetrating the gate electrode 130 and the interlayer insulating layer 120, a horizontal extension (e.g., the horizontal extension 170H in FIG. 2) extending from the vertical extension 170V onto the first gate electrode portion 130a and the first contact insulating layer 161, and a conductive liner 173 covering the side surface of the vertical extension 170V and the surface of the horizontal extension 170H. In one example, the vertical extension 170V may extend in a third direction (Z direction) penetrating the first and second gate electrode portions 130a and 130b and the interlayer insulating layer 120. The horizontal extension 170H may extend horizontally from the vertical extension 170V and overlap and / or contact the first gate electrode portion 130a and the first contact insulating layer 161 in the third direction (Z direction). The horizontal extension 170H may include a first horizontal extension 170Ha in contact with the first contact insulating layer 161 and a second horizontal extension 170Hb in contact with the first gate electrode portion 130a. In one example, the vertical height of the first horizontal extension 170Ha may be greater than the vertical height of the second horizontal extension 170Hb.

[0060] The conductive liner 173 may function as a metal barrier layer of the contact plug 170. The conductive liner 173 may be disposed according to the surface profiles of the vertical extension 170V and the horizontal extension 170H. The conductive liner 173 may cover a side surface of the vertical extension 170V and may extend from the side surface of the vertical extension 170V to cover a surface of the horizontal extension 170H. That is, the conductive liner 173 may extend between the horizontal extension 170H and the cell region insulating layer 190, between the second horizontal extension 170Hb and the first gate electrode portion 130a, and between the first horizontal extension 170Ha and the first contact insulating layer 161. The conductive liner 173 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0061] The first gate electrode portion 130a may include a first conductive layer CP1 and a first barrier layer PP1 extending from at least a portion of the outer surface of the first conductive layer CP1 and disposed on a lower surface of the first conductive layer CP1. The first barrier layer PP1 may be a barrier layer in which a conductive liner 173 extends between the first conductive layer CP1 and the first contact insulating layer 161 to cover a lower surface of the first conductive layer CP1. The first conductive layer CP1 may be covered by the conductive liner 173 and the first barrier layer PP1. In one example, the first gate electrode portion 130a may further include a first blocking layer BP1 covering a portion of the first conductive layer CP1. The first blocking layer BP1 may extend from between the first barrier layer PP1 and the first contact insulating layer 161 to cover a lower surface of the first barrier layer PP1.

[0062] The second gate electrode portion 130b may include a second conductive layer CP2 and a second barrier layer PP2 disposed according to a surface profile of the second conductive layer CP2, and may further include a second blocking layer BP2 covering the second barrier layer PP2.

[0063] A height H1 from the lower surface of the first gate electrode portion 130a to the upper surface of the horizontal extension portion 170H may be greater than a height H3 in the third direction (Z direction) of the second gate electrode portion 130b.

[0064] The height H2 of the first gate electrode portion 130a in the third direction (Z direction) may be smaller than the height H3 of the second gate electrode portion 130b in the third direction (Z direction). For example, the height H2 of the first gate electrode portion 130a may be about 17 nm to about 21 nm, and the height H3 of the second gate electrode portion 130b may be about 26 nm to about 27 nm.

[0065] The first and second conductive layers CP1 and CP2 may include a metal material. For example, the first and second conductive layers CP1 and CP2 may include tungsten (W). In one example, the first and second conductive layers CP1 and CP2 may include the same material as the vertical extension portion 170V and the horizontal extension portion 170H of the contact plug 170. However, without being limited thereto, the first and second conductive layers CP1 and CP2 may include a different metal material from the vertical extension portion 170V and the horizontal extension portion 170H of the contact plug 170.

[0066] The first and second barrier layers PP1 and PP2 may include the same material as the conductive liner 173. However, without being limited thereto, the first and second barrier layers PP1 and PP2 may include a different conductive material from the conductive liner 173. For example, the first and second barrier layers PP1 and PP2 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0067] The first and second blocking layers BP1 and BP2 may include a metal oxide, for example, aluminum oxide (AlO).

[0068] The first contact insulating layer 161 may be disposed between the first gate electrode portion 130a and the vertical extension 170V. An outer surface of the first contact insulating layer 161 adjacent to the first gate electrode portion 130a may be in contact with the first blocking layer BP1, and an upper surface of the first contact insulating layer 161 may be in contact with the conductive liner 173. In one example, the upper surface of the first contact insulating layer 161 may be disposed at a lower level than the upper surface of the first gate electrode portion 130a.

[0069] The second contact insulating layer 162 may be disposed between the second gate electrode portion 130b and the vertical extension 170V. An outer surface of the second contact insulating layer 162 may be in contact with the second blocking layer BP2, and upper and lower surfaces of the second contact insulating layer 162 may be in contact with the interlayer insulating layer 120. The upper and lower surfaces of the second contact insulating layer 162 may be disposed at the same level as the upper and lower surfaces of the second gate electrode portion 130b.

[0070] The first contact insulating layer 161 and the second contact insulating layer 162 may include first insulating patterns IL1a, IL2a and second insulating patterns IL1b, IL2b partially surrounded by the first insulating patterns IL1a, IL2a. The first contact insulating layer 161 may include a 1-1 insulating pattern IL1a and a 1-2 insulating pattern IL1b partially surrounded by the 1-1 insulating pattern IL1a. The second contact insulating layer 162 may include a 2-1 insulating pattern IL2a and a 2-2 insulating pattern IL2b partially surrounded by the 2-1 insulating pattern IL2a.

[0071] The first insulating patterns IL1a, IL2a may include horizontally flat first flat portions IL1a_1, IL2a_1, and first protruding portions IL1a_2, IL2a_2 extending from the first flat portions IL1a_1, IL2a_1 and protruding toward the interlayer insulating layer 120 between the first flat portions IL1a_1, IL2a_1 and the vertical extension portion 170V.

[0072] The second insulating patterns IL1b, IL2b may include second flat portions IL1b_1, IL2b_1 surrounded by the first flat portions IL1a_1, IL2a_1 of the first insulating patterns IL1a, IL2a, second protrusions IL1b_2, IL2b_2 surrounded by the first protrusions IL1a_2, IL2a_2 of the first insulating patterns IL1a, IL2a and whose thickness gradually increases toward the vertical extension 170V corresponding to the first protrusions IL1a_2, IL2a_2, and third protrusions IL1b_3, IL2b_3 protruding from the ends of the second protrusions IL1b_2, IL2b_2 toward the vertical extension 170V.

[0073] The first flat portions IL1a_1 and IL2a_1 may have a first height in the third direction (Z direction), and the first protrusion portions IL1a_2 and IL2a_2 may have a second height higher than the first height. The first contact insulating layer 161 and the second contact insulating layer 162 may include a bent portion due to the difference in height between the first flat portions IL1a_1 and IL2a_1 and the first protrusion portions IL1a_2 and IL2a_2. In one example, a bent portion due to the difference in height between the first flat portion IL1a_1 and the first protrusion portion IL1a_2 in the third direction (Z direction) may be disposed and / or formed on a lower surface of the first contact insulating layer 161. Bent portions due to the difference in height between the first flat portion IL2a_1 and the first protrusion portion IL2a_2 in the third direction (Z direction) may be disposed and / or formed on an upper surface and a lower surface of the second contact insulating layer 162.

[0074] In one example, the top surface of the first flat portion IL1a_1 of the first contact insulating layer 161 may have a flat shape. In one example, the top surface of the first flat portion IL1a_1 of the first contact insulating layer 161 may be disposed at a lower level than the top surface of the first gate electrode portion 130a. The top surface of the first flat portion IL2a_1 of the second contact insulating layer 162 may be disposed at the same level as the top surface of the second gate electrode portion 130b.

[0075] Since the first protrusions IL1a_2, IL2a_2 of the first and second contact insulating layers 161, 162 protrude toward the interlayer insulating layer 120, the thickness of the interlayer insulating layer 120 in contact with the lower parts of the first flat portions IL1a_1, IL2a_1 may be greater than the thickness of the interlayer insulating layer 120 in contact with the lower parts of the first protrusions IL1a_2, IL2a_2.

[0076] In one example, the second protrusions IL1b_2, IL2b_2 may extend from the second flat portions IL1b_1, IL2b_1 and have a tapered shape in which the thickness in the third direction (Z direction) gradually increases toward the vertical extension portion 170V. The third protrusions IL1b_3, IL2b_3 may extend from ends of the second protrusions IL1b_2, IL2b_2 and have a height smaller than the height of the ends of the second protrusions IL1b_2, IL2b_2 in the third direction (Z direction).

[0077] On the same axis in the third direction (Z direction), the height of the first contact insulating layer 161 in the third direction (Z direction) may be smaller than the height of the second contact insulating layer 162 in the third direction (Z direction).

[0078] The distance from the upper surface of the second flat portion IL1b_1 of the first contact insulating layer 161 to the upper surface of the first flat portion IL1a_1 may be smaller than the distance from the lower surface of the second flat portion IL1b_1 to the lower surface of the first flat portion IL1a_1 of the first contact insulating layer 161. The upper surface of the first flat portion IL1a_1 of the first contact insulating layer 161 may be partially etched during the manufacturing process of the semiconductor device 100a to have a flat surface.

[0079] The distance from the upper surface of the second flat portion IL2b_1 of the second contact insulating layer 162 to the upper surface of the first flat portion IL2a_1 may be substantially the same as the distance from the lower surface of the second flat portion IL2b_1 of the second contact insulating layer 162 to the lower surface of the first flat portion IL2a_1.

[0080] The conductive liner 173 may extend between the horizontal extension 170H and the first flat portion IL1a_1 of the first contact insulating layer 161, between the vertical extension 170V and the first and second contact insulating layers 161, 162, and between the vertical extension 170V and the interlayer insulating layer 120. The conductive liner 173 may be disposed according to a surface profile of the third protrusion IL1b_3 protruding toward the vertical extension 170V. The conductive liner 173 may be disposed according to a surface profile of the uneven structure of the sidewall of the vertical extension 170V, which is caused by a difference in etching rate between the first insulating patterns IL1a, IL2a and the second insulating patterns IL1b, IL2b of the first and second contact insulating layers 161, 162 in the manufacturing process of the semiconductor device.

[0081] The second insulating patterns IL1b, IL2b may include a first void 161V and a second void 162V.

[0082] The second insulating pattern IL1b of the first contact insulating layer 161 may include a first void 161V. The first void 161V may include a first void 161Va and a second void 161Vb that is horizontally spaced apart from the first void 161Va and adjacent to the vertical extension portion 170V. In one example, the first void 161Va and the first void 161Vb may be arranged horizontally spaced apart across a second protrusion portion IL1b_2 of the first contact insulating layer 161. The first void 161Va may be arranged within the second flat portion IL1b_1, and the first void 161Vb may be arranged within the third protrusion portion IL1b_3.

[0083] The second insulating pattern IL2b of the second contact insulating layer 162 may include a second void 162V. The second void 162V may include a 2-1 void 162Va and a 2-2 void 162Vb that is horizontally spaced apart from the 2-1 void 162Va and adjacent to the vertical extension portion 170V. In one example, the 2-1 void 162Va and the 2-2 void 162Vb may be arranged horizontally spaced apart across a second protrusion portion IL2b_2 of the second contact insulating layer 162. The 2-1 void 162Va may be arranged within the second flat portion IL2b_1, and the 2-2 void 162Vb may be arranged within the third protrusion portion IL2b_3.

[0084] The first void 161V and the second void 162V are empty spaces formed without being filled with an insulating material. During the process of forming the second insulating patterns IL1b and IL2b, a first-1 void 161Va and a second-1 void 162Va may be formed in second flat portions IL1b_1 and IL2b_1 disposed between the first flat portions IL1a_1 and IL2a_1 due to the narrow and deep shape between the first flat portions IL1a_1 and IL2a_1 of the first insulating patterns IL1a and IL2a, respectively. During the manufacturing process, a first-2 void 161Vb and a second-2 void 162Vb may be disposed and / or formed in third protrusions IL1b_3 and IL2b_3 disposed in the narrow and deep shape.

[0085] By making the first and second contact insulating layers 161 and 162 have shapes that protrude toward the interlayer insulating layer 120, the first insulating patterns IL1a and IL2a may include first flat portions IL1a_1 and IL2a_1 and first protrusions IL1a_2 and IL2a_2 extending from the first flat portions IL1a_1 and IL2a_1 in accordance with the surface profile. As a result, the second protrusions IL1b_2 and IL2b_2 of the second insulating patterns IL1b and IL2b may have tapered shapes that increase in thickness toward the vertical extensions 170V in accordance with the shapes of the first protrusions IL1a_2 and IL2a_2, and first voids 161V and second voids 162V may be formed in the second insulating patterns IL1b and IL2b based on the second protrusions IL1b_2 and IL2b_2.

[0086] The horizontal lengths of the first-1 void 161Va and the second-1 void 162Va can be greater than the horizontal lengths of the first-2 void 161Vb and the second-2 void 162Vb.

[0087] The first insulating patterns IL1a, IL2a and the second insulating patterns IL1b, IL2b may include an insulating material. In one example, the first insulating patterns IL1a, IL2a may include a first insulating material, and the second insulating patterns IL1b, IL2b may include a second insulating material different from the first insulating material. For example, the first insulating patterns IL1a, IL2a may include silicon oxide, and the second insulating patterns IL1b, IL2b may include silicon nitride.

[0088] The semiconductor device according to the present invention may include a first contact insulating layer 161 disposed between the first gate electrode portion 130a and the vertical extension 170V and a second contact insulating layer 162 disposed between the second gate electrode portion 130b and the vertical extension 170V. The second contact insulating layer 162 may include a first insulation pattern IL2a having a first protrusion protruding toward the interlayer insulating layer 120 and a second insulation pattern IL2b having a second protrusion having a tapered shape and disposed between the first insulation pattern IL2a corresponding to the first protrusion. As a result, second-1 voids 161Va and 162Va and second-2 voids 161Vb and 162Vb spaced apart in the horizontal direction based on the tapered shape may be formed in the second insulation pattern IL2b. Even if the second-2 void 162Vb adjacent to the vertical extension 170V is deformed or ruptured during the manufacturing process of the semiconductor device, the second-1 void 162Va adjacent to the second gate electrode portion 130b can be protected based on the tapered second protrusion of the second insulation pattern IL2b. That is, the contact plug 170 and the second gate electrode portion 130b can be properly insulated via the second contact insulation layer 162, thereby providing a semiconductor device with improved reliability.

[0089] 4a to 4c are enlarged views showing another embodiment of region B of the semiconductor device of FIG.

[0090] 4a, in the semiconductor device 100b, the remaining configuration, excluding the first contact insulating layer 161′, may be the same as or correspond to the configuration shown in FIG 3a. Of the remaining configuration, excluding the first contact insulating layer 161′, the same or corresponding components as those shown in FIG 3a will not be described again.

[0091] 4a, the first contact insulating layer 161' may include a first insulating pattern IL1a' and a second insulating pattern IL1b. An upper surface of the first insulating pattern IL1a' may be disposed at the same level as an upper surface of the first gate electrode portion 130a. The conductive liner 173 may be flat on the first gate electrode portion 130a and the first contact insulating layer 161 without any additional steps.

[0092] 4b, in the semiconductor device 100c, the remaining configuration, excluding the sealing pattern 163, may be the same as or correspond to the configuration shown in Fig. 3a. Of the configuration other than the sealing pattern 163, the same or corresponding components as the configuration shown in Fig. 3a will not be described again.

[0093] The first insulating patterns IL1a, IL2a and the second insulating patterns IL1b, IL2b may include different insulating materials, so that the first insulating patterns IL1a, IL2a exposed toward the vertical extension 170V and the third protrusions IL1b_3, IL2b_3 of the second insulating patterns IL1b, IL2b protruding toward the vertical extension 170V may have different levels in the third direction (Z direction). In one example, the third protrusions IL1b_3, IL2b_3 of the second insulating patterns IL1b, IL2b may protrude toward the vertical extension 170V based on the first flat portions IL1a_1, IL2a_1 of the first insulating patterns IL1a, IL2a.

[0094] The sealing pattern 163 may contact the lower portions of the third protrusions IL1b_3 and IL2b_3 of the second insulation patterns IL1b and IL2b, and may extend between the first protrusions IL1a_2 and IL2a_2 of the first insulation patterns IL1a and IL2a and the vertical extensions 170V, and between the interlayer insulating layer 120 and the vertical extensions 170V. The sealing pattern 163 may be arranged to eliminate uneven structures (or steps) between the first and second contact insulating layers 161 and 162 and the vertical extensions 170V.

[0095] The sealing pattern 163 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In one example, the sealing pattern 163 may include the same insulating material as the second insulating patterns IL1b and IL2b. For example, the sealing pattern 163 may include silicon nitride. In this case, the sealing pattern 163 may not be interfacial with the second insulating patterns IL1b and IL2b. That is, the sealing pattern 163 and the second insulating patterns IL1b and IL2b may extend and be integrated between the first insulating pattern IL1a and the vertical extension 170V of the first contact insulating layer 161, between the interlayer insulating layer 120 and the vertical extension 170V, and between the first insulating pattern IL2a of the second contact insulating layer 162. The second insulating pattern IL1b of the first contact insulating layer 161 and the second insulating pattern IL2b of the second contact insulating layer 162 may be integrated.

[0096] The conductive liner 173 extends from between the horizontal extension 170H and the first contact insulating layer 161 to between one side of the second insulating patterns IL1b, IL2b and the vertical extension 170V, and between the sealing pattern 163 and the vertical extension 170V, and may be arranged according to a surface profile. The conductive liner 173 may be arranged according to a flat side profile with the vertical extension 170V.

[0097] The semiconductor device according to the embodiment of the present invention includes a sealing pattern 163 that fills the uneven or bent portion between the first and second contact insulating layers 161 and 162 and the vertical extension 170V, so that the vertical extension 170V can have a flat sidewall structure. This can improve the electric field concentration phenomenon caused by the uneven sidewall structure and minimize defects that cause voids in the contact plug 170.

[0098] Referring to FIG. 4c, in the semiconductor device 100d, the remaining configurations except for the first and second contact insulating layers 161″, 162″, the interlayer insulating layer 120″, and the sealing pattern 163 may be the same as or correspond to the configurations shown in FIG. 3a. Of the remaining configurations except for the first and second contact insulating layers 161″, 162″, and the sealing pattern 163, redundant descriptions of components that are the same as or correspond to the configurations shown in FIG. 3a will be omitted.

[0099] The first and second contact insulating layers 161" and 162" may include first insulating patterns IL1a" and IL2a" and second insulating patterns IL1b" and IL2b" that are partially surrounded by the first insulating patterns IL1a" and IL2a". The height of the first contact insulating layer 161" in the third direction (Z direction) may be smaller than the height of the second contact insulating layer 162" in the third direction (Z direction).

[0100] The first contact insulating layer 161″ may include a first insulating pattern IL1a″ and a second insulating pattern IL1b″ partially surrounded by the first insulating pattern IL1a″. The top surface of the second insulating pattern IL1b″ may be in contact with the conductive liner 173. The first insulating pattern IL1a″ may cover a side surface and a portion of a bottom surface of the second insulating pattern IL1b″. The second insulating pattern IL1b″ may include a portion that protrudes toward the vertical extension 170V formed during the manufacturing process due to a difference in insulating material between the second insulating pattern IL1b″ and the first insulating pattern IL1a″. In one example, the bottom surface of the first contact insulating layer 161″ may be disposed at the same level as the bottom surface of the first gate electrode portion 130a.

[0101] The second contact insulating layer 162″ may include a first insulating pattern IL2a″ and a second insulating pattern IL2b″ partially surrounded by the first insulating pattern IL2a″. The second insulating pattern IL2b″ may include a portion protruding toward the vertical extension 170V. An upper surface of the second contact insulating layer 162″ may be disposed at the same level as an upper surface of the second gate electrode portion 130b. A lower surface of the second contact insulating layer 162″ may be disposed at the same level as a lower surface of the second gate electrode portion 130b.

[0102] The sealing pattern 163 may surround the second insulating patterns IL1b″ and IL2b″ protruding toward the horizontal extension 170V and extend between the interlayer insulating layer 120 and the vertical extension 170V. The sealing pattern 163 may fill the uneven structure and / or the bent portion between the first and second contact insulating layers 161″ and 162″ and the vertical extension 170V.

[0103] The conductive liner 173 may be arranged according to the surface profile by extending from between the horizontal extension 170H and the first contact insulating layer 161″ to between the side surfaces of the second insulating patterns IL1b″, IL2b″ and the vertical extension 170V, and to the sealing pattern 163 and the vertical extension 170V. The conductive liner 173 may cover a flat surface between the vertical extension 170V and the sealing pattern 163.

[0104] The thickness of the interlayer insulating layer 120 in the third direction (Z direction) may be constant.

[0105] The semiconductor device according to the embodiment of the present invention includes a sealing pattern 163 that fills the uneven structure or bent portion between the first and second contact insulating layers 161″ and 162″ and the vertical extension 170V, so that the vertical extension 170V can have a flat sidewall structure. This can improve the electric field concentration phenomenon caused by the uneven sidewall structure and minimize defects that cause voids in the contact plug 170.

[0106] Figures 5a to 5f are cross-sectional views showing one embodiment of a method for manufacturing the semiconductor device of Figure 1b. The method for manufacturing the semiconductor device will be described with reference to Figures 5a to 5f, focusing on region D of Figure 1b.

[0107] Referring to FIG. 5a, a laminate structure MS can be formed on a plate layer SS.

[0108] The stacked structure MS may include an interlayer insulating layer 120P and a sacrificial insulating layer 122P. The interlayer insulating layers 120P and the sacrificial insulating layers 122P may be alternately stacked in the third direction (Z direction). The stacked structure MS may be formed in a stepped shape by patterning the interlayer insulating layers 120P and the sacrificial insulating layers 122P. Each sacrificial insulating layer 122P may form a pair with any one of the interlayer insulating layers 120P adjacent in the third direction (Z direction) and extend in the first direction (X direction). The pair formed by the interlayer insulating layer 120P and the sacrificial insulating layer 122P may extend in the first direction (X direction) with different lengths in the second region R2 to form a stepped structure. The stepped structure may provide a plurality of pad regions ST1 to ST3. By forming the plurality of pad regions, at least a portion of the sacrificial insulating layer 122P located below in the third direction (Z direction) may be exposed to the outside.

[0109] The interlayer insulating layer 120P and the sacrificial insulating layer 122P may be formed of materials having a predetermined etching selectivity. In one example, the preliminary interlayer insulating layer 120P may include at least one of a silicon oxide layer and a silicon nitride layer, and the sacrificial insulating layer 122P may be one of a silicon layer, a silicon oxide layer, a silicon carbide layer, and a silicon nitride layer. For example, the preliminary interlayer insulating layer 120P may be made of a different material from the interlayer insulating layer 120P. For example, if the interlayer insulating layer 120P is made of a silicon oxide layer, the sacrificial insulating layer 122P may be made of a silicon nitride layer.

[0110] 5b, a portion of the preliminary interlayer insulating layer 120P is recessed to form the interlayer insulating layer 120. By injecting an etching solution through one side of the preliminary interlayer insulating layer 120P having a stepped structure with different lengths, only the portions of the preliminary interlayer insulating layer 120P disposed under the pad regions ST1 to ST3 are selectively removed, thereby forming the interlayer insulating layer 120.

[0111] 5c, pad structures 151P and 152P may be formed on the sacrificial insulating layer 122. The pad structures 151P and 152P may include a first sacrificial pad layer 151P and a second sacrificial pad layer 152P sequentially formed on the sacrificial insulating layer 122.

[0112] The first sacrificial pad layer 151P may be one of a silicon film, a silicon oxide film, a silicon carbide film, and a silicon nitride film. For example, it may be a different material from the sacrificial insulating layer 122. For example, if the sacrificial insulating layer 122 is a silicon nitride film, the first sacrificial pad layer 151P may include a silicon oxide film. In one example, the first sacrificial pad layer 151P may include polysilicon.

[0113] The height of the first sacrificial pad layer 151P in the third direction (Z direction) may be smaller than the height of the second sacrificial pad layer 152P in the third direction (Z direction). For example, the height of the first sacrificial pad layer 151P may be about 5 nm. The height of the second sacrificial pad layer 152P may be about 17 nm.

[0114] 5d, first and second sacrificial pad layers 151 and 152 may be formed on the pad regions ST1 to ST3 by node-separating the first and second sacrificial pad layers 151P and 152P for each of the pad regions ST1 to ST3 to expose the interlayer insulating layer 120. The first and second sacrificial pad layers 151 and 152 may be formed by a patterning process.

[0115] A cell region insulating layer 190 may be formed to cover the first and second sacrificial pad layers 151 and 152 and the stacked structure MS disposed on the pad regions ST1 to ST3.

[0116] The first and second sacrificial pad layers 151 and 152 may be regions that are alternated with horizontal extensions of contact plugs (for example, horizontal extensions 170H in FIG. 2) to be described later.

[0117] Referring to FIG. 5e, a through hole OPN may be formed in the second region R2 in a region where a contact plug (eg, contact plug 170 in FIG. 1b) is to be formed.

[0118] In the second region R2, a through hole OPN may be formed through the cell region insulating layer 190, the first and second sacrificial pad layers 151 and 152, and the staircase structure of the stacked structure MS. The through hole OPN may have a cylindrical hole shape.

[0119] Referring to FIG. 5f, a trench TR may be formed by removing a portion of the sacrificial insulating layer 122 exposed through the through hole OPN.

[0120] An etchant may be introduced through the through hole OPN to remove a predetermined length of the sacrificial insulating layer 122 from around the through hole OPN, thereby forming a trench TR. In another example, a side surface of the sacrificial insulating layer 122 exposed through the through hole OPN may be dry-etched to form the trench TR. The length of the trench TR may be varied.

[0121] 6a to 6j are cross-sectional views showing an embodiment of a method for manufacturing the semiconductor device of FIG. 3a.

[0122] 6a shows an enlarged view of region E of the semiconductor device of FIG. 5f according to one embodiment. Referring to FIG. 6a, an etchant may be introduced through the first vertical through hole OV1 penetrating the sacrificial insulating layer 122 and the interlayer insulating layer 120 to remove a predetermined length of the sacrificial insulating layer 122 from around the first vertical through hole OV1, thereby forming a first horizontal tunnel layer OH1.

[0123] The sacrificial insulating layer 122 may include a first sacrificial insulating layer 122a disposed under the first sacrificial pad layer 151 and a second sacrificial insulating layer 122b disposed between the interlayer insulating layer 120. The first sacrificial insulating layer 122a may be a region that will be replaced with a first gate electrode portion (e.g., first gate electrode portion 130a in FIG. 6e) to be described later. The second sacrificial insulating layer 122b may be a region that will be replaced with a second gate electrode portion (e.g., second gate electrode portion 130b in FIG. 6e) to be described later.

[0124] The height of the first sacrificial insulating layer 122a in the third direction (Z direction) may be smaller than the height of the second sacrificial insulating layer 122b in the third direction (Z direction). During the process of recessing a portion of the preliminary interlayer insulating layer 120P in FIG. 5b, a portion of the top surface of the sacrificial insulating layer 122P disposed below the interlayer insulating layer 120P and having an exposed top surface for each of the pad regions ST1 to ST3 may be etched. This may result in the formation of the first sacrificial insulating layer 122a having an exposed top surface and the second sacrificial insulating layer 122b having an unexposed top surface as it is covered by the interlayer insulating layer 120.

[0125] 6b, the first horizontal tunnel layer OH1 may be further enlarged in a third direction (Z direction) toward the interlayer insulating layer 120 and the first sacrificial pad layer 151 to form a second horizontal tunnel layer OH2. The first horizontal tunnel layer OH1 may be directional etched in the third direction (Z direction) using a dry etching process. A portion of the first sacrificial pad layer 151 overlapping the first horizontal tunnel layer OH1 may be partially removed in the third direction (Z direction). The second horizontal tunnel layer OH2 may protrude toward the interlayer insulating layer 120 and the first sacrificial pad layer 151.

[0126] 6c, a third horizontal tunnel layer OH3 may be formed by performing a pull-back process or an etching process on the side of the sacrificial insulating layer 122 exposed through the second horizontal tunnel layer OH2. The third horizontal tunnel layer OH3 may include a 3-1 horizontal tunnel layer OH3a having an extension toward the first sacrificial pad layer 151 and the interlayer insulating layer 120 and a 3-2 horizontal tunnel layer OH3b extending horizontally toward the sacrificial insulating layer 122.

[0127] Referring to FIGS. 6c and 6d, an insulating structure 20 may be formed in the first vertical through hole OV1 and the third horizontal tunnel layer OH3 connected to the first vertical through hole OV1.

[0128] The insulating structure 20 may include a first insulating liner 25, a second insulating liner 23, and a sacrificial liner 21 that extend along the side of the first vertical through-hole OV1 and into the third horizontal tunnel layer OH3 and are formed sequentially through deposition processes. The deposition process may include an atomic layer deposition (ALD) process. The thickness of the sacrificial liner 21 may be thicker than the thicknesses of the first and second insulating liners 25 and 23.

[0129] The first insulating liner 25 may have a uniform thickness, extend from the side of the first vertical through hole OV1 into the third horizontal tunnel layer OH3, and be conformally formed according to the surface profile of the third horizontal tunnel layer OH3. The second insulating liner 23 may be deposited on the first insulating liner 25. That is, the second insulating liner 23 may be deposited to extend from the first insulating liner 25 formed on the side of the first vertical through hole OV1 to between the first insulating liner 25 in the third horizontal tunnel layer OH3. A sacrificial liner 21 may be deposited on the second insulating liner 23 disposed on the side of the first vertical through hole OV1.

[0130] The first insulating liner 25 can include a first insulating material, and the second insulating liner 23 can include a second insulating material different from the first insulating material. The sacrificial liner 21 can include carbon (C) or polysilicon. For example, the first insulating liner 25 can include silicon oxide, and the second insulating liner 23 can include silicon nitride.

[0131] The second insulating liner 23 may have a 1-1 void 161Va formed between the first sacrificial insulating layer 122a and the first insulating liner 25 in the adjacent 3-2 horizontal tunnel layer OH3b, and a 1-2 void 161Vb formed between the first insulating liner 25 in the 3-1 horizontal tunnel layer OH3a.

[0132] A 2-1 void 162Va may be formed during the process of forming the second insulating liner 23 between the first insulating liner 25 formed in the second sacrificial insulating layer 122b and the adjacent 3-2 horizontal tunnel layer OH3b, and a 2-2 void 162Vb may be formed during the process of forming the second insulating liner 23 between the first insulating liner 25 in the 3-1 horizontal tunnel layer OH3a.

[0133] The thickness of the second insulating liner 23 in the third horizontal tunneling layer OH3 adjacent to the first sacrificial insulating layer 122a may be smaller than the thickness of the second insulating liner 23 in the third horizontal tunneling layer OH3 adjacent to the second sacrificial insulating layer 122b.

[0134] 6d and 6e, the sacrificial insulating layer 122 may be removed to form the first and second gate electrode portions 130a and 130b. The sacrificial insulating layer 122 may be removed by a wet etching process. Before forming the first and second gate electrode portions 130a and 130b, a first blocking layer BP1_P may be deposited in the space where the first sacrificial insulating layer 122a was removed, and a second blocking layer BP2 may be deposited in the space where the second sacrificial insulating layer 122b was removed. The first blocking layer BP1_P and the second blocking layer BP2 may be conformally formed according to the inner wall surface profile of the space where the sacrificial insulating layer 122 was removed. The first blocking layer BP1_P and the second blocking layer BP2 may have a uniform thickness. The first blocking layer BP1_P and the second blocking layer BP2 may include a metal oxide. For example, the first blocking layer BP1_P and the second blocking layer BP2 may include aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), or aluminum oxide carbide (AlOC).

[0135] A first gate electrode portion 130a may be formed on the first blocking layer BP1_P, and a second gate electrode portion 130b may be formed on the second blocking layer BP2. In one example, a first barrier layer PP1 and a first conductive layer CP1 may be sequentially deposited on the first blocking layer BP1_P. A second barrier layer PP2 and a second conductive layer CP2 may be sequentially deposited on the second blocking layer BP2. In one example, the first and second barrier layers PP1 and PP2 may be conformally formed according to the surface profiles of the first blocking layer BP1_P and the second blocking layer BP2.

[0136] 6e and 6f, the insulating structure 20 surrounding the second vertical through hole OV2 may be removed. An etching process may be performed to remove the sacrificial liner 21 in the second vertical through hole OV2 and further partially remove the first and second insulating liners 25 and 23. The second insulating liner 23 may have a slower etching rate than the first insulating liner 25. In one example, the first insulating liner 25 may be etched to leave first insulating patterns IL1a_P1 and IL2a_P1 in the third horizontal tunnel layer OH3, and the second insulating liner 23 may be etched to leave second insulating patterns IL1b and IL2b between the first insulating patterns IL1a_P1 and IL2a_P1, including portions protruding from ends of the first insulating patterns IL1a_P1 and IL2a_P1 toward the second vertical through hole OV2. In one example, the top surfaces of the first insulation patterns IL1a_P1 and IL2a_P1 may be disposed at the same level as the top surfaces of the first and second gate electrode portions 130a and 130b.

[0137] 6g, the fourth horizontal tunnel layer OH4 may be formed by removing the first and second sacrificial pad layers 151 and 152. The first and second sacrificial pad layers 151 and 152 may be removed by an etching process. The etching process may include a wet etching process and / or a dry etching process.

[0138] During the process of removing the first and second sacrificial pad layers 151 and 152, the top surface of the first insulation pattern IL1a_P1 in contact with the first sacrificial pad layer 151 may be partially etched to form a first insulation pattern IL1a_P2. The top surface of the first insulation pattern IL1a_P2 may be at a lower level than the top surface of the first gate electrode portion 130a.

[0139] The first insulation pattern IL1a_P2 may be exposed through the 4-1 horizontal tunnel layer OH4a, and the first blocking layer BP1_P covering the first gate electrode portion 130a may be exposed through the 4-2 horizontal tunnel layer OH4b.

[0140] 6h, a sacrificial layer 183 may be formed to cover the side surface of the third vertical through hole OV3 and the fourth horizontal tunnel layer OH4. The sacrificial layer 183 may include a material having an etch selectivity with respect to the interlayer insulating layer 120. For example, the sacrificial layer 183 may include silicon nitride.

[0141] In one embodiment, the process of forming the sacrificial film 183 according to the surface profiles of the side surfaces of the third vertical through holes OV3 and the fourth horizontal tunnel layer OH4 may be omitted. In this case, after the process of removing the first and second sacrificial pad layers 151 and 152, the conductive liner 173 may be deposited according to the surface profiles of the third vertical through holes OV3 and the fourth horizontal tunnel layer OH4.

[0142] Referring to FIG. 6i, the first blocking layer BP1_P exposed through the sacrificial layer 183 and the fourth horizontal tunnel layer OH4 may be removed. In one example, the sacrificial layer 183 arranged according to the side surface of the third vertical through hole OV3 and the surface profile of the fourth horizontal tunnel layer OH4 may be removed by an etching process. In the process of removing the sacrificial layer 183, a portion of the top surface of the first insulation pattern IL1a_P2 may be etched to form the first insulation pattern IL1a. The top surface of the first insulation pattern IL1a may be exposed through the 5-1 horizontal tunnel layer OH5a. In one example, as the first blocking layer BP1_P exposed through the fourth horizontal tunnel layer OH4 is removed, the top surface of the first gate electrode portion 130a may be exposed through the 5-2 horizontal tunnel layer OH5b. In one example, the first barrier layer PP1 in contact with the top surface of the first blocking layer BP1_P may be removed together with the first blocking layer BP1_P. However, the present invention is not limited thereto, and the first barrier layer PP1 in contact with the top surface of the first blocking layer BP1_P may not be removed. In this case, a portion of the first barrier layer PP1 in contact with the top surface of the first blocking layer BP1_P may be removed or left through a separate process.

[0143] 6j, a conductive liner 173 may be deposited according to the surface profiles of the fourth vertical through hole OV4 and the fifth horizontal tunnel layer OH5. The conductive liner 173 may cover the top surfaces of the first gate electrode portion 130a and the first contact insulating layer 161 exposed through the fifth horizontal tunnel layer OH5. The conductive liner 173 may extend from the top surfaces of the first gate electrode portion 130a and the first contact insulating layer 161 along side surfaces of the first and second contact insulating layers 161 and 162 and the interlayer insulating layer 120.

[0144] Next, referring to FIG. 3a, a contact plug 170 may be formed by depositing a conductive material in the fourth vertical through hole OV4 and the fifth horizontal tunnel layer OH5.

[0145] 7a to 7c are cross-sectional views showing one embodiment of a method for manufacturing the semiconductor device of FIG. 4b.

[0146] 7a to 7c may be sequentially performed as a subsequent process to the process of removing the insulating structure 20 surrounding the second vertical through-hole OV2 in FIG. 6f.

[0147] 7a, a sealing pattern 163P may be deposited on the side of the second vertical through hole OV2. The sealing pattern 163P may fill the step between the first insulating patterns IL1a_P, IL2a and the second insulating patterns IL1b, IL2b exposed on the side of the second vertical through hole OV2 and the space within the uneven structure of the second contact insulating layer 162 due to the difference in etching rate during the process of removing the insulating structure 20 surrounding the second vertical through hole OV2.

[0148] 7b, a fourth horizontal tunnel layer OH4 may be formed by removing the first and second sacrificial pad layers 151 and 152. A trimming process may be performed on the sealing pattern 163P to form a sealing pattern 163 that exposes the side surfaces of the second insulating patterns IL2b and IL2b.

[0149] The first and second sacrificial pad layers 151 and 152 may be removed by an etching process. The etching process may include wet etching and / or dry etching. During the process of removing the first and second sacrificial pad layers 151 and 152, the top surface of the first insulation pattern IL1a_P in contact with the first sacrificial pad layer 151 may be partially etched to form the first insulation pattern IL1a.

[0150] A trimming process for the sealing pattern 163P can be performed to remove the side surfaces of the first and second sacrificial pad layers 151 and 152 and the sealing pattern 163P disposed on the second vertical through hole OV2 contacting the cell region insulating layer 190. The sealing pattern 163P can be partially etched horizontally on the lower surfaces of the second insulating patterns IL1b and IL2b protruding toward the third vertical through hole OV3 to expose the side surfaces of the second insulating patterns IL1b and IL2b. The side surfaces of the second insulating patterns IL1b and IL2b exposed toward the third vertical through hole OV3 and the outer surface of the sealing pattern 163 can form a flat surface at a level in the third direction (Z direction).

[0151] After removing the first and second sacrificial pad layers 151 and 152, one surface of the first blocking layer BP1_P may be exposed through the fourth horizontal tunnel layer OH4. The first blocking layer BP1 may be formed by removing the first blocking layer BP1_P exposed through the fourth horizontal tunnel layer OH4. The top surface of the first gate electrode portion 130a may be exposed by removing the first blocking layer BP1_P exposed through the fourth horizontal tunnel layer OH4. In one example, the first barrier layer PP1 in contact with the top surface of the first blocking layer BP1_P may be removed together with the first blocking layer BP1_P. However, the present invention is not limited thereto, and the first barrier layer PP1 in contact with the top surface of the first blocking layer BP1_P may not be removed.

[0152] 7c, a conductive liner 173 may be deposited according to the surface profiles of the third vertical through hole OV3 and the fourth horizontal tunnel layer OH4. The conductive liner 173 may cover the top surfaces of the first gate electrode portion 130a and the first contact insulating layer 161 exposed through the fourth horizontal tunnel layer OH4. The conductive liner 173 may extend from the top surfaces of the first gate electrode portion 130a and the first contact insulating layer 161 to side surfaces of the second insulating patterns IL1b and IL2b and the sealing pattern 163.

[0153] Next, referring to FIG. 4b, a contact plug 170 may be formed by depositing a conductive material in the third vertical through hole OV3 and the fourth horizontal tunnel layer OH4.

[0154] 8a to 8g are cross-sectional views showing an embodiment of a method for manufacturing the semiconductor device of FIG. 4c.

[0155] 8A is an enlarged view of region E of the semiconductor device of FIG. 5F according to another embodiment. Referring to FIG. 8A, an etchant may be introduced through the first vertical through hole OV1 penetrating the sacrificial insulating layer 122 and the interlayer insulating layer 120 to remove a predetermined length of the sacrificial insulating layer 122 from around the first vertical through hole OV1, thereby forming a first horizontal tunnel layer OH1′.

[0156] Referring to FIG. 8b, a first insulating liner 25 and a second insulating liner 23 may be formed in the first vertical through hole OV1 and the first horizontal tunnel layer OH1' connected to the first vertical through hole OV1.

[0157] The first insulating liner 25 and the second insulating liner 23 may be formed by sequential deposition processes to extend along the side of the first vertical through hole OV1 and within the first horizontal tunnel layer OH1'.

[0158] The first insulating liner 25 may have a uniform thickness, extend from the side of the first vertical through-hole OV1 into the first horizontal tunnel layer OH1′, and be conformally formed according to the surface profile of the first horizontal tunnel layer OH1′. The second insulating liner 23 may be deposited on the first insulating liner 25. That is, the second insulating liner 23 may be deposited to extend from the first insulating liner 25 formed on the side of the first vertical through-hole OV1 to between the first insulating liner 25 in the third horizontal tunnel layer OH3. The first insulating liner 25 may include a first insulating material, and the second insulating liner 23 may include a second insulating material different from the first insulating material.

[0159] 8c, the first and second gate electrode portions 130a and 130b may be formed by removing the sacrificial insulating layer 122. The sacrificial insulating layer 122 may be removed by a wet etching process. Before forming the first and second gate electrode portions 130a and 130b, a first blocking layer BP1_P may be deposited in the space where the first sacrificial insulating layer 122a was removed, and a second blocking layer BP2 may be deposited in the space where the second sacrificial insulating layer 122b was removed. The first blocking layer BP1_P and the second blocking layer BP2 may be conformally formed according to the inner wall surface profile of the space where the sacrificial insulating layer 122 was removed.

[0160] A first gate electrode portion 130a may be formed on the first blocking layer BP1_P, and a second gate electrode portion 130b may be formed on the second blocking layer BP2. In one example, a first barrier layer PP1 and a first conductive layer CP1 may be sequentially deposited on the first blocking layer BP1_P. A second barrier layer PP2 and a second conductive layer CP2 may be sequentially deposited on the second blocking layer BP2.

[0161] 8d, the first insulating liner 25 and the second insulating liner 23 surrounding the second vertical through hole OV2 may be removed. The second insulating liner 23 may have a slower etching rate than the first insulating liner 25. The first insulating liner 25 may be etched to leave first insulating patterns IL1a″_P, IL2a″ in the first horizontal tunnel layer OH1′, and the second insulating liner 23 may be etched to leave second insulating patterns IL1b″_P, IL2b″ formed between the first insulating patterns IL1a″_P, IL2a″ and including portions protruding from ends of the first insulating patterns IL1a″_P, IL2a″ toward the second vertical through hole OV2. In one example, the top surfaces of the first insulating patterns IL1a″_P, IL2a″ may be disposed at the same level as the top surfaces of the first and second gate electrode portions 130a, 130b. The bottom surfaces of the first insulation patterns IL1a″_P and IL2a″ may be disposed at the same level as the bottom surfaces of the first and second gate electrode portions 130a and 130b.

[0162] 8e, a sealing pattern 163_P may be deposited on the side of the second vertical through hole OV2. The sealing pattern 163_P may fill a step between the first insulating pattern IL1a″_P and the second insulating pattern IL1b″_P exposed on the side of the second vertical through hole OV2 and a space within the uneven structure of the second contact insulating layer 162″ due to a difference in etching rate during the process of removing the first insulating liner 25 and the second insulating liner 23 surrounding the second vertical through hole OV2.

[0163] 8f, the first and second sacrificial pad layers 151 and 152 may be removed to form a fourth horizontal tunnel layer OH4. A trimming process may be performed on the sealing pattern 163_P to form a sealing pattern 163 that exposes the sides of the second insulating patterns IL1b″ and IL2b″.

[0164] The first and second sacrificial pad layers 151 and 152 may be removed by an etching process. The etching process may include a wet etching process and / or a dry etching process. During the removal of the first and second sacrificial pad layers 151 and 152, an upper surface of the first insulation pattern IL1a″_P in contact with the first sacrificial pad layer 151 may be partially etched to form the first insulation pattern IL1a″. In one example, an upper surface of the second insulation pattern IL1b″_P may be partially etched to expose the upper surface of the second insulation pattern IL1b″ through the fourth horizontal tunnel layer OH4. A trimming process may be performed on the sealing pattern 163_P to remove the sealing pattern 163_P disposed on the side surfaces of the first and second sacrificial pad layers 151 and 152 and the second vertical through hole OV2 in contact with the cell region insulating layer 190. The sealing pattern 163_P disposed on the lower surfaces of the second insulation patterns IL1b″ and IL2b″ protruding toward the third vertical through hole OV3 may be partially etched in the horizontal direction to expose the side surfaces of the second insulation patterns IL1b″ and IL2b″. The side surfaces of the second insulation patterns IL1b″ and IL2b″ exposed toward the third vertical through hole OV3 and the outer surface of the sealing pattern 163 may form a flat surface in the third direction (Z direction).

[0165] The first blocking layer BP1_P exposed through the fourth horizontal tunnel layer OH4 may be removed to form a first blocking layer BP1 covering one side and a bottom surface of the first gate electrode portion 130a. The top surface of the first insulation pattern IL1a″ may be exposed through the 4-1 horizontal tunnel layer OH4a. In one example, the top surface of the first gate electrode portion 130a may be exposed by removing the first blocking layer BP1_P exposed through the fourth horizontal tunnel layer OH4.

[0166] 8g, a conductive liner 173 may be deposited according to the surface profiles of the third vertical through hole OV3 and the fourth horizontal tunnel layer OH4. The conductive liner 173 may cover the top surfaces of the first gate electrode portion 130a and the first contact insulating layer 161″ exposed through the fourth horizontal tunnel layer OH4. The conductive liner 173 may extend from the top surfaces of the first gate electrode portion 130a and the first contact insulating layer 161″ along side surfaces of the second insulating patterns IL1b″ and IL2b″ and the sealing pattern 163.

[0167] Next, referring to FIG. 4c, a contact plug 170 may be formed by depositing a conductive material in the third vertical through hole OV34 and the fourth horizontal tunnel layer OH4.

[0168] 9 and 10 are schematic cross-sectional views of a semiconductor device according to another embodiment of the present invention.

[0169] Referring to FIG. 9, in a semiconductor device 100e, the configurations of the gate structure GSe, the channel structure CHe, and the contact plug 170e may be different from those in the embodiment of FIG. 1b.

[0170] The gate structure GSe may include first and second stacked structures GS1 and GS2 stacked vertically. Each of the channel structures CHe may include first and second channel portions CH1 and CH2 penetrating the first and second stacked structures GS1 and GS2, respectively. Each of the contact plugs 170e may include first and second contact portions MC1 and MC2 stacked in the third direction (Z direction). The first and second contact portions MC1 and MC2 may penetrate the first and second stacked structures GS1 and GS2 of the gate structure GS, respectively. In this embodiment, the interface between the first contact portion MC1 and the second contact portion MC2 may be located at the same level as the interface between the first and second channel portions CH1 and CH2.

[0171] Thus, in an exemplary embodiment, the number of stacked structures constituting the gate structure GS can be varied, and accordingly, the number of portions stacked along the third direction (Z direction) in each of the channel structure CHe and the contact plug 170e can be varied.

[0172] Referring to FIG. 10, a semiconductor device 100f may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded by a wafer bonding method.

[0173] The first semiconductor structure S1 may be the same as the peripheral circuit region PERI described above with reference to FIG. 1b. However, the first semiconductor structure S1 may further include bonding structures, such as a first bonding via 297, a first bonding metal layer 298, and a first bonding insulating layer 299. The first bonding via 297 may be disposed on an uppermost circuit wiring line 280 and connected to the circuit wiring line 280. At least a portion of the first bonding metal layer 298 may be connected to the first bonding via 297 on the first bonding via 297. The first bonding metal layer 298 may be connected to the second bonding metal layer 198 of the second semiconductor structure S2. The bonding metal layer 298, together with the second bonding metal layer 198, may provide an electrical connection path by bonding the first semiconductor structure S1 and the second semiconductor structure S2. A portion of the first bonding metal layer 298 may be disposed solely for bonding and not connected to the underlying circuit wiring line 280. The first bonding via 297 and the first bonding metal layer 298 may include a conductive material, such as copper (Cu). The first bonding insulating layer 299 may be disposed around the first bonding metal layer 298. The first bonding insulating layer 299 may also function as a diffusion barrier for the first bonding metal layer 298 and may include at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0174] 1a to 1c may be applied to the second semiconductor structure S2 unless otherwise specified. The second semiconductor structure S2 may further include bonding structures, such as a second bonding via 197, a second bonding metal layer 198, and a second bonding insulating layer 199. The second semiconductor structure S2 may further include a passivation layer 106 covering the top surface of the second substrate 101.

[0175] The second bonding via 197 and the second bonding metal layer 198 may be disposed under the lowermost cell wiring line 195. The second bonding via 197 connects the cell wiring line 195 and the second bonding metal layer 198, and the second bonding metal layer 198 may be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 may be bonded to and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 197 and the second bonding metal layer 198 may include a conductive material, for example, copper (Cu). The second bonding insulating layer 199 may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN, for example.

[0176] The first and second semiconductor structures S1, S2 may be bonded by bonding the first bonding metal layer 298 to the second bonding metal layer 198 and bonding the first bonding insulating layer 299 to the second bonding insulating layer 199. The bonding between the first bonding metal layer 298 and the second bonding metal layer 198 may be, for example, copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199 may be, for example, dielectric-dielectric bonding such as SiCN-SiCN bonding. The first and second semiconductor structures S1, S2 may be bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0177] The passivation layer 106 may be disposed on the upper surface of the plate layer 101 to protect the semiconductor device 100f. The passivation layer 106 may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon carbide. The substrate insulating layer 121 may be disposed broadly in the second region R2 to cover the upper ends of the contact plugs 170. However, in an exemplary embodiment, the substrate insulating layer 121 may have various configurations as long as it electrically isolates the contact plugs 170 from the plate layer 101.

[0178] FIG. 11 is a diagram illustrating a data storage system including a semiconductor device according to an embodiment of the present invention.

[0179] 11 , an electronic system 1000 according to an exemplary embodiment of the present invention may include a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0180] The semiconductor device 1100 may be a nonvolatile memory device, such as the NAND flash memory device described above with reference to FIGS. 1a to 1c. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0181] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary depending on the embodiment.

[0182] In an exemplary embodiment, the upper transistors UT1 and UT2 may comprise string select transistors, and the lower transistors LT1 and LT2 may comprise ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0183] In an exemplary embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation that erases data stored in the memory cell transistor MCT using a gate-induced drain leakage (GIDL) phenomenon.

[0184] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 via a first connecting line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 via a second connecting line 1125 extending from the first structure 1100F to the second structure 1100S.

[0185] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by a logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending from within the first structure 1100F to the second structure 1100S.

[0186] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the electronic system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 may control the multiple semiconductor devices 1100.

[0187] The processor 1210 may control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a controller interface 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. may be transmitted via the controller interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0188] FIG. 12 is a perspective view that schematically illustrates a data storage system including a semiconductor device according to an embodiment of the present invention.

[0189] 12, an electronic system 2000 according to an exemplary embodiment of the present invention may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0190] The main board 2001 may include a connector 2006 including a plurality of pins to be coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on a communication interface between the electronic system 2000 and the external host. In an exemplary embodiment, the electronic system 2000 may communicate with the external host according to any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0191] The controller 2002 can write data to or read data from the semiconductor package 2003, which can improve the operating speed of the electronic system 2000.

[0192] The DRAM 2004 may be a buffer memory for mitigating the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a type of cache memory and provide space for temporarily storing data in control operations for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0193] The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each of the semiconductor chips 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0194] The package substrate 2100 may be a printed circuit board including package upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to the input / output pad 1101 in FIG. 11. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include the semiconductor device described above with reference to FIGS. 1a to 1c.

[0195] In an exemplary embodiment, the connecting structure 2400 may be a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV), instead of the connecting structure 2400 using a bonding wire method.

[0196] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate other than the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0197] FIG. 13 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present invention.

[0198] FIG. 13 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 12, and conceptually illustrates a region obtained by cutting the semiconductor package 2003 of FIG. 12 along cutting line III-III'.

[0199] 13, in a semiconductor package 2003, a package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, package upper pads (2130 in FIG. 12) disposed on an upper surface of the package substrate body 2120, lower pads 2125 disposed on a lower surface of the package substrate body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The upper pads 2130 may be electrically connected to a connecting structure 2400. The lower pads 2125 may be connected to a wiring pattern 2005 of a main board 2001 of an electronic system 2000 via a conductive connecting portion 2800, as shown in FIG. 12.

[0200] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a contact plug (contact plug 170 in FIG. 1b) electrically connected to a word line (gate electrode 130 in FIG. 1a) of the gate stack structure 3210. The first semiconductor structure 3100 may further include a contact insulating layer 160, as shown in an enlarged view. The contact insulating layer 160 may include a first contact insulating layer 161 disposed between the gate contact region 130P and the vertical extension 170V of the contact plug 170, and a second contact insulating layer 162 disposed between the gate stack region 130G below the gate contact region 130P and the vertical extension 170V. The contact plug 170 may include the vertical extension 170V penetrating the gate electrode 130 and the interlayer insulating layer 120, and a horizontal extension 170H extending from the vertical extension 170V to contact the first contact insulating layer 161 and the gate contact region 130P.

[0201] Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may be disposed outside the gate stack structure 3210 and may further be disposed to penetrate the gate stack structure 3210. Each of the semiconductor chips 2200 may further include an input / output pad (2210 in FIG. 2) electrically connected to the peripheral wiring 3110 of the first structure 3100.

[0202] Although the present invention has been described above with reference to an embodiment thereof, those skilled in the art will understand that various modifications and variations of the present invention are possible without departing from the spirit and scope of the present invention as set forth in the claims. [Explanation of symbols]

[0203] PERI Peripheral circuit area 201 First board 220 Circuit Elements CELL Memory cell area 101 Second board 130 gate electrode 130P gate contact area 130G gate stack area 130a first gate electrode portion 130b second gate electrode portion 160 Contact insulating layer 161 First contact insulating layer 161V, 162V Void 162 Second contact insulating layer 163 Sealing Pattern 170 Contact plug 170V Vertical Extension 170H horizontal extension 173 Conductive Liner

Claims

1. a first semiconductor structure including a substrate, a circuit element on the substrate, and a circuit wiring on the circuit element; a second semiconductor structure disposed on the first semiconductor structure, the second semiconductor structure having a first region and a second region; The second semiconductor structure is a plate layer; gate electrodes stacked on the plate layer in a direction perpendicular to an upper surface of the plate layer and spaced apart from each other, extending on the second region in a first direction intersecting the perpendicular direction with different lengths, each including a gate contact region; interlayer insulating layers arranged alternately with the gate electrodes; a channel structure extending along the vertical direction and penetrating the gate electrode and the interlayer insulating layer in the first region; contact plugs that penetrate the gate electrode in the second region, extend along the perpendicular direction, and electrically connect the gate electrode to a portion of the circuit wiring; contact insulating layers, which are alternately arranged with the interlayer insulating layers, surround the contact plug, and include a first contact insulating layer arranged between the gate contact region and the contact plug; Each of the contact plugs comprises: a vertical extension portion extending along the vertical direction; a horizontal extension extending horizontally from the vertical extension and overlapping the gate contact region and the first contact insulating layer in the vertical direction; a conductive liner extending between the horizontal extension and the first contact insulating layer, between the horizontal extension and the gate contact region. Semiconductor device.

2. the contact plug includes the same first conductive material as the gate electrode; The semiconductor device of claim 1 , wherein the conductive liner comprises a second conductive material different from the first conductive material.

3. 2. The semiconductor device according to claim 1, wherein an upper surface of said gate contact region is disposed at a higher level than an upper surface of each of said first contact insulating layers.

4. 2. The semiconductor device according to claim 1, wherein a height of a first portion of said horizontal extension overlapping said gate contact region is lower than a height of a second portion of said horizontal extension overlapping said first contact insulating layer.

5. the contact insulating layer further includes a second contact insulating layer surrounding the contact plug below the gate contact region; The semiconductor device according to claim 1 , wherein the height of each of said second contact insulating layers is greater than the height of each of said first contact insulating layers.

6. the gate electrode further includes a gate stack region in contact with the second contact insulating layer; The semiconductor device according to claim 5 , wherein the height of said gate stack region is greater than the height of said gate contact region.

7. a sealing pattern extending from the contact insulating layer and disposed between the interlayer insulating layer and the vertical extension; The semiconductor device of claim 1 , wherein the sealing pattern comprises silicon nitride.

8. 8. The semiconductor device according to claim 7, wherein the conductive liner extends between the contact insulating layer and the vertical extension and between the sealing pattern and the vertical extension.

9. Each of the contact insulating layers includes a first insulating pattern and a second insulating pattern partially surrounded by the first insulating pattern; the first insulating pattern includes silicon oxide; The semiconductor device of claim 1 , wherein the second insulating pattern comprises silicon nitride.

10. 10. The semiconductor device of claim 9, wherein a first thickness of the first insulating pattern of the first contact insulating layer on an upper surface of the second insulating pattern of the first contact insulating layer is smaller than a second thickness of the first insulating pattern of the first contact insulating layer on a lower surface of the second insulating pattern of the first contact insulating layer.

11. The semiconductor device of claim 9 , wherein the second insulating pattern includes a first void and a second void spaced apart from the first void in the first direction.

12. The semiconductor device according to claim 11 , wherein the length of the first void in the first direction is greater than the length of the second void in the first direction.

13. 12. The semiconductor device of claim 11, wherein each of the first insulating pattern and the second insulating pattern includes a flat portion extending in the horizontal direction and a protruding portion extending from the flat portion, disposed between the flat portion and the vertical extension portion, and protruding toward the interlayer insulating layer.

14. The semiconductor device according to claim 13 , wherein the protrusion is disposed between the first void and the second void.

15. a stacked pattern having a memory cell array region and a staircase region; a stacked structure extending from the memory cell array region to the staircase region on the stacked pattern, the stacked structure including interlayer insulating layers and gate electrodes alternately arranged in a vertical direction, the gate electrodes including gate contact pads arranged in a staircase pattern on the staircase region; a channel structure extending vertically through the stacked structure in the memory cell array region; a contact plug penetrating the gate electrode and the interlayer insulating layer in the step region; contact insulating layers alternately arranged with the interlayer insulating layers and surrounding the contact plugs; the contact insulating layer includes a first contact insulating layer disposed between the gate contact pad and the contact plug, and a second contact insulating layer disposed alternately with the interlayer insulating layer below the gate contact pad and surrounding the contact plug; each of the contact plugs includes a vertical extension extending in the vertical direction and a horizontal extension extending horizontally from the vertical extension and contacting the first contact insulating layer and the gate contact pad, a height of each of the first contact insulating layers being lower than a height of each of the second contact insulating layers;

16. the interlayer insulating layer includes a first interlayer insulating layer disposed below the first contact insulating layer and a second interlayer insulating layer disposed below the second contact insulating layer; each of the first contact insulating layers includes a first flat portion and a first protruding portion extending from the first flat portion and protruding toward the first interlayer insulating layer; 16. The semiconductor device according to claim 15, wherein each of the second contact insulating layers includes a second flat portion and a second protruding portion extending from the second flat portion and protruding toward the first interlayer insulating layer and the second interlayer insulating layer.

17. each of the interlayer insulating layers includes a first insulating pattern and a second insulating pattern including a first portion partially surrounded by the first insulating pattern and a second portion extending from the first portion and protruding toward the vertical extension; the first insulating pattern includes a first insulating material; The semiconductor device of claim 15 , wherein the second insulating pattern comprises a second insulating material different from the first insulating material.

18. a sealing pattern extending from the second portion of the second insulating pattern to between the interlayer insulating layer and the vertical extension; The semiconductor device of claim 17 , wherein each of the contact plugs further comprises a conductive liner covering an upper surface of the gate contact pad, an upper surface of the first contact insulating layer, and an outer surface of the sealing pattern.

19. 1. A data storage system comprising: a semiconductor memory device including a first semiconductor structure including a circuit element and circuit wiring electrically connected to the circuit element; a second semiconductor structure disposed on one surface of the first semiconductor structure and including a first region and a second region; and an input / output pad electrically connected to the circuit element; a controller electrically connected to the semiconductor memory device via the input / output pad and controlling the semiconductor memory device; The second semiconductor structure is a plate layer; gate electrodes stacked on the plate layer in a direction perpendicular to an upper surface of the plate layer and spaced apart from each other, extending on the second region in a first direction intersecting the perpendicular direction with different lengths, each including a gate contact region; an interlayer insulating layer alternately arranged with the gate electrodes; a channel structure extending along the vertical direction and penetrating the gate electrode and the interlayer insulating layer in the first region; contact plugs extending along the perpendicular direction through the gate contact regions of the gate electrodes in the second region and electrically connecting the gate electrodes to portions of the circuit wiring; a first contact insulating layer that is alternately disposed with the interlayer insulating layer between the gate contact region and the contact plug and surrounds the contact plug; a second contact insulating layer disposed alternately with the interlayer insulating layer below the gate contact region and surrounding the contact plug; A data storage system, wherein each of the contact plugs includes a vertical extension extending along the vertical direction, a horizontal extension extending horizontally from the vertical extension and overlapping the respective first contact insulating layer and the gate contact region, and a conductive liner disposed between the horizontal extension and the gate contact region and extending between the horizontal extension and the first contact insulating layer.

20. 20. The data storage system of claim 19, wherein the conductive liner extends between the first and second contact insulating layers and the vertical extension, and between the interlayer insulating layer and the vertical extension.

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