Storage device

Abstract

To provide a semiconductor device with less variation in transistor characteristic.SOLUTION: A transistor includes an oxide semiconductor film, a source electrode and a drain electrode on the oxide semiconductor film, an interlayer insulating film disposed covering the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode on the oxide semiconductor film. The interlayer insulating film has an opening formed overlapping with a region between the source electrode and the drain electrode. The gate electrode is disposed in the opening of the interlayer insulating film. The source electrode and the drain electrode are formed of a conductive film with a compression stress.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed significantly, especially in LSIs, CPUs, and memories. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in a non-conducting state. For example, a low-power CPU utilizing the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 1). Also, for example, a memory device capable of retaining stored data for a long period of time utilizing the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in semiconductor devices including integrated circuits. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a transistor including an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film arranged to cover the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode over the oxide semiconductor film, wherein an opening is formed in the interlayer insulating film so as to overlap a region between the source electrode and the drain electrode, the gate electrode is arranged in the opening of the interlayer insulating film, and the source electrode and the drain electrode have compressive stress.

[0013] Another embodiment of the present invention is a transistor including an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, a barrier insulating film arranged to cover the oxide semiconductor film, the source electrode, and the drain electrode, an interlayer insulating film over the barrier insulating film, a gate insulating film over the oxide semiconductor film, and a gate electrode over the gate insulating film, wherein openings are formed in the barrier insulating film and the interlayer insulating film to overlap with regions between the source electrode and the drain electrode, the gate insulating film and the gate electrode are arranged in the openings of the interlayer insulating film, the barrier insulating film contains silicon nitride, the source electrode and the drain electrode have compressive stress, and the oxide semiconductor film has a first region overlapping with the source electrode or the drain electrode that has a lower density than a second region overlapping with the gate electrode.

[0014] In the above, the first region preferably has a higher hydrogen concentration than the second region.

[0015] In the above, the magnitude of the compressive stress is preferably 1000 MPa or more. Also, in the above, the source electrode and the drain electrode are preferably made of a nitride containing tantalum. Also, in the above, it is preferable that the source electrode and the drain electrode are formed by sputtering.

[0016] In the above, the oxide semiconductor film preferably contains one or more selected from In, Ga, and Zn.

[0017] Another embodiment of the present invention is an electronic device including any of the above transistors. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0020] [Figure 1] 1A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 3] Fig. 3A is a diagram showing a calculation model shown in this embodiment, and Fig. 3B is a diagram showing calculation results shown in this embodiment. [Figure 4] Figure 4A is a diagram explaining the classification of IGZO crystal structures, Figure 4B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 4C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 5] 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6]6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 16 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 17] FIG. 17 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 18] FIG. 18 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 19] 19A and 19B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 21] FIG. 21 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 22] FIG. 22 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A and 23B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 24 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 25] FIG. 25 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 26A is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention, and FIG. 26B is a schematic diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 27] 27A to 27H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 28] FIG. 28A is a block diagram of a semiconductor device according to one embodiment of the present invention, and FIG. 28B is a schematic diagram of the semiconductor device according to one embodiment of the present invention. [Figure 29] 29A and 29B are diagrams illustrating an example of an electronic component. [Figure 30] 30A to 30E are schematic diagrams of a memory device that is one embodiment of the present invention. [Figure 31] 31A to 31H illustrate electronic devices according to embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0022] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals may be used in common between different drawings for identical parts or parts having similar functions, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0023] In order to make the invention easier to understand, particularly in top views (also called "plan views") or perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0024] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0025] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0026] Furthermore, when it is explicitly stated in this specification that X and Y are connected, it is understood that the present specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0028] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms source and drain may be used interchangeably in this specification and the like.

[0029] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0031] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0032] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0033] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0034] Note that impurities in a semiconductor refer to, for example, anything other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0035] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. For example, silicon oxynitride is a material whose composition contains more oxygen than nitrogen. Furthermore, a nitride oxide is a material whose composition contains more nitrogen than oxygen. For example, silicon nitride oxide is a material whose composition contains more nitrogen than oxygen.

[0036] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0037] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0038] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0039] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0040] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0041] <Configuration example of semiconductor device> The structure of a semiconductor device including a transistor 200 will be described with reference to FIGS. 1A to 1D. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0042] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, and an insulator 285 over the insulator 283. The insulators 212, 214, 280, 282, 283, and 285 function as interlayer insulating films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 200 and functioning as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug. In addition, on the insulator 285 and the conductor 240, a conductor 246 (conductor 246a and conductor 246b) is provided, which is electrically connected to the conductor 240 and functions as wiring.

[0043] Insulator 241a is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 285. A first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inward. Insulator 241b is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 285. A first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inward. Here, the height of the top surface of conductor 240 and the height of the top surface of insulator 285 in the region overlapping with conductor 246 can be made approximately the same. Note that, although the transistor 200 illustrates a configuration in which the first conductor of conductor 240 and the second conductor of conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured to have a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, the layers may be distinguished by assigning ordinal numbers to indicate the order of formation.

[0044] [Transistor 200] As shown in FIGS. 1A to 1D, the transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductors 205a, 205b, and 205c) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxide 243a and oxide 243b) on the oxide 230b, a conductor 242a on the oxide 243a, and a conductor 242a on the oxide 243a. The oxide 243b has an insulator 271a on the oxide 243b, a conductor 242b on the oxide 243b, an insulator 271b on the conductor 242b, an insulator 250 (insulator 250a and insulator 250b) on the oxide 230b, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping with part of the oxide 230b, and an insulator 275 arranged to cover the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 271a, and the insulator 271b.

[0045] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. The conductor 242a and the conductor 242b may be collectively referred to as the conductor 242. The insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0046] Openings that reach the oxide 230b are provided in the insulator 280 and the insulator 275. The insulator 250 and the conductor 260 are disposed in the openings. In addition, in the channel length direction of the transistor 200, the conductor 260 and the insulator 250 are provided between the insulator 271a, the conductor 242a, and the oxide 243a and the insulator 271b, the conductor 242b, and the oxide 243b. The insulator 250 has a region that contacts the side surface of the conductor 260 and a region that contacts the bottom surface of the conductor 260.

[0047] The oxide 230 preferably has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0048] Note that in the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230b may have a single layer or a stacked structure of three or more layers, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0049] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulating film, and the insulators 224 and 222 function as a second gate insulating film. The conductor 242a functions as one of a source electrode and a drain electrode, and the conductor 242b functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0050] FIG. 2 shows an enlarged view of the vicinity of the channel formation region in FIG. 1B. As shown in FIG. 2, the oxide 230b includes a region 230bc that functions as a channel formation region of the transistor 200, and a pair of regions 230ba and 230bb that are provided on either side of the region 230bc and function as a source region or a drain region. The region 230bc at least partially overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the pair of conductors 242a and 242b. The region 230ba is provided overlapping with the conductor 242a, and the region 230bb is provided overlapping with the conductor 242b.

[0051] The region 230bc, which functions as a channel formation region, has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a low carrier concentration. The regions 230ba and 230bb, which function as a source region or drain region, have many oxygen vacancies or high impurity concentrations such as hydrogen, nitrogen, and metal elements, which increases the carrier concentration and reduces the resistance. In other words, the regions 230ba and 230bb have a higher carrier concentration and lower resistance than the region 230bc.

[0052] Here, the carrier concentration of the region 230bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm-3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0053] The carrier concentration of the regions 230ba and 230bb that function as source and drain regions is, for example, 1×10 17 cm -3 It is preferable that the concentration is 1×10 or more. 18 cm -3 More preferably, it is 1×10 or more. 19 cm -3 The upper limit of the carrier concentration of the regions 230ba and 230bb that function as source and drain regions is not particularly limited, but may be, for example, 1×10 21 cm -3 It can be said that:

[0054] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, in which the carrier concentration is equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. That is, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. The junction region may also have oxygen vacancies equal to or lower than those of region 230ba and region 230bb, and equal to or higher than those of region 230bc.

[0055] 2 shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0056] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in regions closer to the channel formation region.

[0057] In the transistor 200, the oxide 230 including the channel formation region (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0058] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0059] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0060] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0061] In this way, by disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0062] Furthermore, since the oxide 230a and the oxide 230b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Because the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0063] The oxide 230b preferably has crystallinity, and it is particularly preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0064] CAAC-OS has a highly crystalline and dense structure and is free of impurities or defects (e.g., oxygen vacancies (V O ) and the like. In particular, by subjecting the formed metal oxide to heat treatment at a temperature (e.g., 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize, the CAAC-OS can be made to have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0065] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0066] In a transistor using an oxide semiconductor, if impurities or oxygen vacancies exist in a channel formation region of the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancies is formed as a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0067] On the other hand, the source and drain regions in the oxide semiconductor preferably have a high carrier concentration and are n-type. Therefore, the source and drain regions in the oxide semiconductor preferably have V O However, V contained in the source region and the drain region is preferably contained. O The diffusion of H into the channel formation region must be suppressed. For this reason, V contained in the source region and the drain region O It is preferable that H is stable. In particular, V contained in the source and drain regions O Variations in H within the substrate surface result in variations in the characteristics of semiconductor devices having transistors.

[0068] That is, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type. On the other hand, the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. The i-type or substantially i-type region 230bc and the n-type regions 230ba and 230bb are preferably stable.

[0069] Therefore, in this embodiment, a strain that expands in the tensile direction (hereinafter, sometimes referred to as tensile strain) is formed in the region 230ba and the region 230bb by forming the source electrode and the drain electrode using a conductive film having compressive stress. O By forming H stably, the regions 230ba and 230bb can be stable n-type regions. Furthermore, by forming tensile strain in the regions 230ba and 230bb, the region 230bc is compressed to form a dense structure, and the strain in the region 230bc is reduced in the compressive direction (hereinafter, such strain may be referred to as compressive strain), which can suppress hydrogen diffusion into the strain. This allows the region 230bc to be a stable i-type region.

[0070] The stress of the conductor 242 and the strain formed in the oxide 230b will be described below with reference to FIG.

[0071] As shown in FIG. 2, the conductor 242a has a stress 20a, and the conductor 242b has a stress 20b. Hereinafter, the stresses 20a and 20b may be collectively referred to as stress 20. The stress 20a is a compressive stress having a vector directed from the center to the end of the conductor 242a (a stress that attempts to relax the compressed shape of the conductor 242a). Similarly, the stress 20b is a compressive stress having a vector directed from the center to the end of the conductor 242b. The magnitudes of the stresses 20a and 20b may be sufficient to form the strains 30a and 30b described below. For example, the magnitudes of the stresses 20a and 20b may be 1000 MPa or more, preferably 1500 MPa or more, and more preferably 2000 MPa or more. The magnitudes of the stresses 20a and 20b may be determined by measuring the stress of a sample prepared by depositing a film similar to the conductor 242 on a substrate.

[0072] The stress 20 causes a strain 30a to be formed in the region 230ba, and a strain 30b to be formed in the region 230bb. Here, the strains 30a and 30b are strains (tensile strains) that are expanded in the tensile direction by the action of the stress 20. The strains 30a and 30b contain oxygen vacancies V. O , and V O H is formed. Also, distortions in the crystal lattice arrangement, which will be described later, are formed. In the distortions 30a and 30b, V O and V O H is easily formed and these easily take a stable structure, so that the regions 230ba and 230bb become stable n-type regions with high carrier concentrations.

[0073] Furthermore, the region 230bc is compressed from both sides by forming strains in the tensile direction in the regions 230ba and 230bb, and the region 230bc has a dense structure. As a result, the region 230bc is formed with strains 30c that are contracted in the compression direction. Since the strain 30c is a compressive strain, V O and V O In addition, hydrogen is less likely to diffuse into the strain 30c, so a stable i-type region can be formed.

[0074] A conductive film having tensile stress may be used for the conductor 260. The tensile stress acts on the region 230bc as an external force in a compressive direction, so that the region 230bc can have a denser structure.

[0075] Here, the density of strain 30a and strain 30b is low because the interatomic distance of the elements constituting oxide 230b is large. In contrast, the density of strain 30c is high because the interatomic distance of the elements constituting oxide 230b is small. Therefore, the density of region 230ba (region 230bb) where much strain 30a (strain 30b) is formed is lower than that of region 230bc where strain 30c is formed.

[0076] Although the strain formed in the oxide 230b has been described above, the present invention is not limited to this.Similar strains 30a to 30c may be formed in the oxide 230a.

[0077] <V in strain in metal oxides O , and V O Ease of H formation> In this section, we consider the V O , and V O The ease of H formation is evaluated using calculations. Specifically, using first-principles calculations, V O The formation energy of V O Calculate the formation energy of H.

[0078] <<Calculation model>> Here, the calculation model used in the first-principles calculation will be explained.

[0079] As a calculation model for strain in metal oxides, we prepared a model of amorphous In-Ga-Zn oxide. Hereafter, this model of amorphous In-Ga-Zn oxide will be referred to as the a-IGZO model. The a-IGZO model was created using the melt-quench method.

[0080] The composition of the a-IGZO model is In:Ga:Zn:O=1:1:1:4 [atomic ratio]. The a-IGZO model is composed of 84 atoms. Three types of a-IGZO models with different densities were prepared, each with a density of 5.6 g / cm. 3 , 5.8g / cm 3 , 6.0g / cm 3 Here, 5.6 g / cm 3 The a-IGZO model is a model in which tensile strain is formed in a metal oxide, and the strain is 6.0 g / cm 3 The a-IGZO model is a model in which compressive strain is formed in a metal oxide.

[0081] Next, one oxygen atom is replaced with one hydrogen atom in each of the a-IGZO models. After the replacement, each of the a-IGZO models has a V O H. In the following, the model is called V O This is sometimes called the a-IGZO model containing H. Here, V O The a-IGZO model including H is shown in Figure 3A. The model shown in Figure 3A is V O This is an example of an a-IGZO model containing H. The a-IGZO model has 48 oxygen atoms, so for each density of the a-IGZO model, V O There will be 48 a-IGZO models available, including H.

[0082] Next, one oxygen atom is removed from each of the a-IGZO models. After the removal, each of the a-IGZO models has a V O In the following, this model is called V O It is sometimes called an a-IGZO model that includes V O a-IGZO models including V O As with the a-IGZO model containing H, V O There will be 48 a-IGZO models available, including:

[0083] This concludes the explanation of the calculation model.

[0084] <<Calculation conditions>> Next, the calculation conditions for the first-principles calculation will be described.

[0085] The first-principles calculations were performed using the first-principles electronic structure calculation package VASP. The calculation conditions are shown in Table 1.

[0086] [Table 1]

[0087] The electronic state pseudopotential was generated by the PAW method, and the functional was GGA / PBE. The k-point grid was set to 1×1×1.

[0088] Under the above calculation conditions, for the a-IGZO model with each density, V O The formation energy of H and V O The formation energy of and were calculated.

[0089] V O The formation energy of H is calculated using the following equation (1):

[0090]

number

[0091] Here, E(IGZO) is the total energy of the a-IGZO model. O H) is V O The total energy of the a-IGZO model including H is shown in Fig. 1. Note that V O The formation energy of H is 48 E(IGZO:V O H) are average values.

[0092] Also, μ O is the chemical potential of oxygen, calculated using half the energy of an oxygen molecule.H is the chemical potential of hydrogen, calculated using half the energy of a hydrogen molecule.

[0093] V O The formation energy of is calculated using the following equation (2):

[0094]

number

[0095] Here, E(IGZO:V O ) is V O The total energy of the a-IGZO model including V O The formation energy of IGZO:V is 48 times larger than that of E(IGZO:V O ) is the average value.

[0096] Using the above formula, V O The formation energy of H and V O The calculated results of the formation energy of and are shown in Figure 3B. The horizontal axis of Figure 3B shows the film density [g / cm 3 ] and the vertical axis is the formation energy [eV].

[0097] As shown in Figure 3B, V O The formation energy of H, and V O A positive correlation was observed between the formation energy of V and the film density of each calculation model. O A significant positive correlation was observed between the formation energy of H and the film density of each calculation model.

[0098] From this calculation result, when tensile strain is formed in the metal oxide, V O H, and V O The formation energy of V is low. O H, and V O In addition, when compressive strain is formed in the metal oxide, V O H, and V OThe formation energy of V is high. O H, and V O It was shown that the formation of

[0099] Therefore, as in the transistor described in this embodiment, tensile strain is formed in the source and drain regions of the oxide semiconductor film by the source and drain electrodes having compressive stress, and V O H, and V O This suggests that stable n-type regions can be formed in the source and drain regions of the oxide semiconductor film in the transistor described in this embodiment.

[0100] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0101] 1 and other figures, the side of the opening into which the conductor 260 and the like are embedded, including the groove in the oxide 230b, is generally perpendicular to the surface on which the oxide 230b is to be formed, but this embodiment is not limited to this. For example, the bottom of the opening may be gently curved, i.e., U-shaped. Also, for example, the side of the opening may be inclined relative to the surface on which the oxide 230b is to be formed.

[0102] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (also referred to as rounded).

[0103] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 230b with the insulator 250 and the conductor 260.

[0104] The oxide 230 preferably has a stacked structure of multiple oxides with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0105] The oxide 230b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), a highly crystalline, and a dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 230b. This reduces the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0106] Here, the conduction band minimum changes gradually at the junction between the oxide 230a and the oxide 230b. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0107] Specifically, when the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0108] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0109] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0110] By configuring the oxide 230a and the oxide 230b as described above, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, which reduces the influence of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0111] At least one of the insulators 212, 214, 271, 275, 282, and 283 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 275, 282, and 283 is preferably an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., through which the above oxygen is less likely to permeate).

[0112] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing (also referred to as gettering) a corresponding substance.

[0113] For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used for the insulators 212, 214, 271, 275, 282, and 283. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulators 212, 275, and 283. Furthermore, for example, aluminum oxide or magnesium oxide, which has a high ability to capture and fix hydrogen, is preferably used for the insulators 214, 271, and 282. This can prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it can prevent impurities such as water and hydrogen from diffusing from an interlayer insulating film disposed outside the insulator 283 to the transistor 200 side. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing toward the substrate side through the insulators 212 and 214. Alternatively, oxygen contained in the insulator 280 or the like can be prevented from diffusing upward from the transistor 200 through the insulator 282 or the like. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 275, 282, and 283, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0114] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 271, 275, 282, and 283. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured that have excellent characteristics.

[0115] Note that the insulators 212, 214, 271, 275, 282, and 283 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 212, 214, 271, 275, 282, and 283 may also have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0116] The insulators 212, 214, 271, 275, 282, and 283 may be deposited by, for example, sputtering. Sputtering does not require the use of hydrogen as a deposition gas, and therefore can reduce the hydrogen concentration of the insulators 212, 214, 271, 275, 282, and 283. Note that the deposition method is not limited to sputtering, and other methods such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD) may also be used as appropriate.

[0117] It may also be preferable to reduce the resistivity of the insulators 212 and 283. For example, it is preferable to reduce the resistivity of the insulators 212 and 283 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 212 and the insulator 283 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 during treatment using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212 and the insulator 283 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0118] Furthermore, the insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer insulating film can reduce parasitic capacitance between wirings. For example, the insulators 216 and 280 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like, as appropriate.

[0119] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be embedded in an opening formed in the insulator 216. Note that a portion of the conductor 205 may be provided so as to be embedded in the insulator 214.

[0120] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the top surface of the conductor 205b is lower than the top surface of the conductor 205a and the top surface of the insulator 216. The conductor 205c is provided in contact with the top surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the top surface of the conductor 205c is approximately the same as the height of the top of the conductor 205a and the height of the top surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0121] Here, the conductors 205a and 205c are preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0122] By using a conductive material that reduces hydrogen diffusion for the conductors 205a and 205c, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material that suppresses oxygen diffusion for the conductors 205a and 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductors 205a and 205c may be formed as a single layer or a multilayer structure using the above conductive materials. For example, the conductors 205a and 205c may be made of titanium nitride.

[0123] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0124] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current compared to when no potential is applied to the conductor 205. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to when no potential is applied.

[0125] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0126] As shown in FIG. 1A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to areas outside the ends of the oxides 230a and 230b that intersect with the channel width direction. In other words, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator outside the side surfaces of the oxide 230 in the channel width direction. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0127] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0128] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0129] Note that, in the transistor 200, the conductor 205 has a stacked structure of conductors 205a, 205b, and 205c, but the present invention is not limited to this. For example, the conductor 205 may have a single-layer, two-layer, or four or more-layer structure. For example, the conductor 205 may have a two-layer structure of conductors 205a and 205b.

[0130] The insulators 222 and 224 function as gate insulating films.

[0131] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0132] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 and the oxide 230.

[0133] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0134] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0135] Silicon oxide, silicon oxynitride, or the like can be used as the insulator 224. By providing the insulator 224 containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0136] Furthermore, the insulator 224 in contact with the oxide 230 may contain excess oxygen (desorbing oxygen when heated). Oxides that desorb oxygen when heated are oxides in which the amount of desorbed oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0137] Furthermore, it is preferable that the insulator 224 is processed into an island shape so as to overlap with the oxide 230a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the upper surface of the insulator 222. This allows the insulator 224 and the insulator 280 to be separated by the insulator 275, thereby preventing oxygen contained in the insulator 280 from diffusing into the insulator 224 and causing an excess of oxygen in the insulator 224.

[0138] In addition, during the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100°C or higher and 600°C or lower, more preferably 350°C or higher and 550°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0139] By subjecting the oxide 230 to oxygen addition treatment, oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 230 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0140] The insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be stacked structures made of different materials. While FIG. 1B and other figures show a configuration in which the insulator 224 is formed in an island shape by overlapping with the oxide 230a, the present invention is not limited to this. As long as the amount of oxygen contained in the insulator 224 can be appropriately adjusted, the insulator 224 may be configured without being patterned, similar to the insulator 222.

[0141] An oxide 243a and an oxide 243b are provided on the oxide 230b. The oxide 243a and the oxide 243b are provided to be spaced apart with the conductor 260 interposed therebetween.

[0142] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243, which has a function of suppressing oxygen permeation, between the conductor 242 functioning as a source or drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. This structure can improve the electrical characteristics and reliability of the transistor 200. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0143] A metal oxide containing element M may be used as oxide 243. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 243 has a higher concentration of element M than oxide 230b. Alternatively, oxide 243 may be gallium oxide. Alternatively, oxide 243 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, the film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Furthermore, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, oxygen release from oxide 230 can be effectively suppressed. For example, oxide 243 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 230.

[0144] The conductor 242a is preferably provided in contact with the top surface of the oxide 243a, and the conductor 242b is preferably provided in contact with the top surface of the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0145] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0146] Here, it is preferable to use a film with a large compressive stress as the conductor 242, for example, a tantalum nitride film formed by sputtering. The stress of the conductor 242 causes distortion in the crystal structure of the regions 230ba and 230bb, which causes oxygen vacancies V in these regions. O As a result, V generated in the region 230ba and the region 230bb O Since the amount of H increases, the carrier concentration in the regions 230ba and 230bb can be increased to make them n-type.

[0147] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0148] Preferably, no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By forming the conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction can be increased, as shown in FIG. 1D. This increases the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0149] The insulator 271a is provided in contact with the top surface of the conductor 242a, and the insulator 271b is provided in contact with the top surface of the conductor 242b. The insulator 271 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 271 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 271 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a transistor 200 and a semiconductor device with excellent characteristics and high reliability.

[0150] The insulator 271 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. In this case, the insulator 271 may be, for example, a nitride containing silicon, such as silicon nitride.

[0151] The insulator 275 is provided in contact with the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243, the side surface of the conductor 242, and the side surface and top surface of the insulator 271. The insulator 275 has openings formed in the regions where the insulator 250 and the conductor 260 are provided.

[0152] The insulator 275 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 275 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen, and preferably has a function of capturing impurities such as hydrogen. The insulator 275 may be, for example, a single layer or a stack of insulators such as aluminum oxide or silicon nitride. For example, an amorphous aluminum oxide film may be provided, and a silicon nitride film may be stacked thereon.

[0153] Furthermore, by providing insulators 214, 271, and 275, which have the function of capturing impurities such as hydrogen, in the region sandwiched between insulators 212 and 275, impurities such as hydrogen contained in insulator 224 or insulator 216 can be captured, and the amount of hydrogen in the region can be kept constant. In this case, it is preferable that insulator 275 contains aluminum oxide with an amorphous structure.

[0154] The insulator 250 has an insulator 250a and an insulator 250b on the insulator 250a, and functions as a gate insulating film. The insulator 250a is preferably disposed in contact with the top surface of the oxide 230b, the side surface of the oxide 243, the side surface of the conductor 242, the side surface of the insulator 271, the side surface of the insulator 275, and the side surface of the insulator 280. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0155] The insulator 250a can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, etc. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0156] As with the insulator 224, the insulator 250a preferably has a reduced concentration of impurities such as water and hydrogen.

[0157] Preferably, the insulator 250a is formed using an insulator that releases oxygen when heated, and the insulator 250b is formed using an insulator that has a function of suppressing oxygen diffusion. With this structure, it is possible to suppress the oxygen contained in the insulator 250a from diffusing into the conductor 260. In other words, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. It is also possible to suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250b can be formed using the same material as the insulator 222.

[0158] When silicon oxide or silicon oxynitride is used for the insulator 250a, the insulator 250b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a stacked structure of the insulators 250a and 250b, a thermally stable stacked structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

[0159] Specifically, the insulator 250b may be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). The thickness of the insulator 250b is preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 1.5 nm or less.

[0160] 1B and 1C, the insulator 250 is illustrated as having a two-layer laminated structure, but the present invention is not limited to this. The insulator 250 may have a single layer or a laminated structure of three or more layers.

[0161] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0162] The metal oxide may function as part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 may be used as the metal oxide. In this case, the electrical conductor 260a may be formed by sputtering to reduce the electrical resistance of the metal oxide, thereby making it a conductor. This may be called an OC (Oxide Conductor) electrode.

[0163] The inclusion of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0164] The conductor 260 is provided on the insulator 250b and functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 1B and 1C, the top surface of the conductor 260 is substantially flush with the top of the insulator 250. Although the conductor 260 is shown in FIGS. 1B and 1C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0165] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0166] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0167] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0168] Here, it is preferable to use a film with a large tensile stress as the conductor 260. For example, a structure may be used in which titanium nitride is used for the conductor 260a and tungsten is used for the conductor 260b. In this case, the conductors 260a and 260b may be formed using a metal CVD method. The stress of the conductor 260 makes the structure of the region 230bc dense, which can suppress the diffusion of hydrogen. As a result, the V generated in the region 230bc O The amount of H is reduced, so that the region 230bc can be made i-type or substantially i-type.

[0169] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0170] 1C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0171] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are to be provided. The upper surface of the insulator 280 may be flattened. In this case, it is preferable that the upper surface of the insulator 280 roughly coincides with the top of the insulator 250 and the upper surface of the conductor 260.

[0172] The insulator 280, which functions as an interlayer insulating film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer insulating film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating.

[0173] Like the insulator 224, the insulator 280 may have an excess oxygen region or excess oxygen. Furthermore, the insulator 280 preferably has a reduced concentration of impurities such as water and hydrogen. For example, the insulator 280 may be made of an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate. By providing the insulator 280 in contact with the insulator 250a, oxygen can be supplied to the oxide 230 through the insulator 250a. The oxygen reduces oxygen vacancies in the oxide 230, thereby improving the reliability of the transistor 200.

[0174] The insulator 282 is provided in contact with the top surface of the insulator 280, the top surface of the insulator 250, and the top surface of the conductor 260. The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses the permeation of oxygen. For example, an insulator such as aluminum oxide may be used as the insulator 282. By providing the insulator 282 in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and having a function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured and the amount of hydrogen in the region can be kept constant. In particular, using aluminum oxide having an amorphous structure or aluminum oxide with an amorphous structure as the insulator 282 is preferable because it may be possible to more effectively capture or fix hydrogen. As a result, a highly reliable transistor 200 and a semiconductor device having favorable characteristics can be manufactured.

[0175] The insulator 283 functions as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from above into the insulator 280. The insulator 283 is disposed on the insulator 282. The insulator 283 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 283 may be formed using silicon nitride deposited by a sputtering method. By depositing the insulator 283 by a sputtering method, a silicon nitride film that is high in density and less likely to form voids can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film deposited by an ALD method on a silicon nitride film deposited by a sputtering method. This structure is preferable because even if defects, such as voids, occur in the silicon nitride film deposited by the sputtering method, the voids can be filled by the silicon nitride film deposited by the ALD method, which has good coverage, thereby improving sealing performance.

[0176] The insulator 285 is provided on the insulator 283. The insulator 285 is preferably provided using, for example, the same material as the insulator 280. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Note that although FIGS. 1B and 1C illustrate a structure in which the insulator 285 is provided, the present invention is not limited to this. A configuration in which the insulator 285 is not provided and the conductor 246 is provided in contact with the insulator 283 may also be used.

[0177] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0178] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductor in contact with the insulator 241. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from mixing into the oxide 230 through the conductor 240a and the conductor 240b.

[0179] The insulators 241a and 241b may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 241a and 241b are provided in contact with the insulators 283, 282, 275, and 271, and thus can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0180] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surfaces of the conductors 240a and 240b, functioning as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0181] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0182] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0183] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0184] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using high-k materials for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulating film can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0185] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0186] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0187] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0188] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0189] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0190] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0191] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0192] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0193] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Hereinafter, metal oxides that can be used as the oxide 230 and the oxide 243 according to the present invention will be described.

[0194] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0195] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0196] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0197] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be explained using Fig. 4A. Fig. 4A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0198] As shown in FIG. 4A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0199] The structure within the bold frame in Figure 4A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0200] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 4B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by GIXD measurement shown in Figure 4B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 4B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 4B is 500 nm.

[0201] As shown in Figure 4B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as shown in Figure 4B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0202] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). Figure 4C shows the diffraction pattern of a CAAC-IGZO film. Figure 4C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 4C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0203] As shown in Figure 4C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0204] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from that shown in FIG. 4A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0205] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0206] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0207] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0208] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0209] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0210] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0211] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction or the change in interatomic bond distance caused by metal atom substitution.

[0212] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0213] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, because the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0214] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0215] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0216] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0217] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0218] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (also called a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0219] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0220] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0221] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0222] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0223] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0224] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0225] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0226] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0227] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0228] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0229] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0230] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0231] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0232] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0233] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0234] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0235] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0236] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0237] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0238] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0239] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0240] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0241] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device shown in FIGS. 1A to 1D, which is one embodiment of the present invention, will be described with reference to FIGS. 5A to 15A, 5B to 15B, 5C to 15C, and 5D to 15D.

[0242] 5A to 15A are top views. FIGS. 5B to 15B are cross-sectional views corresponding to the portion indicated by the dashed dotted line A1-A2 in FIGS. 5A to 15A, and are also cross-sectional views of the transistor 200 in the channel length direction. FIGS. 5C to 15C are cross-sectional views corresponding to the portion indicated by the dashed dotted line A3-A4 in FIGS. 5A to 15A, and are also cross-sectional views of the transistor 200 in the channel width direction. FIGS. 5D to 15D are cross-sectional views of the portion indicated by the dashed dotted line A5-A6 in FIGS. 5A to 15A. Note that some elements are omitted from the top views in FIGS. 5A to 15A for clarity.

[0243] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0244] There are three types of sputtering methods: RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0245] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods (sometimes called plasma chemical vapor deposition), which use plasma, thermal CVD (TCVD) methods (thermal CVD), which use heat, and photo-CVD (photo-CVD), which use light. They can also be further divided into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods (sometimes called metal organic chemical vapor deposition) depending on the source gas used.

[0246] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0247] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0248] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD method utilizes plasma, which can be preferable because it allows film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0249] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0250] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0251] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate (see FIGS. 5A to 5D). The insulator 212 is preferably formed by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to sputtering, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0252] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. The use of pulsed DC sputtering can suppress particle generation due to arcing on the target surface, resulting in a more uniform film thickness distribution. Furthermore, the use of pulsed voltage can make the discharge rise and fall steeper than with high-frequency voltage. This allows for more efficient supply of power to the electrodes, improving the sputtering rate and film quality.

[0253] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the upward diffusion of the metal through the insulator 212.

[0254] Next, the insulator 214 is deposited on the insulator 212 (see FIGS. 5A to 5D). The insulator 214 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0255] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is set to 0 W / cm. 2Over 1.86W / cm 2 The following is true. In other words, the amount of oxygen suitable for the transistor characteristics can be changed and implanted by adjusting the RF power used when forming the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be implanted. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0256] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high ability to capture and fix hydrogen, as the insulator 214. This allows hydrogen contained in the insulator 216 to be captured or fixed and prevents the hydrogen from diffusing into the oxide 230. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0257] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to sputtering, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0258] In this embodiment, a silicon oxide film is formed by pulse DC sputtering using a silicon target in an atmosphere containing oxygen gas as the insulator 216. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0259] The insulators 212, 214, and 216 are preferably successively deposited without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows the insulators 212, 214, and 216 to be deposited with reduced hydrogen content and also reduces the amount of hydrogen mixed into the films between deposition steps.

[0260] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. It is also preferable to select an insulator for the insulator 214 that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be made of silicon nitride, aluminum oxide, or hafnium oxide. Note that a recess may be formed in the insulator 214, overlapping the opening in the insulator 216.

[0261] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0262] After the openings are formed, a conductive film that becomes the conductor 205a is formed. The conductive film that becomes the conductor 205a preferably includes a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 205a can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0263] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 205a. By providing such a metal nitride in contact with the bottom and side surfaces of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0264] Next, a conductive film to be the conductor 205b is formed. As the conductive film to be the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film to be the conductor 205b.

[0265] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216 (see FIGS. 5A to 5D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP process may remove a portion of the insulator 216.

[0266] Next, etching is performed to remove the upper portion of the conductor 205b (see FIGS. 6A to 6D). As a result, the upper surface of the conductor 205b becomes lower than the upper surfaces of the conductor 205a and the insulator 216. The conductor 205b can be etched by dry etching or wet etching, but dry etching is preferable for fine processing.

[0267] Next, a conductive film to become the conductor 205c is formed on the insulator 216, the conductor 205a, and the conductor 205b. The conductive film to become the conductor 205c preferably contains a conductor that has a function of suppressing oxygen permeation, similar to the conductive film to become the conductor 205a.

[0268] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 205c. By using such a metal nitride as the upper layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 222 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0269] Next, a portion of the conductive film that will become the conductor 205c is removed by CMP processing, exposing the insulator 216 (see FIGS. 7A to 7D). As a result, the conductors 205a, 205b, and 205c remain only in the openings. This allows the formation of a conductor 205 with a flat upper surface. Furthermore, the conductor 205b is surrounded by the conductors 205a and 205c. This prevents impurities such as hydrogen from the conductor 205b from diffusing out of the conductors 205a and 205c, and also prevents oxygen from entering the conductors 205a and 205c, which would otherwise oxidize the conductor 205b. Note that the CMP processing may remove a portion of the insulator 216.

[0270] Next, the insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 8A to 8D). The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water can prevent hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby preventing oxygen vacancies from being generated in the oxide 230.

[0271] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method.

[0272] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0273] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulator 222 as much as possible.

[0274] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4 slm:1 slm. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0275] Next, an insulating film 224A is formed on the insulator 222. The insulating film 224A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is formed as the insulating film 224A by sputtering. By using a sputtering method that does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulating film 224A can be reduced. Since the insulating film 224A will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0276] Next, oxide films 230A and 230B are sequentially formed on insulating film 224A (see FIGS. 8A to 8D). Preferably, oxide films 230A and 230B are successively formed without being exposed to the atmosphere. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0277] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MOCVD method, an MBE method, a PLD method, an ALD method, or the like.

[0278] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0279] During the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulating film 224A. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0280] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0281] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0282] Next, an oxide film 243A is formed on the oxide film 230B (see FIGS. 8A to 8D). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0283] It is preferable to form the insulator 222, the insulating film 224A, the oxide film 230A, the oxide film 230B, and the oxide film 243A by sputtering without exposing them to the atmosphere. For example, a multi-chamber film formation apparatus can be used. This allows the insulator 222, the insulating film 224A, the oxide film 230A, the oxide film 230B, and the oxide film 243A to be formed with reduced hydrogen content and also reduces the incorporation of hydrogen into the films between film formation steps.

[0284] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not polycrystallize, i.e., 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish the desorbed oxygen.

[0285] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being absorbed into oxide film 230A, oxide film 230B, oxide film 243A, and the like as much as possible.

[0286] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for one hour, followed by another heat treatment in an oxygen atmosphere at 400°C for one hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This reduces the diffusion of oxygen or impurities in the oxide film 230B.

[0287] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 8A to 8D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 242A by sputtering. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0288] Next, an insulating film 271A is formed on the conductive film 242A (see FIGS. 8A to 8D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, aluminum oxide may be formed as the insulating film 271A by a sputtering method.

[0289] Note that the conductive film 242A and the insulating film 271A are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This allows the conductive film 242A and the insulating film 271A to be formed with reduced hydrogen content and also reduces the amount of hydrogen mixed into the films between film formation steps. Furthermore, when a hard mask is provided on the insulating film 271A, the film that will become the hard mask may also be formed continuously without exposure to the atmosphere.

[0290] Next, the insulating film 224A, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, and the insulating film 271A are processed into island shapes using lithography to form the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 9A to 9D). This processing can be performed using a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. The insulating film 224A, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the insulating layer 271B may be processed under different conditions.

[0291] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. A conductor, semiconductor, or insulator can then be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0292] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242A and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask. In this embodiment, the insulating layer 271B is used as the hard mask.

[0293] Here, since the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side surface and top surface, as shown in FIGS. 9B to 9D. As a result, the conductors 242a and 242b shown in FIGS. 1B and 1D have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where the side surfaces and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger than when the ends have a curved surface. This reduces the resistance of the conductor 242, thereby increasing the on-current of the transistor 200.

[0294] The insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are formed so as to at least partially overlap with the conductor 205. Preferably, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are approximately perpendicular to the top surface of the insulator 222. When the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are approximately perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when providing multiple transistors 200. Alternatively, the angles formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 may be small. In this case, the angles formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 are preferably 60 degrees or more and less than 70 degrees. By using such a shape, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0295] Furthermore, by-products generated in the etching process may form layers on the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B. In this case, the layered by-products are formed between the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the insulator 275. Similarly, layered by-products may be formed on the insulator 224. Even if the insulator 275 is formed with the layered by-products formed on the insulator 224, the layered by-products would prevent oxygen from being added to the insulator 224. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 224.

[0296] Next, the insulator 275 is formed on the insulator 224 and the insulating layer 271B (see FIGS. 10A to 10D). The insulator 275 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulator 275 is preferably an insulating film that has the function of suppressing oxygen permeation. For example, the insulator 275 may be formed by sputtering a silicon nitride film. Alternatively, the insulator 275 may be formed by sputtering an aluminum oxide film, and then a silicon nitride film may be formed thereon.

[0297] In this way, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B can be covered with the insulator 275 and the insulating layer 271B, which have the function of suppressing oxygen diffusion, thereby reducing the diffusion of oxygen into the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B in a later process.

[0298] Next, an insulating film to be the insulator 280 is formed on the insulator 275. The insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be formed by sputtering. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require hydrogen as a deposition gas. Heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be reduced. The heat treatment conditions described above can be used for the heat treatment.

[0299] Next, the insulating film that will become the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIGS. 10A to 10D). Alternatively, a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the silicon nitride reaches the insulator 280.

[0300] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap with the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 11A to 11D).

[0301] When forming the opening, the upper portion of the oxide 230b is removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0302] Furthermore, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b can be processed by dry etching or wet etching. Dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. The processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B may be performed under different conditions from the processing of a portion of the oxide 230b.

[0303] Here, impurities may adhere to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductor 242, the side surfaces of the insulator 280, etc., or may diffuse into these surfaces. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 230b. Such damaged regions may be removed. Examples of such impurities include those originating from components contained in the insulator 280, the insulator 275, part of the insulating layer 271B, and the conductive layer 242B, components contained in the materials used in the device used to form the opening, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0304] In particular, impurities such as aluminum or silicon inhibit the formation of a CAAC-OS oxide 230b. Therefore, it is preferable to reduce or eliminate impurity elements such as aluminum or silicon that inhibit the formation of a CAAC-OS oxide. For example, the concentration of aluminum atoms in and around the oxide 230b may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0305] Note that the region of the metal oxide where the CAAC-OS transformation is inhibited by impurities such as aluminum or silicon and becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC region of the oxide 230b be reduced or eliminated.

[0306] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom edge of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the bottom edge of the conductor 242a (conductor 242b) has the CAAC structure. In this way, even at the drain edge, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor 200 can be further suppressed. Furthermore, the reliability of the transistor 200 can be improved.

[0307] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0308] For wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0309] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as "diluted ammonia water." The concentration, temperature, and other parameters of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0310] It is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning, as this frequency can reduce damage to the oxide 230b and the like.

[0311] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0312] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of or diffused into the oxides 230a and 230b can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0313] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100°C or higher and 500°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 350°C or higher and 400°C or lower. The heat treatment may be performed in an atmosphere of nitrogen gas, inert gas, or oxidizing gas. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or inert gas containing 10 ppm or higher, 1% or higher, or 10% or higher of oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O The heat treatment can reduce the amount of oxide 230b. In addition, by performing such heat treatment, the crystallinity of the oxide 230b can be improved. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed successively in a nitrogen atmosphere without exposure to the air. In addition, when the heat treatment in an oxygen atmosphere is performed successively in a nitrogen atmosphere without exposure to the air, the heat treatment in the oxygen atmosphere may be performed for a longer time than the heat treatment in the nitrogen atmosphere.

[0314] Next, the insulating film 250A is formed (see FIGS. 12A to 12D). Heat treatment may be performed before the formation of the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed immediately after the formation of the insulating film 250A without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0315] The insulating film 250A can be formed by a method such as sputtering, CVD, PECVD, MBE, PLD, or ALD. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulating film 250A. The insulating film 250A will become the insulator 250a that contacts the oxide 230b in a later process, so it is preferable that the hydrogen concentration be reduced in this manner.

[0316] Furthermore, the insulating film 250A is preferably formed using the ALD method. The insulator 250, which functions as the gate insulating film of the miniaturized transistor 200, must be extremely thin (e.g., between 5 nm and 30 nm) and have minimal variation in thickness. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness control. This allows for the precision of the gate insulating film thickness required by the miniaturized transistor 200 to be achieved. Furthermore, as shown in FIGS. 12B and 12C , the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Because atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250A can be formed with good coverage on the opening.

[0317] Furthermore, when the insulating film 250A is formed by the PECVD method using a gas containing hydrogen such as SiH4 (or Si2H6) as the film formation gas, the film formation gas containing hydrogen is decomposed in the plasma to generate a large amount of hydrogen radicals. The reduction reaction of the hydrogen radicals extracts oxygen from the oxide 230b, resulting in V O When H is formed, the hydrogen concentration in the oxide 230b increases. However, when the insulating film 250A is formed using the ALD method, the generation of hydrogen radicals can be suppressed both when introducing the precursor and when introducing the reactant. Therefore, by forming the insulating film 250A using the ALD method, the hydrogen concentration in the oxide 230b can be prevented from increasing.

[0318] If the above-mentioned impurities are not removed before forming the insulating film 250A, the impurities may remain between the oxide 230a, the oxide 230b, the conductor 242, the insulator 280, etc. and the insulator 250a.

[0319] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere (see FIGS. 12A to 12D). Here, microwave treatment refers to treatment using, for example, a device with a power source that generates high-density plasma using microwaves. In this specification and elsewhere, microwaves may refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0320] In Figures 12B to 12D, dotted lines indicate high-frequency oxygen plasma such as microwaves or RF, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device may be 300 MHz to 300 GHz, preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. Furthermore, the power of the power supply that applies microwaves to the microwave processing device may be 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave processing device may also have a power supply that applies RF to the substrate side. Using high-density plasma allows for the generation of high-density oxygen radicals. Furthermore, applying RF to the substrate side allows for the efficient introduction of oxygen ions generated by high-density plasma into the oxide 230b.

[0321] The microwave treatment is preferably carried out under reduced pressure, with the pressure being 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, and even more preferably 400 Pa or higher. For example, the pressure may be 10 Pa or higher to 1000 Pa or lower, preferably 300 Pa or higher to 700 Pa or lower. The treatment temperature may be 750°C or lower, preferably 500°C or lower, for example, about 400°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. For example, the temperature may be 100°C or higher to 750°C or lower, preferably 300°C or higher to 500°C or lower.

[0322] Furthermore, for example, the microwave treatment may be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / O2+Ar) may be greater than 0% and less than or equal to 100%. Preferably, the oxygen flow ratio (O2 / O2+Ar) may be greater than 0% and less than or equal to 50%. More preferably, the oxygen flow ratio (O2 / O2+Ar) may be greater than 10% and less than or equal to 40%. Even more preferably, the oxygen flow ratio (O2 / O2+Ar) may be greater than 10% and less than or equal to 30%. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the region 230bc can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in the regions 230ba and 230bb can be prevented. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, excessive oxidation of the side surfaces of the conductors 242a and 242b can be prevented.

[0323] As shown in Figures 12B to 12D, microwave processing is performed in an atmosphere containing oxygen, whereby oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 230bc. In other words, microwaves or high-frequency oxygen plasma such as RF can be applied to the region 230bc shown in Figure 2. The action of plasma, microwaves, etc., can increase the V of the region 230bc. O H can be split off and hydrogen H can be removed from the region 230bc. O H → H + V O " reaction occurs, and V contained in region 230bc O Therefore, oxygen vacancies and V in the region 230bc can be reduced. OBy supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, and the carrier concentration can be lowered.

[0324] 2, conductors 242a and 242b are provided on regions 230ba and 230bb. Here, conductor 242 preferably functions as a shielding film against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, and the like when microwave processing is performed in an oxygen-containing atmosphere. Therefore, conductor 242 preferably has the function of blocking electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0325] 12B to 12D, the conductors 242a and 242b shield the effects of microwaves or high-frequency oxygen plasma such as RF, so that these effects do not reach the regions 230ba and 230bb. As a result, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0326] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be prevented, maintaining the n-type conductivity. This prevents fluctuations in the electrical characteristics of the transistor 200 and prevents the electrical characteristics of the transistor 200 from varying across the substrate.

[0327] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0328] Next, an insulating film that will become the insulator 250b is formed. The insulating film that will become the insulator 250b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film that will become the insulator 250b is preferably formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the oxygen contained in the insulator 250a from diffusing into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulating film 250A can be formed using a material that can be used for the insulator 250a described above, and the insulating film that will become the insulator 250b can be formed using a material similar to that of the insulator 222.

[0329] Specifically, the insulating film that becomes the insulator 250b can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator that contains an oxide of one or both of aluminum and hafnium.

[0330] In this embodiment, silicon oxynitride is deposited as the insulating film 250A by the CVD method, and hafnium oxide is deposited as the insulating film that becomes the insulator 250b by the thermal ALD method.

[0331] Microwave treatment may be performed after the formation of the insulating film that will become the insulator 250b. The microwave treatment may be performed under the same conditions as those used for the microwave treatment performed after the formation of the insulating film 250A. Alternatively, the microwave treatment may be performed after the formation of the insulating film that will become the insulator 250b, without performing the microwave treatment performed after the formation of the insulating film 250A.

[0332] Furthermore, after the formation of the insulating film 250A and the insulating film that will become the insulator 250b, a heat treatment may be performed while maintaining a reduced pressure after each microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, the insulating film that will become the insulator 250b, the oxide 230b, and the oxide 230a. Some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a step of performing a heat treatment may be repeated multiple times while maintaining a reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 250A, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0333] Furthermore, by performing microwave processing to modify the film quality of the insulating film 250A and the insulating film that will become the insulator 250b, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 250 in a post-process such as film formation of the conductive film that will become the conductor 260, or in a post-treatment such as heat treatment.

[0334] Next, a conductive film that will become the conductor 260a and a conductive film that will become the conductor 260b are formed in this order. The conductive film that will become the conductor 260a and the conductive film that will become the conductor 260b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film that will become the conductor 260a is formed using an ALD method, and the conductive film that will become the conductor 260b is formed using a CVD method.

[0335] Next, the insulating film 250A, the insulating film that will become the insulator 250b, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished by CMP until the insulator 280 is exposed, thereby forming the insulator 250a, the insulator 250b, the conductor 260a, and the conductor 260b (see FIGS. 13A to 13D). As a result, the insulator 250 is disposed so as to cover the opening that reaches the oxide 230b and the inner walls (side walls and bottom surface) of the groove in the oxide 230b. The conductor 260 is disposed so as to fill the opening and the groove via the insulator 250.

[0336] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0337] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 14A to 14D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced. Furthermore, by forming the insulator 282 by a sputtering method in an atmosphere containing oxygen, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. At this time, the insulator 282 is preferably formed while heating the substrate.

[0338] In this embodiment, an aluminum oxide film is formed as the insulator 282 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. In addition, the RF power applied to the substrate is 1.86 W / cm. 2 Preferably, 0 W / cm 2 More than 0.31W / cm 2 The amount of oxygen injected into the insulator 280 can be suppressed by reducing the RF power. In this embodiment, the insulator 282 is formed in a two-layer laminate structure. The lower layer of the insulator 282 is formed by applying 0 W / cm RF power to the substrate. 2 The upper layer of the insulator 282 was formed as follows: the RF power applied to the substrate was 0.31 W / cm 2 The film is formed as follows.

[0339] Next, the insulator 283 is formed on the insulator 282 (see FIGS. 14A to 14D). The insulator 283 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulator 283 is preferably formed by sputtering. By using a sputtering method that does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be multilayered. For example, a silicon nitride film may be formed by sputtering, and another silicon nitride film may be formed on the silicon nitride by CVD.

[0340] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. As shown in FIG. 2, this heat treatment allows oxygen added by the formation of the insulator 282 to diffuse into the insulators 280 and 250 and to be selectively supplied to the channel formation region of the oxide 230. Note that this heat treatment may be performed not only after the formation of the insulator 283 but also after the formation of the insulator 282.

[0341] Next, an insulator 285 is formed on the insulator 283. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be formed as the insulating film by a CVD method.

[0342] Next, openings are formed in the insulators 271, 275, 280, 282, 283, and 285, reaching the conductor 242 (see FIGS. 15A to 15D). The openings may be formed using lithography. Note that, although the shape of the openings is circular in top view in FIG. 15A, the shape is not limited to this. For example, the openings may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in top view.

[0343] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIGS. 15A to 15D). The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film that will become the insulator 241. For example, it is preferable to form a film of aluminum oxide using the ALD method. Alternatively, it is preferable to form a film of silicon nitride using the PEALD method. Silicon nitride is preferable because it has a high barrier property against hydrogen.

[0344] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0345] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that will become the conductor 240a and the conductor 240b is preferably a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0346] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 240a and 240b, exposing the upper surface of the insulator 285. As a result, the conductive film remains only in the openings, thereby forming the conductors 240a and 240b with flat upper surfaces (see FIGS. 15A to 15D). Note that the CMP processing may remove portions of the upper surface of the insulator 285.

[0347] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0348] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 246a that contacts the upper surface of the conductor 240a and the conductor 246b that contacts the upper surface of the conductor 240b. At this time, a part of the insulator 285 in the region where the conductor 246a and the conductor 246b do not overlap with the insulator 285 may be removed.

[0349] 1A to 1D can be manufactured. As shown in FIGS. 5A to 15A, 5B to 15B, 5C to 15C, and 5D to 15D, the transistor 200 can be manufactured by the method for manufacturing a semiconductor device described in this embodiment.

[0350] <Microwave processing equipment> A microwave processing apparatus that can be used in the manufacturing method of the semiconductor device will be described below.

[0351] First, the configuration of a manufacturing apparatus that can reduce the amount of impurities mixed in during the manufacturing of semiconductor devices and the like will be described with reference to FIGS.

[0352] 16 is a schematic top view of a single-wafer processing multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 has an atmosphere-side substrate supply chamber 2701 equipped with a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning the substrates, an atmosphere-side substrate transfer chamber 2702 for transferring substrates from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading substrates and for switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading substrates and for switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in a vacuum, chambers 2706a, 2706b, 2706c, and 2706d.

[0353] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to chambers 2706a, 2706b, 2706c and 2706d.

[0354] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robots 2763a and 2763b.

[0355] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 In addition, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0356] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer, for example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0357] It is also desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less.

[0358] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are caused by gases entering from outside the vacuum system due to tiny holes or poor seals. Internal leaks are caused by leaks from partitions such as valves within the vacuum system, or gases released from internal components. In order to keep the leak rate below the above-mentioned values, measures must be taken to prevent both external and internal leaks.

[0359] For example, it is advisable to seal the opening and closing portions of the transfer chamber 2704 and each chamber with a metal gasket. It is preferable to use a metal gasket coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. Furthermore, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket can be suppressed, thereby reducing internal leakage.

[0360] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit little impurity-containing gases, are used as components constituting the manufacturing apparatus 2700. Furthermore, the aforementioned metals that emit little impurity-containing gases may be coated on alloys containing iron, chromium, nickel, and the like. Alloys containing iron, chromium, nickel, and the like are rigid, heat-resistant, and suitable for processing. Here, reducing the surface roughness of the components by polishing or the like to reduce the surface area can reduce the amount of emitted gases.

[0361] Alternatively, the components of the manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0362] It is preferable that the components of the manufacturing apparatus 2700 be constructed solely from metal as much as possible, and even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress gas emissions.

[0363] The adsorbed matter present in the transfer chamber 2704 and each chamber is adsorbed to the inner walls and does not affect the pressure of the transfer chamber 2704 or each chamber. However, it can cause gas emissions when the transfer chamber 2704 or each chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with high evacuation capacity to desorb as much adsorbed matter as possible from the transfer chamber 2704 and each chamber and evacuate them in advance. To promote the desorption of adsorbed matter, the transfer chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed matter by approximately 10 times. Baking can be performed at temperatures between 100°C and 450°C. In this case, introducing an inert gas into the transfer chamber 2704 and each chamber while removing adsorbed matter can further increase the desorption rate of water and other substances that are difficult to desorb by evacuation alone. Heating the introduced inert gas to the same temperature as the baking temperature can further increase the desorption rate of adsorbed matter. A rare gas is preferably used as the inert gas.

[0364] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuating the transfer chamber 2704 and each chamber again after a certain period of time has elapsed. The introduction of heated gas can desorb adsorbed substances from the transfer chamber 2704 and each chamber, thereby reducing impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process two to 30 times, preferably five to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C to 400°C, preferably 50°C to 200°C, the pressure in the transfer chamber 2704 and each chamber can be adjusted to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa. The pressure can be maintained for a period of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0365] Next, chamber 2706b and chamber 2706c will be described with reference to the cross-sectional schematic diagram shown in FIG.

[0366] Chamber 2706b and chamber 2706c are chambers capable of, for example, performing microwave processing on an object to be processed. Note that chamber 2706b and chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0367] Chamber 2706b and chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also provided outside chamber 2706b and chamber 2706c are a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0368] The high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is delivered to chambers 2706b and 2706c via a gas pipe 2806 that passes through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 evacuates gases and other gases from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching box 2815.

[0369] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically or mechanically chucking the substrate 2811. It also has a function as an electrode to which power is supplied from a high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0370] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used as the vacuum pump 2817. A cryotrap may also be used in addition to the vacuum pump 2817. The use of a cryopump or a cryotrap is particularly preferable because it allows water to be efficiently pumped out.

[0371] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heating processing using high-temperature gas. The gas used is an inert gas.

[0372] The gas supply source 2801 may be connected to a refiner via a mass flow controller. The gas used preferably has a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used.

[0373] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of, for example, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 (described later), providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0374] The high-frequency generator 2803 has the function of generating microwaves in the range of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. The mode converter 2805 converts the microwaves transmitted in TE mode to TEM mode. The microwaves are then transmitted to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 has multiple slot holes, and the microwaves pass through the slot holes and a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the gas species supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0375] At this time, the ions and radicals generated by the high-density plasma 2810 can modify the film or the like on the substrate 2811. It may be preferable to apply a bias to the substrate 2811 side using a high-frequency power supply 2816. For example, an RF power supply with a frequency of 13.56 MHz or 27.12 MHz may be used as the high-frequency power supply 2816. By applying a bias to the substrate side, ions in the high-density plasma 2810 can be efficiently delivered to the depths of openings in the film or the like on the substrate 2811.

[0376] For example, oxygen radical treatment using high density plasma 2810 can be performed in chamber 2706b or chamber 2706c by introducing oxygen from gas supply source 2801.

[0377] Next, chamber 2706a and chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0378] Chamber 2706a and chamber 2706d are chambers capable of irradiating an object to be treated with electromagnetic waves, for example. Chamber 2706a and chamber 2706d differ only in the type of electromagnetic waves. Since the other configurations are largely common, they will be described together below.

[0379] Chamber 2706a and chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Also, outside chamber 2706a and chamber 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0380] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed opposite a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has a function of heating the substrate 2824.

[0381] A light source capable of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source capable of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0382] For example, the lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.

[0383] For example, the electromagnetic waves emitted from the lamps 2820 can be partially or completely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Note that if the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0384] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0385] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0386] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0387] <Application examples of semiconductor devices> 19A and 19B , an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural Example of Semiconductor Device> and the above <Modification of Semiconductor Device>, will be described. In the semiconductor device shown in FIGS. 19A and 19B , structures having the same functions as those of the semiconductor device shown in <<Structural Example of Semiconductor Device>> (see FIGS. 1A to 1D ) are denoted by the same reference numerals. In this section, the materials described in detail in <Structural Example of Semiconductor Device> can be used to form the transistor 200.

[0388] 19A and 19B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 19A and 19B, this is not a limitation. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors 200_1 to 200_n may be arranged without any regularity depending on the design.

[0389] As shown in FIG. 19A , a portion where the insulator 283 and the insulator 212 contact each other (hereinafter, sometimes referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate. In this case, it is preferable that the insulator 285 is provided in the sealing portion 265 so as to fill the recesses of the insulator 283.

[0390] 19A , insulators 216, 222, 275, 280, and 282 are preferably patterned in the region surrounded by sealing portion 265. In addition, insulator 283 is structured to cover insulators 216, 222, 275, 280, and 282. That is, insulator 283 contacts the top surface of insulator 282, the side surfaces of insulators 216, 222, 275, and 280, and the top surface of insulator 214. As a result, insulators 216, 222, 224, 280, and 282, including oxide 230, are isolated from the outside by insulators 283, 214, and 212. In other words, the plurality of transistors 200_1 to 200_n are arranged in a region sealed with the insulators 283, 214, and 212.

[0391] For example, the insulators 214 and 282 may be formed using a material that can capture and fix hydrogen. The insulators 212 and 283 may be formed using a material that can suppress the diffusion of hydrogen and oxygen. Typically, the insulators 214 and 282 can be made of aluminum oxide. Typically, the insulators 212 and 283 can be made of silicon nitride.

[0392] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from being mixed into the sealed region.

[0393] 19A shows a structure in which the insulator 212 and the insulator 283 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may have a stacked structure of two or more layers.

[0394] Also, dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. The substrate is divided along the dicing lines, so that a group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0395] 19A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in FIG. 19B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In FIG. 19B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0396] In this manner, by using a structure in which the plurality of transistors 200_1 to 200_n are surrounded by a plurality of sealing portions, the contact area between the insulator 283 and the insulator 214 increases, thereby further improving the adhesion between the insulator 283 and the insulator 214. This makes it possible to more reliably seal the plurality of transistors 200_1 to 200_n.

[0397] In this case, a dicing line may be provided overlapping the sealing portion 265a or the sealing portion 265b, or may be provided between the sealing portion 265a and the sealing portion 265b.

[0398] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0399] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or other embodiments.

[0400] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0401] [Storage device 1] 20 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0402] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0403] 20 , a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0404] Moreover, the memory device shown in FIG. 20 can be arranged in a matrix to form a memory cell array.

[0405] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0406] Here, in the transistor 300 shown in FIG. 20, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0407] Note that the transistor 300 illustrated in FIG. 20 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0408] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably the same as the insulator 275 described in the above embodiment.

[0409] For example, the conductor 112 and the conductor 110 can be formed simultaneously over the conductor 240. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 112 and the conductor 110 correspond to the conductor 246 in the above embodiment.

[0410] 20, the conductor 112 and the conductor 110 are shown as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0411] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0412] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0413] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0414] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide or resin with pores, etc.

[0415] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0416] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0417] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0418] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 20, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0419] Similarly, a conductor 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0420] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0421] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 210, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0422] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0423] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0424] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0425] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0426] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Therefore, the insulators 214, 212, and 350 can be formed using insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0427] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0428] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0429] For example, the conductors 328, 330, 356, conductor 218, and conductor 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten or molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce wiring resistance.

[0430] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0431] 20, for example, an insulator 241 may be provided between the insulator 285 and the insulator 280, which contain excess oxygen or impurities, and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 275, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0432] That is, the insulator 241 can prevent excess oxygen in the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0433] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because it has a high barrier property against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0434] As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 285, 150, and the like into the insulator 280 and the like.

[0435] Here, the conductor 240 penetrates the insulators 283 and 282, and the conductor 218 penetrates the insulators 214 and 212. As described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that gets mixed into the inside of the insulators 212, 214, 282, and 283 via the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, 241, and 217, making it possible to reduce the intrusion of impurities such as hydrogen contained in the insulator 285 from the outside.

[0436] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0437] 20, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214 so that the area where the insulator 283 and the insulator 212 contact each other overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 275, 222, 216, and 214 near the area that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0438] That is, the insulators 212 and 283 are in contact with each other through openings formed in the insulators 282, 280, 275, 222, 216, and 214. For example, the insulators 212 and 283 may be formed using the same material and the same method. Providing the insulators 212 and 283 using the same material and the same method can improve adhesion. For example, it is preferable to use silicon nitride.

[0439] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side surface of the divided substrate and diffusing into the transistor 200.

[0440] Furthermore, this structure can prevent excess oxygen in the insulator 280 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. This allows the oxide in which a channel is formed in the transistor 200 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0441] 20, the shape of the capacitor 100 is a planar type, but the shape of the capacitor 100 in this embodiment is not limited to this. For example, as shown in FIG. 21, the shape of the capacitor 100 may be a cylindrical type. Note that the configuration below the insulator 150 of the memory device shown in FIG. 21 is the same as that of the semiconductor device shown in FIG.

[0442] The capacitor 100 shown in FIG. 21 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. At least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the openings formed in the insulator 150 and the insulator 142. An insulator 154 is disposed on the insulator 152, and a conductor 153 and an insulator 156 are disposed on the insulator 154. The conductor 140 is disposed in an opening formed in the insulator 130, the insulator 150, the insulator 142, the insulator 145, the insulator 152, and the insulator 154.

[0443] The conductor 115 functions as the lower electrode of the capacitor 100, the conductor 125 functions as the upper electrode of the capacitor 100, and the insulator 145 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 150 and 142, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0444] The insulator 152 may be an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be an insulator that can be used for the insulator 214.

[0445] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be rectangular, a polygonal shape other than a rectangular, a polygonal shape with curved corners, or a circular shape including an ellipse. Here, it is preferable that the area over which the openings and the transistor 200 overlap in the top view is large. With such a configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0446] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The top of the conductor 115 preferably roughly coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0447] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0448] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

[0449] Examples of high-dielectric-constant (high-k) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials ensures sufficient capacitance of the capacitor 100 even when the insulator 145 is thick. By thickening the insulator 145, leakage current between the conductor 115 and the conductor 125 can be suppressed.

[0450] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN) formed using the ALD method is x ), silicon oxide (SiO x ), silicon nitride (SiN x ) can be used. By using such an insulator with high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0451] The conductor 125 is arranged to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0452] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0453] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.

[0454] <Memory device configuration example> 22 is a cross-sectional view of a semiconductor device including a memory device 290. The memory device 290 shown in Fig. 22 includes a capacitor device 292 in addition to the transistor 200 shown in Fig. 1A to Fig. 1D. Fig. 22 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0455] The capacitor 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 275 provided to cover the conductor 242b and the insulator 271b, and a conductor 294 on the insulator 275. That is, the capacitor 292 constitutes a metal-insulator-metal (MIM) capacitor. One of a pair of electrodes of the capacitor 292, i.e., the conductor 242b, can also serve as a source electrode of a transistor. Furthermore, a dielectric layer of the capacitor 292 can also serve as a protective layer provided in the transistor, i.e., the insulator 271 and the insulator 275. Therefore, part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitor 292, resulting in a highly productive semiconductor device. Furthermore, because one of the pair of electrodes of the capacitor 292, i.e., the conductor 242b, also serves as a source electrode of the transistor, the area in which the transistor and the capacitor are arranged can be reduced.

[0456] The conductor 294 may be made of, for example, a material that can be used for the conductor 242.

[0457] <Modifications of memory devices> 23A, 23B, 24, and 25 will be used to describe an example of a semiconductor device including a transistor 200 and a capacitor 292 according to one embodiment of the present invention, which is different from those described in the previous <Configuration Example of Memory Device>. In the semiconductor devices illustrated in FIGS. 23A, 23B, 24, and 25, the same reference numerals are used to designate structures having the same functions as those in the semiconductor device (see FIG. 22) described in the previous embodiment and <Configuration Example of Memory Device>. In this section, the transistor 200 and the capacitor 292 can be made of materials described in detail in the previous embodiment and <Configuration Example of Memory Device>.

[0458] <<Memory Device Variation 1>> An example of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b according to one embodiment of the present invention will be described below with reference to FIG. 23A.

[0459] 23A is a cross-sectional view in the channel length direction of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b. The capacitor 292a includes a conductor 242a, an insulator 271a provided over the conductor 242a, an insulator 275 provided to cover the conductor 242a and the insulator 271a, and a conductor 294a provided over the insulator 275. The capacitor 292b includes a conductor 242b, an insulator 271b provided over the conductor 242b, an insulator 275 provided to cover the conductor 242b and the insulator 271b, and a conductor 294b provided over the insulator 275.

[0460] As shown in FIG. 23A , the semiconductor device 600 has a symmetrical configuration with the dashed line A3-A4 as the axis of symmetry. Conductor 242c serves as both the source electrode or drain electrode of transistor 200a and the source electrode or drain electrode of transistor 200b. An insulator 271c is provided on conductor 242c. An oxide 243c is provided below conductor 242c. Conductor 246, which functions as wiring, and transistors 200a and 200b are also connected by conductor 240, which functions as a plug. By configuring the two transistors, two capacitance devices, and the connections between the wiring and plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0461] The configuration examples of the semiconductor device shown in FIGS. 1A to 1D and 22 can be referred to for the configurations and effects of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b.

[0462] <<Memory Device Variation 2>> In the above, the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b are given as examples of the configuration of the semiconductor device, but the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 23B , a configuration may be adopted in which a semiconductor device 600 and a semiconductor device having a configuration similar to that of the semiconductor device 600 are connected via a capacitance unit. In this specification, a semiconductor device including the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b is referred to as a cell. For the configurations of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b, the above descriptions of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b can be referred to.

[0463] FIG. 23B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b, and a cell having a configuration similar to that of the semiconductor device 600, connected via a capacitance section.

[0464] As shown in FIG. 23B, the conductor 294b, which functions as one electrode of the capacitance device 292b of the semiconductor device 600, also serves as one electrode of the capacitance device of a semiconductor device 601 having a similar configuration to the semiconductor device 600. Although not shown, the conductor 294a, which functions as one electrode of the capacitance device 292a of the semiconductor device 600, also serves as one electrode of the capacitance device of the semiconductor device adjacent to the left side of the semiconductor device 600, i.e., in the A1 direction in FIG. 23B. The same configuration is also true for the cells on the right side of the semiconductor device 601, i.e., in the A2 direction in FIG. 23B. In other words, a cell array (also referred to as a memory device layer) can be configured. This cell array configuration reduces the spacing between adjacent cells, thereby reducing the projected area of ​​the cell array and enabling higher integration. Furthermore, by arranging the cell array configuration shown in FIG. 23B in a matrix, a matrix cell array can be configured.

[0465] As described above, by forming the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b in the configuration shown in this embodiment, the cell area can be reduced, and miniaturization or high integration of a semiconductor device having a cell array can be achieved.

[0466] Furthermore, the cell array may be configured not only in a plane but also in a stacked configuration. Fig. 24 shows a cross-sectional view of a configuration in which cell arrays 610 are stacked in n layers. As shown in Fig. 24, by stacking multiple cell arrays (cell arrays 610_1 to 610_n), cells can be integrated and arranged without increasing the area occupied by the cell arrays. In other words, a 3D cell array can be configured.

[0467] <Memory Device Modification Example 3> FIG. 25 shows an example in which a memory unit 470 includes a transistor layer 413 including a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0468] Each of the memory device layers 415_1 to 415_4 includes a plurality of memory devices 420.

[0469] The memory device 420 is electrically connected to the memory device 420 in a different memory device layer 415 and the transistor 200T in the transistor layer 413 via the conductor 424 and the conductor 205.

[0470] The memory unit 470 is sealed by the insulators 212, 214, 282, and 283 (hereinafter referred to as a sealing structure for convenience). An insulator 285 is provided around the insulator 283. Furthermore, a conductor 440 is provided on the insulators 285, 283, and 212, and is electrically connected to the element layer 411.

[0471] Furthermore, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen when heated. Alternatively, the insulator 280 has an excess oxygen region.

[0472] Note that the insulators 212 and 283 are preferably made of a material having a high barrier property against hydrogen, and the insulators 214 and 282 are preferably made of a material having a function of capturing or fixing hydrogen.

[0473] For example, examples of materials having a high barrier property against hydrogen include silicon nitride and silicon nitride oxide, while examples of materials having a function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0474] Note that the crystal structure of the materials used for the insulators 212, 214, 282, and 283 is not particularly limited, and may be amorphous or crystalline. For example, an amorphous aluminum oxide film is preferably used as a material capable of capturing or fixing hydrogen. Amorphous aluminum oxide may be able to capture and fix a larger amount of hydrogen than aluminum oxide with high crystallinity.

[0475] Insulators 282 and 214 are preferably provided between the transistor layer 413 and the memory device layer 415 or between the memory device layers 415. Insulators 296 are preferably provided between the insulators 282 and 214. The insulator 296 can be made of a material similar to that of the insulator 283. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, a known insulating material can be used.

[0476] Here, the excess oxygen in the insulator 280 can be considered as follows for the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.

[0477] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. Due to the diffusion of hydrogen, excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, which then diffuses through the insulator 280. When the hydrogen atom having the OH bond reaches a material (typically, the insulator 282) that has the function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom that is bonded to an atom (e.g., a metal atom) in the insulator 282, and is captured or fixed in the insulator 282. Meanwhile, the oxygen atom of the excess oxygen that had the OH bond is presumably left as excess oxygen in the insulator 280. In other words, the excess oxygen in the insulator 280 is highly likely to play a bridging role in the diffusion of hydrogen.

[0478] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0479] For example, the insulator 280 containing excess oxygen is formed over an oxide semiconductor, and then the insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and further preferably 8 hours or longer.

[0480] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280 and the insulator 282. That is, the absolute amount of hydrogen present in and around the oxide semiconductor can be reduced.

[0481] After the heat treatment, the insulator 283 is formed. The insulator 283 is a material having a high barrier property against hydrogen, and therefore can prevent hydrogen diffused to the outside or hydrogen present outside from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0482] Note that the heat treatment described above is performed after the insulator 282 is formed, but is not limited thereto. For example, the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layers 415_1 to 415_3 are formed. When hydrogen is diffused outward by the heat treatment, the hydrogen diffuses upward or laterally in the transistor layer 413. Similarly, when the heat treatment is performed after the memory device layers 415_1 to 415_3 are formed, the hydrogen diffuses upward or laterally.

[0483] By using the above manufacturing process, the insulator 212 and the insulator 283 are bonded together, thereby forming the above-described sealing structure.

[0484] As described above, by using the above structure and manufacturing process, a semiconductor device including an oxide semiconductor with a reduced hydrogen concentration can be provided. Therefore, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided.

[0485] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiments.

[0486] (Embodiment 3) 26A, 26B, and 27A to 27H will be used to describe a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0487] <Storage device configuration example> 26A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0488] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0489] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0490] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0491] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0492] 26A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 26B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0493] 27A to 27H will be used to explain examples of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0494] [DOSRAM] 27A to 27C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as DOSRAM (registered trademark, Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 27A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes called a top gate) and a back gate.

[0495] A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitor CA is connected to a wiring LL.

[0496] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, the wiring LL may be set to ground potential or a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0497] 27A corresponds to the memory device shown in FIG 22. That is, the transistor M1 corresponds to the transistor 200, and the capacitance element CA corresponds to the capacitance device 292.

[0498] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 27B. Furthermore, for example, the memory cell MC may be configured as a memory cell including a single-gate transistor, i.e., a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 27C.

[0499] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0500] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0501] [NOSRAM] 27D to 27G show circuit configuration examples of a gain cell type memory cell with two transistors and one capacitor. The memory cell 1474 shown in FIG. 27D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0502] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0503] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. When writing and reading data, it is preferable to apply a high-level potential to the wiring CAL. Furthermore, when retaining data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0504] 27D corresponds to the memory device shown in Fig. 20. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0505] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 27E. Furthermore, for example, the memory cell MC may be configured as a memory cell having a single gate structure, that is, a memory cell including a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 27F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 27G.

[0506] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0507] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0508] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0509] FIG. 27H shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 27H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The GNDL wiring is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0510] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0511] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, or the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-channel transistors.

[0512] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0513] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0514] In general, various memory devices (memories) are used depending on the application in semiconductor devices such as computers. The semiconductor device of one embodiment of the present invention can be suitably used for, for example, a memory integrated as a register in an arithmetic processing unit such as a CPU, a static random access memory (SRAM), a dynamic random access memory (DRAM), or a 3D NAND memory.

[0515] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0516] SRAM is used, for example, in caches. Caches have the function of storing a copy of the information stored in main memory. By storing copies of frequently used data in the cache, access speed to the data can be increased.

[0517] DRAM is used, for example, as main memory. Main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0518] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that requires long-term storage, as well as various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0519] A storage device according to one embodiment of the present invention has a high operating speed and is capable of long-term data retention. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area including both a tier where a cache is located and a tier where a main memory is located. Alternatively, the storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area including both a tier where a main memory is located and a tier where a storage is located.

[0520] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0521] (Fourth embodiment) 28A and 28B, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0522] As shown in FIG. 28A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0523] 28B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of the PCB 1201, which is connected to a motherboard 1203.

[0524] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0525] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0526] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0527] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0528] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0529] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0530] The network circuit 1216 has a function of controlling connections with a LAN (Local Area Network), etc. It may also have a circuit for network security.

[0531] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0532] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0533] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0534] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0535] (Embodiment 5) This embodiment mode will describe examples of electronic components and electronic devices in which the memory device or the like described in the above embodiment mode is incorporated.

[0536] <Electronic components> First, an example of an electronic component incorporating memory device 720 will be described with reference to FIGS. 29A and 29B.

[0537] FIG. 29A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 29A has memory device 720 inside mold 711. Parts of FIG. 29A are omitted to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to memory device 720 by wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0538] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0539] 29B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 provided on interposer 731.

[0540] In the electronic component 730, an example is shown in which the storage device 720 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0541] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be a silicon interposer, a resin interposer, etc.

[0542] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, with a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0543] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require the provision of active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0544] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0545] Furthermore, in SiP or MCM using silicon interposers, a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on the interposer.

[0546] A heat sink (heat dissipation plate) may be provided over the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0547] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 29B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0548] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0549] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0550] (Sixth embodiment) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIGS. 30A to 30E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0551] 30A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 or the like.

[0552] FIG. 30B is a schematic diagram of the appearance of an SD card, and FIG. 30C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0553] FIG. 30D is a schematic diagram of the appearance of an SSD, and FIG. 30E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be a DOSRAM chip, for example. By providing a memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 or the like.

[0554] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0555] (Embodiment 7) A semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in FIGS.

[0556] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be incorporated into various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio players. By incorporating a semiconductor device according to one embodiment of the present invention into such electronic devices, highly reliable electronic devices can be provided. Furthermore, by incorporating a GPU or chip according to one embodiment of the present invention into an electronic device, artificial intelligence can be implemented in the electronic device.

[0557] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, or the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0558] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0559] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 31A to 31H.

[0560] [Information terminal] 31A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0561] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, or the like input by a user to a touch panel provided in the display portion 5102 and displays the characters, figures, or the like on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0562] 31B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0563] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0564] In the above description, a smartphone and a notebook information terminal are illustrated as examples of electronic devices in Figures 31A and 31B, but information terminals other than smartphones and notebook information terminals can also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0565] [Game consoles] FIG. 31C illustrates a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play a game simultaneously. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0566] 31D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wired connection.

[0567] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0568] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0569] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0570] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0571] 31C and 31D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0572] [Mainframe Computer] The GPU or chip of one embodiment of the present invention can be applied to a mainframe computer.

[0573] 31E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 31F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0574] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0575] The supercomputer 5500 is a large-scale computer primarily used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from circuits, thereby reducing the impact of heat generation on the circuits themselves, peripheral circuits, and modules.

[0576] 31E and 31F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), etc.

[0577] [Moving object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0578] Fig. 31G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0579] The display panels 5701 to 5703 can provide various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. Furthermore, the display items or layout displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0580] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0581] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0582] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0583] [electric appliances] 31H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0584] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0585] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0586] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0587] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes. [Explanation of symbols]

[0588] BGL: wiring, BIL: wiring, CA: capacitance element, CB: capacitance element, CC: capacitance element, CAL: wiring, GNDL: wiring, LL: wiring, MC: memory cell, M1: transistor, M2: transistor, M3: transistor, M4: transistor, M5: transistor, M6: transistor, RBL: wiring, RWL: wiring, SL: wiring, WBL: wiring, WOL: wiring, WWL: wiring, 20: stress, 20a: stress, 20b: stress, 30a: strain, 30b: strain, 30c: strain, 100: capacitance element, 110: conductor, 112: conductor, 115: conductor, 120: conductor, 12 5: conductor, 130: insulator, 140: conductor, 142: insulator, 145: insulator, 150: insulator, 152: insulator, 153: conductor, 154: insulator, 156: insulator, 200: transistor, 200_n: transistor, 200_1: transistor, 200a: transistor, 200b: transistor, 200T: transistor, 205: conductor, 205a: conductor, 205b: conductor, 205c: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 217: insulator, 218: conductor, 222: insulator, 224: insulator, 224A: insulating film, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230ba: region, 230bb: region, 230bc: region, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor, 242B: conductive layer, 242c: conductor, 243: oxide, 243a: oxide, 243A: oxide film, 243b: oxide, 243B: oxide layer, 243c: oxide, 246: conductor, 246 a: conductor, 246b: conductor, 250: insulator, 250a: insulator, 250A: insulating film, 250b: insulator, 260: conductor, 260a: conductor, 260b: conductor, 265: sealing portion, 265a: sealing portion, 265b: sealing portion, 271: insulator, 271a: insulator, 271A: insulating film, 271b: insulator, 271B: insulating layer, 271c: insulator, 275: insulator, 280: insulator, 282: insulator, 283: insulator, 285: insulator, 290: memory device, 292: capacitance device, 292a: capacitance device, 292b: capacitance device, 294: conductor,294a: conductor, 294b: conductor, 296: insulator, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 411: element layer, 413: transistor layer, 415: memory device layer, 415_1: memory device layer, 415_3: memory device layer, 415_4: memory device layer, 420: memory device, 424: conductor, 440: conductor, 470: memory unit, 600: semiconductor device, 601: semiconductor device, 610: cell array, 610_n: cell array, 610_1: cell array, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 711: mold, 712: land, 713: electrode pad, 714: wire, 720: memory device, 721: drive circuit layer, 722: memory circuit layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 1001: wiring, 1 002: Wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring, 1100: USB memory, 1101: Housing, 1102: Cap, 1103: USB connector, 1104: Board, 1105: Memory chip, 1106: Controller chi...

Claims

[Claim 1] an oxide semiconductor film; a source electrode and a drain electrode having a region disposed above the oxide semiconductor film; an interlayer insulating film having a region covering the oxide semiconductor film, the source electrode, and the drain electrode; a gate electrode above the oxide semiconductor film, the interlayer insulating film has an opening overlapping a region located between the source electrode and the drain electrode, the gate electrode is disposed in the opening; each of the source electrode and the drain electrode has a compressive stress; Transistor.

Images