Frequency adjustment device

Abstract

To output a stable waveform to a device which operates at frequencies lower than a clock.SOLUTION: The frequency adjustment device includes: a counter section 2 of a binary counter for counting a clock signal CLK; and a waveform output section 3 for outputting a waveform in accordance with an output from the counter section 2 and returning a cycle-delayed value to the counter section 2. By performing frequency division with an addition value FIN[7:0], a frequency-division circuit outputs a pulse output PLSOUT having a frequency lower than the clock signal CLK, and a fluctuation-prevention circuit prevents cycle fluctuation caused by a carry generated when counting is completed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a frequency adjustment device. [Background technology]

[0002] An arbitrary waveform generator is known that divides a high-frequency pulse signal emitted from a clock by a set addition value and converts it into a low-frequency waveform that is suitable for the target device (see, for example, Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Eugene Palatnik, "Arbitrary Waveform Generator Made with FPGA", [online], July 1, 2008, EDN Japan, [Retrieved March 21, 2024], Internet<URL:https: / / edn.itmedia.co.jp / edn / articles / 0807 / 01 / news156.html> Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the above-mentioned arbitrary waveform generator is operated, fluctuations in frequency occur, and a stable waveform cannot always be obtained.

[0005] The present disclosure is intended to solve the above-mentioned problems, and aims to output a stable waveform to a device that operates at a frequency lower than the clock frequency. [Means for solving the problem]

[0006] The frequency adjustment device of the present disclosure is characterized by comprising a counter section of a binary counter that counts a clock signal, and a waveform output section that outputs a waveform according to the output from the counter section and returns the cycle delay value of the waveform to the counter section, a frequency divider circuit that outputs a waveform of a lower frequency than the clock signal by dividing by an added value, and a fluctuation prevention circuit that prevents fluctuations in the period of the waveform due to carryover when the count in the count section expires. [Effects of the Invention]

[0007] According to the frequency adjustment device of the present disclosure, fluctuations due to carryover when the count expires are prevented, so that a waveform with a lower frequency than the clock can be stably output. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a configuration of a frequency adjustment device according to a first embodiment; [Figure 2] 1 is a block diagram showing a configuration of a test device using a frequency adjustment device according to a first embodiment; [Figure 3] 2 is a circuit diagram showing a detailed configuration of a frequency adjustment device according to the first embodiment. FIG. [Figure 4] FIG. 10 is a block diagram showing a configuration of a frequency adjustment device according to a second embodiment. [Figure 5] FIG. 10 is a circuit diagram showing a detailed configuration of a frequency adjustment device according to a second embodiment. [Figure 6] FIG. 10 is a block diagram showing a configuration of a frequency adjustment device according to a third embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a detailed configuration of a frequency adjustment device according to a third embodiment. [Figure 8] FIG. 10 is a timing diagram for explaining the operation of the frequency adjustment device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiment 1 1 to 3 are diagrams for explaining the configuration and operation of the frequency adjustment device according to the first embodiment, in which FIG. 1 is a block diagram showing the overall configuration of the frequency adjustment device, FIG. 2 is a block diagram showing an example of a test device using the frequency adjustment device, and FIG. 3 is a circuit diagram showing a specific example of the detailed configuration.

[0010] 1, the frequency adjustment device 1 according to the first embodiment includes a counter unit 2, which is a binary counter that counts high-frequency pulses (clock signal CLK) and outputs a count at each expiration, and a waveform output unit 3 that outputs a pulse waveform corresponding to the output from the counter unit 2. The counter unit 2 is configured to add a value D13 (add_fd_reg[7:0]) delayed by one cycle in the waveform returned from the waveform output unit 3 to the added value FIN[7:0] and output the result to the waveform output unit 3.

[0011] The configuration up to this point, including the following embodiments, is the same as the conventional arbitrary waveform generator described in the background art. Before describing the characteristic configuration of the frequency adjustment device 1 of the present disclosure, we will now explain the problems that have arisen in the arbitrary waveform generator described in the background art.

[0012] The frequency adjustment device 1 of the present disclosure and the arbitrary waveform generator described in the background art section may be used in the configuration of a system such as a test device that outputs a square wave with a period corresponding to the speed detected by a speed detector 900, as shown in Fig. 2. Note that the speed pulse counter 10 that receives a pulse speed signal from the speed detector 900, counts the number of pulses within a certain time period, and calculates the sum FIN[7:0], and the frequency adjustment device 1 are built in a logic device 100 such as an ASIC (Application Specific Integrated Circuit) or a PLD (Programmable Logic Device).

[0013] In the arbitrary waveform generator described in the background art, a high-frequency pulse (clock signal CLK) can be converted to a frequency suitable for the operation of the target device by setting an additional value (count number in the literature). Although a stable frequency was basically obtained, the period was sometimes disrupted and fluctuations occurred.

[0014] Therefore, when examining signal changes in a system such as that shown in Fig. 2, the speed detector 900 is attached to the axle or the like, and the number of pulses (speed pulse signal) output within a certain time period changes according to the vehicle speed (number of rotations). Therefore, we simulated the changes in the speed pulse signal and verified it under various conditions, and found that when a value other than a power of 2 is set as the additional value, the carryover at the end of the count interferes with the next count, causing fluctuations.

[0015] In contrast, in such a system, as described above, the output addition value FIN[7:0] from the speed pulse counter 10 changes depending on the vehicle speed, and there is a high possibility that an addition value other than a power of 2 will be input depending on the vehicle speed.

[0016] Therefore, in the frequency adjustment device 1 of the present disclosure, we have proposed several aspects of the frequency adjustment device 1 that are equipped with a fluctuation prevention circuit so that a stable waveform output without fluctuations can be obtained even when an additional value other than a power of 2 is set.

[0017] In the first embodiment, a rounding unit 4 is provided as a fluctuation prevention circuit in the preceding stage of the counter unit 2, which rounds the addition value FIN[7:0] output from an addition value setting unit (not shown) to a power of 2 and outputs the rounded value. The operation of this configuration will be described below.

[0018] As shown in FIG. 3, the rounding unit 4 is configured by arranging eight selectors in a stage preceding the flip-flop FF, and rounds the received 8-bit addition value FIN[7:0] to a power of 2 and outputs it to the counter unit 2. For example, when a power of 2 such as 55 (2, 4, 8, 16, 32, 64, . . . 2) is rounded, the rounding unit 4 outputs the power of 2 to the counter unit 2. nAny number other than 1 (n is a natural number) is converted to the previous power of 2, 32 (D11=fin_reg[7:0]), and output. The clock signal CLK is output to the clock terminal of each flip-flop FF, and the reset signal RST_N is output to the reset terminal of each flip-flop FF.

[0019] Counter unit 2 adds value D13 (add_fd_reg[7:0]), which is returned from waveform output unit 3 with a one-cycle delay, to the sum (D11) rounded to a power of 2. Then, it outputs the added value D12 (add_fd[7:0]) to waveform output unit 3. Waveform output unit 3 outputs the most significant bit of value D12 as a pulse output PLSOUT.

[0020] This eliminates the carryover of the count when it expires, so the pulse output PLSOUT does not fluctuate and can be output to the target device as a stable pulse signal. In other words, the high-frequency clock signal CLK can be output as a pulse signal (pulse output PLSOUT) with a frequency that is suitable for the operation of the target device and is stable and free of fluctuations.

[0021] Embodiment 2 In the above-mentioned first embodiment, an example has been described in which the occurrence of fluctuations is prevented by correcting the added value to a value rounded to a power of 2. In the second embodiment, an example will be described in which the occurrence of fluctuations is prevented by resetting the value carried over when the count expires.

[0022] 4 and 5 are diagrams for explaining the configuration and operation of a frequency adjustment device according to embodiment 2, with Fig. 4 being a block diagram showing the overall configuration of the frequency adjustment device and Fig. 5 being a circuit diagram showing a specific example of the detailed configuration. Note that in embodiment 2, the configuration and operation of the waveform output unit are the same as in embodiment 1, and therefore a description of the similar parts will be omitted.

[0023] As shown in Fig. 4, the frequency adjustment device 1 according to the second embodiment is provided with a carryover determination unit 5 as a fluctuation prevention circuit between the output system from the waveform output unit 3 to the counter unit 2, which determines whether or not a count has expired and a carryover will occur. As in the first embodiment, the clock signal CLK is output to the clock terminal of each flip-flop FF, and the reset signal RST_N is output to the reset terminal of each flip-flop FF. The operation in this configuration will be described below.

[0024] 5, the carryover determination unit 5 determines whether or not a carryover will occur based on the input addition value FIN[7:0] and the value D23 (add_fd_reg[7:0]) output from the waveform output unit 3. Then, the output D21 (add_fd_sel[7:0]) to the counter unit 2 is set to 0 if a carryover will occur, and to output the value D23 returned from the waveform output unit 3 with a delay of one cycle as is if a carryover will not occur.

[0025] Then, counter unit 2 adds output D21 output via carryover determination unit 5 to input addition value FIN[7:0] and outputs the result as output D22 (add_fd[7:0]) to waveform output unit 3. Waveform output unit 3 outputs the most significant bit of output D22 as pulse output PLSOUT, and at the same time outputs value D23, which is output D22 delayed by one cycle, to carryover determination unit 5.

[0026] As a result, as in the first embodiment, even if a carryover occurs when the count expires, the next count is not affected, and the pulse output PLSOUT does not fluctuate, so that it can be output to the target device as a stable pulse signal. In other words, it is possible to output the high-frequency clock signal CLK as a pulse signal (pulse output PLSOUT) with a frequency that is suitable for the operation of the target device and that is stable and free from fluctuations.

[0027] Embodiment 3 In the above-mentioned first and second embodiments, examples have been described in which a carryover is not performed when the count expires, or in which a carryover is performed without causing any problems. In the frequency adjustment device according to the third embodiment, an example will be described in which the output waveform is counted only the first time, and thereafter the count value is used to decode and generate the output waveform.

[0028] 6 to 8 are diagrams for explaining the configuration and operation of a frequency adjustment device according to a third embodiment, with Fig. 6 being a block diagram showing the overall configuration of the frequency adjustment device and Fig. 7 being a circuit diagram showing a specific example of the detailed configuration. Fig. 8 is a timing chart for explaining the operation. In the third embodiment, the configuration and operation of the counter unit and waveform output unit are the same as in the first embodiment, and therefore a description of the similar parts will be omitted.

[0029] As shown in Fig. 6, the frequency adjustment device 1 according to the third embodiment has a first waveform counting unit 6 that counts the first waveform, an output waveform decoding unit 7 that decodes the output waveform, and an output waveform switching unit 8 that switches the output waveform depending on whether it is the first or not, all arranged in this order after the waveform output unit 3, and are provided as a fluctuation prevention circuit. As in the first and second embodiments, the clock signal CLK is output to the clock terminal of each flip-flop FF, and the reset signal RST_N is output to the reset terminal of each flip-flop FF. The operation of this configuration will be described below.

[0030] 7, counter unit 2 adds the input addition value FIN[7:0] to value D33 (add_fd_reg[7:0]) delayed by one cycle and returned from waveform output unit 3, and outputs the result as output D31 (add_fd[7:0]) to waveform output unit 3. Waveform output unit 3 outputs the most significant bit of value D31 as output D32 (add_fd[7]) to initial waveform counting unit 6. At the same time, it outputs value D33, which is output D31 delayed by one cycle, to counter unit 2, and outputs the most significant bit D33M (add_fd_reg[7]) of value D33 to initial waveform counting unit 6 and output waveform switching unit 8.

[0031] 7, the initial waveform counting unit 6 counts the initial L time and H time of the output D32, and outputs count values ​​D34l (l_cnt[6:0]) and D34h (h_cnt[6:0]), respectively, to the output waveform decoding unit 7. At the same time, it also outputs signals D36l (lcnt_en) and D36h (hcnt_en), which indicate that the initial L time and H time of the output D32 are being counted, to the output waveform decoding unit 7 and the output waveform switching unit 8.

[0032] As shown in the lower part of FIG. 7, the output waveform decoding unit 7 outputs a waveform D35(dec_pls) to the output waveform switching unit 8 based on the count values ​​D34l and D34h, and the signals D36l and D36h.

[0033] When the output waveform switching unit 8 is counting the initial L time and H time based on the signals D36l and D36h output from the initial waveform counting unit 6, it outputs the value D33 output from the waveform output unit 3 as the pulse output PLSOUT. On the other hand, thereafter, it outputs the waveform D35 output from the output waveform decoding unit 7 as the pulse output PLSOUT.

[0034] Furthermore, based on the timing diagram of Figure 8, we will explain the change in the signal when 55, which is not a power of 2, is input as the addition value FIN[7:0] (second stage). In this case, the output D31 from the counter unit 2 increases by 55 as shown in the third stage, from 0, 55, 110, ..., but in an 8-bit counter, it increases by 256 (=2 8 ) the count will end at 220, which is smaller than the previous number, and the next count will begin at the carried-over number of 19.

[0035] In this case, as shown in the tenth row, the waveform add_fd[7] (D32) output from the waveform output unit 3 has a second interval that differs from the first interval, and if this continues to be output as the pulse output PLSOUT, fluctuations will occur. In contrast, the frequency adjustment device 1 according to the third embodiment generates the regular count Pls_cnt[7:0] shown in the second row from the bottom based on the first count value h_cnt[6:0] (D34h) of the first waveform counting unit 6.

[0036] Then, for the second and subsequent counts, the waveform dec_pls (D35) decoded from the generated regular count pls_cnt[7:0] is repeatedly used.

[0037] As a result, even if an addition value FIN[7:0] other than a power of 2 that causes a carryover when the count expires is input, it does not affect the next count, and the pulse output PLSOUT does not fluctuate, allowing it to be output to the target device as a stable pulse signal.In other words, it is possible to output a pulse signal (pulse output PLSOUT) with a high-frequency clock signal CLK that is compatible with the operation of the target device and has a stable frequency without fluctuations.

[0038] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are contemplated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0039] For example, although the above example illustrates the case where the pulse output PLSOUT is used as the output waveform, the present invention is not limited to this. For example, the frequency adjustment device 1 according to the first embodiment and the frequency adjustment device 1 according to the second embodiment can also output waveforms other than the pulse output PLSOUT, such as a sine wave.

[0040] As described above, the frequency adjustment device 1 of the present disclosure includes a counter unit 2, which is a binary counter that counts the clock signal CLK, and a waveform output unit 3 that outputs a waveform (pulse output PLSOUT) according to the output (D12, D22, D32: add_fd[7:0]) from the counter unit 2 and returns a cycle delay value (D13, D23, D33: add_fd_reg[7:0]) of the waveform to the counter unit 2. The frequency adjustment device 1 is also configured to include a frequency divider circuit that divides the frequency by the addend FIN[7:0] to output a waveform (pulse output PLSOUT) with a lower frequency than the clock signal CLK, and a fluctuation prevention circuit (rounding unit 4, carryover determination unit 5, initial waveform counting unit 6, output waveform decoding unit 7, and output waveform switching unit 8) that prevents fluctuations in the period of the waveform (pulse output PLSOUT) caused by carryover when the counter unit 2 reaches its count limit. This allows a stable waveform to be output to a device that operates at a frequency lower than the clock frequency.

[0041] In this case, if a rounding unit 4 is provided as a fluctuation prevention circuit, which converts the input addition value into a value D11 (fin_reg[7:0]) rounded to a power of 2 and outputs it to the counter unit 2, there will be no carryover when the count reaches its limit, and fluctuations will not occur.

[0042] Alternatively, if a fluctuation prevention circuit is provided with a carryover determination unit 5 that determines whether a carryover will occur and, when a carryover occurs, outputs 0 to the counter unit as the value D21 (add_fd_sel[7:0]) to be returned from the waveform output unit 3 to the counter unit 2 instead of the cycle delay value D23 (add_fd_reg[7:0]), the carryover that occurs when the count expires will be reset, so fluctuations due to the carryover will not occur.

[0043] Alternatively, if an output waveform switching unit 8 (and initial waveform counting unit 6 and output waveform decoding unit 7) is provided as a fluctuation prevention circuit that stores the waveform (output D32:add_fd[7]) output from the waveform output unit 3 up to the first count expiration, and switches from the waveform output from the waveform output unit (output D32) to the stored waveform D35 after the first expiration, even if an addition value FIN[7:0] that causes a carryover is input, the waveform up to the first count expiration before the carryover occurs can be repeatedly output, so no fluctuation will occur. [Explanation of symbols]

[0044] 1: Frequency adjustment device, 2: Counter section, 3: Waveform output section, 4: Rounding section, 5: Carryover determination section, 6: Initial waveform count section, 7: Output waveform decoding section, 8: Output waveform switching section, CLK: Clock signal, FIN[7:0]: Addition value, PLSOUT: Pulse output (waveform).

Claims

1. a frequency divider circuit including a counter unit of a binary counter that counts clock signals, and a waveform output unit that outputs a waveform according to the output from the counter unit and returns a cycle delay value of the waveform to the counter unit, and that outputs a waveform with a lower frequency than the clock signal by dividing the frequency by the added value; a fluctuation prevention circuit that prevents fluctuations in the period of the waveform caused by carryover when the count in the counter unit is completed; A frequency adjustment device comprising:

2. 2. The frequency adjustment device according to claim 1, further comprising, as the fluctuation prevention circuit, a rounding unit that converts the input sum into a value rounded to a power of 2 and outputs the value to the counter unit.

3. 2. The frequency adjustment device according to claim 1, further comprising, as the fluctuation prevention circuit, a carryover determination unit that determines whether the carryover will occur and, when the carryover occurs, outputs 0 to the counter unit instead of the cycle delay value as the value to be returned from the waveform output unit to the counter unit.

4. 2. The frequency adjustment device according to claim 1, further comprising, as the fluctuation prevention circuit, an output waveform switching unit that stores a waveform output from the waveform output unit up to the first expiration of the count, and switches from the waveform output from the waveform output unit to the stored waveform after the first expiration.

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