Storage device

Abstract

To provide a storage device that prevents a polarization state of ferroelectric capacitors from deteriorating.SOLUTION: A memory circuit 100 includes: a transistor T1 having a first terminal S1 connected to a first power supply VSS, a second terminal D1 connected to a bit line BL, and a control terminal G1; a ferroelectric capacitor F1 of which one end is connected to the control terminal of the transistor T1 and the other end is connected to a word line WL; a write circuit that writes data to the ferroelectric capacitor by applying a write voltage between the one end and the other end of the ferroelectric capacitor; and a read circuit 24 that reads data written to the ferroelectric capacitor from the bit line, in which the read circuit determines that the data written when the voltage or the current of the bit line is within a first range is the first bit, and determines that the data written when the voltage or the current of the bit line is within a second range is the second bit, and the write circuit writes the first bit to the ferroelectric capacitor when the voltage or the current on the bit line is within a third range.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a storage device. [Background technology]

[0002] Ferroelectric memory devices using ferroelectric capacitors are known as nonvolatile memory devices. A memory cell with an MFMIS (Metal Ferroelectric Metal Insulator Semiconductor) structure in which a ferroelectric capacitor is connected between a control terminal of a transistor and a word line is known (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-250608 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-308291 Summary of the Invention [Problem to be solved by the invention]

[0004] Ferroelectric memory devices with an MFMIS structure are capable of non-destructive readout. However, repeated readout operations can deteriorate the polarization state of the ferroelectric capacitor, making it impossible to determine the readout state.

[0005] An object of the present disclosure is to provide a memory device capable of suppressing deterioration of the polarization state of a ferroelectric capacitor. [Means for solving the problem]

[0006] According to an embodiment of the present disclosure, a memory device includes a transistor having a first terminal connected to a first power supply, a second terminal connected to a bit line, and a control terminal; a ferroelectric capacitor having one end connected to the control terminal of the transistor and the other end connected to a word line; a write circuit that writes data to the ferroelectric capacitor by applying a write voltage between one end and the other end of the ferroelectric capacitor; and a read circuit that reads the data written to the ferroelectric capacitor from the bit line, wherein the read circuit determines the written data to be a first bit when a voltage or current of the bit line is within a first range out of a first range and a second range separated by a first threshold, and determines the written data to be a second bit when the voltage or current of the bit line is within the second range; and the write circuit writes the first bit to the ferroelectric capacitor when the voltage or current of the bit line is within a third range between the first threshold and a second threshold within the first range. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to suppress the deterioration of the polarization state of a ferroelectric capacitor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a storage device according to the first embodiment. [Figure 2] 2(a) to 2(c) are diagrams showing a method for reading data from a memory cell. [Figure 3] 3(a) and 3(b) are diagrams showing polarization P versus voltage VF. [Figure 4] 4(a) and 4(b) are diagrams showing polarization P versus voltage VF. [Figure 5] FIG. 5 is a diagram showing the voltage VOUT and the current ID relative to the number of reads. [Figure 6] FIG. 6 is a flowchart showing a read operation in the memory device according to the first embodiment. [Figure 7]FIG. 7 is a circuit diagram showing a first circuit example of the readout circuit in the first embodiment. [Figure 8] FIG. 8 is a circuit diagram showing a second circuit example of the readout circuit in the first embodiment. [Figure 9] FIG. 9 is a block diagram of a storage device according to the second embodiment. [Figure 10] FIG. 10 is an enlarged circuit diagram of a memory cell according to the second embodiment. [Figure 11] FIG. 11 is a plan view of a memory cell MC in the second embodiment. [Figure 12] FIG. 12 is a plan view of a memory cell MC in the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along the line AA in FIGS. [Figure 14] FIG. 14 is a cross-sectional view taken along the line AA in FIGS. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present disclosure is not limited to the described configurations and numerical values. In each drawing, the same components are given the same reference numerals, and duplicate explanations may be omitted as appropriate. The size, positional relationship, etc. of each component shown in each drawing may be exaggerated to facilitate understanding of the invention.

[0010] (First embodiment) 1 is a block diagram of a memory device according to the first embodiment. As shown in FIG. 1, a memory circuit 100 according to the first embodiment includes memory cells MC, a read circuit 24, a write circuit 25, and a control circuit 29.

[0011] The memory cell MC includes transistors T1 and T2 and a ferroelectric capacitor F1. The transistor T1 is, for example, an NMOSFET (N Metal Oxide Semiconductor Field Effect Transistor). The transistor T1 has a source S1 (first terminal), a drain D1 (second terminal), and a gate G1 (control terminal). The source S1 is electrically connected to a ground line SL. The ground line SL is electrically connected to a first power supply VSS. The drain D1 is electrically connected to a bit line BL. The gate G1 is electrically connected to a node N1.

[0012] The transistor T2 is, for example, an NMOSFET. The transistor T2 has a source S2, a drain D2, and a gate G2. The source S2 is electrically connected to the plate line PL. The drain D2 is electrically connected to the node N1. The gate G2 is electrically connected to the write word line wWL. One end of the ferroelectric capacitor F1 is electrically connected to the word line W1, and the other end is electrically connected to the node N1.

[0013] The read circuit 24 reads data written in the ferroelectric capacitor F1 from the bit line BL. The bit line BL is connected to a power supply line DL via a resistor RL. The power supply line DL is supplied with the voltage of the second power supply VDD. The voltage of the second power supply VDD is higher than the voltage of the first power supply VSS. The voltage of a node N2 between the resistor RL and the bit line BL is the output voltage VOUT.

[0014] A write word line wWL and a plate line PL are connected to the write circuit 25. The write circuit 25 writes data into the memory cell MC by applying a voltage to the write word line wWL that turns on the transistor T2 and applying a write voltage to the plate line PL.

[0015] The control circuit 29 controls the read circuit 24 and the write circuit 25. When reading data from a memory cell MC, the control circuit 29 sets the word line WL to a high level and sets the write word line wWL and the plate line PL to a low level or open. The read circuit 24 reads the data written in the memory cell MC based on the output voltage VOUT.

[0016] When writing data to the memory cell MC, the control circuit 29 sets the word line WL to high level. The write circuit 25 sets the write word line wWL to high level and applies a voltage corresponding to the data to be written to the plate line PL.

[0017] 2(a) to 2(c) are diagrams showing a method for reading data from a memory cell. 2(a) and 2(b) are diagrams showing cross sections of a transistor T1 and a ferroelectric capacitor F1. 2(a) and 2(b) show the states in which a bit B0 ("0") and a bit B1 ("1") are written to a memory cell MC, respectively. 2(c) is a diagram showing the drain current ID versus the voltage VW of the word line WL.

[0018] As shown in FIGS. 2(a) and 2(b), the transistor T1 includes a semiconductor substrate 10, a source region 11, a drain region 12, a gate insulating film 13, and a gate electrode 14. The semiconductor substrate 10 (or a well in the semiconductor substrate 10) is p-type. The source region 11 and the drain region 12 are n-type. The gate electrode 14 is provided on the semiconductor substrate 10 between the source region 11 and the drain region 12, with the gate insulating film 13 sandwiched therebetween. A source voltage VS is applied to the source region 11 from a ground line SL, and a drain voltage VD is applied to the drain region 12 from a bit line BL. The gate electrode 14 is electrically connected to a node N1. The voltage at the node N1 corresponds to a gate voltage VG.

[0019] The ferroelectric capacitor F1 has a ferroelectric film 20 and electrodes 21 and 22. The electrodes 21 and 22 sandwich the ferroelectric film 20. The electrode 21 is electrically connected to a node N1. A voltage VW is applied to the electrode 22 from a word line WL. The voltage between the ground line SL and the node N1 is a gate voltage VG, and the voltage between the node N1 and the word line WL is a voltage VF applied to the ferroelectric capacitor F1.

[0020] As shown in FIG. 2(a), when bit B0 is written to memory cell MC, polarization direction 23 of ferroelectric film 20 is from electrode 22 to electrode 21. At this time, polarization is -P, and the ferroelectric film 20 is polarized positively on the electrode 21 side and negatively on the electrode 22 side. At this time, the potential of node N1 is determined by the charge stored in the gate capacitance of transistor T1 and the polarization of ferroelectric capacitor F1. Gate voltage VG is VG0, and the voltage applied to ferroelectric capacitor F1 is voltage VF0. VW=VG0+VF0.

[0021] As shown in FIG. 2(b), when bit B1 is written to memory cell MC, polarization direction 23 of ferroelectric film 20 is from electrode 21 to electrode 22. At this time, polarization is +P, and the ferroelectric film 20 is polarized positively on the electrode 22 side and negatively on the electrode 21 side. At this time, gate voltage VG is VG1, and the voltage applied to ferroelectric capacitor F1 is voltage VF1. VW=VG1+VF1. Voltage VG1 becomes lower than VG0, and voltage VF1 becomes higher than VF0.

[0022] As shown in Figure 2(c), when the drain voltage VD is kept constant and the word line voltage VW is increased, the drain current ID of transistor T1 increases. Even at the same voltage VW, the gate voltage VG of bit B0 is higher than that of bit B1. Therefore, in bit B0, the drain current ID begins to flow at a low voltage VW, while in bit B1, the drain current ID does not flow until the voltage VW is high.

[0023] 3(a) to 4(b) are diagrams showing polarization P versus voltage VF. The thin solid line 50 is a curve showing polarization P versus voltage VF applied to ferroelectric capacitor F1. The polarization P when voltage VF is 0V corresponds to bits B0 and B1. When voltage VF is 0V and bit B0 is in the state, polarization P is negative. As voltage VF is applied positive from the state of bit B0, polarization P increases and becomes positive. Then, as voltage VF is lowered, polarization P decreases. Even when voltage VF becomes 0V, polarization P remains positive, and bit B1 is in the state. When voltage VF is applied negative from the state of bit B1, polarization P decreases and becomes negative. Then, when voltage VF is returned to 0V, bit B0 is in the state.

[0024] The values ​​of the gate voltage VG and the voltage VF when the voltage VW is applied to the word line WL in the states of the bits B0 and B1 will be described.

[0025] 3(a), the thick dashed line 51 indicates the gate capacitance CG of transistor T1 versus gate voltage VG. To calculate voltages VG0 and VF0 when voltage VW is applied to word line WL in the state of bit B0, the graph of gate capacitance CG is plotted with voltage VF at voltage VW and polarization P at bit B0 as the origin, and the negative direction of voltage VF is taken as gate voltage VG. As gate voltage VG increases, gate capacitance CG increases.

[0026] In the state of bit B0, when a voltage VW is applied to the word line WL, the voltage VF0 and gate voltage VG0 applied to the ferroelectric capacitor F1 are the voltages when the charge stored in the gate capacitance CG and the polarization P are balanced. The charge stored in the gate capacitance CG is proportional to the gate capacitance CG. Here, it is assumed that the gate capacitance CG and the charge are equal. At the point where the charge stored in the gate capacitance CG and the polarization P match, i.e., at point 52 where solid line 50 and dashed line 51 intersect, the voltage VF is voltage VF0, and the voltage VG is voltage VG0.

[0027] 3(b), the voltages VG1 and VF1 are determined when a voltage VW is applied to the word line WL in the state of bit B1. The graph of gate capacitance CG is plotted with voltage VF at voltage VW and polarization P at bit B1 as the origin, and the negative direction of voltage VF is taken as gate voltage VG. At point 52, where solid line 50 and dashed line 51 intersect, voltage VF is voltage VF1, and voltage VG is voltage VG1.

[0028] As shown in FIGS. 3(a) and 3(b), the voltage VG1 is lower than VG0, and the voltage VF1 is higher than VF0.

[0029] In Figure 1, when reading data written to the ferroelectric capacitor F1, the word line WL goes high, and the transistor T1 and resistor RL are connected in series between the ground line SL and the power supply line DL. When the data in the ferroelectric capacitor F1 is bit B0, the drain current ID of the transistor T1 is large, so the voltage VOUT at the node N1 is low. When the data in the ferroelectric capacitor F1 is bit B1, the drain current ID of the transistor T1 is small, so the voltage VOUT at the node N1 is high. Therefore, the data in the ferroelectric capacitor F1 can be read by determining whether the voltage VOUT is higher or lower than the threshold Vt.

[0030] In FIG. 3(a), when bit B0 is read, the polarization P is at point 52 in the direction indicated by arrow 53, where it becomes smaller.

[0031] As shown in Figure 4(a), a dashed line 51 is drawn, with the bit B0 point as the origin, to plot the gate capacitance CG against the voltage VG. When the voltage of the word line WL becomes 0V, a negative voltage VF is applied to the ferroelectric capacitor F1, as indicated by arrow 53, due to the charge stored in the gate capacitance, and this reaches point 54 on the dashed line 51. When the voltage VF returns to 0V from point 54, the polarization P at bit B0 becomes slightly smaller.

[0032] As shown in Figure 4(b), when bit B0 is repeatedly read, the polarization P gradually decreases in a loop 55. As a result, the polarization P of bit B0 decreases as indicated by arrow 56, and becomes positively polarized as in bit B0d. This may make it impossible to read bit B0.

[0033] As shown in FIG. 3(b), when bit B1 is read, the voltage VF is applied in the direction in which the polarization P increases, as indicated by the arrow 56, so the problem that occurs with bit B0 does not occur.

[0034] FIG. 5 is a diagram showing the voltage VOUT and current ID versus the number of reads. In FIG. 5, the voltages VOUT when bits B0 and B1 are first written are V0 and V1, respectively. The voltage VOUT when bit B0 is read increases as the number of reads increases. On the other hand, the voltage VOUT when bit B1 is read remains almost unchanged even when the number of reads increases.

[0035] The threshold value Vt (first threshold value) is a threshold voltage that the read circuit 24 uses to determine whether the data written in the ferroelectric capacitor F1 is bit B0 or ​​B1. The range A0 (first range) and A1 (second range) are separated by the threshold value Vt. When the voltage VOUT is within the range A0, the read circuit 24 determines that the data written in the ferroelectric capacitor F1 is bit B0, and when the voltage VOUT is within the range A1, the read circuit 24 determines that the data written in the ferroelectric capacitor F1 is bit B1.

[0036] The threshold value VRW (second threshold value) is a threshold voltage that determines whether the write circuit 25 rewrites the bit B0. The threshold value VRW is located within the range A0. The write circuit 25 writes the bit B0 to the ferroelectric capacitor F1 when the voltage VOUT is in a range A2 (third range) between the threshold value Vt and VRW.

[0037] When the read circuit 24 reads data written in the ferroelectric capacitor F1 using the current ID flowing through the bit line BL, the current ID decreases as the voltage VOUT increases. The voltages V0 and V1 correspond to the currents I0 and I1, respectively, and the thresholds Vt and VRW correspond to the thresholds It and IRW, respectively.

[0038] Fig. 6 is a flowchart showing a read operation in the memory device according to the first embodiment. The read circuit 24 is a dedicated circuit as shown in Figs. 7 and 8, which will be described later. Fig. 6 is used to explain the operation of the read circuit 24.

[0039] 6, when performing a read operation, the control circuit 29 sets the word line WL to high level and sets the write word line wWL and plate line PL to open or low level. The read circuit 24 measures the voltage VOUT (step S10).

[0040] Next, the readout circuit 24 determines whether the voltage VOUT is equal to or lower than the threshold Vt (step S11). If the result is No, the readout circuit 24 determines that the bit is B1 (step S13). The readout circuit 24 outputs the bit B1 to the control circuit 29 and ends the readout operation.

[0041] If the answer is Yes in step S11, the read circuit 24 determines that it is bit B0 (step S12). The read circuit 24 outputs bit B0 to the control circuit 29. Next, the read circuit 24 determines whether the voltage VOUT is equal to or greater than the threshold VRW (step S14). If the answer is No, the process ends. If the answer is Yes, the write circuit 25 rewrites bit B0 to the ferroelectric capacitor F1 (step S15). Specifically, the read circuit 24 sends a rewrite signal for bit B0 to the control circuit 29. The control circuit 29 instructs the write circuit 25 to rewrite bit B0. The write circuit 25 rewrites bit B0 to the ferroelectric capacitor F1. Thereafter, the read operation ends.

[0042] 7 is a circuit diagram showing a second circuit example of the read circuit in the first embodiment. The first circuit example is an example of a circuit that reads data written in the ferroelectric capacitor F1 using the voltage of the bit line BL.

[0043] 7, the readout circuit 24 includes comparators 42 and 43, an AND circuit 44, and an inverting circuit 45. The voltage VOUT at a node N1 between the bit line BL and the resistor RL is input to the negative input terminal of the comparator 42. A threshold Vt is input to the positive input terminal of the comparator 42. As a result, when the voltage VOUT is equal to or lower than the threshold Vt, the output signal of the comparator 42 is at a high level, and when the voltage VOUT is higher than the threshold Vt, the output signal of the comparator 42 is at a low level.

[0044] The output of the comparator 42 is output as a read bit RB via an inverting circuit 45. When the voltage VOUT is equal to or lower than the threshold Vt, the bit RB becomes bit B0 (low level), and when the voltage VOUT is higher than the threshold Vt, the bit RB becomes bit B1 (high level).

[0045] The voltage VOUT is input to the positive input terminal of the comparator 43. The threshold value VRW is input to the negative input terminal of the comparator 43. As a result, when the voltage VOUT is lower than the threshold value VRW, the output signal of the comparator 43 is at a low level, and when the voltage VOUT is equal to or higher than the threshold value VRW, the output signal of the comparator 43 is at a high level.

[0046] The output signals of the comparators 42 and 43 are input to the AND circuit 44. The AND circuit 44 outputs a rewrite signal RW. When the voltage VOUT is equal to or lower than the threshold Vt and equal to or higher than the threshold VRW, the write signal RW goes high; otherwise, the write signal RW goes low. When the write signal RW is high, the control circuit 29 instructs the write circuit 25 to rewrite bit B0.

[0047] 8 is a circuit diagram showing a circuit example 1 of the read circuit in the first embodiment. Circuit example 2 is an example of a circuit that reads out data written in the ferroelectric capacitor F1 using a current ID flowing through the bit line BL.

[0048] As shown in FIG. 8, the readout circuit 24 includes current sources 46 and 47 and resistors R1 to R4 in addition to the components of circuit example 1. It does not include resistor RL. Resistors R1 and R3 are connected in parallel between the bit line BL and the second power supply VDD. Resistors R1 and R3 are commonly connected to node N2. The drain current ID of transistor T1 flowing through the bit line BL is branched into current ID1 flowing through resistor R1 and current ID2 flowing through resistor R3. When the resistance values ​​of resistors R1 and R3 are equal, ID1=ID2=ID / 2.

[0049] The node N2 is connected to the negative input terminal of the comparator 42. The resistor R2 and the current source 46 are connected in series between the first power supply VSS and the second power supply VDD. The node N3 between the resistor R2 and the current source 46 is connected to the positive input terminal of the comparator 42. The current of the current source 46 has a threshold value It / 2.

[0050] For example, if the resistance values ​​of resistors R1 and R2 are the same, when current ID1 is equal to or greater than threshold value It / 2, the output signal of comparator 42 becomes high level, and when current ID1 is smaller than threshold value It / 2, the output signal of comparator 42 becomes low level.

[0051] The node N2 is connected to the positive input terminal of the comparator 43. The resistor R4 and the current source 47 are connected in series between the first power supply VSS and the second power supply VDD. The node N4 between the resistor R4 and the current source 47 is connected to the negative input terminal of the comparator 43. The current of the current source 47 is a threshold IRW / 2.

[0052] For example, assume that resistors R3 and R4 have the same resistance value. In this case, when current ID2 is greater than threshold value IRW / 2, the output signal of comparator 43 is at low level, and when current ID2 is equal to or less than threshold value IRW / 2, the output signal of comparator 43 is at high level. Other operations are the same as in circuit example 1, and therefore will not be described here.

[0053] As in the circuit example 2, the read circuit 24 may generate the bit RB and the restore signal RW based on the current flowing through the bit line BL.

[0054] According to the first embodiment, the read circuit 24 determines that the data written to the ferroelectric capacitor F1 is bit B0 (first bit) when the voltage VOUT (or current ID) of the bit line BL is within the range A0 (first range) in FIG. 5. The read circuit 24 determines that the data written to the ferroelectric capacitor F1 is bit B1 (second bit) when the voltage VOUT (or current ID) is within the range A1 (second range) (steps S11 to S13 in FIG. 6). The write circuit 25 writes bit B0 to the ferroelectric capacitor F1 when the voltage VOUT (or current ID) is within the range A2 (third range) between the threshold Vt (or It) and the threshold VRW (or IRW) (steps S14 and S15 in FIG. 6). As a result, even if the number of read operations increases and the voltage VOUT of bit B0 increases (or the current ID decreases), bit B0 is rewritten before the voltage VOUT (or current ID) of bit B0 reaches the threshold Vt (or It), as shown in Figure 5. This makes it possible to suppress deterioration of the polarization state even when read operations are repeated.

[0055] In FIG. 5, if range A2 is too small, bit B0 may be erroneously determined to be bit B1. From this perspective, |Vt-VRW| is preferably 0.1 times or more, more preferably 0.2 times or more, of |V1-Vt|. Also, |Vt-VRW| is preferably 0.1 times or more, more preferably 0.2 times or more, of |Vt-V0|. If range A2 is too large, rewriting will occur even if the number of times bit B0 is read is small. From this perspective, |Vt-VRW| is preferably 0.9 times or less, more preferably 0.8 times or less, of |Vt-V0|.

[0056] Similarly, when the read circuit 24 uses the current ID to read data, |It - IRW| is preferably 0.1 times or more, more preferably 0.2 times or more, of |I1 - It|. Also, |It - IRW| is preferably 0.1 times or more, more preferably 0.2 times or more, of |It - I0|. |It - IRW| is preferably 0.9 times or less, more preferably 0.8 times or less, of |It - I0|.

[0057] As in step S14 of FIG. 6, the read circuit 24 determines whether the voltage VOUT (or current ID) of the bit line BL is within range A2. As in step S15, the write circuit 25 writes bit B0 to the ferroelectric capacitor F1 when it is determined that the voltage VOUT (or current ID) is within range A2. The read circuit 24 does not write either bit B0 or ​​B2 to the ferroelectric capacitor F1 when it is determined that the voltage VOUT (or current ID) is not within range A2. This makes it possible to prevent bit B0 from becoming unable to be read even when the read operation is repeated.

[0058] The transistor T1 may be a transistor other than an NMOSFET. For example, the transistor T1 may be a PMOSFET. When the transistor T1 is an NMOSFET, the source S1, the drain D1, and the gate G1 correspond to the first terminal, the second terminal, and the control terminal, respectively.

[0059] When the transistor T1 is an NMOSFET, the voltage in the range A0 becomes lower than the voltage of the threshold Vt, as shown in Fig. 5. As a result, when the polarization of the bit B0, which deteriorates with the number of reads, becomes smaller, the write circuit 25 can rewrite the bit B0.

[0060] 7, the read circuit 24 has a resistor RL (element). One end of the resistor RL is connected to the bit line BL, and the other end is connected to a second power supply VDD. The read circuit 24 can generate a bit RB and a rewrite signal RW based on a voltage VOUT at a node N1 between the resistor RL and the bit line BL.

[0061] 8, the read circuit 24 may read the written data using a current ID flowing through the bit line BL. In this case, the range of the current ID1 corresponding to the bit B0 whose polarization deteriorates with an increase in the number of reads is larger than the current of the threshold It (first threshold) as shown in FIG.

[0062] The read circuit 24 reads the written data using a current ID that flows from the second power supply VDD to the first power supply VSS via the transistor T1, thereby generating a bit RB and a restore signal RW based on the current ID.

[0063] The write circuit 25 may apply the write voltage to the ferroelectric capacitor F1 via the transistor T1 without providing the transistor T2. In this case, the voltage is divided between the transistor T1 and the ferroelectric capacitor F1. Therefore, in order to apply a desired voltage to the ferroelectric capacitor F1, the write voltage must be high.

[0064] Therefore, a transistor T2 is provided as a switch, with one end connected to the plate line PL and the other end connected to node N1. A write circuit 25 turns on the switch when writing data to the ferroelectric capacitor F1. This allows the write voltage to be applied directly to the electrode 21 of the ferroelectric capacitor F1. Therefore, the write voltage can be lowered compared to when the write voltage is applied to the ferroelectric capacitor F1 via the transistor T1. When the transistor T2 is an NMOSFET, the source S2, drain D2, and gate G2 correspond to one end, the other end, and the control terminal of the switch, respectively.

[0065] (Second embodiment) The second embodiment is an example of a storage device using the first embodiment. Fig. 9 is a block diagram of the storage device according to the second embodiment. As shown in Fig. 9, the storage device 102 according to the second embodiment includes a read circuit 24, a write circuit 25, a memory array 26, a row decoder 27, a column decoder 28, and a control circuit 29.

[0066] The memory array 26 includes a plurality of memory cells MC. The memory cells MC are arranged in a matrix. Word lines WL1 to WLn and plate lines PL1 to PLn extend in the row direction. Bit lines BL1 to BLm and write word lines wWL1 to wWLm extend in the column direction. A word line WLi, a plate line PLi, a bit line BLj, and a write word line wWLj are connected to the memory cell MC in the i-th row (an integer from 1 to n) and j-th column (an integer from 1 to m).

[0067] The row decoder 27 selects a word line WLi and a plate line PLi of a desired row address in response to instructions from the control circuit 29. The column decoder 28 selects a bit line BLj and a write word line wWLj of a desired column address in response to instructions from the control circuit 29. The read circuit 24 is connected to the bit line BLj selected by the column decoder 28. The write circuit 25 is connected to the bit line BLj and the write word line wWLj selected by the column decoder 28. The operations of the read circuit 24, the write circuit 25, and the control circuit 29 are the same as those in the first embodiment.

[0068] 10 is an enlarged circuit diagram of a memory cell in the second embodiment. As shown in FIG. 10, the source, drain, and gate of transistor T1 of each memory cell MC are connected to the ground line SL, bit line BL1 or BL2, and node N1, respectively. The source, drain, and gate of transistor T2 are connected to node N1, plate line PL1 or PL2, and write word line wWL1 or wWL2, respectively. One end and the other end of ferroelectric capacitor F1 are connected to word line WL1 or WL2 and node N1, respectively.

[0069] 11 and 12 are plan views of a memory cell MC in the second embodiment. FIG. 11 shows word lines WL, plate lines PL, bit lines BL, ground lines SL, write word lines wWL, and plugs P1 to P6. FIG. 12 shows transistors T1 and T2, a ferroelectric capacitor F1, and plugs P1 to P6. FIG. 13 is a cross-sectional view taken along line AA in FIGS. 11 and 12. FIG. 13 shows cross sections of both plugs P3 and P4. FIG. 14 is a cross-sectional view taken along line BB in FIGS. 11 and 12.

[0070] 11 to 14, the thickness direction of the semiconductor substrate 10 is the Z direction, the extension direction of the word lines WL and plate lines PL is the X direction, and the extension direction of the bit lines BL and write word lines wWL is the Y direction.

[0071] As shown in FIGS. 11 to 14, a well 10A is provided in a semiconductor substrate 10. The semiconductor substrate 10 is, for example, a single-crystal silicon substrate. The well 10A is a p-type diffusion region. An element isolation oxide film 15 is provided so as to surround the well 10A. The element isolation oxide film 15 is, for example, an STI (Shallow Trench Isolation) film.

[0072] A source region 11 and a drain region 12 are provided in the well 10A. The source region 11 and the drain region 12 are n-type diffusion regions. A gate electrode 14 is provided on the well 10A between the source region 11 and the drain region 12, with a gate insulating film (not shown) sandwiched therebetween. The gate electrode 14 is, for example, a polysilicon film or a metal film. Sidewalls 16 are provided on both sides of the gate electrode 14. The sidewalls 16 are, for example, insulating films such as silicon oxide.

[0073] The source region 11, drain region 12, and gate electrode 14 of transistor T1 correspond to the source S1, drain D1, and gate G1 of transistor T1, respectively. The source region 11, drain region 12, and gate electrode 14 of transistor T2 correspond to the source S2, drain D2, and gate G2 of transistor T2, respectively.

[0074] The wiring 14A is provided on the element isolation oxide film 15. The wiring 14A corresponds to the write word line wWL. The wiring 14A and sidewalls 16 on both sides of the wiring 14A are formed simultaneously with the gate electrode 14 and sidewalls 16 on both sides of the gate electrode.

[0075] A cover film 30A and an interlayer insulating film 30B are provided to cover the transistors T1, T2, and the wiring 14A. A plug 37 is provided that penetrates the cover film 30A and the interlayer insulating film 30B. A cover film 31A and an interlayer insulating film 31B are provided on the interlayer insulating film 30B. A wiring 35 is provided that penetrates the cover film 31A and the interlayer insulating film 31B. A cover film 32A and an interlayer insulating film 32B are provided on the interlayer insulating film 31B. A plug 38 is provided that penetrates the cover film 32A and the interlayer insulating film 32B. Note that the plug 38 (P6) penetrates not only the cover film 32A and the interlayer insulating film 32B but also the cover film 31A and the interlayer insulating film 31B.

[0076] A ferroelectric capacitor F1 is provided on the interlayer insulating film 32B. An electrode 21 is provided on the interlayer insulating film 32B. A ferroelectric film 20 is provided on the electrode 21. The electrode 21 is provided on the ferroelectric film 20. The ferroelectric film 20 includes a ferroelectric oxide having a perovskite crystal structure, such as PZT (Pb(Zr,Ti)O3) or SBT (SrBi2Ta2O9), or HZO (HfZrO2). The electrodes 21 and 22 are conductive films.

[0077] A cover film 33A and an interlayer insulating film 33B are provided to cover the ferroelectric capacitor F1. A plug 39 is provided to penetrate the cover film 33A and the interlayer insulating film 33B. A wiring 36 is provided on the interlayer insulating film 33B. A cover film 34 is provided to cover the wiring 36.

[0078] The cover films 30A, 31A, 32A, and 33A are insulating films such as silicon nitride films. The interlayer insulating films 30B, 31B, 32B, and 33B and the cover film 34 are insulating films such as silicon oxide films. The wirings 35 and 36 and the plugs 37, 38, and 39 are conductive films such as copper films.

[0079] The wiring 35 forms the bit line BL, the ground line SL, and the node N1. The wiring 36 forms the word line WL and the plate line PL. The plugs P1 to P3 and P5 are formed by the plug 37. The plug P3A is formed by the plug 38. The plug P4 is formed by the plug 39. The plug P6 is formed by the plugs 37, 38, and 39.

[0080] The source region 11 (source S1) of the transistor T1 is connected to the wiring 35 (ground line SL) via a plug P2. The drain region 12 (drain D1) of the transistor T1 is connected to the wiring 35 (bit line BL) via a plug P1. The gate electrode 14 (gate G1) of the transistor T1 is connected to the wiring 35 (node ​​N1) via a plug P3.

[0081] An electrode 21 of the ferroelectric capacitor F1 is connected to a wiring 35 (node ​​N1) via a plug P3 A. An electrode 22 of the ferroelectric capacitor F1 is connected to a wiring 36 (word line WL) via a plug P4.

[0082] The source region 11 (source S2) of the transistor T2 is connected to the wiring 36 (plate line PL) via a plug P6. The drain region 12 (drain D2) of the transistor T2 is connected to the wiring 35 (node ​​N1) via a plug P5. The gate electrode 14 (gate G2) of the transistor T2 is connected to the wiring 14A (write word line wWL).

[0083] In the second embodiment, as shown in FIG. 9, a memory array 26 includes a plurality of memory cells MC. A read circuit 24 determines whether the data written to a selected memory cell MC among the plurality of memory cells MC is bit B0 or ​​B1. A write circuit 25 writes bit B0 to the ferroelectric capacitor F1 of the selected memory cell MC when the voltage VOUT or current ID of the bit line BL is within range A2 of FIG. 5. This allows bit B0 to be written to a memory cell MC among the plurality of memory cells MC in which bit B0 has deteriorated.

[0084] Although the present disclosure has been described above based on the embodiments, the present invention is not limited to the requirements set forth in the above embodiments. These requirements can be changed without departing from the spirit of the present disclosure, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0085] 23 Polarization direction 24 Readout circuit 25 Write circuit B0, B1 bits T1 and T2 transistors F1 ferroelectric capacitor BL bit line WL Word Line SL ground wire PL plate line wWL Write word line A0, A1, A2 range Vt, VRW, It, IRW thresholds

Claims

1. a transistor having a first terminal connected to a first power supply, a second terminal connected to a bit line, and a control terminal; a ferroelectric capacitor having one end connected to a control terminal of the transistor and the other end connected to a word line; a write circuit that writes data into the ferroelectric capacitor by applying a write voltage between one end and the other end of the ferroelectric capacitor; a read circuit that reads data written in the ferroelectric capacitor from the bit line; Equipped with the read circuit determines the written data to be a first bit when the voltage or current of the bit line is within a first range of a first range and a second range separated by a first threshold value, and determines the written data to be a second bit when the voltage or current of the bit line is within the second range; The write circuit writes the first bit to the ferroelectric capacitor when the voltage or current on the bit line is within a third range between the first threshold and a second threshold within the first range.

2. the read circuit determines whether the voltage or current of the bit line is within the third range; 2. The memory device according to claim 1, wherein the write circuit writes the first bit to the ferroelectric capacitor when it is determined that the voltage or current of the bit line is within the third range, and writes neither the first bit nor the second bit to the ferroelectric capacitor when it is determined that the voltage or current of the bit line is not within the third range.

3. the transistor is an NMOSFET, the read circuit reads the written data using the voltage of the bit line; the first range of voltages is less than the first threshold voltage; 3. The storage device according to claim 1.

4. the read circuit has an element having one end connected to the bit line and the other end connected to a second power supply; the voltage of the second power supply is higher than the voltage of the first power supply; 3. The memory device of claim 2, wherein the voltage on the bit line is a voltage at a node between the element and the bit line.

5. the transistor is an NMOSFET, the read circuit reads the written data using a current flowing through the bit line; the first range of current is greater than the first threshold current; 3. The storage device according to claim 1.

6. the current flowing through the bit line is a current flowing from a second power supply to the first power supply via the transistor, 6. The storage device according to claim 5, wherein the voltage of said second power supply is higher than the voltage of said first power supply.

7. a switch having one end to which a write voltage is supplied and the other end connected to a node between a control terminal of a transistor and one end of the ferroelectric capacitor; 3. The storage device according to claim 1, wherein the write circuit turns on the switch when writing data to the ferroelectric capacitor.

8. a plurality of memory cells each comprising the ferroelectric capacitor and the transistor; the read circuit determines whether the written data is a first bit or a second bit for a selected memory cell from among the plurality of memory cells; 3. The memory device according to claim 1, wherein said write circuit writes said first bit into said ferroelectric capacitor for said selected memory cell when the voltage or current of said bit line is within said third range.

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