Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor in which improvement of humidity resistance is attained.SOLUTION: In a multilayer ceramic capacitor 100, external electrodes 120 and 130 are provided on a first end face 115 and a second end face 116 and connected with a plurality of internal electrode layers 151 and the like. In a central part of an element assembly part in a length direction, on a cross section in a lamination direction and a width direction W, a maximum displacement amount in the plurality of internal electrode layers in the width direction W is 5 μm or less. Both edge parts 155 in each of the plurality of internal electrode layers in the width direction W consist of two straight line parts 155a and two curved line parts 155b. The two straight line parts extend linearly in the longer direction L at an interval in the width direction W. The two curved line parts 155b are connected to the two straight line parts 155a. The two curved line parts 155b are bent at a fixed curvature so as to approach each other in the width direction W as separated from the two straight line parts 155a in the length direction L.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2017-147429 (Patent Document 1) is a prior art document that discloses the configuration of a multilayer ceramic capacitor. The multilayer ceramic capacitor described in Patent Document 1 includes a laminated portion having a substantially rectangular parallelepiped shape in which ceramic layers and internal electrodes are alternately stacked in multiple layers, side margin portions that cover a pair of side surfaces in the width direction of the laminated portion, and a joint portion that is disposed between the laminated portion and the side margin portions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-147429 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, multilayer ceramic capacitors have become smaller and larger in capacitance. Specifically, while the external dimensions of multilayer ceramic capacitors are becoming smaller, the area occupied by the internal electrode layers relative to the external dimensions is increasing, which can lead to thinner side margins that sandwich the stacked internal electrode layers in the width direction.

[0005] When the side margins are thinned in this manner, the path for moisture to penetrate from the pair of widthwise side surfaces of the multilayer ceramic capacitor via the longitudinal end faces of the multilayer ceramic capacitor to the internal electrode layers exposed at these end faces becomes shorter, which may result in a decrease in the moisture resistance of the multilayer ceramic capacitor.

[0006] SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multilayer ceramic capacitor with improved moisture resistance. [Means for solving the problem]

[0007] A multilayer ceramic capacitor according to the present invention comprises an element body and external electrodes. The element body includes a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and has first and second main surfaces facing each other in the stacking direction, first and second side surfaces facing each other in a width direction perpendicular to the stacking direction, and first and second end faces facing each other in a length direction perpendicular to the stacking direction and the width direction. The external electrodes are provided on each of the first end faces and the second end faces and connected to the plurality of internal electrode layers. In a cross section along the stacking direction and the width direction at a central portion of the element body in the length direction, the maximum deviation in the width direction of the plurality of internal electrode layers is 5 μm or less. Both edge portions in the width direction of each of the plurality of internal electrode layers are composed of two straight lines and two curved lines. The two straight lines extend linearly in the length direction with a gap between them in the width direction. The two curved lines are connected to the two straight lines, respectively. In addition, the two curved portions are curved at a constant curvature so as to approach each other in the width direction as they move away from the two straight portions in the length direction. In the multilayer ceramic capacitor according to the present invention, connection ends located at ends in the length direction of each of the plurality of internal electrode layers and connected to the external electrodes are connected to the two curved portions, and the maximum amount of deviation in the width direction at the connection ends of the plurality of internal electrode layers on the first end face and the second end face is 5 μm or less.

[0008] In the multilayer ceramic capacitor according to the present invention, the body portion may include a ridge portion where two adjacent faces among the first side surface, the second side surface, the first end face, and the second end face intersect, and in this case, the curvature of each of the two curved portions may be smaller than the curvature of the ridge portion.

[0009] In the multilayer ceramic capacitor according to the present invention, in the element body, each of side margin portions located between the first side surface and the plurality of internal electrode layers and between the second side surface and the plurality of internal electrode layers in the width direction may be composed of a plurality of layers stacked in the width direction.

[0010] In the multilayer ceramic capacitor according to the present invention, the body portion may include a ridge portion where two adjacent surfaces from among the first side surface, the second side surface, the first end surface, and the second end surface intersect. In this case, an innermost layer located innermost in the width direction among the multiple layers constituting each of the side margin portions may be provided along the multiple internal electrode layers. In this case, the curvature of the surface of the innermost layer located outermost in the width direction may be greater than the curvature of each of the two curved portions and smaller than the curvature of the ridge portion.

[0011] In the multilayer ceramic capacitor according to the present invention, Mg may be segregated at both edge portions in the width direction of each of the plurality of internal electrode layers. [Effects of the Invention]

[0012] According to the present invention, it is possible to provide a multilayer ceramic capacitor with improved moisture resistance. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a perspective view schematically illustrating the appearance of a multilayer ceramic capacitor according to an embodiment. [Figure 2]1 is a perspective view schematically showing an element body of a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 3] FIG. 3 is an exploded perspective view for schematically explaining the configuration of the element body shown in FIG. 2. [Figure 4] FIG. 2 is a schematic cross-sectional view taken along line IV-IV shown in FIG. [Figure 5] FIG. 2 is a schematic cross-sectional view taken along line VV shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along line VI-VI shown in FIG. [Figure 7] FIG. 7 is a schematic enlarged cross-sectional view of the vicinity of the connection end shown in FIG. 6. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9] FIG. 9 is a schematic enlarged cross-sectional view of the vicinity of the connection end shown in FIG. 8. [Figure 10] 5 is a schematic cross-sectional view illustrating a shift in the width direction of opposing portions of internal electrode layers in the multilayer ceramic capacitor according to the embodiment. FIG. [Figure 11] 5 is a schematic cross-sectional view illustrating a shift in the width direction of lead portions of internal electrode layers in the multilayer ceramic capacitor according to the embodiment. FIG. [Figure 12] FIG. 2 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to an embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view of a multilayer ceramic capacitor according to a first modified example. [Figure 14] FIG. 14 is a schematic enlarged cross-sectional view of the vicinity of the connection end shown in FIG. [Figure 15] FIG. 10 is a schematic cross-sectional view of a multilayer ceramic capacitor according to a second modified example. [Figure 16] FIG. 10 is a schematic cross-sectional view of a multilayer ceramic capacitor according to a second modified example. [Figure 17] 17 is a schematic enlarged plan view for explaining the positional relationship between the first internal electrode layer shown in FIG. 15 and the second internal electrode layer shown in FIG. 16. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiments shown below, the same or common parts are denoted by the same reference numerals in the drawings, and the description thereof will not be repeated. In the drawings, the length direction of the element body is indicated by L, the width direction of the element body is indicated by W, and the stacking direction of the element body is indicated by T. The element body will be described in detail later.

[0015] (Embodiment) (A. Configuration of Multilayer Ceramic Capacitor) FIG. 1 is a perspective view schematically showing the appearance of a multilayer ceramic capacitor according to an embodiment. FIG. 2 is a perspective view schematically showing the element body of the multilayer ceramic capacitor according to the embodiment. FIG. 3 is an exploded perspective view for schematically explaining the configuration of the element body shown in FIG. 2. FIG. 4 is a schematic cross-sectional view taken along line IV-IV shown in FIG. 1. FIG. 5 is a schematic cross-sectional view taken along line V-V shown in FIG. 1. The configuration of the multilayer ceramic capacitor 100 according to the present embodiment will be described with reference to FIGS. 1 to 5.

[0016] As shown in FIGS. 1 to 5, the multilayer ceramic capacitor 100 according to the present embodiment includes an element body 110 and external electrodes. The multilayer ceramic capacitor 100 includes a first external electrode 120 and a second external electrode 130 as external electrodes.

[0017] The element body 110 has a substantially rectangular parallelepiped shape. The element body 110 has a first main surface 111 and a second main surface 112 that face each other in the stacking direction T, a first side surface 113 and a second side surface 114 that face each other in the width direction W orthogonal to the stacking direction T, and a first end surface 115 and a second end surface 116 that face each other in the length direction L orthogonal to the stacking direction T and the width direction W.

[0018] The element body 110 includes multiple corners 110a. The corners 110a are portions where three surfaces of the element body 110 intersect. That is, the multiple corners 110a are formed at portions where three adjacent surfaces among the first main surface 111, the second main surface 112, the first side surface 113, the second side surface 114, the first end surface 115, and the second end surface 116 intersect. It is preferable that all of the multiple corners 110a are rounded.

[0019] The body part 110 includes a plurality of ridges 110b. The plurality of ridges 110b are formed at the intersections of two adjacent faces among the first side face 113, the second side face 114, the first end face 115, and the second end face 116. It is preferable that all of the plurality of ridges 110b are rounded.

[0020] The element body 110 includes a plurality of main surface side ridges 110c. The plurality of main surface side ridges 110c are formed by portions where the first main surface 111 intersects with each of the first side surface 113, second side surface 114, first end surface 115, and second end surface 116, and portions where the second main surface 112 intersects with each of the first side surface 113, second side surface 114, first end surface 115, and second end surface 116. It is preferable that all of the plurality of main surface side ridges 110c are rounded.

[0021] 1 and 4, the first external electrode 120 is provided on the first end surface 115. Specifically, the first external electrode 120 is formed over the entire first end surface 115, and is formed so as to extend from the first end surface 115 to the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114.

[0022] The second external electrode 130 is provided on the second end surface 116. Specifically, the second external electrode 130 is formed over the entire second end surface 116, and is formed so as to extend from the second end surface 116 to the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114.

[0023] The first external electrode 120 and the second external electrode 130 each include, for example, a base electrode layer and a plating layer disposed on the base electrode layer. The base electrode layer includes at least one layer selected from the group consisting of a fired electrode layer, a resin electrode layer, and a thin-film electrode layer.

[0024] The baked electrode layer is a layer containing glass and metal, and may be a single layer or multiple layers. The baked electrode layer is made of, for example, one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, such as an alloy of Ag and Pd.

[0025] The fired electrode layer can be formed by applying and firing a conductive paste containing glass and metal to the element body 110. The firing may be performed simultaneously with or after firing of the element body 110.

[0026] The resin electrode layer can be formed, for example, as a layer containing conductive particles and a thermosetting resin. When forming a resin electrode layer, the resin electrode layer may be formed directly on the element body part 110 without forming a baked electrode layer. The resin electrode layer may be a single layer or multiple layers.

[0027] The thin-film electrode layer is, for example, a layer of 1 μm or less in thickness in which metal particles are deposited, and can be formed by a known thin-film forming method such as sputtering or vapor deposition.

[0028] The plating layer disposed on the base electrode layer is composed of, for example, one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, such as an alloy of Ag and Pd. The plating layer may be a single layer or multiple layers. However, the plating layer preferably has a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. The Ni plating layer functions to prevent the base electrode layer from being eroded by solder when mounting the multilayer ceramic capacitor 100. The Sn plating layer functions to improve the wettability of the solder when mounting the multilayer ceramic capacitor 100.

[0029] Each of the first external electrode 120 and the second external electrode 130 may not include a base electrode layer and may instead be composed of a plating layer that is disposed directly on the element body part 110. In this case, the plating layer is directly connected to the first internal electrode layer 151 or the second internal electrode layer 152, which will be described later. Below, details of the plating layer when each of the first external electrode 120 and the second external electrode 130 does not include a base electrode layer and instead includes a plating layer that is formed directly on the element body part 110 will be described.

[0030] The plating layer preferably includes a first plating layer formed on the element body part 110 and a second plating layer formed on the first plating layer. However, when the plating layer is formed by electroless plating, a catalyst may be provided on the element body part 110.

[0031] Each of the first plating layer and the second plating layer preferably contains, for example, one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal.

[0032] When Ni is used as the internal electrode layer, it is preferable to use Cu, which has good bonding properties with Ni, as the first plating layer. Also, it is preferable to use Sn or Au, which have good solder wettability, as the second plating layer. Furthermore, Ni, which has solder barrier properties, may be used as the first plating layer.

[0033] The second plating layer may be formed as needed. That is, each of the first external electrode 120 and the second external electrode 130 may be configured to include only the first plating layer. Alternatively, each of the first external electrode 120 and the second external electrode 130 may be configured to further include, in addition to the first plating layer and the second plating layer, another plating layer formed on the second plating layer.

[0034] The ratio of metal per unit volume of the plating layer is preferably 99% by volume or more. The plating layer preferably does not contain glass. The plating layer preferably has grains grown along its thickness direction, and in this case, the plating layer is configured in a columnar shape.

[0035] 2 and 3, the element body 110 includes a laminate 101 and a side margin portion. The side margin portion has a first side margin portion S1 and a second side margin portion S2.

[0036] The laminate 101 has a pair of main surfaces 101a and 101b facing each other in the stacking direction T, a pair of side surfaces 101c and 101d facing each other in the width direction W, and a pair of end surfaces 101e and 101f facing each other in the length direction L.

[0037] The pair of main surfaces 101a, 101b constitute a part of the first main surface 111 and the second main surface 112 of the element body part 110. The side surface 101c is covered by a first side margin part S1. The side surface 101d is covered by a second side margin part S2. The pair of end surfaces 101e, 101f constitute a part of the first end surface 115 and the second end surface 116 of the element body part 110.

[0038] As shown in FIGS. 3 to 5, the laminate 101 has a plurality of dielectric layers 140 and a plurality of internal electrode layers 150 alternately stacked along the stacking direction T.

[0039] The multiple internal electrode layers 150 include multiple first internal electrode layers 151 and multiple second internal electrode layers 152. The multiple first internal electrode layers 151 and the multiple second internal electrode layers 152 are alternately stacked in the stacking direction T.

[0040] The plurality of first internal electrode layers 151 are extended to the first end surface 115. The plurality of first internal electrode layers 151 are connected to the first external electrode 120. The plurality of second internal electrode layers 152 are extended to the second end surface 116. The plurality of second internal electrode layers 152 are connected to the second external electrode 130. Both end portions in the width direction W of the plurality of first internal electrode layers 151 and the plurality of second internal electrode layers 152 are exposed to the side surfaces 101c, 101d.

[0041] 2 to 5 show an example in which seven first internal electrode layers 151 and seven second internal electrode layers 152 are provided, but the number of each of the first internal electrode layers 151 and the second internal electrode layers 152 is not limited to seven. The number of the multiple internal electrode layers 150 is preferably 50 to 300. From the viewpoint of miniaturization and high capacity of the multilayer ceramic capacitor, the thickness of the internal electrode layers 150 is preferably 0.4 μm to 0.9 μm.

[0042] Each of the first internal electrode layer 151 and the second internal electrode layer 152 is made of one kind of metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, such as an alloy of Ag and Pd. In this embodiment, each of the first internal electrode layer 151 and the second internal electrode layer 152 contains Ni as a main component. Each of the first internal electrode layer 151 and the second internal electrode layer 152 may further contain dielectric particles having the same composition as the ceramic contained in the dielectric layer 140. Furthermore, each of the first internal electrode layer 151 and the second internal electrode layer 152 may contain Sn at the interface with the dielectric layer 140.

[0043] The plurality of dielectric layers 140 are composed of outer dielectric layers located between the first main surface 111 and the internal electrode layer 150 located closest to the first main surface 111 in the stacking direction T, and between the second main surface 112 and the internal electrode layer 150 located closest to the second main surface 112 in the stacking direction T. In addition, inner dielectric layers are located between the internal electrode layers 150 adjacent to each other in the stacking direction T. The number of the plurality of dielectric layers 140 is preferably 100 to 500. From the viewpoint of miniaturization and high capacitance of the multilayer ceramic capacitor, the thickness of each of the plurality of dielectric layers 140 is preferably 0.5 μm to 0.8 μm.

[0044] Each of the plurality of dielectric layers 140 may be made of a ceramic material such as a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components. In this case, the content of the subcomponents is less than the content of the main component.

[0045] 4, the laminate 101 is divided into an inner layer portion C, a first outer layer portion X1, a second outer layer portion X2, and a first end margin portion E1 and a second end margin portion E2. The inner layer portion C has a capacitance due to a first opposing portion 151C (described later) of the first internal electrode layer 151 and a second opposing portion 152C (described later) of the second internal electrode layer 152 being stacked in the stacking direction T.

[0046] The first outer layer portion X1 and the second outer layer portion X2 sandwich the inner layer portion C in the stacking direction T. The first outer layer portion X1 is located outside the inner layer portion C in the stacking direction T, on the first main surface 111 side. The second outer layer portion X2 is located outside the inner layer portion C in the stacking direction T, on the second main surface 112 side. The thickness of each of the first outer layer portion X1 and the second outer layer portion X2 is preferably 30 μm or more and 50 μm or less.

[0047] Each of the first outer layer portion X1 and the second outer layer portion X2 is an outer dielectric layer and is made of a dielectric ceramic material mainly composed of a perovskite compound containing Ba and Ti. The first outer layer portion X1 and the second outer layer portion X2 may be made of the same dielectric ceramic material as the plurality of dielectric layers 140, or may be made of a different dielectric ceramic material from the plurality of dielectric layers 140. In this embodiment, the outer dielectric layers have a higher Mn content than the inner dielectric layers. That is, the first outer layer portion X1 and the second outer layer portion X2 have a higher Mn content than the dielectric layers 140 of the multilayer body 101 (more specifically, the inner dielectric layers of the inner layer portion C). This makes the first outer layer portion X1 and the second outer layer portion X2 denser, improving moisture resistance and ensuring the moisture resistance of the multilayer ceramic capacitor 100.

[0048] The first end margin E1 and the second end margin E2 sandwich the inner layer portion C in the longitudinal direction L. The first end margin E1 is located outside the inner layer portion C in the longitudinal direction L, on the side of the first end face 115. The second end margin E2 is located outside the inner layer portion C in the longitudinal direction L, on the side of the second end face 116.

[0049] The side margins are located in the element body 110 between the first side surface 113 and the plurality of internal electrode layers 150, and between the second side surface 114 and the plurality of internal electrode layers 150 in the width direction W.

[0050] Specifically, the first side margin portion S1 is provided so as to cover the entire side surface 101c of the laminate 101. The first side margin portion S1 exists in the element body portion 110 from one end of the internal electrode layer 150 located on one side in the width direction W to the first side surface 113.

[0051] The second side margin portion S2 is provided so as to cover the entire side surface 101d of the laminate 101. The second side margin portion S2 exists in the element body portion 110 from the other end of the internal electrode layer 150 located on the other side in the width direction W to the second side surface 114.

[0052] The first side margin portion S1 and the second side margin portion S2 are made of a dielectric ceramic material whose main component is a perovskite compound containing Ba and Ti. The first side margin portion S1 and the second side margin portion S2 may be made of the same dielectric ceramic material as the plurality of dielectric layers 140, or may be made of a different dielectric ceramic material from the plurality of dielectric layers 140.

[0053] The first side margin portion S1 and the second side margin portion S2 may contain at least one of Si and Mg, or may contain Mn.

[0054] Si may be segregated in the first side margin portion S1 and the second side margin portion S2. Specifically, Si may be segregated in a portion of the first side margin portion S1 closer to the side surface 101c, and Si may be segregated in a portion of the second side margin portion S2 closer to the side surface 101d. The segregation of Si can be confirmed by observing the cross section using, for example, SEM / EDX. Mn can be confirmed by observing the main components Ba or Ti using, for example, EPMA.

[0055] In this embodiment, the first side margin portion S1 and the second side margin portion S2 are each composed of a single layer. The first side margin portion S1 and the second side margin portion S2 may be composed of multiple layers stacked in the width direction W. The multiple layers do not necessarily require that the interface between the layers be observed. For example, the grain size may be different between the side surface side and the internal electrode layer 150 side, i.e., the grain size may vary in the width direction W. The grain size can be measured using an electron microscope such as a TEM. For example, the area of ​​each grain within a field of view is measured within an area of ​​approximately 10 μm × 10 μm. The equivalent circle diameter is calculated based on the area of ​​each grain, and the average of the equivalent circle diameters is used as the grain size.

[0056] As described above, the size of the multilayer ceramic capacitor 100 including the base body portion 110, the first external electrode 120, and the second external electrode 130 is not particularly limited, and for example, the following ranges can be adopted.

[0057] As shown in FIG. 4, the maximum distance L0 between the first end face 115 and the second end face 116 of the base body portion 110 is preferably, for example, 0.2 mm or more and 1.0 mm or less. The maximum distance T0 between the first main face 111 and the second main face 112 of the base body portion 110 is preferably 0.1 mm or more and 0.5 mm or less. As shown in FIG. 5, the maximum distance W0 between the first side face 113 and the second side face 114 of the base body portion 110 is preferably, for example, 0.1 mm or more and 0.5 mm or less.

[0058] The base body portion 110 has, for example, a size with a length dimension L0 of 0.6 mm, a width dimension W0 of 0.3 mm, and a thickness dimension T0 of 0.3 mm. Note that tolerances are taken into account for the above sizes.

[0059] <B. Detailed Configuration of Internal Electrode Layers> FIG. 6 is a schematic cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a schematic enlarged cross-sectional view near the connection end shown in FIG. 6. FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII shown in FIG. 4. FIG. 9 is a schematic enlarged cross-sectional view near the connection end shown in FIG. 8. FIG. 10 is a schematic cross-sectional view for explaining the state of the opposing portion of the internal electrode layer in the multilayer ceramic capacitor according to the embodiment. Specifically, in FIG. 10, a cross-section of the base body portion 110 parallel to the stacking direction T and the width direction W at the central portion of the base body portion 110 in the length direction L is shown. FIG. 11 is a schematic cross-sectional view for explaining the state of the lead-out portion of the internal electrode layer in the multilayer ceramic capacitor according to the embodiment. Specifically, in FIG. 11, a cross-section of the base body portion 110 parallel to the stacking direction T and the width direction W at the end portion of the base body portion 110 in the length direction L is shown. The detailed configurations of the first internal electrode layer 151 and the second internal electrode layer 152 will be described with reference to FIGS. 6 to 11.

[0060] Note that Figures 10 and 11 are illustrated for convenience in order to explain the amount of misalignment of the opposing portions and the amount of misalignment of the lead-out portions, respectively, and the shape of the body portion 110, the position of the opposing portions, the position of the lead-out portions, etc. are not limited to the aspects shown in Figures 10 and 11.

[0061] As shown in FIGS. 6 and 7, the first internal electrode layer 151 includes a first opposing portion 151C and a first lead portion 151X. The first opposing portion 151C faces the adjacent second internal electrode layer 152 in the stacking direction T. The first lead portion 151X is led out to the first end face 115. As a result, the first lead portion 151X connects the first opposing portion 151C and the first external electrode 120. The first opposing portion 151C and the first lead portion 151X are integrally configured.

[0062] As shown in FIGS. 8 and 9, the second internal electrode layer 152 includes a second opposing portion 152C and a second lead portion 152X. The second opposing portion 152C faces the adjacent first internal electrode layer 151 in the stacking direction T. The second lead portion 152X is led out to the second end face 116. As a result, the second lead portion 152X connects the second opposing portion 152C and the second external electrode 130. The second opposing portion 152C and the second lead portion 152X are integrally formed.

[0063] When the first opposing portion 151C and the second opposing portion 152C are not particularly distinguished from each other, they may simply be referred to as opposing portions, and when the first lead portion 151X and the second lead portion 152X are not particularly distinguished from each other, they may simply be referred to as lead portions. Similarly, when the first internal electrode layer 151 and the second internal electrode layer 152 are not particularly distinguished from each other, they may simply be referred to as internal electrode layers. When the first external electrode 120 and the second external electrode 130 are not particularly distinguished from each other, they may simply be referred to as external electrodes.

[0064] 6 to 9, both edge portions 155 in the width direction W of each of the multiple internal electrode layers 150 are configured by two straight line portions 155a and two curved line portions 155b connected to the two straight line portions 155a, respectively. The two straight line portions 155a extend linearly in the length direction L with a gap between them in the width direction W. The two curved line portions 155b are curved at a constant curvature so as to approach each other in the width direction W as they move away from the two straight line portions 155a in the length direction L.

[0065] The first side margin S1 and the second side margin S2 are located outside both edge portions 155 in the width direction W so as to cover both edge portions 155. Therefore, the thickness in the width direction W of the first side margin S1 at the portion covering the two curved portions 155b is configured to be greater than the thickness in the width direction W of the first side margin S1 at the portion covering the two straight portions 155a. This is also true for the second side margin S2.

[0066] In this embodiment, the portions of both edge portions 155 of each of the plurality of internal electrode layers 150 that correspond to the plurality of opposing portions are made up of only two straight line portions 155a. Also, the portions of both edge portions 155 of each of the plurality of internal electrode layers 150 that correspond to the plurality of lead-out portions are made up of only two curved line portions 155b.

[0067] The connection ends 156 of each of the internal electrode layers 150, which are located at the ends in the length direction L and connected to the external electrodes, are connected to the two curved portions 155b. This configuration makes it possible to obtain a multilayer ceramic capacitor with improved moisture resistance, which will be described in detail later.

[0068] 7 and 9, the curvature of each of the two curved portions 155b is preferably smaller than the curvature of the ridge portion 110b. Specifically, when the curvature radius of each of the two curved portions 155b is R1 and the curvature radius of the ridge portion 110b is R2, it is preferable that R1>R2 be satisfied.

[0069] The radius of curvature R1 of each of the two curved portions 155b is preferably 20% to 40% of the dimension W1 of the portion of the opposing portion having the largest dimension in the width direction W. The radius of curvature R1 is preferably 10 μm to 40 μm.

[0070] The dimension W2 in the width direction W of each of the connection ends 156 of the plurality of internal electrode layers 150 is preferably 60% or more and 80% or less of the dimension W1.

[0071] 10, the maximum deviation D1 in the width direction W between the opposing portion closest to the first side face 113 and the opposing portion closest to the second side face 114 among the plurality of opposing portions (more specifically, the plurality of first opposing portions 151C and the plurality of second opposing portions 152C) is 5 μm or less. That is, in a cross section taken along the stacking direction T and the width direction W at the center of the element body portion 110 in the length direction L, the maximum deviation D1 in the width direction W of the plurality of internal electrode layers 150 is 5 μm or less.

[0072] 11 , the maximum deviation D2 in the width direction W between the first lead portion 151X located closest to the first side face 113 and the first lead portion 151X located closest to the second side face 114 among the multiple first lead portions 151X is 5 μm or less. The maximum deviation in the multiple second lead portions 152X is also the same as the maximum deviation D2 in the first lead portion 151X. That is, on each of the first end face 115 and the second end face 116 of the element body portion 110, the maximum deviation in the width direction W at the connection ends 156 of the multiple internal electrode layers 150 is 5 μm or less.

[0073] In this way, when the widthwise ends of the multiple first extraction portions 151X are not aligned in the stacking direction T but are shifted in the widthwise direction W, it is possible that a portion of an internal electrode layer 150 adjacent in the thickness direction will be close to one of the widthwise end portions 151t1, 151t2 of the multiple first extraction portions 151X.

[0074] In this embodiment, Mg is segregated at both end portions 151t1, 151t2 in the width direction W of each of the multiple first lead portions 151X. This improves the insulation of the both end portions 151t1, 151t2, and therefore it is possible to prevent a short circuit from occurring even if one of the both end portions 151t1, 151t2 is close to the internal electrode layer 150 adjacent in the thickness direction. As a result, it is possible to improve the reliability of the multilayer ceramic capacitor 100. Mg is also segregated at the end portions in the width direction of each of the multiple second lead portions 152X, and the same effects as those described above are obtained.

[0075] Furthermore, Mg is segregated at both end portions 151t3 and 151t4 of each of the first opposing portions 151C in the width direction W, and at both end portions 152t3 and 152t4 of each of the second opposing portions 152C in the width direction W. In other words, Mg is segregated at both edge portions 155 of each of the internal electrode layers 150 in the width direction W. This also achieves the same effects as those described above. Note that the depth of the Mg segregation layer thus provided at both edge portions 155 (more specifically, the dimension of the segregation layer in the width direction W) is preferably uniform in the length direction L. The segregation of Mg can be confirmed, for example, by observing a cross section of the element body 110 parallel to the width direction W and the length direction L using SEM / EDX.

[0076] The above-described shape and length relationship explained above using Figure 10 can be observed by exposing a cross section passing through the center of the length direction L of the element body 110 and parallel to the width direction W and stacking direction T by polishing or the like, and then observing the cross section using an optical microscope or an electron microscope.

[0077] The relationship between the shape and length described above using Figure 11 can be confirmed by polishing the element body portion 110 to the extent that the first end face 115 is exposed from the first external electrode 120 side, and observing a cross section of the element body portion 110 parallel to the stacking direction T and the width direction W using an optical microscope, an electron microscope, or the like.

[0078] When observing with an optical microscope or an electron microscope, it is preferable to appropriately use bright field and dark field as needed.

[0079] <C. Parentheses> In the multilayer ceramic capacitor 100 according to this embodiment, as described above, both edge portions 155 in the width direction W of each of the plurality of internal electrode layers 150 are composed of two straight portions 155a and two curved portions 155b. Further, connection ends 156 of each of the plurality of internal electrode layers 150 are connected to the two curved portions 155b.

[0080] By configuring in this way, the path of the moisture intrusion path (see the arrow RT in FIGS. 7 and 9) from the first side surface 113 or the second side surface 114 of the body portion 110 to the connection end 156 exposed on the first end surface 115 or the second end surface 116 via the first end surface 115 or the second end surface 116 can be made longer compared to the above path when all of the both edge portions 155 are composed of the straight portions 155a.

[0081] Therefore, it becomes difficult for the moisture that has intruded into the multilayer ceramic capacitor 100 to reach the internal electrode layer 150, and as a result, it is possible to improve the moisture resistance of the multilayer ceramic capacitor 100.

[0082] Therefore, by configuring as in the multilayer ceramic capacitor 100 according to this embodiment, a multilayer ceramic capacitor with improved moisture resistance can be obtained.

[0083] Also, in the multilayer ceramic capacitor 100 according to this embodiment, as described above, the curvature of each of the two curved portions 155b is configured to be smaller than the curvature of the ridge line portion 110b. By configuring in this way, the path of the above moisture intrusion path can be made even longer. Therefore, it becomes possible to further improve the moisture resistance of the multilayer ceramic capacitor 100.

[0084] In the multilayer ceramic capacitor 100 according to the above-described embodiment, among both edge portions 155 of each of the plurality of internal electrode layers 150, portions corresponding to the plurality of opposing portions are constituted only by two straight portions 155a, and among both edge portions 155 of each of the plurality of internal electrode layers 150, portions corresponding to the plurality of lead-out portions are constituted only by two curved portions 155b. However, the configuration of both edge portions 155 of each of the plurality of internal electrode layers 150 is not particularly limited to this configuration.

[0085] That is, among both edge portions 155 of each of the plurality of internal electrode layers 150, portions corresponding to the plurality of opposing portions may be constituted only by a part of two straight portions 155a, and among both edge portions 155 of each of the plurality of internal electrode layers 150, portions corresponding to the plurality of lead-out portions may be constituted by the remaining part of two straight portions 155a and two curved portions 155b. Alternatively, among both edge portions 155 of each of the plurality of internal electrode layers 150, portions corresponding to the plurality of opposing portions may be constituted by two straight portions 155a and a part of two curved portions 155b, and among both edge portions 155 of each of the plurality of internal electrode layers 150, portions corresponding to the plurality of lead-out portions may be constituted only by the remaining part of two curved portions 155b.

[0086] <D. Manufacturing Method of Multilayer Ceramic Capacitor> FIG. 12 is a flowchart showing a manufacturing method of a multilayer ceramic capacitor according to an embodiment. Hereinafter, a manufacturing method of the multilayer ceramic capacitor 100 according to the present embodiment will be described.

[0087] As shown in FIG. 12, first, a ceramic dielectric slurry is prepared (step ST1). Specifically, a ceramic dielectric powder, an additive powder, a binder resin, a dissolving liquid, etc. are dispersed and mixed. Thereby, a ceramic dielectric slurry is prepared.

[0088] The ceramic dielectric powder is, for example, dielectric particles with a perovskite structure such as BaTiO3, CaTiO3, SrTiO3, CaZrO3, or CaHfO3. The additive powder is, for example, composed of at least one of Si compounds, Mg compounds, Mn compounds, Fe compounds, Cr compounds, Ni compounds, and Co compounds. Examples of binder resins that can be used include polyurethane resins, urea resins, melamine resins, epoxy resins, vinyl acetate resins, acrylic resins, and water-based polymers such as polyvinyl alcohol (PVA) and polyvinyl butyral (PVB). These may be used alone or in combination. The ceramic dielectric slurry may be either solvent-based or water-based. When the ceramic dielectric slurry is used as a water-based paint, the ceramic dielectric slurry is prepared by mixing a water-soluble binder and dispersant with the dielectric raw material dissolved in water.

[0089] Next, a ceramic dielectric sheet is formed (step ST2). Specifically, the ceramic dielectric slurry is formed into a sheet on a carrier film using a die coater, gravure coater, microgravure coater, or the like, and then dried. This forms a ceramic dielectric sheet.

[0090] Next, a mother sheet is formed (step ST3). More specifically, a conductive paste is applied to a ceramic dielectric sheet in a predetermined pattern. This results in a mother sheet having a predetermined internal electrode pattern on the ceramic dielectric sheet. The conductive paste contains Ni powder, a solvent, a dispersant, a binder, etc., and is prepared to have a constant viscosity. PVA, PVB, or the like is used as the binder. Methods for applying the conductive paste include screen printing, inkjet printing, gravure printing, etc. In addition to mother sheets having internal electrode patterns, ceramic dielectric sheets that have not undergone step ST3 above are also prepared as mother sheets.

[0091] Next, a plurality of mother sheets are stacked (step ST4). Specifically, a predetermined number of mother sheets, each consisting of only ceramic dielectric sheets and without an internal electrode pattern, are stacked. A predetermined number of mother sheets, each having an internal electrode pattern, are stacked on top of these. A further predetermined number of mother sheets, each consisting of only ceramic dielectric sheets and without an internal electrode pattern, are stacked on top of these. This completes the mother sheet group.

[0092] Next, the mother sheet group is pressed together to form a dielectric block (step ST5). Specifically, the mother sheet group is pressed in the stacking direction using a hydrostatic press or a rigid press, and is pressed together. This forms the dielectric block. At this time, the ceramic dielectric sheets are pressed at a predetermined temperature, so that the ceramic dielectric sheets adhere to each other. Furthermore, a ceramic dielectric sheet of a certain thickness is placed on the outermost layer in the stacking direction and pressed. This makes it possible to protect the dielectric sheet on which the internal electrode patterns are formed.

[0093] Next, the dielectric block is divided into chips (step ST6). Specifically, the dielectric block is divided into a matrix shape by press-cutting, dicing, or laser cutting, thereby being separated into a plurality of chips. When dividing the dielectric block, the dielectric block may be divided in a state in which it is softened by heating.

[0094] Next, side margins are formed (step ST7). This step includes steps ST71 to ST74, which will be described below.

[0095] First, a plurality of singulated chips are sequentially supplied onto a conveyor belt (step ST71). The chips supplied onto the conveyor belt are placed on the conveyor belt with one of the surfaces that will define the first side surface 113 or the second side surface 114 of the element part 110 after undergoing a firing step (step ST8) described below facing the conveyor belt. The chips thus placed on the conveyor belt are sequentially conveyed by the conveyor belt in a predetermined conveying direction.

[0096] In the following, the surface that defines the first side 113 of the chip and the surface that defines the second side 114, opposite the side facing the conveying belt, will also be referred to as the exposed surface.

[0097] Next, ceramic paste is applied to the exposed surface (step ST72). Specifically, the ceramic paste is dropped onto the exposed surface of the chip from a dispenser disposed opposite the conveyor belt.

[0098] The ceramic paste contains a dielectric ceramic material whose main component is a perovskite compound containing Ba and Ti, and a solvent, etc. The solvent is prepared to have a constant viscosity, for example, water or an organic solvent such as alcohol.

[0099] The ceramic paste is not particularly limited to this, and can be selected appropriately depending on the characteristics of the multilayer ceramic capacitor 100. For example, the ceramic paste may contain the same type of ceramic dielectric powder as the ceramic dielectric powder contained in the ceramic dielectric sheet described above, or may contain a different type of ceramic dielectric powder from the ceramic dielectric powder contained in the ceramic dielectric sheet.

[0100] The viscosity of the ceramic paste is preferably in the range of approximately 5 mPa·s to 1000 mPa·s when the ceramic paste is dripped. That is, the viscosity of the ceramic paste is preferably in the range of approximately 5 mPa·s to 1000 mPa·s at the ambient temperature at which the ceramic paste is applied. By setting the viscosity of the ceramic paste to 5 mPa·s or more, dripping of the ceramic paste from the exposed surface can be suppressed, and by setting the viscosity of the ceramic paste to 1000 mPa·s or less, the ceramic paste can be applied appropriately. This allows for the formation of a thin side margin portion with a uniform thickness.

[0101] The viscosity of the ceramic paste can be adjusted by changing the blending ratio of the dielectric ceramic material and the solvent. Here, the viscosity of the ceramic paste means the viscosity measured at 10 rpm using an E-type viscometer.

[0102] The amount of ceramic paste to be dispensed can be appropriately set depending on the thickness of the side margin portion to be formed on the exposed surface. 3 Over 1.0mm 3 It can be set to the following extent.

[0103] Next, air is blown onto the exposed surface (step ST73). Specifically, a blowing mechanism is disposed facing the conveyor belt at a position downstream of the dispenser in the conveying direction. Air is blown from this blowing mechanism onto the exposed surface onto which the ceramic paste has been dropped. This allows the ceramic paste to be spread evenly over the entire exposed surface.

[0104] The gas blown onto the exposed surface is not limited to air, and gases other than air, such as nitrogen gas, may also be blown onto the exposed surface.

[0105] Next, the ceramic paste is dried (step ST74). Specifically, a drying furnace is disposed downstream of the spraying mechanism in the transport direction, and the chip is passed through the drying furnace. This dries the ceramic paste applied to the exposed surface. By going through the above steps ST71 to ST74, a side margin portion is formed on one of the surfaces that will define the first side surface 113 and the second side surface 114 of the chip.

[0106] Next, the attitude of the chip is changed, and then the above steps ST72 to ST74 are performed on the chip.

[0107] In detail, first, the orientation of the chip is changed so that the surface on which the side margin is formed, of the surfaces that will define the first side surface 113 and the second side surface 114 of the chip, faces the conveyor belt. As a result, the surface on which the side margin is not formed, of the surfaces that will define the first side surface 113 and the second side surface 114 of the chip, defines the exposed surface. Next, the chip whose orientation has been changed in this way is subjected to the above-mentioned steps ST72 to ST74. As a result, side margins are formed on both the surfaces that will define the first side surface 113 and the second side surface 114 of the chip.

[0108] The position of the tip may be changed by, for example, a rotation mechanism having a gripping portion configured to grip and rotate the tip.

[0109] Next, the chip is fired (step ST8). Specifically, the chip is heated to fire the dielectric material and conductive material contained in the chip, forming element part 110. The firing temperature is, for example, 900°C or higher and 1300°C or lower. The firing temperature is set appropriately depending on the dielectric material and conductive material.

[0110] Next, external electrodes are formed (step ST9). In detail, a paste containing Ni as a main component and a dielectric material is applied to both end surfaces of the element body 110. As an application method, for example, a paste layer that will become the base electrode layer is formed on a plate, and the end surfaces of the element body 110 are immersed in the paste layer, etc. After application, the element body 110 and the base electrode layer are fired together. After firing, plating is performed, for example, in the order of Cu plating and Sn plating. Electrolytic plating is preferred as a plating method.

[0111] By going through the steps described above, the multilayer ceramic capacitor 100 according to this embodiment can be manufactured.

[0112] (First Modification) Fig. 13 is a schematic cross-sectional view of a multilayer ceramic capacitor according to a first modified example. More specifically, Fig. 13 is a schematic cross-sectional view of a portion of the multilayer ceramic capacitor according to the first modified example, which corresponds to Fig. 6. Fig. 14 is a schematic enlarged cross-sectional view of the vicinity of the connection end shown in Fig. 13. Hereinafter, a multilayer ceramic capacitor 100A according to the first modified example, which is based on the above-described embodiment, will be described with reference to Figs. 13 and 14.

[0113] As shown in FIGS. 13 and 14, the multilayer ceramic capacitor 100A according to this modification differs from the multilayer ceramic capacitor 100 according to the above-described embodiment in the configuration of the side margin portion of the element body portion 110.

[0114] More specifically, in the multilayer ceramic capacitor 100A, the first side margin portion S1 and the second side margin portion S2 are each composed of multiple layers stacked in the width direction W. Interfaces are present between these multiple layers. In the following description, the first side margin portion S1 and the second side margin portion S2 may be simply referred to as side margin portions when no distinction is made between them.

[0115] In this modification, the side margin portion is composed of a total of two layers: a first layer S11 and a second layer S12. The first layer S11 is provided along the multiple internal electrode layers 150. The second layer S12 is provided on the outer main surface of the first layer S11 in the width direction W so as to cover the main surface.

[0116] Therefore, in this modified example, the first layer S11 corresponds to the innermost layer located furthest in the width direction W among the multiple layers constituting the side margin portion, and the second layer S12 corresponds to the outermost layer located furthest in the width direction W among the multiple layers constituting the side margin portion.

[0117] The end of each of the first layer S11 and the second layer S12 on the connection end 156 side in the length direction L is rounded.

[0118] The curvature of the surface of the first layer S11 located on the outside in the width direction W is smaller than the curvature of the surface of the second layer S12 located on the outside in the width direction W. In this way, when the laminate is made up of multiple layers stacked in the width direction W, it is preferable that the curvature of the surface of each of the multiple layers located on the outside in the width direction W increases from the inside to the outside in the width direction W.

[0119] In this modification, as described above, the second layer S12 corresponds to the outermost layer, and therefore the curvature of the surface of the second layer S12 located on the outer side in the width direction W matches the curvature of the ridge portion 110b.

[0120] Even in this case, the same effects as those described in the above-described embodiment can be obtained, and a multilayer ceramic capacitor with improved moisture resistance can be obtained.

[0121] In this modification, the curvature of the surface of the first layer S11, which serves as the innermost layer, located on the outside in the width direction W is greater than the curvature of each of the two curved portions 155b of both edge portions 155 of the internal electrode layer 150, and is smaller than the curvature of the ridge portion 110b. Specifically, when the radius of curvature of the surface of the first layer S11 located on the outside in the width direction W is R11, the relationship R1>R11>R2 is satisfied.

[0122] By configuring in this manner, the path of moisture penetration can be made longer, thereby further improving the moisture resistance of the multilayer ceramic capacitor.

[0123] The side margin portion made up of a plurality of layers in this manner can be formed by, for example, performing steps ST72 to ST74 in the method for manufacturing the multilayer ceramic capacitor 100 described above a plurality of times.

[0124] Furthermore, in the multilayer ceramic capacitor 100A according to this modified example, the side margin portion is illustrated as being composed of two layers, but the number of layers constituting the side margin portion is not particularly limited to two, and may be three or more.

[0125] (Second Modification) 15 and 16 are schematic cross-sectional views of a multilayer ceramic capacitor according to a second modified example. More specifically, FIG. 15 is a schematic cross-sectional view of a portion of the multilayer ceramic capacitor according to the second modified example, corresponding to FIG. 6. FIG. 16 is a schematic cross-sectional view of a portion of the multilayer ceramic capacitor according to the second modified example, corresponding to FIG. 8. FIG. 17 is a schematic enlarged plan view for explaining the positional relationship between the first internal electrode layer shown in FIG. 15 and the second internal electrode layer shown in FIG. 16. More specifically, FIG. 17 is an enlarged plan view of one first internal electrode layer among a plurality of first internal electrode layers and a second internal electrode layer adjacent to the first internal electrode layer in the stacking direction T and positioned below the first internal electrode layer, viewed from the first main surface 111. Hereinafter, a multilayer ceramic capacitor 100B according to a second modified example based on the above-described embodiment will be described with reference to FIGS. 15 to 17. In FIG. 17, a pattern is applied to the second internal electrode layer for ease of understanding.

[0126] As shown in FIGS. 15 to 17, the multilayer ceramic capacitor 100B according to this modification differs from the multilayer ceramic capacitor 100 according to the above-described embodiment in the configuration of the internal electrode layers 150.

[0127] 17, in the multilayer ceramic capacitor 100B, when the first internal electrode layer 151 and the second internal electrode layer 152 adjacent thereto in the stacking direction T are viewed along the stacking direction T, a pair of corners 160 of the second internal electrode layer 152, which are located on the edge opposite to the connection end 156 side in the length direction L and on both ends in the width direction W, protrude outward in the width direction W from the curved portion 155b of the first internal electrode layer 151. Note that, although not shown here, a pair of corners located on the edge opposite to the connection end 156 side in the length direction L of the first internal electrode layer 151 and on both ends in the width direction W also protrude outward in the width direction W from the curved portion 155b of the second internal electrode layer 152.

[0128] Even in this case, the same effects as those described in the above-described embodiment can be obtained, and a multilayer ceramic capacitor with improved moisture resistance can be obtained.

[0129] Furthermore, by configuring the pair of corners 160 of the first internal electrode layer 151 and the pair of corners of the second internal electrode layer 152 as described above, it is possible to effectively suppress the occurrence of electric field concentration at these corners, thereby improving the reliability of the multilayer ceramic capacitor 100B.

[0130] In the multilayer ceramic capacitor 100B according to this modified example, the case where a pair of corners 160 of the first internal electrode layer 151 and a pair of corners of the second internal electrode layer 152 protrude as described above has been exemplified, but the pair of corners of only one of the first internal electrode layer 151 and the second internal electrode layer 152 may protrude as described above.

[0131] (Other forms, etc.) The shape, configuration, size, number, material, etc. of each part shown in the above-described embodiment of the present invention and its modified examples can be changed in various ways without departing from the spirit of the present invention.

[0132] Furthermore, the characteristic configurations shown in the above-described embodiments of the present invention and their modifications can naturally be combined with each other within the scope of the present invention.

[0133] As such, the above-described embodiments and their modifications disclosed herein are illustrative in all respects and are not restrictive. The technical scope of the present invention is defined by the claims, and includes all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0134] 100, 100A, 100B multilayer ceramic capacitor, 101 laminate, 101a, 101b main surface, 101c, 101d side surface, 101e, 101f end surface, 110 element portion, 110a corner portion, 110b ridge portion, 110c main surface side ridge portion, 111 first main surface, 112 second main surface, 113 first side surface, 114 second side surface, 115 first end surface, 116 second end surface, 120 first external electrode, 121 base electrode layer, 130 second external electrode, 140 dielectric layer, 150 internal electrode layer, 151 first internal electrode layer, 151C first opposing portion, 151X first lead portion, 151t1 to 151t4, 152t3, 152t4 both end portions, 152 Second internal electrode layer, 152C second opposing portion, 152X second lead-out portion, 155 both edge portions, 155a straight portion, 155b curved portion, 156 connecting end, 160 corner, C inner layer portion, E1 first end margin portion, E2 second end margin portion, S1 first side margin portion, S2 second side margin portion, S11 first layer, S12 second layer, X1 first outer layer portion, X2 second outer layer portion.

Claims

1. an element body portion including a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in a length direction perpendicular to the stacking direction and the width direction; an external electrode provided on each of the first end surface and the second end surface and connected to the plurality of internal electrode layers; a maximum deviation amount in the width direction of the plurality of internal electrode layers in a cross section along the stacking direction and the width direction at a central part of the element body part in the length direction is 5 μm or less; both edge portions in the width direction of each of the plurality of internal electrode layers are configured by two straight line portions extending linearly in the length direction with a gap between them in the width direction, and two curved line portions connected to the two straight line portions, respectively, and curved at a constant curvature so as to approach each other in the width direction as they move away from the two straight line portions in the length direction, a connection end located at an end in the length direction of each of the plurality of internal electrode layers and connected to the external electrode is connected to the two curved portions, a maximum deviation amount in the width direction at the connection ends of the plurality of internal electrode layers on the first end face and the second end face is 5 μm or less.

2. the element body portion includes a ridge portion that is a portion where two adjacent faces out of the first side surface, the second side surface, the first end surface, and the second end surface intersect, 2. The multilayer ceramic capacitor according to claim 1, wherein the curvature of each of the two curved portions is smaller than the curvature of the ridge portion.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein in the element body, each of side margin portions located between the first side surface and the plurality of internal electrode layers and between the second side surface and the plurality of internal electrode layers in the width direction is composed of a plurality of layers stacked in the width direction.

4. the element body portion includes a ridge portion that is a portion where two adjacent faces out of the first side surface, the second side surface, the first end surface, and the second end surface intersect, an innermost layer located at the innermost side in the width direction among the plurality of layers constituting each of the side margin portions is provided along the plurality of internal electrode layers, 4. The multilayer ceramic capacitor according to claim 3, wherein a curvature of a surface of the innermost layer positioned outward in the width direction is greater than the curvature of each of the two curved portions and smaller than the curvature of the ridge portion.

5. 5. The multilayer ceramic capacitor according to claim 1, wherein Mg is segregated at both edge portions in the width direction of each of the plurality of internal electrode layers.

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