Photoelectric conversion device and apparatus

Abstract

To provide a technique advantageous for a further improvement in the accuracy of A / D conversion.SOLUTION: A photoelectric conversion device comprises: a pixel array in which a plurality of pixels are arranged, a plurality of A / D conversion circuits converting pixel signals output from the pixel array into digital signals, and a plurality of reference signal lines supplied with reference signals different in the gradient of change from each other. Each of the plurality of A / D conversion circuits includes: a comparison circuit that compares the pixel signals with the reference signals; a selection unit that selects a reference signal line supplied with a reference signal used for A / D conversion, from among the plurality of reference signal lines; and a connection unit that connects the reference signal line selected by the selection unit, from among the plurality of reference signal lines, to the comparison circuit via a buffer, and connects a reference signal line not selected by the selection unit, from among the plurality of reference signal lines, to a load capacitance element via a buffer different from the above-mentioned buffer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] It is known that photoelectric conversion devices perform A / D conversion by comparing pixel signals output from pixels with a time-varying reference signal using a comparator. Patent Document 1 discloses that in a solid-state imaging device to which multiple types of reference signals with different change slopes are supplied, a reference signal to be used for A / D conversion is selected for each column from which signals are read out, depending on the signal level of the pixel signal. When selecting a reference signal for each column, the number of loads connected to each reference signal line changes with each A / D conversion, and fluctuations in the loads may change the signal level of the reference signal, potentially reducing the accuracy of the A / D conversion. Figure 16 of Patent Document 1 shows a configuration in which buffers are connected between each reference signal line and a comparator, thereby suppressing fluctuations in the loads connected to each reference signal line regardless of which reference signal line is used. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-179577 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a technique that is advantageous for further improving the accuracy of A / D conversion. [Means for solving the problem]

[0005] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device including a pixel array in which a plurality of pixels are arranged, a plurality of A / D conversion circuits that convert pixel signals output from the pixel array into digital signals, and a plurality of reference signal lines to which reference signals having different change slopes are supplied, wherein each of the plurality of A / D conversion circuits includes: a comparison circuit that compares the pixel signal with the reference signal; a selection unit that selects, from the plurality of reference signal lines, a reference signal line to which a reference signal used for A / D conversion is supplied; and a connection unit that connects, from the plurality of reference signal lines, the reference signal line selected by the selection unit to the comparison circuit via a buffer, and connects, from the plurality of reference signal lines, reference signal lines not selected by the selection unit to a load capacitance element via a buffer other than the buffer. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a technique that is advantageous for further improving the accuracy of A / D conversion. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 3] 2 is a diagram showing an example of the configuration of an A / D conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 4] 2 is a timing chart showing an example of the operation of the photoelectric conversion device of FIG. 1. [Figure 5] 2 is a diagram showing an example of the configuration of an A / D conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 6] 2 is a diagram showing an example of the configuration of an A / D conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 7] FIG. 2 is a diagram showing an example of the configuration of a device incorporating the photoelectric conversion device of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0009] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to Figures 1 to 6. Figure 1 is a diagram showing an example configuration of a photoelectric conversion device 100 according to this embodiment. The photoelectric conversion device 100 includes a pixel array 101, a vertical readout circuit 102, an analog-to-digital (A / D) conversion circuit 104, a column memory 106, a horizontal scanning circuit 107, a signal processing circuit 115, a signal output circuit 112, a vertical scanning circuit 110, and a timing generator 111. The photoelectric conversion device 100 also includes a reference bias circuit 103, a reference bias circuit 105, a ramp signal generation circuit 108, a phase locked loop (PLL) circuit 113, and a counter 109.

[0010] The pixel array 101 includes a plurality of pixels 121 arranged in a two-dimensional array, for example, to form a plurality of rows and a plurality of columns. The vertical readout circuit 102 is arranged to read out pixel signals from the pixel array 101. The reference bias circuit 103 generates a reference bias for the vertical readout circuit 102 and can also generate a pulse signal to control the vertical readout circuit 102. The A / D conversion circuit 104 converts analog pixel signals output from the pixel array 101 into digital signals. Although the A / D conversion circuit 104 is shown as a single block in FIG. 1 , the photoelectric conversion device 100 includes a plurality of A / D conversion circuits 104 arranged to correspond to, for example, a plurality of vertical output lines 114 arranged to correspond to pixel columns of the pixel array 101. Details of the A / D conversion circuits 104 will be described later. The reference bias circuit 105 generates a reference bias for the A / D conversion circuit 104 and can also generate a pulse signal to control the A / D conversion circuit 104. The ramp signal generation circuit 108 generates a reference signal (ramp signal) used for comparison with the pixel signal in the A / D conversion circuit 104. The ramp signal generation circuit 108 supplies multiple types of reference signals, each with a different gradient of temporal change, via multiple reference signal lines. The column memory 106 holds the value of the counter 109 according to the conversion result of the A / D conversion circuit 104. The PLL circuit 113 generates a reference clock used by the counter 109. The horizontal scanning circuit 107 transfers the digital value held in the column memory 106 to the signal processing circuit 115. The signal output circuit 112 is a circuit for outputting the signal processed in the signal processing circuit 115 from the photoelectric conversion device 100 to the outside. The vertical scanning circuit 110 scans the pixel array 101 in the vertical direction. When the vertical scanning circuit 110 scans the pixel array, a pixel signal is output from the pixel 121. The timing generator 111 supplies control signals to the reference bias circuits 103 and 105, the ramp signal generating circuit 108, the counter 109, the vertical scanning circuit 110, and the PLL circuit 113, and controls the operation of each of the above-mentioned components arranged in the photoelectric conversion device 100. Here, the vertical readout circuit 102 is configured to include a current source load for reading out pixel signals from the pixels 121, or a current source load and a column amplifier for signal amplification.In this embodiment, the vertical readout circuit 102 will be described as a current source load.

[0011] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel 121. Also shown in FIG. 2 is the connection relationship between the pixel 121, the vertical readout circuit 102, and the A / D conversion circuit 104. The pixel 121 includes a photodiode 201, a transfer transistor 202, a reset transistor 203, an amplification transistor 205, and a selection transistor 206. The photodiode 201 generates an electric charge according to incident light. The transfer transistor 202 transfers the electric charge photoelectrically converted by the photodiode 201 to a floating diffusion 204. The reset transistor 203 resets the floating diffusion 204 to the potential of the power supply line VDD. The amplification transistor 205 is an amplification transistor that converts a signal from the floating diffusion 204 into a voltage signal. A selection transistor 206 is disposed between the amplification transistor 205 and the vertical output line 114. When the selection transistor 206 is turned on (conductive), a pixel signal is output from the pixel 121 to the vertical scanning line 141.

[0012] A control signal pTX is supplied to the gate of the transfer transistor 202. When the control signal pTX is at a high level (Hi), the transfer transistor 202 is turned on, and the charge photoelectrically converted by the photodiode 201 is transferred to the floating diffusion 204. A control signal pFDRES is supplied to the gate of the reset transistor 203. When the control signal pFDRES is at a high level, the reset transistor 203 is turned on, conduction is established between the floating diffusion 204 and the power supply line VDD, and the floating diffusion 204 is reset to the potential of the power supply line VDD. A control signal pSEL is supplied to the gate of the selection transistor 206. When the control signal pSEL is at a high level, the selection transistor is turned on, and the source of the amplification transistor 205 and the vertical output line 114 are electrically connected.

[0013] The vertical output line 114 is connected to the vertical readout circuit 102 and the A / D conversion circuit 104. In this embodiment, the vertical readout circuit 102 is a current source load as described above.

[0014] FIG. 3 is a circuit diagram showing an example of the configuration of the A / D conversion circuit 104 of this embodiment. As described above, the photoelectric conversion device 100 includes multiple A / D conversion circuits 104, but FIG. 3 shows the circuit configuration of one A / D conversion circuit 104. The A / D conversion circuit 104 may include a comparison circuit 304, a selection unit 303, buffers 301 and 302, and a connection unit. The comparison circuit 304 compares a pixel signal supplied from the pixel array 101 with a reference signal supplied from the ramp signal generation circuit 108. The selection unit 303 selects a reference signal line, from multiple reference signal lines 321 and 322 connected to the ramp signal generation circuit 108, that receives a reference signal used for A / D conversion. The connection unit connects the reference signal line selected by the selection unit 303 from the multiple reference signal lines 321 and 322 to the comparison circuit 304 via one of the buffers 301 and 302. Furthermore, the connection unit connects one of the multiple reference signal lines 321, 322 that is not selected by the selection unit 303 as the reference signal line to be used for A / D conversion to the load capacitance element 310 via the other of the buffers 301, 302. In the configuration shown in FIG. 3, two reference signal lines 321, 322 are provided, and two types of reference signals with different temporal change slopes are supplied. Also, two buffers 301, 302 are provided. However, this is not limited thereto. Three or more reference signal lines may be provided, and three or more types of reference signals with different temporal change slopes may be supplied, and three or more buffers may be provided depending on the number of reference signal lines. The number of reference signal lines that supply reference signals may be the same as the number of buffers provided in one A / D conversion circuit 104.

[0015] 3, multiple reference signal lines 321 and 322 are connected to the input nodes of multiple buffers 301 and 302, respectively, so that one reference signal line corresponds to one buffer. Specifically, the input node of buffer 301 is connected to reference signal line 321, and the input node of buffer 302 is connected to reference signal line 322. Reference signal 1 and reference signal 2, which have different change slopes, are supplied to reference signal line 321 and reference signal line 322, respectively, from ramp signal generation circuit 108.

[0016] The output node of buffer 301 is connected to one of two terminals of switches 311 and 314. The output node of buffer 302 is connected to one of two terminals of switches 312 and 313. The one of the two terminals of switch 311 that is not connected to buffer 301 and the one of the two terminals of switch 312 that is not connected to buffer 302 are connected to load capacitance element 310. As shown in FIG. 3, load capacitance element 310 may be a ground capacitance element having one terminal connected to the ground level. The one of the two terminals of switch 314 that is not connected to buffer 301 and the one of the two terminals of switch 313 that is not connected to buffer 302 are connected to clamp capacitance element 307 that is connected to the positive input terminal, which is one of the input nodes of comparison circuit 304.

[0017] A switch 305 is arranged between the positive input terminal and negative output terminal of the comparison circuit 304. The vertical output line 114 is connected to the negative input terminal of the comparison circuit 304 via a clamp capacitance element 308. A switch 306 is arranged between the negative input terminal and positive output terminal of the comparison circuit 304. The negative output terminal of the comparison circuit 304 is connected to the selection unit 303 and the column memory 106.

[0018] The selection unit 303 also functions as a determination circuit that determines the signal level of the supplied pixel signal, and selects one of the multiple reference signal lines 321, 322 to which a reference signal used for A / D conversion is supplied, based on the determination result. When the output of the selection unit 303 is low level (Lo), the switches 311 and 313 are turned off (non-conductive). Furthermore, the output of the inverter 309 is high level, and the switches 312 and 314 are turned on. When the output of the selection unit 303 is high level, the switches 311 and 313 are turned on, and the output of the inverter 309 is low level, and the switches 312 and 314 are turned off. In other words, as described above, the selection unit 303 functions as a circuit that selects the reference signal lines 321, 322 to which a reference signal used for A / D conversion is supplied. The switches 311 to 314 also function as the above-mentioned connection units that connect the reference signal lines 321 and 322 to the comparison circuit 304 or the load capacitance element 310 via the buffers 301 and 302. The switches 311 to 314 are configured to switch the connections between the output nodes of the buffers 301 and 302 and the input nodes of the comparison circuit 304 and the load capacitance element 310, respectively.

[0019] Control signals 1 to 3 are supplied to the selection unit 303. The control signals 1 to 3 may be supplied from the timing generator 111, or may be supplied from a selection unit control circuit that operates in accordance with the control signals supplied from the timing generator 111. Control signal 1 is a reset signal for the selection unit 303. For example, when a high-level signal is supplied, the selection unit 303 is reset. Control signal 2 is an input enable signal for the selection unit 303, and when at a high level, the selection unit 303 accepts an input signal. Control signal 3 is an output enable signal for the selection unit 303, and when at a high level, the selection unit 303 outputs the above-mentioned determination result.

[0020] 4, the operation of the pixel 121 and the A / D conversion circuit 104 will be described. At time t1, the control signal pSEL goes high, causing the selection transistor 206 to transition to the on state, connecting the source of the amplification transistor 205 to the vertical output line 114. During the period from time t0 to time t3, the control signal pFDRES goes high, causing the reset transistor 203 to turn on, and resetting the floating diffusion 204 to the potential of the power supply line VDD.

[0021] The potential PIXSIG of the vertical output line 114 when the floating diffusion 204 is reset is defined as potential Vn. When the reset transistor 203 transitions to an off state, the potential of the floating diffusion 204 fluctuates, which in turn appears as a potential fluctuation in the potential PIXSIG. However, for the sake of simplicity, this specification does not mention the potential fluctuation when the reset transistor 203 changes between an on state and an off state.

[0022] During the period from time t0 to time t2, control signal 1 supplied to selection unit 303 goes high, resetting the state of selection unit 303. The output of reset selection unit 303 goes low. Because control signal 3 remains low until time t13, selection unit 303 continues to output a low signal until time t13. Therefore, from time t0 to time t13, switches 311 and 313 are off (non-conductive), and switches 312 and 314 are on. Therefore, buffer 301 connected to reference signal line 321 is connected to comparison circuit 304 via clamp capacitance element 307, and buffer 302 connected to reference signal line 322 is connected to load capacitance element 310. In other words, the potential of node C between buffers 301 and 302 and clamp capacitance element 307 (comparison circuit 304) is the potential of reference signal line 321 until time t13.

[0023] A potential Vrampres, which is the initial potential of the ramp signal generating circuit 108, is supplied to the reference signal line 321 from time t0 to time t4. Moreover, the potential Vrampres is supplied from the ramp signal generating circuit 108 to the reference signal line 322 from time t0 to time t14.

[0024] During the period from time t4 to time t5, the control signal pAZ is at high level. The control signal pAZ is a signal that controls the switches 305 and 306, and while the control signal pAZ is at high level, the switches 305 and 306 are in the on state. During the period from time t4 to time t6, a potential that is lower by ΔVoffset than the potential Vrampres is supplied to the reference signal line 321.

[0025] While the control signal pAZ is at a high level, the reference signal line 321 is connected to the clamp capacitor 307 via the buffer 301, and the vertical output line 114 is connected to the clamp capacitor 308. The respective potentials at this time are written to the clamp capacitor 307 and the clamp capacitor 308. At time t5, the control signal pAZ goes low, the switches 305 and 306 transition to the off state, and the clamp operation ends.

[0026] This clamping operation causes the potentials of the positive and negative input terminals of the comparator circuit 304 to become the same potential, and the output comp_o of the comparator circuit 304 becomes the same potential as each input terminal. The potential at this time varies depending on the circuit configuration, but here the explanation will proceed assuming it to be the potential Vcres.

[0027] At time t6, the potential of the reference signal line 321 returns to potential Vrampres. At this time, the potential Vinp of the positive input terminal and the potential Vinn of the negative input terminal of the comparator circuit 304 have the relationship Vinp>Vinn, so the output comp_o of the comparator circuit 304 becomes low level. At time t7, reference signal 1 is supplied to the reference signal line 321, and the potential of the reference signal line 321 decreases from potential Vrampres at a slope A.

[0028] In conjunction with the change in the potential of the reference signal line 321, when the potential of node C drops from the potential Vrampres by approximately ΔVoffset, the potential Vinp at the positive input terminal and the potential Vinn at the negative input terminal of the comparison circuit 304 satisfy the relationship Vinp < Vinn. Therefore, the output comp_o of the comparison circuit 304 transitions to a high level. This transition occurs near the time tn1 shown in FIG. 3, and the A / D conversion of the potential Vn of the vertical output line 114 at time tn1 is performed.

[0029] At time t8, the potential of the reference signal line 321 returns to the potential Vrampres. As a result, the potential Vinp at the positive input terminal and the potential Vinn at the negative input terminal of the comparison circuit 304 satisfy the relationship Vinp > Vinn, so the output comp_o of the comparison circuit 304 becomes a low level.

[0030] At time t9, the control signal pTX becomes a high level, and the charge photoelectrically converted by the photodiode 201 is transferred to the floating diffusion 204. When no light is incident on the photodiode 201 and no charge is accumulated in the photodiode 201 (in the dark), no charge is transferred to the floating diffusion 204, and the potential PIXSIG maintains the potential Vn as shown by the solid line. In reality, the potential of the floating diffusion 204 fluctuates due to the dark current component and when the transfer transistor 202 operates, but this is not considered here. On the other hand, when charge is accumulated in the photodiode 201 and transferred to the floating diffusion 204, the potential PIXSIG changes as shown by the dashed line. Let the voltage change of the vertical output line 114 caused by this accumulated charge be ΔVsigs.

[0031] At time t10, when the control signal pTX becomes a low level, the transfer transistor 202 turns off. Thereby, the transfer of charge from the photodiode 201 to the floating diffusion 204 is completed.

[0032] Also, during the period from time t9 to time t12, the potential of the reference signal line 321 drops by ΔVjdg from the potential Vrampres. This ΔVjdg is a comparison voltage for determining the signal level of the potential PIXSIG. The selection unit 303 determines whether ΔVsig is greater than or less than (ΔVjdg - ΔVoffset). The operation of this determination is described below.

[0033] In the dark, at time t9, with respect to the end of the clamping operation, the change amount of the potential Vinn at the negative input terminal of the comparison circuit 304 is 0V, and the change amount of the potential Vinp at the positive input terminal is -(ΔVjdg - ΔVoffset). Therefore, Vinp < Vinn, the output comp_o of the comparison circuit 304 transitions to a high level, and is input to the selection unit 303.

[0034] On the other hand, when light is irradiated and the potential PIXSIG changes by ΔVsigs, the following operation occurs. With respect to the end of the clamping operation, the change amount of the negative input terminal Vinn of the comparison circuit 304 is -ΔVsigs, and the change amount of the positive input terminal Vinp is -(ΔVjdg - ΔVoffset). When ΔVsig < (ΔVjdg - ΔVoffset), similar to the dark state, since Vinp < Vinn, the output comp_o of the comparison circuit 304 becomes a high level and is input to the selection unit 303. When ΔVsig > (ΔVjdg - ΔVoffset), since Vinp > Vinn, the output comp_o of the comparison circuit 304 becomes a low level and is input to the selection unit 303.

[0035] During the period from time t10 to time t11, the control signal 2 for controlling the selection unit 303 becomes a high level. Depending on the level of the output comp_o of the comparison circuit 304 input to the selection unit 303 during the period when this control signal 2 is at a high level, the selection unit 303 holds the determination result. Here, assume the determination result is as follows. When the output comp_o of the comparison circuit 304 is at a high level (when the pixel signal is smaller than the determination signal), the selection unit 303 outputs a low level. When the output comp_o of the comparison circuit 304 is at a low level (when the pixel signal is greater than the determination signal), the selection unit 303 outputs a high level.

[0036] At time t12, the potential of the reference signal line 321 returns to the potential Vrampres, causing the output comp_o of the comparison circuit 304 to go low.

[0037] Next, at time t13, the control signal 3 that controls the selection unit 303 goes high, allowing the selection unit 303 to output the determination result. As described above, when ΔVsigs<(ΔVjdg-ΔVoffset), the selection unit 303 outputs a low level. As a result, the switches 312 and 314 are turned on, the switches 311 and 313 are turned off, and the output node of the buffer 301 connected to the reference signal line 321 is connected to node C. Furthermore, the output node of the buffer 302 connected to the reference signal line 322 is connected to the load capacitance element 310. On the other hand, when ΔVsigs>(ΔVjdg-ΔVoffset), the selection unit 303 outputs a high level. As a result, the switches 312 and 314 are turned off, the switches 311 and 313 are turned on, and the output node of the buffer 302 connected to the reference signal line 322 is connected to node C. Furthermore, the output node of the buffer 301 connected to the reference signal line 321 is connected to the load capacitance element 310. The period from time t9 to time t13 may be referred to as a signal level determination period.

[0038] At time t14, reference signal 1 is supplied to reference signal line 321, and the potential of reference signal line 321 decreases from potential Vrampres with slope A. Also, reference signal 2 is supplied to reference signal line 322, and the potential of reference signal line 322 decreases from potential Vrampres with slope B. Here, the relationship is slope A < slope B, and reference signal 1 has a higher gain than reference signal 2. When it is determined by the signal level determination of potential PIXSIG that the signal level is smaller than (ΔVjdg - ΔVoffst), A / D conversion is performed using reference signal 1 with slope A which has a high gain. On the other hand, when it is determined that the signal level is larger than (ΔVjdg - ΔVoffst), A / D conversion is performed using reference signal 2 with slope B which has a low gain.

[0039] During darkness, since A / D conversion is performed using reference signal 1, the potential of node C transitions with slope A as shown by the solid line. At time ts1, the potential Vinp of the positive input terminal and the potential Vinn of the negative input terminal of comparison circuit 304 have the relationship Vinp < Vinn, and the output comp_o of comparison circuit 304 transitions to the high level. Thereby, the A / D conversion of the pixel signal output from photodiode 201 during darkness is completed.

[0040] On the other hand, when photoelectric conversion is performed and potential PIXSIG changes by ΔVsigs and ΔVsigs > (ΔVjdg - ΔVoffst), since A / D conversion is performed using reference signal 2, the potential of node C transitions with slope B as shown by the dashed line. At time ts2, the potential of node C becomes (Vrampres - ΔVoffset - ΔVsigs). Thereby, the potential Vinp of the positive input terminal and the potential Vinn of the negative input terminal of comparison circuit 304 have the relationship Vinp < Vinn, the output comp_o of comparison circuit 304 transitions to the high level, and the A / D conversion of ΔVsigs is completed.

[0041] At time t15, both reference signal 1 and reference signal 2 become potential Vrampres. Along with this, the output comp_o of comparison circuit 304 transitions to the low level. The period from time t14 to time t15 may be called the S conversion period.

[0042] In this embodiment, the reference signal used during the S conversion period is switched depending on the result of the signal level determination period. This means that the ratio of reference signal 1 to reference signal 2 used during the S conversion period changes depending on the luminance of light incident on the photodiode. For example, if buffers 301 and 302 are circuits including source follower circuits such as source follower amplifiers, the load connected to the output side of buffers 301 and 302 may affect the input side. Therefore, if the loads connected to the output nodes of buffers 301 and 302 are not matched between buffers 301 and 302, the loads connected to reference signal lines 321 and 322 will change each time the ratio of reference signals 1 and 2 used changes. As a result, the slopes A and B of reference voltages 1 and 2 may fluctuate depending on the luminance during the S conversion period. As a result, the linearity of A / D conversion may be reduced and smear may occur, potentially degrading the image quality of the resulting image.

[0043] In contrast, in the A / D conversion circuit 104 of this embodiment, the output node of the buffer 301 or the buffer 302 connected to the reference signal line 321 or the reference signal line 322 that is not used for A / D conversion is connected to the load capacitance element 310. For example, when the reference signal 1 flowing through the reference signal line 321 is used for A / D conversion, the buffer 302 connected to the reference signal line 322 that is different from the buffer 301 connected to the reference signal line 321 is connected to the load capacitance element 310. This suppresses changes in the loads connected to the reference signal lines 321 and 322, respectively, regardless of changes in the ratios of the reference signals 1 and 2 used for A / D conversion.

[0044] The capacitance value of the load capacitance element 310 is set taking into consideration the parasitic capacitance during the layout of the photoelectric conversion device 100 and the input capacitance of the positive input terminal of the comparison circuit 304. Depending on the circuit constants and layout, the capacitance value of the load capacitance element 310 is, for example, on the order of several hundred fF. The load capacitance element 310 may be formed using a Metal-Insulator-Metal (MIM) structure or as a MOS capacitor. It may also be a PIP structure capacitor with an insulating layer sandwiched between multiple polysilicon layers. All other capacitance elements described in this specification and the drawings may also be MIM structure capacitors, MOS capacitors, or PIP structure capacitors. In this specification, capacitance provided as a structure is referred to as a capacitance element. On the other hand, parasitic capacitance associated with wiring, transistors, etc. will be referred to as parasitic capacitance without the term "element."

[0045] By providing the A / D conversion circuit 104 with the above-described configuration, it is possible to minimize changes in the loads connected to the output nodes of the buffers 301 and 302. This allows for highly accurate A / D conversion, such as by suppressing the aforementioned degradation in linearity and the occurrence of smear. As a result, degradation in the quality of the image obtained using the photoelectric conversion device 100 is suppressed.

[0046] 5 is a circuit diagram showing a modified example of the A / D conversion circuit 104 described above. In the A / D conversion circuit 104 shown in FIG. 3, the connection relationship between the reference signal lines 321 and 322 and the buffers 301 and 302 is fixed. Furthermore, switches 311 to 314 functioning as a connection unit are configured to switch the connection between the output nodes of the buffers 301 and 302 and the input nodes of the comparison circuit 304 and the load capacitance element 310. On the other hand, in the configuration shown in FIG. 5, the output node of the buffer 301 is connected to the input node of the comparison circuit 304 via the clamp capacitance element 307, and the output node of the buffer 302 is connected to the output node of the load capacitance element 310. In other words, the connection relationship between the output nodes of the buffers 301 and 302 and the input nodes of the comparison circuit 304 and the load capacitance element 310 is fixed. On the other hand, switches 511 to 514 functioning as connection units are configured to switch the connections between the respective reference signal lines 321 and 322 and the input nodes of the buffers 301 and 302.

[0047] The switch 511 is arranged between the reference signal line 322 and the buffer 301. The switch 512 is arranged between the reference signal line 321 and the buffer 301. The output node of the buffer 301 is connected to the positive input terminal side, which is the input node of the comparison circuit 304, via the clamp capacitance element 307. The switch 513 is arranged between the reference signal line 322 and the buffer 302. The switch 514 is arranged between the reference signal line 321 and the buffer 302. The output node of the buffer 302 is connected to the load capacitance element 310. Similar to the switches 311 to 314 described above, the switches 511 to 514 are connected in the following states depending on the determination result of the selection unit 303.

[0048] During the signal level determination period, when the output comp_o of the comparison circuit 304 is at a high level (when the pixel signal is smaller than the determination level), the selection unit 303 outputs a low level after time t13. This causes the switches 512 and 513 to be turned on, and the switches 511 and 514 to be turned off. As a result, the reference signal line 321 is connected to the buffer 301, and the potential of the reference signal line 321 is supplied to the node C via the buffer 301. In addition, the reference signal line 322 is connected to the load capacitance element 310 via the buffer 302.

[0049] On the other hand, during the signal level determination period, when the output comp_o of the comparison circuit 304 is at a low level (when the pixel signal is greater than the determination level), the selection unit 303 outputs a high level after time t13. This causes the switches 511 and 514 to be turned on, and the switches 512 and 513 to be turned off. As a result, the reference signal line 322 is connected to the buffer 301, and the potential of the reference signal line 322 is supplied to the node C via the buffer 301. In addition, the reference signal line 321 is connected to the load capacitance element 310 via the buffer 302.

[0050] 5, similarly to the above-described embodiment, during the S conversion period, the reference signal line 321 or the reference signal line 322 that is not used in A / D conversion is connected to the load capacitance element 310 via the buffer 302. This suppresses changes in the loads connected to the reference signal lines 321 and 322, respectively, regardless of changes in the ratio of the reference signals 1 and 2 used in A / D conversion. In other words, even in the configuration shown in FIG. 5, A / D conversion can be performed with high precision, for example, by suppressing degradation in linearity and the occurrence of smear, and degradation in the quality of the image obtained using the photoelectric conversion device 100 is suppressed.

[0051] 5, regardless of whether reference signal 1 or reference signal 2 is used, the same buffer supplies the reference signal to comparison circuit 304. For example, when A / D conversion is performed at a high gain, the configuration shown in FIG. 5 is considered to be more suitable than the configuration shown in FIG. 3.

[0052] During the period from time t4 to time t5, the clamp capacitor 307 clamps (Vrampres-ΔVoffset). Consider a case where, as a result of the signal level determination period, the reference signal to be used is changed and supplied from a different buffer. In this case, due to the influence of the buffer offset potential Vbofst, the potential of node C may be shifted by Vbofst from the potential Vrampres, resulting in A / D conversion starting at a potential (Vrampres+Vbofst). In this case, the timing at which the comparator circuit 304 inverts during A / D conversion during the S conversion period is delayed if the potential Vbofst is positive and accelerated if the potential Vbofst is negative. This results in an error in the A / D converted value. The influence of the potential Vbofst becomes significant when the slope of the reference signal is small and a high gain is applied. Therefore, the configuration shown in FIG. 5, in which the buffer connected to the comparator circuit 304 is fixed to the buffer 301, can perform A / D conversion with higher accuracy than the configuration shown in FIG. 3.

[0053] Fig. 6 is a circuit diagram showing a modified example of the A / D conversion circuit 104 shown in Fig. 5. The configuration shown in Fig. 6 differs from the configuration shown in Fig. 5 in the configuration of the clamp capacitance element between the buffer 301 and the positive input terminal which is the input node of the comparison circuit 304, and the configuration of the load capacitance element connected to the buffer 302. The other configurations may be the same as the configuration shown in Fig. 5 described above, so the differences will be mainly described below.

[0054] 6, the load capacitance element 610 connected to the output node of the buffer 302 has a variable capacitance value. The load capacitance element 610 may also be called a variable capacitance element. In addition to the clamp capacitance element 307, a clamp capacitance element 607 is also provided. One of the two terminals of the clamp capacitance element 607 is connected to the positive input terminal of the comparison circuit 304. The other of the two terminals of the clamp capacitance element 607 is connected to the buffer 301 via a switch 611 and to the ground level via a switch 612. The ground level may be, for example, the same as the potential level of the power supply line GND connected to the current source of the vertical readout circuit 102 shown in FIG. 2.

[0055] The switches 611 and 612 are controlled exclusively, so that when the switch 611 is on, the switch 612 is off, and when the switch 611 is off, the switch 612 is on. That is, when the switch 611 is on and the switch 612 is off, the clamp capacitor 307 and the clamp capacitor 607 are connected in parallel between the positive input terminal of the comparator circuit 304 and the buffer 301. When the switch 611 is off and the switch 612 is on, the clamp capacitor 607 is connected to the ground level.

[0056] Consider, for example, a case where the clamp capacitor 307 and the clamp capacitor 607 have the same capacitance value. Compared to when the switch 611 is on and the switch 612 is off, when the switch 611 is off and the switch 612 is on, the slope of the reference signal input to the positive input terminal of the comparator circuit 304 for the same reference signal input can be reduced to approximately half. In other words, the gain can be increased. Here, the case where the switch 611 is on and the switch 612 is off is called the 1x gain mode, and the case where the switch 611 is off and the switch 612 is on is called the 2x gain mode.

[0057] If the capacitance value of the parasitic capacitance parasitic on the output node of the buffer 301 is Cp, the capacitance value of each of the clamp capacitance elements 307 and 607 is C1, and the capacitance value of the input capacitance of the comparison circuit 304 is Cin, the capacitance value connected to the output node of the buffer 301 in the 1x gain mode is (2C1×Cin) / (2C1+Cin)+Cp ··· (1) On the other hand, in the double gain mode, the capacitance value connected to the output node of the buffer 301 is (C1 2 +C1×Cin) / (2C1+Cin)+Cp ··· (2) becomes.

[0058] 6, the capacitance value of load capacitive element 610 is made variable, and the capacitance value of load capacitive element 610 is changed according to the gain mode, taking into account the change in the load connected to buffer 301 due to the gain mode. This makes it possible to reduce degradation in linearity and the occurrence of smear, even when the gain is changed using clamp capacitive element 307 and clamp capacitive element 607.

[0059] The capacitance value of the load capacitance element 610 may be set to compensate for variations in load due to manufacturing variations in the photoelectric conversion device 100. Also, in the configurations shown in Figs. 3 and 5, a load capacitance element 610 with a variable capacitance value may be used instead of the load capacitance element 310.

[0060] The configuration shown in FIG. 6 also enables highly accurate A / D conversion, suppressing degradation in the quality of images obtained using the photoelectric conversion device 100. Furthermore, in the configuration shown in FIG. 6, clamp capacitors 307 and 607 are provided as clamp capacitors, and two capacitance values ​​can be set for the clamp capacitors connected to the input node (positive input terminal) of the comparison circuit 304. This allows the gain during A / D conversion to be changed more significantly than in the configurations shown in FIGS. 3 and 5. While the capacitance values ​​of the clamp capacitors 307 and 607 have been set to the same value in the above description, this is not limitative. Depending on the specifications required for the photoelectric conversion device 100 (A / D conversion circuit 104), the capacitance values ​​of the clamp capacitors 307 and 607 may be different from each other. Furthermore, another clamp capacitor or the like may be provided, allowing the capacitance value of the clamp capacitor to be selected from three or more capacitance values.

[0061] An application example of the photoelectric conversion device 100 of this embodiment will now be described with reference to FIG. 7. FIG. 7 is a schematic diagram of an apparatus 9191 including the photoelectric conversion device 100. As shown in FIG. 7, the photoelectric conversion device 100 is housed in a package 920. The package 920 can include a base to which the photoelectric conversion device 100 is fixed, and a lid such as glass that faces the photoelectric conversion device 100. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to pads provided on the photoelectric conversion device 100.

[0062] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric conversion device 100. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0063] The processing device 960 processes the signal output from the photoelectric conversion device 100. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device 100. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device 100. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0064] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the photoelectric conversion device 100 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 may further include a storage device 980 and a processing device 960 in addition to the storage circuit and arithmetic circuit provided in the photoelectric conversion device 100. The mechanical device 990 may be controlled based on the signal output from the photoelectric conversion device 100.

[0065] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the photoelectric conversion device 100 for vibration isolation operations.

[0066] The device 9191 can also be applied to an on-board camera mounted on transportation equipment such as a vehicle, a ship, an airplane, or an industrial robot. The mechanical device 990 in transportation equipment can be used as a mobile device. The device 9191 as transportation equipment is suitable for transporting the photoelectric conversion device 100 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a mobile device based on information obtained by the photoelectric conversion device 100. The device 9191 incorporating the photoelectric conversion device 100 is not limited to transportation equipment, and can be widely applied to equipment that uses object recognition, such as an intelligent transport system (ITS). Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, or an office machine such as a copier.

[0067] The disclosure of this specification includes the following photoelectric conversion devices and instruments.

[0068] (Item 1) A photoelectric conversion device comprising: a pixel array in which a plurality of pixels are arranged; a plurality of A / D conversion circuits that convert pixel signals output from the pixel array into digital signals; and a plurality of reference signal lines to which reference signals having different change slopes are supplied, a comparison circuit that compares the pixel signal with the reference signal; a selection unit that selects one of the plurality of reference signal lines to which a reference signal used for A / D conversion is supplied; and a connection unit that connects the reference signal line selected by the selection unit to the comparison circuit via a buffer, and connects the reference signal line not selected by the selection unit to a load capacitance element via a buffer other than the buffer.

[0069] (Item 2) 2. The photoelectric conversion device according to item 1, wherein the buffer and the other buffer include a source follower circuit.

[0070] (Item 3) 3. The photoelectric conversion device according to item 1 or 2, wherein the capacitance value of the load capacitance element is variable.

[0071] (Item 4) a clamp capacitance element connected to an input node of the comparison circuit to which the reference signal is supplied; 4. The photoelectric conversion device according to item 3, wherein the clamp capacitance element is configured so that two or more capacitance values ​​can be set.

[0072] (Item 5) The photoelectric conversion device according to any one of items 1 to 4, characterized in that the selection unit determines a signal level of the pixel signal, and selects, from the plurality of reference signal lines, a reference signal line to which a reference signal used for A / D conversion is supplied according to the determination result.

[0073] (Item 6) a plurality of buffers including the buffer and the other buffer are provided; each of the plurality of reference signal lines is connected to an input node of each of the plurality of buffers so that one reference signal line corresponds to one buffer; The photoelectric conversion device described in any one of items 1 to 5, characterized in that the connection unit is configured to switch connections between the output nodes of each of the plurality of buffers and the input nodes of the comparison circuit and the load capacitance element.

[0074] (Item 7) an output node of the buffer and an input node of the comparison circuit are connected to each other; an output node of the other buffer and an output node of the load capacitance element are connected to each other; The photoelectric conversion device described in any one of items 1 to 5, characterized in that the connection unit is configured to switch connections between each of the plurality of reference signal lines and each of the input nodes of the buffer and the other buffer.

[0075] (Item 8) 8. The photoelectric conversion device according to any one of items 1 to 7, wherein the load capacitance element is a ground capacitance element.

[0076] (Item 9) A photoelectric conversion device according to any one of items 1 to 8, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

[0077] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0078] 100: Photoelectric conversion device, 101: Pixel array, 104: A / D conversion circuit, 121: Pixel, 303: Selection unit, 304: Comparison circuit, 310, 610: Load capacitance element, 311, 312: Reference signal line

Claims

1. A photoelectric conversion device comprising: a pixel array in which a plurality of pixels are arranged; a plurality of A / D conversion circuits that convert pixel signals output from the pixel array into digital signals; and a plurality of reference signal lines to which reference signals having different change slopes are supplied, a comparison circuit that compares the pixel signal with the reference signal; a selection unit that selects one of the plurality of reference signal lines to which a reference signal used for A / D conversion is supplied; and a connection unit that connects the reference signal line selected by the selection unit from the plurality of reference signal lines to the comparison circuit via a buffer, and connects the reference signal line not selected by the selection unit from the plurality of reference signal lines to a load capacitance element via a buffer other than the buffer.

2. 2. The photoelectric conversion device according to claim 1, wherein the buffer and the other buffer include a source follower circuit.

3. 2. The photoelectric conversion device according to claim 1, wherein the capacitance value of the load capacitance element is variable.

4. a clamp capacitance element connected to an input node of the comparison circuit to which the reference signal is supplied; 4. The photoelectric conversion device according to claim 3, wherein the clamp capacitance element is configured so that two or more capacitance values ​​can be set.

5. The photoelectric conversion device according to claim 1, characterized in that the selection unit determines the signal level of the pixel signal and, depending on the determination result, selects a reference signal line from the plurality of reference signal lines to which a reference signal used for A / D conversion is supplied.

6. a plurality of buffers including the buffer and the other buffer are provided; each of the plurality of reference signal lines is connected to an input node of each of the plurality of buffers so that one reference signal line corresponds to one buffer; 2. The photoelectric conversion device according to claim 1, wherein the connection unit is configured to switch connections between output nodes of the plurality of buffers and input nodes of the comparator circuit and the load capacitance element.

7. an output node of the buffer and an input node of the comparison circuit are connected to each other; an output node of the other buffer and an output node of the load capacitance element are connected to each other; 2. The photoelectric conversion device according to claim 1, wherein the connection unit is configured to switch connections between each of the plurality of reference signal lines and each of the input nodes of the buffer and the other buffer.

8. 2. The photoelectric conversion device according to claim 1, wherein the load capacitance element is a ground capacitance element.

9. The photoelectric conversion device according to any one of claims 1 to 8, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

Images