Semiconductor package

Abstract

To provide a semiconductor package with improved electrical characteristics.SOLUTION: A semiconductor package includes a first structural body ST1 and a second structural body ST2. The first structural body includes: a first semiconductor chip 100; a second semiconductor chip 200 disposed on the first semiconductor chip and horizontally shifted and disposed from the first semiconductor chip in a first direction; a first insulating pattern 410 covering a side surface of the first semiconductor chip and whose width decreases from a bottom surface of the first semiconductor chip toward an upper surface of the first semiconductor chip; a first molding film 510 surrounding the first semiconductor chip, the second semiconductor chip, and the first insulating pattern; a first conductive post 310 vertically penetrating the first molding film and connected to the upper surface of the first semiconductor chip; and a second conductive post 320 connected to the upper surface of the second semiconductor chip and exposed on the upper surface of the first molding film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package with improved electrical characteristics. [Background technology]

[0002] 2. Description of the Related Art With the development of the electronics industry, there is an increasing demand for higher performance, higher speed, and smaller size of electronic components. In response to this trend, recent packaging technology has progressed toward mounting multiple semiconductor chips within a single package. A semiconductor package is a device that embodies an integrated circuit chip in a form suitable for use in an electronic product. Typically, a semiconductor package is formed by mounting a semiconductor chip on a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps.

[0003] 2. Description of the Related Art In recent years, with the development of the electronics industry, semiconductor packages have been developed in various directions, with the aim of achieving smaller size, lighter weight, and reduced manufacturing costs. Furthermore, as the application field of semiconductor devices has expanded to include large-capacity storage means, various types of semiconductor packages have appeared. As semiconductor chips become more highly integrated, the size of the semiconductor chips is gradually decreasing.

[0004] However, as semiconductor chips become smaller, it becomes more difficult to attach the desired number of solder balls, and handling and testing of the solder balls also becomes more difficult. In addition, there is a problem that the boards on which the semiconductor chips are mounted must be diversified according to the size of the semiconductor chips. To solve this problem, a fan-out package was proposed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 10,643,973 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the above-mentioned problems with conventional semiconductor packages, and an object of the present invention is to provide a semiconductor package with improved electrical characteristics. Another object of the present invention is to provide a semiconductor package with improved structural stability. Another object of the present invention is to provide a semiconductor package manufactured through a semiconductor package manufacturing method with a simple manufacturing process. [Means for solving the problem]

[0007] In order to achieve the above object, a semiconductor package according to the present invention includes a first structure and a second structure, wherein the first structure includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and shifted horizontally relative to the first semiconductor chip in a first direction, a first insulating pattern covering a side surface of the first semiconductor chip, wherein the width of the first insulating pattern decreases from a lower surface of the first semiconductor chip toward an upper surface of the first semiconductor chip, a first molding film surrounding the first semiconductor chip, the second semiconductor chip, and the first insulating pattern, a first conductive post vertically penetrating the first molding film and connected to the upper surface of the first semiconductor chip, and a second conductive post connected to the upper surface of the second semiconductor chip and exposed on the upper surface of the first molding film.

[0008] In addition, a semiconductor package according to the present invention, which has been made to achieve the above-mentioned object, is characterized in that it comprises a first chip stack including a plurality of first semiconductor chips stacked on top of each other, wherein each of the first semiconductor chips includes a first chip pad provided on its upper surface, a first molding film covering the first chip stack, a passivation film covering the upper surface of the first molding film, first conductive posts vertically penetrating the first molding film and connected to the first chip pads, and a first seed pattern vertically penetrating the passivation film and connected to the first conductive posts.

[0009] In order to achieve the above object, a semiconductor package according to the present invention includes a first structure, the first structure including a first semiconductor chip, wherein the first semiconductor chip includes first chip pads provided on an upper surface of the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and horizontally shifted relative to the first semiconductor chip in a first direction, and wherein the second semiconductor chip includes second chip pads provided on an upper surface of the second semiconductor chip, a first molding film covering the first semiconductor chip and the second semiconductor chip, a first seed pattern provided on an upper surface of the first chip pad, a first conductive post vertically penetrating the first molding film and contacting the first seed pattern, and a second conductive post vertically penetrating the first molding film and contacting the second chip pad.

[0010] a first insulating pattern on a side surface of the first semiconductor chip, the first insulating pattern having an inclined surface connecting a top surface of the carrier substrate and a top surface of the first semiconductor chip; forming a first seed layer covering the carrier substrate, the first insulating pattern, and the first semiconductor chip; forming first conductive posts on the first seed layer, the first conductive posts being located on the first semiconductor chip, and patterning the first seed layer using the first conductive posts as a mask; attaching a second semiconductor chip on the first semiconductor chip to be horizontally spaced apart from the first conductive posts, the second semiconductor chip having second conductive posts provided on its top surface; forming a first molding layer on the carrier substrate to cover the first and second semiconductor chips; and forming a passivation layer covering the first molding layer, the passivation layer having openings exposing the first and second conductive posts. [Effects of the Invention]

[0011] The semiconductor package according to the present invention provides thick and wide conductive posts for vertical connection of the semiconductor chips of the bottom first chip stack. Therefore, the conductive posts provided between the semiconductor chip and the pad layer can firmly support the semiconductor chip and the pad layer. Furthermore, the electrical resistance of the conductive posts between the semiconductor chip and the pad layer can be reduced. That is, a semiconductor package with improved structural stability and electrical characteristics can be provided. By forming an insulating pattern having an inclined surface on the side surface of the lower semiconductor chip, it is easy to form a seed layer on the carrier substrate and the lower semiconductor chip. Therefore, a method for manufacturing a semiconductor package with fewer defects can be provided. Furthermore, the conductive posts for electrical connection to the lower semiconductor chip can be formed in one process, which simplifies the manufacturing process of the semiconductor package. Furthermore, conductive posts for electrical connection of the upper semiconductor chip can be formed during the step of forming the upper semiconductor chip on the semiconductor wafer. Therefore, it is not necessary to form terminals for electrical connection on the uppermost semiconductor chip of the stack, which reduces the difficulty of the manufacturing process of the semiconductor package. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged cross-sectional view of region A in FIG. [Figure 3] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 4] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 5] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 6] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 8] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 25] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 26] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 27]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 28] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] Next, specific examples of embodiments for carrying out a semiconductor package according to the present invention will be described with reference to the drawings.

[0014] FIG. 1 is a cross-sectional view for explaining a schematic configuration of a semiconductor package according to an embodiment of the present invention, and FIG. 2 is an enlarged cross-sectional view showing region A of FIG. 1 and 2, the semiconductor package includes a first structure ST1 and a second structure ST2 disposed on the first structure ST1.

[0015] The first structure ST1 includes a first chip stack. The first chip stack has a plurality of semiconductor chips (100, 200) stacked vertically. The semiconductor chip arranged at the bottom among the semiconductor chips (100, 200) in the first chip stack is referred to as the first semiconductor chip 100, and the semiconductor chip arranged at the top among the semiconductor chips (100, 200) in the first chip stack is referred to as the second semiconductor chip 200. In this specification, the first semiconductor chip 100 and the second semiconductor chip 200 are simply used to refer to the semiconductor chips located at the bottom and top of the first chip stack for ease of explanation, and even though the first and second semiconductor chips (100, 200) are called by different names, this does not mean that they are different semiconductor chips.

[0016] The first and second semiconductor chips (100, 200) may include the same semiconductor chip or may include different semiconductor chips. For example, the first and second semiconductor chips (100, 200) may be memory chips such as DRAM, SRAM, MRAM, or flash memory. Alternatively, the first semiconductor chip 100 may be a logic chip, and the second semiconductor chip 200 may be a memory chip. Although FIG. 1 shows a first chip stack having two semiconductor chips (100, 200), the present invention is not limited to this. The first chip stack may further include at least one semiconductor chip vertically stacked between the first semiconductor chip 100 and the second semiconductor chip 200 .

[0017] The first semiconductor chip 100 has a front surface and a back surface opposite to the front surface. The top surface of the first semiconductor chip 100 is the front surface, and the bottom surface of the first semiconductor chip 100 is the back surface. That is, the first semiconductor chip 100 is placed face up. The first semiconductor chip 100 has first chip pads 110 provided on its top surface. The first chip pads 110 are electrically connected to the integrated circuit of the first semiconductor chip 100 . The second semiconductor chip 200 is placed face up on the first semiconductor chip 100 . For example, the second semiconductor chip 200 has a back surface facing the first semiconductor chip 100 and a front surface opposite to the back surface. That is, the lower surface of the second semiconductor chip 200 is the back surface, and the upper surface of the second semiconductor chip 200 is the front surface. The second semiconductor chip 200 has second chip pads 210 provided on the top surface of the second semiconductor chip 200 . The second chip pads 210 are electrically connected to the integrated circuit of the second semiconductor chip 200 .

[0018] In FIG. 1, each of the first and second semiconductor chips (100, 200) is shown as having one chip pad (110, 210), but this is because only one chip pad (110, 210) is shown in the cross-sectional view of FIG. 1, and each of the first and second semiconductor chips (100, 200) may have multiple chip pads (110, 210). The first and second semiconductor chips (100, 200) are arranged in an offset stacked configuration. For example, the second semiconductor chip 200 may be stacked inclined in a first direction D1 parallel to the top surface of the first semiconductor chip 100, forming an upwardly inclined staircase shape (ie, a cascade shape). Specifically, the second semiconductor chip 200 protrudes in the first direction D1 from the first semiconductor chip 100 located thereunder. As the first and second semiconductor chips 100 and 200 are stacked in a staircase shape, a portion of the top surface of the first semiconductor chip 100 (hereinafter referred to as the exposed surface) is exposed. Along the offset stacking direction of the first and second semiconductor chips (100, 200), the exposed surface of the first semiconductor chip 100 is located adjacent to the side surface of the second semiconductor chip 200 in the opposite direction to the first direction D1.

[0019] Here, the offset stacking direction is defined as the direction in which a semiconductor chip is shifted relative to another semiconductor chip positioned below it when stacked. For example, in FIG. 1, the offset stacking direction of the first and second semiconductor chips (100, 200) is the first direction D1. The top surfaces of the first and second semiconductor chips 100 and 200 are active surfaces. For example, the first chip pads 110 of the first semiconductor chip 100 are provided on an exposed surface on the top surface of the first semiconductor chip 100 , and the second chip pads 210 of the second semiconductor chip 200 are provided on the top surface of the second semiconductor chip 200 . In other words, the first chip pads 110 of the first semiconductor chip 100 are located on one side of the second semiconductor chip 200 located thereon in the opposite direction to the first direction D1. Each of the first semiconductor chip 100 and the second semiconductor chip 200 has vertical connection terminals for vertical wiring. The vertical connection terminals include a first conductive post 310 connected to the first semiconductor chip 100 and a second conductive post 320 connected to the second semiconductor chip 200 .

[0020] First conductive posts 310 are provided on the first semiconductor chip 100 . The first conductive posts 310 are disposed on the top surface of the first semiconductor chip 100 . The first semiconductor chip 100 is electrically connected to at least some of the fourth conductive posts 340, which will be described later, using the first conductive posts 310. The first conductive post 310 is disposed on the first chip pad 110 of the first semiconductor chip 100 . The first conductive post 310 is electrically connected to the top surface of the first chip pad 110 . Each of the first conductive posts 310 is connected to one of the first chip pads 110 . The first conductive post 310 has a vertically extending pillar shape. The width of the first conductive post 310 may be constant depending on the vertical level, or may decrease toward the first chip pad 110 . The vertical level of the top surface of the first conductive post 310 is higher than the vertical level of the top surface of the second semiconductor chip 200 . The first conductive post 310 may include copper or tungsten.

[0021] A first seed pattern 312 is interposed between the first conductive post 310 and the first chip pad 110 . The first seed pattern 312 is connected to the top surface of the first chip pad 110 . The first conductive post 310 is connected to the top surface of the first seed pattern 312 . The width of the first seed pattern 312 is the same as the width of the first conductive post 310 . The side of the first seed pattern 312 is vertically aligned with the side of the first conductive post 310 . If the width of the first conductive post 310 is smaller than the width of the first chip pad 110, a portion of the top surface of the first chip pad 110 is not covered by the first seed pattern 312 and is exposed. The first seed pattern 312 includes a metallic material such as gold.

[0022] Second conductive posts 320 are provided on the second semiconductor chip 200 . The second conductive posts 320 are disposed on the top surface of the second semiconductor chip 200 . The second semiconductor chip 200 is electrically connected to at least some of the fourth conductive posts 340, which will be described later, using the second conductive posts 320. The second conductive posts 320 are disposed on the second chip pads 210 of the second semiconductor chip 200 . The second conductive post 320 is connected to the top surface of the second chip pad 210 . Each of the second conductive posts 320 is connected to one of the second chip pads 210 . The second conductive post 320 may have a vertically extending pillar shape or a bump shape. The vertical level of the top surface of the second conductive post 320 is substantially the same as the vertical level of the top surface of the first conductive post 310 . The second conductive post 320 includes a solder bump.

[0023] The first chip stack further includes a first insulating pattern 410 . The first insulating pattern 410 is disposed on the side surface 100 s of the first semiconductor chip 100 . The first insulating pattern 410 covers the entire side surface 100 s of the first semiconductor chip 100 . The first insulating pattern 410 surrounds the first semiconductor chip 100 in plan view. The cross-sectional shape of the first insulating pattern 410 may include a triangle. More specifically, the cross section of the first insulating pattern 410 may be a triangle with one side in contact with the side surface 100 s of the first semiconductor chip 100 . The width of the first insulating pattern 410 decreases from the bottom surface of the first semiconductor chip 100 toward the top surface of the first semiconductor chip 100 . The top end of the first insulating pattern 410 is located at the same level as the top surface of the first semiconductor chip 100 . The top end of the first insulating pattern 410 contacts the top surface of the first semiconductor chip 100 . The bottom surface of the first insulating pattern 410 is located at the same level as the bottom surface of the first semiconductor chip 100 . The bottom surface of the first insulating pattern 410 is coplanar with the bottom surface of the first semiconductor chip 100 .

[0024] In other words, the first insulating pattern 410 has a side surface that contacts the side surface 100s of the first semiconductor chip 100, a bottom surface that is coplanar with the bottom surface of the first semiconductor chip 100, and an inclined surface that connects the side surface and the bottom surface. The angle θ1 between the top surface of the first semiconductor chip 100 and the inclined surface of the first insulating pattern 410 is greater than 90° and less than 175°. The first insulating pattern 410 includes an insulating material. As an example, the first insulating pattern 410 may include an underfill material. The first insulating pattern 410 may include an epoxy resin.

[0025] The first structure ST1 further includes a first molding film 510. A first molding film 510 embeds the first chip stack. More specifically, the first molding film 510 surrounds the first insulating pattern 410, the first semiconductor chip 100, and the second semiconductor chip 200. The first molding film 510 covers the first insulating pattern 410, the first semiconductor chip 100, and the second semiconductor chip 200 from above. For example, the first molding film 510 covers the inclined surface of the first insulating pattern 410 , the top surface of the first semiconductor chip 100 , and the top surface of the second semiconductor chip 200 . The top surface of the first molding film 510 is spaced apart from the first and second semiconductor chips 100 and 200. The first molding layer 510 exposes the bottom surface of the first semiconductor chip 100 . The bottom surface of the first molding film 510, the bottom surface of the first insulating pattern 410, and the bottom surface of the first semiconductor chip 100 are coplanar. The first molding film 510 surrounds the first and second conductive posts (310, 320). The top surfaces of the first and second conductive posts 310 and 320 are exposed on the top surface of the first molding film 510 . The top surfaces of the first and second conductive posts 310 and 320 and the top surface of the first molding film 510 are coplanar. The first and second conductive posts 310 and 320 vertically penetrate the first molding film 510 and are connected to the first seed pattern 312 or the second chip pad 210 .

[0026] A passivation film 520 is disposed on the first structure ST1. A passivation film 520 covers the top surface of the first molding film 510 . The passivation film 520 has openings that expose the top surfaces of the first and second conductive posts 310 and 320 . The passivation film 520 includes an insulating material. For example, the passivation film 520 may include an insulating polymer or a photosensitive polymer (PID). For example, the photosensitive polymer may include at least one of a photosensitive polyimide, a polybenzoxazole (PBO), a phenolic polymer, or a benzocyclobutene-based polymer.

[0027] A second seed pattern 522 is provided on the passivation film 520 . The second seed pattern 522 is disposed in the opening of the passivation film 520 . For example, each of the second seed patterns 522 is disposed within one of the openings of the passivation film 520 . The second seed pattern 522 conformally covers the inner side and bottom surfaces of the openings in the passivation film 520 . On the bottom surface of the opening, the second seed pattern 522 contacts the top surface of the first conductive post 310 or the top surface of the second conductive post 320 . The second seed pattern 522 is connected to the top surface of the first conductive post 310 or the top surface of the second conductive post 320 . The top end of the second seed pattern 522 is located at a vertical level higher than the top surface of the passivation film 520 . Unlike the example shown in the figure, the top end of the second seed pattern 522 is located at the same vertical level as the top surface of the passivation film 520 . According to another embodiment, the second seed pattern 522 extends onto the top surface of the passivation layer 520 . The second seed pattern 522 includes a metallic material such as gold.

[0028] The second structure ST2 is disposed on the passivation film 520. The second structure ST2 includes a second chip stack. The second chip stack is spaced apart from the second seed pattern 522 in the first direction D1. The second chip stack has multiple semiconductor chips (600, 700) stacked vertically. The semiconductor chip arranged at the bottom among the semiconductor chips (600, 700) of the second chip stack is referred to as the third semiconductor chip 600, and the semiconductor chip arranged at the top among the semiconductor chips (600, 700) of the second chip stack is referred to as the fourth semiconductor chip 700.

[0029] In this specification, the third semiconductor chip 600 and the fourth semiconductor chip 700 are simply used to refer to the semiconductor chips located at the bottom and top of the second chip stack for ease of explanation, and even though the third and fourth semiconductor chips (600, 700) are referred to by different names, they are not different semiconductor chips. The third and fourth semiconductor chips (600, 700) may include the same semiconductor chip as each other, or may include different semiconductor chips. For example, the third and fourth semiconductor chips (600, 700) may be memory chips such as DRAM, SRAM, MRAM, or flash memory. Alternatively, the third semiconductor chip 600 may be a logic chip, and the fourth semiconductor chip 700 may be a memory chip. Although FIG. 1 shows a second chip stack having two semiconductor chips (600, 700), the present invention is not limited thereto. The second chip stack may further include one or more semiconductor chips stacked between the third semiconductor chip 600 and the fourth semiconductor chip 700.

[0030] The third semiconductor chip 600 has a front surface and a back surface opposite to the front surface. The top surface of the third semiconductor chip 600 is the front surface, and the bottom surface of the third semiconductor chip 600 is the back surface. That is, the third semiconductor chip 600 is placed face up on the passivation film 520 . The third semiconductor chip 600 has third chip pads 610 provided on its top surface. The third chip pads 610 are electrically connected to the integrated circuit of the third semiconductor chip 600 . The fourth semiconductor chip 700 is placed face up on the third semiconductor chip 600 . For example, the fourth semiconductor chip 700 has a back surface facing the third semiconductor chip 600 and a front surface opposite the back surface. That is, the lower surface of the fourth semiconductor chip 700 is the back surface, and the upper surface of the fourth semiconductor chip 700 is the front surface. The fourth semiconductor chip 700 has fourth chip pads 710 provided on the top surface of the fourth semiconductor chip 700 . The fourth chip pads 710 are electrically connected to the integrated circuit of the fourth semiconductor chip 700 .

[0031] In FIG. 1, the third and fourth semiconductor chips (600, 700) are each shown as having one chip pad (610, 710), but this is because only one chip pad (610, 710) is shown in the cross-sectional view of FIG. 1, and each of the third and fourth semiconductor chips (600, 700) has multiple chip pads (610, 710). The third and fourth semiconductor chips (600, 700) are arranged in an offset stacked configuration. For example, the fourth semiconductor chip 700 may be stacked inclined in the first direction D1 parallel to the top surface of the third semiconductor chip 600, and may have an upwardly inclined staircase shape (ie, a cascade shape). Specifically, the fourth semiconductor chip 700 protrudes in the first direction D1 from the third semiconductor chip 600 located thereunder. As the third and fourth semiconductor chips 600 and 700 are stacked in a staircase shape, a portion of the top surface of the third semiconductor chip 600 (hereinafter referred to as the exposed surface) is exposed. Along the offset stacking direction of the third and fourth semiconductor chips (600, 700), the exposed surface of the third semiconductor chip 600 is located adjacent to the side surface of the fourth semiconductor chip 700 in the opposite direction to the first direction D1. Here, the offset stacking direction is defined as the direction in which a semiconductor chip is shifted relative to another semiconductor chip positioned below it when stacked.

[0032] For example, in FIG. 1, the offset stacking direction of the third and fourth semiconductor chips (600, 700) is the first direction D1. The top surfaces of the third and fourth semiconductor chips (600, 700) are active surfaces. For example, the third chip pads 610 of the third semiconductor chip 600 are provided on the exposed surface on the top surface of the third semiconductor chip 600, and the fourth chip pads 710 of the fourth semiconductor chip 700 are provided on the top surface of the fourth semiconductor chip 700. In other words, the third chip pads 610 of the third semiconductor chip 600 are disposed on one side of the fourth semiconductor chip 700 positioned thereon in the opposite direction to the first direction D1. In FIG. 1, the offset stacking direction of the first and second semiconductor chips (100, 200) and the offset stacking direction of the third and fourth semiconductor chips (600, 700) are shown as being the same first direction D1, but the present invention is not limited to this. According to another embodiment, the offset stacking direction of the first and second semiconductor chips (100, 200) and the offset stacking direction of the third and fourth semiconductor chips (600, 700) are different from each other.

[0033] Each of the third semiconductor chip 600 and the fourth semiconductor chip 700 has vertical connection terminals for vertical wiring. The vertical connection terminals include a third conductive post 330 connected to the third semiconductor chip 600 and a fourth conductive post 340 connected to the fourth semiconductor chip 700 . The third conductive posts 330 are provided on the third semiconductor chip 600 . The third conductive posts 330 are disposed on the top surface of the third semiconductor chip 600 . The third semiconductor chip 600 is electrically connected to a pad layer 540 (described later) using the third conductive posts 330 . The third conductive posts 330 are disposed on the third chip pads 610 of the third semiconductor chip 600 . The third conductive post 330 is electrically connected to the top surface of the third chip pad 610 . Each of the third conductive posts 330 is connected to one of the third chip pads 610 . The third conductive post 330 has a vertically extending pillar shape. The width of the third conductive post 330 may be constant depending on the vertical level, or may decrease toward the third chip pad 610 . The vertical level of the top surface of the third conductive post 330 is higher than the vertical level of the top surface of the fourth semiconductor chip 700 . The third conductive post 330 may include copper or tungsten.

[0034] A third seed pattern 332 is interposed between the third conductive post 330 and the third chip pad 610 . The third seed pattern 332 is connected to the top surface of the third chip pad 610 . The third conductive post 330 is connected to the top surface of the third seed pattern 332 . The width of the third seed pattern 332 is the same as the width of the third conductive post 330 . The side of the third seed pattern 332 is aligned perpendicularly to the side of the third conductive post 330 . If the width of the third conductive post 330 is smaller than the width of the third chip pad 610, a portion of the top surface of the third chip pad 610 is not covered by the third seed pattern 332 and is exposed. The vertical thickness of the third seed pattern 332 is substantially the same as or similar to the vertical thickness of the second seed pattern 522 . The third seed pattern 332 contains the same material as the second seed pattern 522 . The third seed pattern 332 includes a metal material such as gold.

[0035] Fourth conductive posts 340 are provided on the fourth semiconductor chip 700 . The fourth conductive post 340 is disposed on the top surface of the fourth semiconductor chip 700 . The fourth semiconductor chip 700 is electrically connected to a pad layer 540 (described later) using the fourth conductive posts 340 . The fourth conductive post 340 is disposed on the fourth chip pad 710 of the fourth semiconductor chip 700 . The fourth conductive post 340 is connected to the top surface of the fourth chip pad 710 . Each of the fourth conductive posts 340 is connected to one of the fourth chip pads 710 . The fourth conductive post 340 may have a vertically extending pillar shape or a bump shape. The vertical level of the top surface of the fourth conductive post 340 is substantially the same as the vertical level of the top surface of the third conductive post 330 . The fourth conductive post 340 may include a solder bump.

[0036] The second chip stack further includes a second insulating pattern 420 . The second insulating pattern 420 is disposed on the side surface of the third semiconductor chip 600 . The second insulating pattern 420 covers the entire side surface of the third semiconductor chip 600 . The second insulating pattern 420 surrounds the third semiconductor chip 600 in plan view. The cross-sectional shape of the second insulating pattern 420 may include a triangle. More specifically, the cross section of the second insulating pattern 420 may be a triangle with one side in contact with the side surface of the third semiconductor chip 600 . The width of the second insulating pattern 420 decreases from the bottom surface of the third semiconductor chip 600 toward the top surface of the third semiconductor chip 600 . The top end of the second insulating pattern 420 is located at the same level as the top surface of the third semiconductor chip 600 . The top end of the second insulating pattern 420 contacts the top surface of the third semiconductor chip 600 . The bottom surface of the second insulating pattern 420 is located at the same level as the bottom surface of the third semiconductor chip 600 .

[0037] The bottom surface of the third semiconductor chip 600 and the bottom surface of the second insulating pattern 420 contact the top surface of the passivation film 520 . The bottom surface of the second insulating pattern 420 is coplanar with the bottom surface of the third semiconductor chip 600 . In other words, the second insulating pattern 420 has a side surface in contact with the side surface of the third semiconductor chip 600, a bottom surface coplanar with the bottom surface of the third semiconductor chip 600, and an inclined surface connecting the side surface and the bottom surface. The angle formed between the top surface of the third semiconductor chip 600 and the inclined surface of the second insulating pattern 420 is greater than 90° and less than 175°. The second insulating pattern 420 includes an insulating material. As an example, the second insulating pattern 420 may include an underfill material. The second insulating pattern 420 may include an epoxy resin.

[0038] The second structure ST2 further includes a second molding film 530. A second molding film 530 embeds the second chip stack. More specifically, the second molding film 530 surrounds the second insulating pattern 420, the third semiconductor chip 600, and the fourth semiconductor chip 700. The second molding film 530 covers the second insulating pattern 420, the third semiconductor chip 600, and the fourth semiconductor chip 700 from above. For example, the second molding film 530 covers the inclined surface of the second insulating pattern 420 , the top surface of the third semiconductor chip 600 , and the top surface of the fourth semiconductor chip 700 . The top surface of the second molding film 530 is spaced apart from the third and fourth semiconductor chips 600 and 700. The second molding film 530 exposes the bottom surface of the third semiconductor chip 600 . The bottom surface of the second molding film 530, the bottom surface of the second insulating pattern 420, and the bottom surface of the third semiconductor chip 600 are coplanar. The second molding film 530 surrounds the third and fourth conductive posts (330, 340). The top surfaces of the third and fourth conductive posts 330 and 340 are exposed on the top surface of the second molding film 530 . The top surfaces of the third and fourth conductive posts 330 and 340 and the top surface of the second molding film 530 are coplanar. The third and fourth conductive posts 330 and 340 vertically penetrate the second molding film 530 and are connected to the third seed pattern 332 or the fourth chip pad 710 .

[0039] The first structure ST1 further includes a fifth conductive post 350 for vertically arranging the first and second semiconductor chips (100, 200). The fifth conductive post 350 vertically penetrates the second molding film 530 and is connected to the second seed pattern 522 . The top surface of the fifth conductive post 350 is exposed on the top surface of the second molding film 530 . The top surface of the fifth conductive post 350 and the top surface of the second molding film 530 are coplanar.

[0040] A pad layer 540 is disposed on the second structure ST2. A pad layer 540 covers the top surface of the second molding film 530 . The pad layer 540 is vertically spaced from the second chip stack. For example, the bottom surface of the pad layer 540 and the top surface of the fourth semiconductor chip 700 are spaced apart from each other. The pad layer 540 is provided for external connection of the first to fourth semiconductor chips (100, 200, 600, 700). The pad layer 540 includes a pad insulating layer 542 and a pad 544 within the pad insulating layer 542 . The pad insulating layer 542 comprises an inorganic insulating layer such as silicon oxide or silicon nitride. Alternatively, the pad insulating layer 542 includes a polymer material. The pad insulating layer 542 may include an insulating polymer or a photosensitive polymer (PID). For example, the photosensitive polymer may include at least one of a photosensitive polyimide, a polybenzoxazole (PBO), a phenolic polymer, or a benzocyclobutene-based polymer.

[0041] Pads 544 are provided within the pad insulating layer 542 . The pads 544 are exposed on the upper and lower surfaces of the pad insulating layer 542 . In plan view, the position of the pad 544 corresponds to the third to fifth conductive posts (330, 340, 350). Pad 544 is a pad to which third to fifth conductive posts (330, 340, 350) described later are connected. For example, the third to fifth conductive posts 330, 340, and 350 vertically penetrate the second molding film 530 and are connected to the bottom surface of the pad 544. The first semiconductor chip 100 is electrically connected to the pad 544 through the first conductive post 310 , the second seed pattern 522 , and the fifth conductive post 350 . The second semiconductor chip 200 is electrically connected to the pad 544 through the second conductive post 320 , the second seed pattern 522 , and the fifth conductive post 350 . The third semiconductor chip 600 is electrically connected to the pads 544 through the third conductive posts 330 . The fourth semiconductor chip 700 is electrically connected to the pads 544 through the fourth conductive posts 340 . The pad 544 includes a conductive material. For example, the pad 544 may include copper.

[0042] According to an embodiment of the present invention, a second structure ST2 having a second chip stack is provided on a first structure ST1 having a first chip stack. At this time, first, second and fifth conductive posts (310, 320, 350) having large thicknesses are provided for vertical connection of the first and second semiconductor chips (100, 200) of the first chip stack. Therefore, the first, second, and fifth conductive posts (310, 320, 350) provided between the first and second semiconductor chips (100, 200) and the pad layer 540 firmly support the first and second semiconductor chips (100, 200) and the pad layer 540. In addition, the electrical resistance of the first, second, and fifth conductive posts (310, 320, 350) between the first and second semiconductor chips (100, 200) and the pad layer 540 is small. That is, a semiconductor package having improved structural stability and electrical characteristics is provided.

[0043] In the following embodiments, the components described in the embodiments of FIGS. 1 and 2 are designated by the same reference numerals, and for the sake of simplicity, the description thereof will be omitted or will be briefly described. That is, the differences between the embodiment of FIGS. 1 and 2 and the embodiment below will be mainly described. FIG. 3 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 3, the semiconductor chips (100, 200, 600, 700) of the first structure ST1 and the second structure ST2 include an adhesive layer. The first to fourth adhesive layers (102, 202, 602, 702) include a DAF (die attach film).

[0044] The first semiconductor chip 100 has a first adhesive layer 102 provided on the bottom surface of the first semiconductor chip 100 . The first adhesive layer 102 covers the bottom surface of the first semiconductor chip 100 . The first insulating pattern 410 surrounds the first semiconductor chip 100 and the first adhesive layer 102 . The bottom surface of the first insulating pattern 410 is coplanar with the bottom surface of the first adhesive layer 102 . The second semiconductor chip 200 has a second adhesive layer 202 provided on the bottom surface of the second semiconductor chip 200 . The second adhesive layer 202 covers the bottom surface of the second semiconductor chip 200 . The second semiconductor chip 200 is attached to the top surface of the first semiconductor chip 100 using a second adhesive layer 202 .

[0045] The third semiconductor chip 600 has a third adhesive layer 602 provided on the bottom surface of the third semiconductor chip 600 . The third adhesive layer 602 covers the bottom surface of the third semiconductor chip 600 . The third semiconductor chip 600 is attached to the upper surface of the passivation film 520 using a third adhesive layer 602 . The second insulating pattern 420 surrounds the third semiconductor chip 600 and the third adhesive layer 602 . The bottom surface of the second insulating pattern 420 is coplanar with the bottom surface of the third adhesive layer 602 . The fourth semiconductor chip 700 has a fourth adhesive layer 702 provided on a bottom surface of the fourth semiconductor chip 700 . The fourth adhesive layer 702 covers the bottom surface of the fourth semiconductor chip 700 . The fourth semiconductor chip 700 is attached to the top surface of the third semiconductor chip 600 using a fourth adhesive layer 702 .

[0046] FIG. 4 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 4, a padding layer 540 is provided. The pad layer 540 is disposed on the second structure ST2. The pad layer 540 is vertically spaced apart from the second structure ST2. The pad layer 540 is provided for external connection of the first to fourth semiconductor chips (100, 200, 600, 700). The pad layer 540 includes a pad insulating layer 542 and a pad 544 within the pad insulating layer 542 . The pad 544 may be a pad to which an external connection terminal 546 is provided. Pads 544 are provided within the pad insulating layer 542 . The pad 544 has a damascene structure. For example, pad 544 has a head portion and a tail portion that are integrally connected to one another. The head portion is a wiring portion or pad portion that horizontally extends the wiring in the pad layer 540 . The tail portion is a via portion that vertically connects the wiring in the pad layer 540 .

[0047] Pad 544 has a 'T' shaped cross section. The head portion of the pad 544 is provided on the upper surface of the pad insulating layer 542 , and the tail portion of the pad 544 extends from the lower surface of the head portion into the pad insulating layer 542 . A part of the head portion of the pad 544 corresponds to the pad of the pad layer 540 . For example, a portion of the head portion of the pad 544 is located on the upper surface of the pad insulating layer 542 . That is, the pad 544 protrudes above the upper surface of the pad insulating layer 542 . The third to fifth conductive posts (330, 340, 350) are connected to the lower surface of the tail portion of the pad 544.

[0048] FIG. 5 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 5, the semiconductor package includes a package substrate 550 instead of the pad layer 540 . The package substrate 550 is a rewiring substrate. For example, the package substrate 550 includes at least two or more substrate wiring layers stacked on top of each other. In this specification, the substrate wiring layer refers to a wiring layer formed by patterning one insulating material layer and one conductive material layer, respectively. That is, the conductive patterns in one substrate wiring layer are wirings that extend horizontally and do not need to overlap each other vertically. Each substrate wiring layer includes a substrate insulating pattern 552 and a substrate wiring pattern 554 within the substrate insulating pattern 552 . The board wiring pattern 554 of any one board wiring layer is electrically connected to the board wiring pattern 554 of another adjacent board wiring layer.

[0049] The substrate insulating pattern 552 may include an inorganic insulating layer such as silicon oxide or silicon nitride. Alternatively, the substrate insulating pattern 552 may include a polymer material. The substrate insulating pattern 552 may include an insulating polymer or a photosensitive polymer (PID). For example, the photosensitive polymer may include at least one of a photosensitive polyimide, a polybenzoxazole (PBO), a phenolic polymer, or a benzocyclobutene-based polymer. A substrate wiring pattern 554 is provided within the substrate insulating pattern 552 . The substrate wiring pattern 554 has a damascene structure. For example, the substrate wiring pattern 554 has a head portion and a tail portion that are integrally connected to each other. The head portion is a wiring portion or a pad portion that horizontally extends the wiring within the package substrate 550 . The tail portion is a via portion that vertically connects wiring within the package substrate 550 .

[0050] The board wiring pattern 554 has a 'T' shaped cross section. In each substrate wiring layer, the head portion of the substrate wiring pattern 554 is disposed on the upper surface of the substrate insulating pattern 552 . In each substrate wiring layer, the tail portion of the substrate wiring pattern 554 extends from the lower surface of the head portion and connects to the head portion of another substrate wiring pattern 554 through the substrate insulating pattern 552 of the substrate wiring layer disposed above it. The substrate wiring pattern 554 includes a conductive material. For example, the substrate wiring pattern 554 may include copper (Cu). The substrate wiring pattern 554 rewires the semiconductor chips (100, 200, 600, 700) in the semiconductor package. The tail portion of the board wiring pattern 554 of the board wiring layer arranged at the lowest end among the board wiring layers passes through the lowest board insulating pattern 552 and is connected to the third to fifth conductive posts (330, 340, 350).

[0051] Alternatively, pads to which the third to fifth conductive posts (330, 340, 350) are connected may be provided separately on the bottom board wiring layer, and the bottom board wiring pattern 554 may be connected to the pads by passing through the top board insulating pattern 552. The semiconductor package has a fan-out structure due to the package substrate 550 . The substrate wiring pattern 554 is connected to an external pad 556 disposed on the top surface of the package substrate 550 . The external pad 556 is a pad on which an external connection terminal 558 is arranged. The external pad 556 penetrates the uppermost board insulating pattern 552 and is connected to the board wiring pattern 554 . Although not shown, a protective layer is disposed on the top surface of package substrate 550 . The protective layer covers the substrate insulating pattern 552 and the substrate wiring pattern 554 and exposes the external pads 556 .

[0052] FIG. 6 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 6, the semiconductor package further includes a protective film 560 . A protective film 560 is provided on the lower surface of the first structure ST1. The passivation layer 560 covers the lower surface of the first molding layer 510 , the upper surface of the first insulating pattern 410 , and the lower surface of the first semiconductor chip 100 . The protective film 560 protects the first structure ST1, particularly the first semiconductor chip 100, from external impacts. The protective film 560 may include an insulating polymer.

[0053] FIG. 7 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 7, the second semiconductor chip 200 further includes first dummy bumps 321. The first dummy bumps 321 are disposed on the top surface of the second semiconductor chip 200 . The first dummy bumps 321 contact the top surface of the second semiconductor chip 200 . The first dummy bumps 321 are spaced apart from the second chip pads 210 . The first dummy bumps 321 are electrically insulated from the integrated circuits of the second semiconductor chip 200 . The height of the first dummy bump 321 is substantially the same as the height of the second conductive post 320 . The first dummy bump 321 contacts the lower surface of the passivation film 520 . Therefore, the second semiconductor chip 200 and the first structure ST 1 including the second semiconductor chip 200 are supported on the lower surface of the passivation film 520 by the first dummy bumps 321 . That is, a semiconductor package with improved structural stability is provided. The first dummy bumps 321 may include solder bumps.

[0054] The fourth semiconductor chip 700 further includes second dummy bumps 341 . The second dummy bumps 341 are disposed on the top surface of the fourth semiconductor chip 700 . The second dummy bumps 341 contact the top surface of the fourth semiconductor chip 700 . The second dummy bump 341 is spaced apart from the fourth chip pad 710 . The second dummy bumps 341 are electrically insulated from the integrated circuits of the fourth semiconductor chip 700 . The height of the second dummy bump 341 is substantially the same as the height of the fourth conductive post 340 . The second dummy bump 341 contacts the bottom surface of the pad layer 540 . Therefore, the fourth semiconductor chip 700 and the second structure ST2 including the fourth semiconductor chip 700 are supported on the lower surface of the pad layer 540 by the second dummy bumps 341. That is, a semiconductor package with improved structural stability is provided. The second dummy bumps 341 may include solder bumps.

[0055] FIG. 8 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 8, the first structure ST1 has a plurality of first chip stacks. Although two first chip stacks are shown in FIG. 8, the present invention is not limited to this. The first chip stack may be provided in three or more pieces. The offset stacking directions of the first chip stacks are different from each other. The offset stacking direction of each of the first chip stacks varies depending on the arrangement of the second seed pattern 522 of the passivation film 520 and the arrangement of the first and second chip pads (110, 210) of the first chip stack. For example, as shown in FIG. 8, the offset stacking direction of the first chip stack located in the first direction D1 is the first direction D1. The offset stacking direction of the first chip stack located in the opposite direction to the first direction D1 is the opposite direction to the first direction D1. However, the offset stacking direction of the first chip stack shown in FIG. 8 is only one example, and according to embodiments of the present invention, the offset stacking direction of the first chip stack may be variously provided as needed.

[0056] The second structure ST2 has a plurality of second chip stacks. Although two second chip stacks are shown in FIG. 8, the present invention is not limited to this. The second chip stack may be provided in three or more pieces. The offset stacking directions of the second chip stacks are different from each other. The offset stacking direction of each of the second chip stacks varies depending on the arrangement of the pads 544 of the pad layer 540 and the arrangement of the third and fourth chip pads (610, 710) of the second chip stack. For example, as shown in FIG. 8, the offset stacking direction of the second chip stack located in the first direction D1 is the first direction D1. The offset stacking direction of the second chip stack located in the opposite direction to the first direction D1 is the opposite direction to the first direction D1. However, the offset stacking direction of the second chip stack shown in FIG. 8 is only one example, and according to embodiments of the present invention, the offset stacking direction of the second chip stack may be variously provided as needed.

[0057] 9 to 28 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. Referring to FIG. 9, a carrier substrate 1000 is provided. The carrier substrate 1000 can be an insulating substrate, including glass or polymer, or a conductive substrate, including metal. Although not shown, an adhesive member may be provided on the top surface of the carrier substrate 1000 . As an example, the adhesive member includes an adhesive tape. The first semiconductor chip 100 is attached onto the carrier substrate 1000 using an adhesive material. The first semiconductor chip 100 is placed face up. That is, the back surface (ie, non-active surface) of the first semiconductor chip 100 faces the carrier substrate 1000 , and the first chip pads 110 of the first semiconductor chip 100 face the carrier substrate 1000 .

[0058] According to another embodiment, as shown in FIG. 10, before attaching the first semiconductor chip 100 onto the carrier substrate 1000, a protective film 560 may be attached onto the carrier substrate 1000. The protective film 560 covers the entire top surface of the carrier substrate 1000 . Thereafter, the first semiconductor chip 100 is adhered or placed on the top surface of the protective film 560 . In this case, the semiconductor package described with reference to FIG. 6 is manufactured. The following description will be given based on the result of FIG.

[0059] Referring to FIG. 11, a first insulating pattern 410 is formed on a carrier substrate 1000 . For example, an insulating material is injected between the top surface of the carrier substrate 1000 and the side surface of the first semiconductor chip 100 to form the first insulating pattern 410 . The first insulating pattern 410 is formed on the side surface of the first semiconductor chip 100 . The first insulating pattern 410 covers the side surfaces of the first semiconductor chip 100 . The first insulating pattern 410 surrounds the first semiconductor chip 100 in plan view. The first insulating pattern 410 fills the space between the top surface of the carrier substrate 1000 and the side surface of the first semiconductor chip 100 . More specifically, the cross section of the first insulating pattern 410 is a triangle that contacts the top surface of the carrier substrate 1000 and the side surface of the first semiconductor chip 100 . The first insulating pattern 410 has an inclined surface connecting the top surface of the first semiconductor chip 100 and the top surface of the carrier substrate 1000 .

[0060] Referring to FIG. 12, a first seed film 314 is formed on a carrier substrate 1000 . On the carrier substrate 1000 , the first seed film 314 conformally covers the top surface of the carrier substrate 1000 , the inclined surface of the first insulating pattern 410 , and the top surface of the first semiconductor chip 100 . According to an embodiment of the present invention, depending on the shape of the first semiconductor chip 100, the first semiconductor chip 100 and the carrier substrate 1000 may have a step. However, by forming the first insulating pattern 410 having an inclined surface on the side surface of the first semiconductor chip 100, it becomes easier to form the first seed layer 314 on the carrier substrate 1000 and the first semiconductor chip 100. For example, no empty space is formed between the first seed layer 314 and the side of the first semiconductor chip 100 or between the first seed layer 314 and the top surface of the carrier substrate 1000 . Therefore, a method for manufacturing a semiconductor package with fewer defects is provided.

[0061] Referring to FIG. 13, a first sacrificial layer 1010 is formed on a carrier substrate 1000 . The first sacrificial layer 1010 covers the first semiconductor chip 100 , the first insulating pattern 410 , and the first seed layer 314 on the carrier substrate 1000 . The first sacrificial layer 1010 is patterned to form a first through hole TH1 exposing the first seed layer 314. The first through holes TH1 are located on the first chip pads 110, respectively. The bottom surface of the first through hole TH1 exposes the top surface of the first seed layer 314.

[0062] Referring to FIG. 14, first conductive posts 310 are formed on the first semiconductor chip 100 . For example, the first seed film 314 exposed by the first through hole TH1 is used as a seed to perform a plating process, thereby forming the first conductive post 310 filling the first through hole TH1.

[0063] Referring to FIG. 15, the first sacrificial film 1010 is removed. The first sacrificial layer 1010 is removed to expose the first seed layer 314 . A patterning process is performed using the first conductive posts 310 as a mask to pattern the first seed film 314 . The first seed layer 314 is patterned to form a first seed pattern 312 that remains under the first conductive post 310 . The first conductive post 310 is connected to the first chip pad 110 through the first seed pattern 312 . According to the embodiment of the present invention, the first conductive posts 310 for electrical connection of the first semiconductor chip 100 are formed through a plating process using the first sacrificial layer 1010 . Therefore, a plurality of first conductive posts 310 can be formed at once through one process, which can simplify the manufacturing process of the semiconductor package.

[0064] Referring to FIG. 16, a second semiconductor chip 200 is formed on a semiconductor wafer 201 . For example, integrated circuits such as transistors are formed on one surface of the semiconductor wafer 201, and wiring and second chip pads 210 connected to the integrated circuits are formed. A second conductive post 320 is formed on the second chip pad 210 . For example, a mask film exposing the second chip pads 210 is formed on the semiconductor wafer 201, and then a conductive material is filled on the second chip pads 210 to form the second conductive posts 320. Thereafter, the semiconductor wafer 201 is cut along the sawing lines of the semiconductor wafer 201 to separate the second semiconductor chips 200 from each other. According to an embodiment of the present invention, second conductive posts 320 for electrical connection of the second semiconductor chip 200 arranged on the upper end of the carrier substrate 1000 can be formed during the step of forming the second semiconductor chip 200 on the semiconductor wafer 201. Therefore, there is no need to form terminals for electrical connection on the stacked second semiconductor chip 200, which reduces the difficulty of the manufacturing process of the semiconductor package.

[0065] Referring to FIG. 17, a second semiconductor chip 200 is stacked on a first semiconductor chip 100 . Referring to one first semiconductor chip 100, the second semiconductor chip 200 is attached onto the first semiconductor chip 100 using an adhesive layer. The second semiconductor chip 200 is placed face up. That is, the back surface of the second semiconductor chip 200 faces the carrier substrate 1000 , and the second chip pads 210 and the second conductive posts 320 of the second semiconductor chip 200 are disposed to face the carrier substrate 1000 . The first and second semiconductor chips 100 and 200 are stacked so as to be shifted in the opposite direction of the first direction D1 so that the first chip pads 110 are exposed.

[0066] Referring to FIG. 18, a first molding film 510 is formed on a carrier substrate 1000 . For example, a molding material is applied to the top surface of the carrier substrate 1000 to embed the first and second semiconductor chips 100 and 200 and the first and second conductive posts 310 and 320, and the molding material is hardened to form the first molding film 510. The molding material may include, by way of example, an epoxy molding compound.

[0067] Referring to FIG. 19, a thinning process is performed on the first molding film 510 . The thinning process includes chemical mechanical polishing (CMP) or grinding processes, and the like. The thinning process lowers the top surface of the first molding film 510 . The thinning process is carried out until the top surfaces of the first and second conductive posts (310, 320) are exposed. During the thinning process, portions of the tops of the first and second conductive posts (310, 320) are removed.

[0068] Referring to FIG. 20, a passivation film 520 is formed on the first molding film 510 . An insulating layer is formed on the first molding film 510 . The insulating layer may include an insulating polymer or a photosensitive polymer. Thereafter, the insulating layer is patterned to form a passivation film 520 having openings that expose the top surfaces of the first and second conductive posts 310 and 320.

[0069] Referring to FIG. 21, a third semiconductor chip 600 is attached onto the passivation film 520 using an adhesive material. The third semiconductor chip 600 is placed face up. That is, the back surface (ie, non-active surface) of the third semiconductor chip 600 faces the passivation film 520 , and the third chip pads 610 of the third semiconductor chip 600 are disposed to face the passivation film 520 . The third semiconductor chip 600 is disposed so as to be spaced apart from the opening in the passivation film 520 . The second insulating pattern 420 is formed on the passivation film 520 . For example, an insulating material is injected between the top surface of the passivation film 520 and the side surface of the third semiconductor chip 600 to form the second insulating pattern 420 . The second insulating pattern 420 is formed on the side surface of the third semiconductor chip 600 . The second insulating pattern 420 covers the side surfaces of the third semiconductor chip 600 . The second insulating pattern 420 surrounds the third semiconductor chip 600 in plan view. The second insulating pattern 420 fills the space between the top surface of the passivation film 520 and the side surface of the third semiconductor chip 600 . More specifically, the cross section of the second insulating pattern 420 is a triangle that contacts the top surface of the passivation film 520 and the side surface of the third semiconductor chip 600 . The second insulating pattern 420 has an inclined surface that connects the top surface of the third semiconductor chip 600 and the top surface of the passivation film 520 .

[0070] Referring to FIG. 22, a second seed film 334 is formed on the passivation film 520 . The second seed film 334 conformally covers the upper surface of the passivation film 520 , the inclined surface of the second insulating pattern 420 , and the upper surface of the third semiconductor chip 600 on the passivation film 520 . According to the embodiment of the present invention, depending on the shape of the third semiconductor chip 600, the third semiconductor chip 600 and the passivation film 520 may have a step. However, by forming the second insulating pattern 420 having an inclined surface on the side surface of the third semiconductor chip 600, it becomes easier to form the second seed film 334 on the passivation film 520 and the third semiconductor chip 600. For example, empty spaces are less likely to occur between the second seed film 334 and the side surface of the third semiconductor chip 600 or between the second seed film 334 and the top surface of the passivation film 520 . Therefore, a method for manufacturing a semiconductor package with fewer defects is provided.

[0071] Referring to FIG. 23, a second sacrificial film 1020 is formed on the passivation film 520 . The second sacrificial layer 1020 covers the third semiconductor chip 600 , the second insulating pattern 420 , and the second seed layer 334 on the passivation layer 520 . The second sacrificial layer 1020 is patterned to form a second through hole TH2 and a third through hole TH3 that expose the second seed layer 334. The second through holes TH2 are located on the third chip pads 610, respectively. The third through-hole TH3 is located above the first and second conductive posts (310, 320). The bottom surfaces of the second and third through holes TH2 and TH3 expose the top surface of the second seed layer 334.

[0072] Referring to FIG. 24, third conductive posts 330 are formed on a third semiconductor chip 600 . A fifth conductive post 350 is formed on the first and second conductive posts (310, 320). For example, a plating process is performed using the second seed film 334 exposed by the second and third through holes (TH2, TH3) as a seed to form a third conductive post 330 filling the second through hole TH2 and a fifth conductive post 350 filling the third through hole TH3.

[0073] Referring to FIG. 25, the second sacrificial film 1020 is removed. The second sacrificial film 1020 is removed to expose the second seed film 334 . The second seed film 334 is patterned by performing a patterning process using the third and fifth conductive posts (330, 350) as a mask. The second seed film 334 is patterned to form a first seed pattern 312 that remains under the third and fifth conductive posts (330, 350). The third and fifth conductive posts ( 330 , 350 ) are connected to the first chip pad 110 through the first seed pattern 312 . According to an embodiment of the present invention, the third conductive post 330 for electrical connection of the third semiconductor chip 600 and the fifth conductive post 350 for electrical connection of the first and second semiconductor chips (100, 200) are formed through a plating process using the second sacrificial film 1020. Therefore, the third and fifth conductive posts (330, 350) can be formed at once through one process, which can simplify the manufacturing process of the semiconductor package.

[0074] Referring to FIG. 26, a fourth semiconductor chip 700 is formed. The process for forming the fourth semiconductor chip 700 is the same as or similar to the process for forming the second semiconductor chip 200 described with reference to FIG. For example, an integrated circuit such as a transistor is formed on one surface of a semiconductor wafer, and wiring and fourth chip pads 710 connected to the integrated circuit are formed. A fourth conductive post 340 is formed on the fourth chip pad 710 . Thereafter, the semiconductor wafer is cut along the sawing lines of the semiconductor wafer to separate the fourth semiconductor chips 700 from each other. A fourth semiconductor chip 700 is stacked on the third semiconductor chip 600 . Referring to one third semiconductor chip 600, the fourth semiconductor chip 700 is attached onto the third semiconductor chip 600 using an adhesive layer. The fourth semiconductor chip 700 is placed face up. That is, the back surface of the fourth semiconductor chip 700 faces the passivation film 520 , and the fourth chip pads 710 and the fourth conductive posts 340 of the fourth semiconductor chip 700 are disposed to face the passivation film 520 . The third and fourth semiconductor chips (600, 700) are stacked so as to be shifted in the opposite direction of the first direction D1 so that the third chip pads 610 are exposed.

[0075] Referring to FIG. 27, a second molding film 530 is formed on the passivation film 520 . For example, a molding material is applied to the upper surface of the passivation film 520 so as to embed the third and fourth semiconductor chips (600, 700) and the third to fifth conductive posts (330, 340, 350), and the molding material is hardened to form the second molding film 530. The molding material may include an epoxy molding compound.

[0076] Referring to FIG. 28, a thinning process is performed on the second molding film 530 . The thinning process includes chemical mechanical polishing (CMP) or grinding processes, and the like. The thinning process lowers the top surface of the second molding film 530 . The thinning process is carried out until the top surfaces of the third to fifth conductive posts (330, 340, 350) are exposed. During the thinning process, portions of the tops of the third to fifth conductive posts (330, 340, 350) are removed.

[0077] Referring back to FIG. 1, a pad layer 540 is formed on the second molding film 530 . An insulating layer is formed on the second molding film 530 . The insulating layer is then patterned to form a pad insulating layer 542 having openings that expose the top surfaces of the third to fifth conductive posts (330, 340, 350). The openings are then filled with a conductive material to form pads 544 . According to another embodiment, the package substrate 550 described with reference to FIG. 5 may be formed on the second molding film 530 instead of the pad layer 540 . The carrier substrate 1000 is removed. A sawing process is performed on the pad layer 540 and the second molding film 530 to manufacture a semiconductor package of a required size.

[0078] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0079] 100 First semiconductor chip 110 First chip pad 200 Second semiconductor chip 210 Second chip pad 310 First Conductive Post 312 1st Seed Pattern 320 Second Conductive Post 330 Third Conductive Post 332 3rd seed pattern 340 4th Conductive Post 350 5th Conductive Post 410 First insulation pattern 420 Second insulation pattern 510 First molding film 520 Passivation Film 522 2nd Seed Pattern 530 Second molding film 540 pad layer 542 Pad insulation layer 544 Pad 546, 558 External connection terminal 550 package substrate 552 PCB insulation pattern 554 PCB wiring pattern 556 External Pad 600 Third Semiconductor Chip 610 3rd chip pad 700 4th Semiconductor Chip 710 4th chip pad

Claims

1. a first structure; a second structure, The first structure is a first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip and shifted horizontally relative to the first semiconductor chip in a first direction; a first insulating pattern covering a side surface of the first semiconductor chip; Here, the width of the first insulating pattern decreases from the bottom surface of the first semiconductor chip toward the top surface of the first semiconductor chip, a first molding film surrounding the first semiconductor chip, the second semiconductor chip, and the first insulating pattern; a first conductive post that vertically penetrates the first molding film and is connected to the top surface of the first semiconductor chip; a second conductive post connected to an upper surface of the second semiconductor chip and exposed on an upper surface of the first molding film.

2. the first semiconductor chip includes first chip pads provided on the top surface of the first semiconductor chip and arranged in a direction opposite to the first direction of the second semiconductor chip; The semiconductor package of claim 1 , wherein the first structure further comprises a first seed pattern interposed between the first conductive post and the first chip pad.

3. the second structure is disposed on the first structure; The second structure is a third semiconductor chip; a fourth semiconductor chip disposed on the third semiconductor chip and shifted horizontally relative to the first semiconductor chip in the first direction; a second insulating pattern covering a side surface of the third semiconductor chip; Here, the width of the second insulating pattern decreases from the lower surface of the third semiconductor chip toward the upper surface of the third semiconductor chip, a second molding film surrounding the third semiconductor chip, the fourth semiconductor chip, and the second insulating pattern; a third conductive post vertically penetrating the second molding film and connected to the top surface of the third semiconductor chip; a fourth conductive post connected to an upper surface of the fourth semiconductor chip and exposed on an upper surface of the second molding film; 2. The semiconductor package of claim 1, further comprising: a fifth conductive post that vertically penetrates the second molding film and is electrically connected to the first and second conductive posts of the first structure.

4. a passivation film interposed between the first structure and the second structure; the passivation layer covers an upper surface of the first molding layer of the first structure; 4. The semiconductor package of claim 3, wherein the passivation film covers a lower surface of the second molding film of the second structure, the lower surface of the third semiconductor chip, and a lower surface of the second insulating pattern.

5. further comprising an external pad disposed on the second structure; the external pad is provided on the top surface of the second molding film of the second structure; 4. The semiconductor package of claim 3, wherein the external pads are connected to the third to fifth conductive posts of the second structure.

6. further comprising a rewiring substrate disposed on the second structure; the redistribution substrate includes a substrate insulating layer covering the second molding film of the second structure, and a substrate wiring pattern provided in the substrate insulating layer; 4. The semiconductor package of claim 3, wherein the substrate wiring pattern penetrates the substrate insulating layer and is connected to the top surfaces of the third to fifth conductive posts of the second structure.

7. the first insulating pattern covers the entire side surface of the first semiconductor chip; 2. The semiconductor package of claim 1, wherein the top of the first insulating pattern is positioned at the same vertical level as the top surface of the first semiconductor chip.

8. the top end of the first insulating pattern contacts the top surface of the first semiconductor chip; 2. The semiconductor package of claim 1, wherein the first insulating pattern has an inclined surface connected to the top surface of the first semiconductor chip.

9. The semiconductor package of claim 1 , wherein the first molding film contacts a side surface of the second semiconductor chip.

10. 2. The semiconductor package of claim 1, wherein a bottom surface of the first molding film, the bottom surface of the first semiconductor chip, and a bottom surface of the first insulating pattern are coplanar.

11. a first chip stack including a plurality of first semiconductor chips stacked on top of one another; wherein each of the first semiconductor chips includes a first chip pad provided on its top surface; a first molding film covering the first chip stack; a passivation layer covering an upper surface of the first molding layer; a first conductive post that vertically penetrates the first molding film and is connected to the first chip pad; a first seed pattern that vertically penetrates the passivation film and is connected to the first conductive post.

12. The semiconductor package of claim 11 , further comprising a first insulating pattern covering a side surface of the first semiconductor chip at the bottom of the first chip stack.

13. an uppermost end of the first insulating pattern contacts the upper surface of the lowermost first semiconductor chip; 13. The semiconductor package of claim 12, wherein the first insulating pattern has an inclined surface connected to the top surface of the lowermost first semiconductor chip.

14. 12. The semiconductor package of claim 11, further comprising a second seed pattern interposed between the first chip pad of the first semiconductor chip at the bottom of the first chip stack and one of the first conductive posts.

15. a second chip stack including a second semiconductor chip stacked on the passivation film; wherein each of the second semiconductor chips includes a second chip pad provided on its top surface; a second molding film covering the second chip stack on the passivation film; a second conductive post that vertically penetrates the second molding film and is connected to the second chip pad; a third conductive post that vertically penetrates the second molding film and is electrically connected to the first conductive post; pads provided on an upper surface of the second molding film and connected to the second and third conductive posts; The semiconductor package of claim 11 , wherein the first seed pattern connects the first conductive post and the third conductive post.

16. a first structure; The first structure is a first semiconductor chip; wherein the first semiconductor chip includes a first chip pad provided on an upper surface of the first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip and shifted horizontally relative to the first semiconductor chip in a first direction; wherein the second semiconductor chip includes a second chip pad provided on an upper surface of the second semiconductor chip; a first molding film covering the first semiconductor chip and the second semiconductor chip; a first seed pattern provided on an upper surface of the first chip pad; a first conductive post that vertically penetrates the first molding layer and contacts the first seed pattern; a second conductive post that vertically penetrates the first molding film and contacts the second chip pad.

17. the first structure further includes a first insulating pattern covering a side surface of the first semiconductor chip; 17. The semiconductor package of claim 16, wherein the width of the first insulating pattern decreases from the bottom surface of the first semiconductor chip toward the top surface of the first semiconductor chip.

18. an uppermost end of the first insulating pattern contacts the top surface of the first semiconductor chip; 18. The semiconductor package of claim 17, wherein the first insulating pattern has an inclined surface connected to the top surface of the first semiconductor chip.

19. a second structure disposed on the first structure; The second structure is a third semiconductor chip; wherein the third semiconductor chip includes a third chip pad provided on an upper surface of the third semiconductor chip; a fourth semiconductor chip disposed on the third semiconductor chip and shifted horizontally relative to the third semiconductor chip in the first direction; wherein the fourth semiconductor chip includes a fourth chip pad provided on an upper surface of the fourth semiconductor chip; a second molding film covering the third semiconductor chip and the fourth semiconductor chip; a second seed pattern provided on an upper surface of the third chip pad; a third conductive post vertically penetrating the second molding layer and contacting the second seed pattern; a fourth conductive post that vertically penetrates the second molding film and contacts the fourth chip pad; 17. The semiconductor package of claim 16, further comprising: a fifth conductive post that vertically penetrates the second molding film and is electrically connected to the first and second conductive posts of the first structure.

20. a passivation film interposed between the first structure and the second structure; the passivation layer covers an upper surface of the first molding layer of the first structure; 20. The semiconductor package of claim 19, wherein the passivation film covers a bottom surface of the second molding film of the second structure and a bottom surface of the third semiconductor chip.

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