Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor in which the occurrence of a crack can be suppressed.SOLUTION: A multilayer ceramic capacitor includes: a multilayer chip with an approximately cuboid shape in which dielectric layers mainly containing ceramic and internal electrode layers are alternately stacked, which is covered with cover layers mainly containing ceramic, the cover layers holding the multilayer chip from both directions in the stacking direction, and the stacked internal electrode layers being formed so as to be exposed to two end surfaces that face each other alternately; and a pair of external electrodes formed from the two end surfaces that face each other to at least any side surface of the multilayer chip. In the pair of external electrodes, the first metal layer is in contact with the two end surfaces, the second metal layer is in contact with the cover layer part and the side surface in the two end surfaces, the first metal layer contains more ceramic than the second metal layer, and the second metal layer contains 90 wt% or more of metal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] After mounting a multilayer ceramic capacitor on a substrate, cracks may occur in the multilayer ceramic capacitor due to stress caused by bending of the substrate. A technology for suppressing such cracks has been disclosed (see, for example, Patent Document 1). In Patent Document 1, two metal sintered layers with different glass component contents are used for the external electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-43424 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned technology, the content of the glass component is not specified, and therefore there is a risk that the occurrence of cracks cannot be sufficiently suppressed.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks. [Means for solving the problem]

[0006] The multilayer ceramic capacitor of the present invention comprises a laminated chip having an approximately rectangular parallelepiped shape, in which dielectric layers and internal electrode layers, each primarily composed of ceramic, are alternately stacked and covered with cover layers, each primarily composed of ceramic, sandwiching them from both sides in the stacking direction, with the stacked internal electrode layers exposed at two alternately opposing end faces; and a pair of external electrodes formed from the two opposing end faces to at least one of the side faces of the laminated chip, in which a first metal layer contacts the two end faces and a second metal layer contacts the cover layer portions and the side faces of the two end faces, the first metal layer having a larger ceramic content than the second metal layer, and the second metal layer being a layer containing 90 wt% or more of metal.

[0007] In the multilayer ceramic capacitor, the second metal layer may have a ceramic content of less than 5 wt %.

[0008] In the multilayer ceramic capacitor, the ceramic contained in the first metal layer and the second metal layer may be a glass component or a common material.

[0009] In the above multilayer ceramic capacitor, the ceramic contained in the first metal layer and the second metal layer may be ceramic containing the dielectric layer as a main component.

[0010] In the multilayer ceramic capacitor, the second metal layer may not contain the ceramic. [Effects of the Invention]

[0011] According to the present invention, the occurrence of cracks can be suppressed. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] 10(a) and 10(b) are diagrams for explaining external electrodes according to a comparative embodiment. [Figure 3] 4(a) and 4(b) are diagrams illustrating an external electrode according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 5] 10A to 10C are diagrams illustrating a flow of another method for manufacturing a multilayer ceramic capacitor. [Figure 6] 1A and 1B are diagrams illustrating examples and comparative examples. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described with reference to the drawings.

[0014] (Embodiment) First, the multilayer ceramic capacitor will be described. Fig. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100. As illustrated in Fig. 1, the multilayer ceramic capacitor 100 includes a rectangular parallelepiped-shaped laminated chip 10 and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. The four faces of the laminated chip 10 other than the two end faces are referred to as side faces. The external electrodes 20a, 20b extend to the four side faces. However, the external electrodes 20a, 20b are spaced apart from each other on the four side faces.

[0015] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 on which the external electrodes 20a are provided and at the end face on which the external electrodes 20b are provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrodes 20a and 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. Furthermore, of the four side surfaces of the multilayer chip 10, two side surfaces corresponding to the top and bottom surfaces in the stacking direction of the dielectric layers 11 and the internal electrode layers 12 (hereinafter referred to as the stacking direction) are covered with a cover layer 13. The cover layer 13 is primarily composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layers 11.

[0016] The size of the multilayer ceramic capacitor 100 is, for example, 0.2 mm in length, 0.1 mm in width, and 0.3 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0017] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used for the internal electrode layers 12. The dielectric layers 11 are mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. Note that the perovskite structure is formed by an ABO3 that deviates from the stoichiometric composition. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1) etc. can be used.

[0018] Here, an external electrode 200 according to a comparative example will be described. Fig. 2(a) is a cross-sectional view of the external electrode 200, a partial cross-sectional view taken along line AA in Fig. 1. Note that hatching representing the cross section is omitted in Fig. 2(a). As illustrated in Fig. 2(a), the external electrode 200 has a structure in which a Cu plating layer 22, a conductive resin layer 23, a Ni plating layer 24, and a Sn plating layer 25 are formed on an underlayer 21. The underlayer 21, the Cu plating layer 22, the conductive resin layer 23, the Ni plating layer 24, and the Sn plating layer 25 extend from both end faces of the laminated chip 10 to the four side faces.

[0019] The base layer 21 is primarily composed of metals such as Cu, Ni, Al (aluminum), and Zn (zinc), and also contains glass components for densifying the base layer 21 and co-materials for controlling the sinterability of the base layer 21. The base layer 21, which contains a large amount of these ceramic components, has good adhesion to the cover layer 13, which is primarily composed of a ceramic material. The conductive resin layer 23 is a resin layer containing a metal filler such as Ag. Because the conductive resin layer 23 is flexible, it relieves stress caused by bending of the substrate on which the multilayer ceramic capacitor 100 is mounted.

[0020] However, the conductive resin layer 23 tends to be thick because it is formed by coating or the like. Therefore, a structure in which the conductive resin layer 23 is sandwiched between the base layer 21 and the plating layer is disadvantageous for achieving a smaller size and larger capacitance of the multilayer ceramic capacitor 100. In particular, in low-profile products, the thickness of the external electrodes 20a, 20b on the side surfaces of the multilayer chip 10 has a significant effect. Furthermore, the conductive resin layer 23 is made of an expensive metal such as Ag, which increases costs. Therefore, an external electrode 200a that does not include the conductive resin layer 23 will be considered.

[0021] As shown in FIG. 2(b), when a multilayer ceramic capacitor is mounted on a substrate, the external electrodes 200a on both end faces and either side of the laminated chip 10 are mounted with solder 50. In this case, if the substrate is bent, stress caused by the bending is transmitted to the external electrodes 200a on the side of the laminated chip 10. This causes stress in the area surrounded by the dashed line in FIG. 2(b). As a result, a crack 60 occurs in the laminated chip 10.

[0022] Therefore, in this embodiment, as illustrated in Fig. 3(a), the external electrodes 20a and 20b have a structure in which a Cu plating layer 22, a Ni plating layer 24, and a Sn plating layer 25 are formed on an underlayer 21 on the end faces of the laminated chip 10. Although Fig. 3(a) illustrates the external electrode 20b, the external electrode 20a also has a similar structure.

[0023] The base layer 21 includes a glass component for densifying the base layer 21 and a co-material for improving the sinterability of the base layer 21. The glass component is an oxide of Ba, Sr, Ca, Zn, Al, Si (silicon), B (boron), or the like. The co-material is a ceramic component, such as a ceramic component that is the main component of the dielectric layer 11. The base layer 21 includes 5 wt% or more of the glass component or 5 wt% or more of the co-material. The base layer 21 is provided on the end surface of the laminated chip 10 but does not extend to the side surface of the laminated chip 10. A metal layer 26 is formed from the base layer 21 on the end surface of the laminated chip 10 to the four side surfaces of the laminated chip 10. The metal layer 26 is a layer containing 90 wt% or more of metal and includes less than 5 wt% of the glass component or less than 5 wt% of the co-material. Alternatively, the metal layer 26 does not include a glass component or a co-material. The Cu plating layer 22, the Ni plating layer 24, and the Sn plating layer 25 may extend from the end face of the laminated chip 10 to the side face on which the metal layer 26 extends.

[0024] The adhesion between the base layer 21, which contains a large amount of ceramic components, and the dielectric layer 11, which is primarily composed of ceramic material, is improved. Therefore, good adhesion between the external electrodes 20a, 20b and the laminated chip 10 is achieved at both end surfaces of the laminated chip 10. On the other hand, because the ceramic content in the metal layer 26 is low, sufficient adhesion between the metal layer 26 and the cover layer 13 is not achieved. That is, the external electrodes 20a, 20b are easily peeled off from the laminated chip 10 at the side portions of the laminated chip 10. As a result, as illustrated in FIG. 3(b), if the substrate on which the multilayer ceramic capacitor 100 is mounted bends and stress is transmitted to the side surfaces of the laminated chip 10, the metal layer 26 will peel off from the laminated chip 10. In this case, stress from the substrate is prevented from being transmitted to the laminated chip 10, thereby suppressing cracking of the laminated ceramic capacitor 100. Since peeling of the external electrodes 20a, 20b is suppressed at the end faces of the laminated chip 10, the connection between the external electrodes 20a, 20b and the internal electrode layer 12 is maintained.

[0025] From the viewpoint of ease of peeling, it is preferable that the ceramic content of the glass component, co-material, etc. of the metal layer 26 is small. For example, it is preferable that the ceramic content of the metal layer 26 is 2 wt % or less.

[0026] Note that stress from the substrate is alleviated if at least a portion of the external electrodes 20a, 20b on the side surfaces that function as the mounting surfaces of the laminated chip 10 are made of the metal layer 26. Therefore, it is sufficient that a portion of the external electrodes 20a, 20b on the side surfaces that function as the mounting surfaces of the laminated chip 10 are made of the metal layer 26.

[0027] Furthermore, instead of the portion of the base layer 21 that contacts the end face of the cover layer 13, the metal layer 26 may be provided so as to contact the end face of the cover layer 13. Even in this configuration, the connection between the external electrodes 20a, 20b and the internal electrode layer 12 is maintained.

[0028] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0029] (raw powder production process) First, a predetermined additive compound is added to the ceramic powder, which is the main component of the dielectric layer 11, depending on the purpose. Examples of the additive compound include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Dy (dysprosium), Tm (thulium), Ho (holmium), Tb (terbium), Yb (ytterbium), Sm (samarium), Eu (eurobium), Gd (gadolinium), and Er (erbium)), as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B, Na (sodium), K (potassium), and Si. For example, first, a compound containing the additive compound is mixed with the ceramic powder and calcined. Next, the resulting ceramic material particles are wet-mixed with the additive compound, dried, and pulverized to prepare a ceramic powder.

[0030] (Lamination process) Next, the resulting ceramic material powder is wet-mixed with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer such as dioctyl phthalate (DOP).The resulting slurry is then applied to a substrate by, for example, a die coater or doctor blade method to form a strip-shaped dielectric green sheet with a thickness of, for example, 0.8 μm or less, and then dried.

[0031] Next, a conductive paste for forming internal electrodes is printed on the surface of the dielectric green sheet by screen printing, gravure printing, or the like to arrange the pattern of the internal electrode layers 12. The conductive paste for forming internal electrode layers contains powder of the main component metal of the internal electrode layers 12, a binder, a solvent, and, if necessary, other auxiliary agents. It is preferable to use binders and solvents different from those used in the ceramic slurry described above. In addition, the ceramic material that is the main component of the dielectric layers 11 may be dispersed in the conductive paste for forming internal electrodes as a co-material.

[0032] Next, the dielectric green sheet on which the internal electrode layer pattern is printed is punched out to a predetermined size, and the punched dielectric green sheet is laminated, with the base material peeled off, to a predetermined number of layers (e.g., 200 to 500 layers) so that the internal electrode layers 12 and the dielectric layers 11 alternate, and so that the edges of the internal electrode layers 12 are alternately exposed at both longitudinal end faces of the dielectric layers 11 and alternately drawn out to a pair of external electrodes with opposite polarities. Cover sheets that will become the cover layers 13 are pressure-bonded to the top and bottom of the laminated pattern-forming sheets, and the laminate is cut to a predetermined chip size (e.g., 1.0 mm x 0.5 mm). This results in a ceramic laminate having an approximately rectangular parallelepiped shape.

[0033] (Firing process) The ceramic laminate thus obtained is debindered in an N2 atmosphere at 250-500°C, and then fired in a reducing atmosphere at 1100-1300°C for 10 minutes to 2 hours, causing the compounds constituting the dielectric green sheets to sinter and grow in grains. In this way, a multilayer ceramic capacitor 100 is obtained, which has a laminated chip 10 internally formed by alternating dielectric layers 11 and internal electrode layers 12 made of sintered bodies, and cover layers 13 formed as the outermost layers on the top and bottom of the laminate.

[0034] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0035] (External electrode formation process) Next, external electrodes 20a, 20b are formed on the laminated chip 10. There are two methods for forming the external electrodes 20a, 20b: one is to bake the base layer 21 after firing the laminated chip 10, and the other is to bake the base layer 21 simultaneously with firing the laminated chip 10. First, the method for baking the base layer 21 after firing the laminated chip 10 will be described.

[0036] Metal paste A containing metal filler, glass frit, binder, and solvent is applied to both end surfaces of the laminated chip 10 and dried. The amount of glass frit mixed is, for example, 5 parts or more. Next, metal paste B containing metal filler, binder, and solvent is applied over metal paste A and onto each side of the laminated chip 10 and dried. Metal paste B does not contain glass frit. Note that because the sintering of metal paste B is slow, it is preferable to adjust the sinterability by, for example, reducing the particle size of the metal filler. Then, metal paste A and metal paste B are baked. This forms the base layer 21 and metal layer 26. Note that the binder and solvent volatilize during baking. Then, Cu plating layer 22, Ni plating layer 24, and Sn plating layer 25 are formed on the base layer 21 by plating. Cu or the like is suitable as the metal filler for this method. The baking is preferably performed at 700°C to 900°C for approximately 3 to 30 minutes, and particularly at 760°C to 840°C for 5 to 15 minutes. Depending on the baking conditions, the amount of glass or co-materials (charged amount) contained in the metal paste A may differ from the amount detected in the finished product. For example, for a 10-part charged glass, the amount after baking may be 5 wt% to 9 wt%. This is due to the diffusion of components in the glass or co-materials into the laminated chip 10.

[0037] This method reduces the amount of glass on the side surfaces of the laminated chip 10. This prevents multiple laminated ceramic capacitors from fusing together even when they are in contact with each other. Furthermore, when applying metal paste B, metal paste A absorbs the solvent in metal paste B, increasing the viscosity of metal paste B. This allows the metal layer 26 at the corners of the laminated chip 10 to be thicker.

[0038] Next, a method for simultaneously firing the base layer 21 during firing of the laminated chip 10 will be described. In this case, as illustrated in FIG. 5, the ceramic laminate obtained in the lamination process is debindered in an N2 atmosphere at 250 to 500°C, and then metal paste A containing a metal filler, a co-material, a binder, and a solvent is applied to both end surfaces of the ceramic laminate and dried. Next, metal paste B containing a metal filler, a binder, and a solvent is applied over metal paste A and onto each side surface of the ceramic laminate and dried. Metal paste B does not contain a co-material. Note that, because metal paste B sinters quickly, it is preferable to adjust the sinterability by, for example, increasing the particle size of the metal filler. Then, metal paste A and metal paste B are fired simultaneously with the ceramic laminate. The firing conditions are, for example, as exemplified in the firing process described above. A reoxidation treatment may then be performed in an N2 gas atmosphere at 600 to 1000°C. Thereafter, a Cu plating layer 22, a Ni plating layer 24, and a Sn plating layer 25 are formed on the underlayer 21 by plating. Ni or the like is suitable as the metal filler for this method.

[0039] According to the manufacturing method of this embodiment, a base layer 21 containing 5 wt% or more of ceramic components and a metal layer 26 containing less than 5 wt% of ceramic components are formed. The base layer 21, which contains a large amount of ceramic components, has good adhesion to the dielectric layer 11, which is primarily composed of ceramic material. Therefore, good adhesion is achieved between the external electrodes 20a, 20b and the laminated chip 10 at both end surfaces of the laminated chip 10. On the other hand, the ceramic content of the metal layer 26 is low, so sufficient adhesion is not achieved between the metal layer 26 and the cover layer 13. That is, the external electrodes 20a, 20b are easily peeled off from the laminated chip 10 at the side portions of the laminated chip 10. Therefore, if the substrate on which the multilayer ceramic capacitor 100 is mounted bends and stress is transmitted to the side surfaces of the laminated chip 10, the metal layer 26 will peel off from the laminated chip 10. In this case, stress from the substrate is prevented from being transmitted to the laminated chip 10, thereby preventing cracks in the laminated ceramic capacitor 100. Since peeling of the external electrodes 20a, 20b is suppressed at the end faces of the laminated chip 10, the connection between the external electrodes 20a, 20b and the internal electrode layer 12 is maintained.

[0040] In this embodiment, the base layer 21 is an example of a first metal layer that contacts two end faces of the laminated chip 10 and has a ceramic content of 5 wt% or more. The metal layer 26 is an example of a second metal layer that contacts the side face of the laminated chip 10 and has a ceramic content of less than 5 wt%. [Example]

[0041] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0042] Example 1 A laminated chip 10 was prepared by firing without forming external electrodes. The laminated chip 10 was 3.2 mm long, 1.6 mm wide, and 1.6 mm high, with a capacitance of 10 μF. As illustrated in FIG. 6, metal paste A containing Cu filler, glass frit, binder, and solvent was applied to both end surfaces of the laminated chip 10 and allowed to dry. Next, metal paste B containing Cu filler, binder, and solvent was applied over metal paste A and onto each side of the laminated chip 10 and allowed to dry. Metal paste B did not contain glass frit. Since metal paste B without glass frit sinters slowly, the particle size of the Cu filler was reduced, for example, to about 1 / 10 to 1 / 2, to adjust the sinterability. The amount of glass frit mixed, the binder material, and the solvent material are shown in Table 1. [Table 1]

[0043] Thereafter, the metal paste A and the metal paste B were baked. As a result, the underlayer 21 and the metal layer 26 were formed. The binder and the solvent were evaporated by baking. Thereafter, a Cu plating layer 22, a Ni plating layer 24, and a Sn plating layer 25 were formed on the underlayer 21 by plating. Ten thousand samples according to Example 1 were produced.

[0044] In Comparative Example 1, metal paste A was applied from both end faces to each side face of the laminated chip 10 and dried, without applying and drying metal paste B. The other conditions were the same as in Example 1. Ten thousand samples according to Comparative Example 1 were produced.

[0045] For each of Example 1 and Comparative Example 1, a deflection test (indentation amount: 10 mm) was conducted on 10 out of 10,000 pieces, and the subsequent crack occurrence rate was investigated. The results of the deflection test are shown in Table 2. Cracks occurred in Comparative Example 1. In contrast, crack occurrence was suppressed to 0 / 10 in Example 1. This is thought to be because the metal layer 26 peeled off when stress caused by deflection was transmitted to the external electrodes 20a, 20b. [Table 2]

[0046] The product fusion rate and the average thickness of the metal layer 26 at the corners of the laminated chip 10 were also investigated. The results are shown in Tables 3 and 4. As shown in Table 3, the fusion rate was reduced in Example 1. This is thought to be because the amount of glass on the side surfaces of the laminated chip 10 was reduced. As shown in Table 4, the thickness of the corners was increased in Example 1. This is thought to be because the viscosity of metal paste B increased when metal paste A absorbed the solvent of metal paste B during application of metal paste B. [Table 3] [Table 4]

[0047] Example 2 A laminated chip 10 (laminate) was prepared before firing. When the laminated chip 10 was completed, it had a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm, and a capacitance of 10 μF. Metal paste C containing Ni filler, co-materials, binder, and solvent was applied to both end surfaces of the laminate and allowed to dry. Next, metal paste D containing Ni filler, binder, and solvent was applied over metal paste C to each side of the laminate and allowed to dry. Metal paste D did not contain co-materials. Note that because metal paste D sinters quickly, the sinterability was adjusted by increasing the particle size of the Ni filler, for example, by approximately 2 to 5 times. The amounts of co-materials mixed, binder materials, and solvent materials are shown in Table 5. [Table 5]

[0048] Thereafter, the metal paste C and the metal paste D were fired simultaneously with the laminate. After that, a Cu plating layer 22, a Ni plating layer 24, and a Sn plating layer 25 were formed on the underlayer 21 by plating. Ten thousand samples according to Example 2 were produced.

[0049] In Comparative Example 2, metal paste C was applied from both end faces to each side face of the laminate and dried, without applying and drying metal paste D. The other conditions were the same as in Example 2. Ten thousand samples according to Comparative Example 2 were produced.

[0050] For each of Example 2 and Comparative Example 2, a deflection test (indentation amount: 10 mm) was conducted on 10 out of 10,000 pieces, and the subsequent crack occurrence rate was investigated. The results are shown in Table 6. Cracks occurred in Comparative Example 2. In contrast, crack occurrence was suppressed to 0 / 10 in Example 2. This is thought to be because the metal layer 26 peeled off when stress caused by deflection was transmitted to the external electrodes 20a, 20b. [Table 6]

[0051] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0052] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 20a,20b external electrode 21 Base layer 22 Cu plating layer 23 Conductive resin layer 24 Ni plating layer 25 Sn plating layer 100 Multilayer ceramic capacitors

Claims

1. A multilayer ceramic capacitor mounted on a substrate, a laminated chip having a substantially rectangular parallelepiped shape, in which dielectric layers and internal electrode layers, each composed mainly of ceramic, are alternately laminated and covered with cover layers, each composed mainly of ceramic, sandwiching the dielectric layers from both sides in the lamination direction, and the laminated internal electrode layers are exposed at two end faces that alternately face each other; a pair of external electrodes formed from the two opposing end faces to at least one of the four side faces of the laminated chip; The pair of external electrodes has a first metal layer in contact with the two end faces and a second metal layer in contact with the one side face, the first metal layer has a ceramic content greater than that of the second metal layer, the ceramic content of the first metal layer is 5 wt % or more and 25 wt % or less, and the second metal layer is a layer containing 90 wt % or more of metal, a multilayer ceramic capacitor, wherein a portion of the pair of external electrodes formed on one of the side surfaces is mounted on the substrate via solder;

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the second metal layer has a ceramic content of less than 5 wt %.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein the ceramic contained in the first metal layer and the second metal layer is a glass component or a common material.

4. 2. The multilayer ceramic capacitor according to claim 1, wherein the ceramic contained in the first metal layer and the second metal layer is the ceramic whose main component is the dielectric layer.

5. 2. The multilayer ceramic capacitor according to claim 1, wherein the second metal layer does not contain the ceramic.

6. 2. The multilayer ceramic capacitor according to claim 1, wherein the second metal layer is in contact with the cover layer portions of the two end faces.

7. 2. The multilayer ceramic capacitor according to claim 1, wherein the ceramic content of the first metal layer is 10 wt % or more and 25 wt % or less.

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