Power semiconductor module

Abstract

To suppress gate oscillation.SOLUTION: A power semiconductor module 100 comprises: a first chip 1A including a first switching element; a second chip 1B including a second switching element; a gate wiring part 32 which is electrically connected to a first gate pad of the first switching element and a second gate pad of the second switching element; and a wiring part 32 for control which is electrically connected to a first main pad 11A of the first switching element and a second main pad 11B of the second switching element. A length of the gate wiring part 22 from a first gate pad 10A to a gate confluence point 25 is longer than a length of the wiring part 32 for control from the first main pad 11A to a control confluence point 35. In a view from the first switching element and the second switching element, portions 36A and 36B of the wiring part 32 for control on the side farther than the control confluence point 35 and portions 26A and 26B of the gate wiring part 22 on the side closer than the gate confluence point 25 are adjacent in parallel.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power semiconductor module. [Background technology]

[0002] In a power semiconductor module having multiple semiconductor switching elements operating in parallel, it is known that unintended gate voltage oscillation (gate oscillation) occurs due to variations in wiring constants between the semiconductor switching elements, sudden switching operations, etc. (See Patent Document 1.) In Patent Document 1, the gate pattern is positioned outside the control source pattern and is made thicker than the control source pattern, thereby making the wiring inductance between the gate pads larger than the wiring inductance between the source pads of the semiconductor switching elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 044748 Summary of the Invention [Problem to be solved by the invention]

[0004] However, due to limitations on module size, there is also a limit to how much the gate inductance between parallel chips can be increased. Therefore, the amount of inductance cannot be increased significantly. Furthermore, an increase in gate inductance can cause the loop inductance between the gate and source via the gate drive circuit to become too large, which can lead to concerns about a decrease in switching speed or oscillation in the gate-source loop.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a power semiconductor module in which gate oscillation is suppressed. [Means for solving the problem]

[0006] A power semiconductor module according to one aspect of the present invention includes a first chip including a first switching element, a second chip including a second switching element, a gate wiring portion electrically connected to a first gate pad of the first switching element and a second gate pad of the second switching element, and a control wiring portion electrically connected to a first main pad of the first switching element and a second main pad of the second switching element. The gate wiring portion and the control wiring portion are electrically connectable to a gate drive circuit that controls the on / off of the first switching element and the second switching element. The gate wiring portion has a gate junction point where the gate wiring portion connected to the first gate pad and the gate wiring portion connected to the second gate pad merge. The control wiring portion has a control junction point where the control wiring portion connected to the first main pad and the control wiring portion connected to the second main pad merge. The length of the gate wiring portion from the first gate pad to the gate junction point is longer than the length of the control wiring portion from the first main pad to the control junction point. When viewed from the first switching element and the second switching element, a part of the control wiring portion farther from the control junction point and a part of the gate wiring portion closer to the gate junction point are adjacent to each other in parallel. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a power semiconductor module in which gate oscillation is suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing the configuration of a power semiconductor module 100 according to the first embodiment. [Figure 2] FIG. 2 is an equivalent circuit diagram of the power semiconductor module 100 of FIG. [Figure 3] FIG. 3 is a plan view showing the configuration of a power semiconductor module 101 according to the second embodiment. [Figure 4A] FIG. 4A is a top view showing the configuration of the front surface side of a power semiconductor module 102 according to the third embodiment. [Figure 4B] FIG. 4B is a bottom view showing the configuration of the rear side of the control board 46 in FIG. 4A. [Figure 5] FIG. 5 is a plan view showing the configuration of a power semiconductor module 102A according to a modified example of the third embodiment. [Figure 6] FIG. 6 is a plan view showing the configuration of a power semiconductor module 103 according to a modified example of the fourth embodiment. [Figure 7A] FIG. 7A is a plan view showing the overall configuration of a power semiconductor module 104 according to a modified example of the fifth embodiment. [Figure 7B] FIG. 7B is an enlarged plan view of a region Mg in FIG. 7A. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

[0010] (First embodiment) [Configuration of power semiconductor module 100] The configuration of a power semiconductor module 100 according to the first embodiment will be described with reference to Fig. 1. The power semiconductor module 100 has an insulating substrate 42, a conductor plate 41 bonded to the surface of the insulating substrate 42, and a first chip 1A and a second chip 1B mounted on the conductor plate 41.

[0011] The insulating substrate 42 is made of, for example, ceramics such as silicon nitride, aluminum nitride, or alumina, an insulating sheet containing boron nitride or resin, or resin. The conductor plate 41 is a conductor pattern made of metal such as copper (Cu) or aluminum (Al). The conductor plate 41 may be formed not only on the front surface of the insulating substrate 42 but also on the back surface facing in the opposite direction to the front surface.

[0012] Although not shown, the conductor plate 41 may be connected in series to a source electrode of another power semiconductor element outside the power semiconductor module 100 using a lead frame, a wire, or the like. In the embodiment, an example is shown in which a conductor pattern is used as the conductor plate 41, but a lead frame made of Cu, Al, or a Cu clad material, or a block of Cu, Al, copper molybdenum, or the like may also be used as the conductor plate 41.

[0013] A first switching element (not shown) is formed on the first chip 1A, and a second switching element (not shown) is formed on the second chip 1B.

[0014] A first main pad 11A connected to one main electrode (not shown) of the first switching element and a first gate pad 10A connected to the gate (not shown) of the first switching element are formed on the surface of the first chip 1A. A second main pad 11B connected to one main electrode (not shown) of the second switching element and a second gate pad 10B connected to the gate (not shown) of the second switching element are formed on the surface of the second chip 1B.

[0015] The other main electrodes (not shown) of the first and second switching elements are formed on the back surfaces of first chip 1A and second chip 1B, respectively. The other main electrodes are electrically and thermally connected to conductive plate 41 using solder or a sintered material such as silver or copper.

[0016] The first switching element and the second switching element are semiconductor switching elements formed from semiconductors such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), etc. Examples of the first switching element and the second switching element include power switching semiconductor elements such as metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs).

[0017] In the case of a MOSFET, one main electrode is a source and the other main electrode is a drain. In the case of an IGBT, one main electrode is an emitter and the other main electrode is a collector. In the embodiment, the first switching element and the second switching element are MOSFETs.

[0018] The first switching element and the second switching element are configured to use only elements of the same type, but multiple types of power switching semiconductor elements may be used. Each of the first switching element and the second switching element may be composed of multiple power switching semiconductor elements connected in series or parallel. Each of the first chip 1A and the second chip 1B may have a diode connected in anti-parallel to the MOSFET or IGBT. In the first embodiment (FIGS. 1 and 2), an example is shown in which the power semiconductor module 100 is mounted with two power switching semiconductor elements (chips), but three or more power switching semiconductor elements (chips) may be mounted. An example in which three power switching semiconductor elements (chips) are mounted will be described in the fifth embodiment (FIGS. 7A and 7B).

[0019] 1, a first main pad 11A and a first gate pad 10A are arranged on the surface of the first chip 1A, but a control pad may also be arranged. Like the first main pad 11A, the control pad is connected to one of the main electrodes (sources) of the first switching element, but is an electrode pad for extracting a source potential that serves as a reference for the gate voltage of the first switching element, and is distinguished from the first main pad 11A through which the main current flows. The same is true for the second chip 1B. Conductor wiring 31A and conductor wiring 31B are electrically connected to the control pads of the first chip 1A and the second chip 1B, respectively.

[0020] A sensing pad connected to a diode for sensing the temperature of the first chip 1A, a current pad for detecting the amount of main current, etc. may be further formed on the surface of the first chip 1A. Each pad may be made of Cu, Al, or the like, and the surface of the pad may be plated with a metal such as Cu.

[0021] A conductor wiring 43A is electrically connected to the first main pad 11A. A main current controlled by a first switching element flows through the conductor wiring 43A. A conductor wiring 43B is electrically connected to the second main pad 11B. A main current controlled by a second switching element flows through the conductor wiring 43B. The conductor wirings 43A and 43B are wires made of, for example, Cu or Al. The conductor wirings 43A and 43B have a wire diameter and number that do not cause any problems even if the main current flows through them. Although not shown in the figures, the conductor wirings 43A and 43B are electrically connected outside the power semiconductor module 100.

[0022] A "control wiring section" is electrically connected to the first main pad 11A and the second main pad 11B. The "control wiring section" includes conductor wirings 31A, 31B, and 33, a control source pattern 32, and a control external terminal 34, as shown below.

[0023] One end of conductor wiring 31A made of a wire is electrically connected to the first main pad 11A. The other end of conductor wiring 31A is electrically connected to a control source pattern 32. Like the conductor plate 41, the control source pattern 32 is a conductor pattern made of a metal such as Cu or Al and bonded to the main surface of the insulating substrate 42. One end of conductor wiring 31B made of a wire is electrically connected to the second main pad 11B. The other end of conductor wiring 31B is electrically connected to the control source pattern 32. The control source pattern 32 connected to conductor wiring 31A and the control source pattern 32 connected to conductor wiring 31B merge at a control junction point 35. The control source pattern 32 has a control junction point 35.

[0024] One end of a conductor wiring 33 made of a wire is electrically connected to an end of the control source pattern 32 that is farther from the control junction point 35 when viewed from the first switching element and the second switching element. The other end of the conductor wiring 33 is electrically connected to a control external terminal 34.

[0025] The first gate pad 10A and the second gate pad 10B are electrically connected to a "gate wiring section." The "gate wiring section" includes conductor wirings 21A, 21B, and 23, a gate pattern 22, and a gate external terminal 24, as shown below.

[0026] One end of conductor wiring 21A made of a wire is electrically connected to the first gate pad 10A. The other end of conductor wiring 21A is electrically connected to a gate pattern 22. Like the conductor plate 41, the gate pattern 22 is a conductor pattern made of a metal such as Cu or Al and bonded to the main surface of the insulating substrate 42. One end of conductor wiring 21B made of a wire is electrically connected to the second gate pad 10B. The other end of conductor wiring 21B is electrically connected to the gate pattern 22. The gate pattern 22 connected to conductor wiring 21A and the gate pattern 22 connected to conductor wiring 21B merge at a gate junction 25. The gate pattern 22 has a gate junction 25.

[0027] One end of a conductor wiring 23 made of a wire is electrically connected to a gate junction 25 of the gate pattern 22. The other end of the conductor wiring 23 is electrically connected to a gate external terminal 24.

[0028] The control source pattern 32 and the gate pattern 22 are not limited to conductor patterns bonded to the surface of the insulating substrate 42, but may be metal plates such as lead frames, or may be mounted on a substrate such as ceramic or glass epoxy that is separate from the insulating substrate 42.

[0029] The control external terminals 34 and the gate external terminals 24 are made of a metal such as Cu or Al, and their surfaces may be copper-plated. The control external terminals 34 and the gate external terminals 24 are electrically connected to a gate driver IC (see FIG. 2) mounted on a control board (not shown) or the like outside the power semiconductor module 100.

[0030] FIG. 2 is an equivalent circuit diagram of the power semiconductor module 100 of FIG. 1. The power semiconductor module 100 of FIG. 1 corresponds to the area surrounded by the dashed line in FIG. 2. As shown in FIG. 2, a first switching element 12A and a second switching element 12B each made of a MOSFET are connected in parallel. Specifically, the drains (the other electrodes) of the first switching element 12A and the second switching element 12B are connected on a conductor plate 41. The gates of the first switching element 12A and the second switching element 12B are connected at a gate junction point 25. The control sources of the first switching element 12A and the second switching element 12B are connected at a control junction point 35. The main current sources of the first switching element 12A and the second switching element 12B are connected outside the power semiconductor module 100. Although not shown, the conductor wiring 43A and the conductor wiring 43B are electrically connected.

[0031] Outside the power semiconductor module 100, the control external terminal 34 can be connected to a gate driver IC 44 (an example of a "gate drive circuit"), and the gate external terminal 24 can be connected to the gate driver IC 44 via a gate resistor 45 for adjusting the switching speed and suppressing gate oscillation. The gate driver IC 44 controls the switching operations of the first switching element 12A and the second switching element 12B by controlling the voltage applied between the source and gate of the first switching element 12A and the second switching element 12B.

[0032] The control wiring portion and the gate wiring portion of the power semiconductor module 100 have parasitic partial inductances L1a, L2a, L3a, L4a, L1b, L2b, L3b, and L4b.

[0033] Returning to FIG. 1 , the control source pattern 32 is formed so that the connection points between the conductor wiring 31A and the conductor wiring 31B and the control source pattern 32 are connected by straight lines at the control junction point 35. That is, the connection points are connected to the control junction point 35 by the shortest distance. The control junction point 35 is located midway between the connection points between the conductor wiring 31A and the conductor wiring 31B and the control source pattern 32. The control source pattern 32 extends from the control junction point 35 toward the control external terminal 34.

[0034] In contrast, the gate pattern 22 is not formed so as to connect the connection points of the conductor wiring 21A and the conductor wiring 21B with the gate pattern 22 by straight lines. The gate pattern 22 is formed so as to detour around the outside of the control source pattern 32. Therefore, the distance between each of the connection points and the gate junction point 25 is longer than the similar distance on the source side.

[0035] This allows the length of the gate wiring portion from first gate pad 10A to gate junction point 25 to be longer than the length of the control wiring portion from first main pad 11A to control junction point 35. The length of the gate wiring portion from first gate pad 10A to gate junction point 25 includes the length of conductor wiring 21A and the length of gate pattern 22 from the connection point of conductor wiring 21B and gate pattern 22 to gate junction point 25. The length of the control wiring portion from first main pad 11A to control junction point 35 includes the length of conductor wiring 31A and the length of control source pattern 32 from the connection point of conductor wiring 31A and control source pattern 32 to control junction point 35.

[0036] For the same width and thickness of the wiring, the longer the wiring, the larger the partial inductance parasitic on the wiring. As the length of the gate wiring portion from first gate pad 10A to gate junction point 25 increases, the partial inductances L1a and L2a parasitic on the gate wiring portion from first gate pad 10A to gate junction point 25 increase. As the length of the control wiring portion from first main pad 11A to control junction point 35 decreases, the partial inductance L3a parasitic on the control wiring portion from first main pad 11A to control junction point 35 decreases. The same is true for the gate wiring portion and control wiring portion on the second chip 1B side.

[0037] In this way, the partial inductance of the gate wiring section between the first chip 1A and the second chip 1B connected in parallel (referred to as "between parallel chips") can be increased while the partial inductance of the control wiring section between the parallel chips can be reduced, thereby suppressing gate oscillation.

[0038] As shown in FIG. 1, when viewed from the first switching element and the second switching element, portions 36A, 36B of the control wiring portion farther from the control junction point 35 and portions 26A, 26B of the gate wiring portion closer to the gate junction point 25 are adjacent and parallel to each other.

[0039] Specifically, as viewed from the first switching element, a portion 36A of the control source pattern 32 farther from the control junction point 35 faces a portion 26A of the gate pattern 22 closer to the gate junction point 25. As viewed from the second switching element, a portion 36B of the control source pattern 32 farther from the control junction point 35 faces a portion 26B of the gate pattern 22 closer to the gate junction point 25. This causes the control source pattern 32 and the gate pattern 22 to cancel out each other's magnetic fields. This reduces the inductance of the gate-source loop passing through the gate driver IC 44, making it possible to suppress a decrease in switching speed and gate oscillation caused by the gate-source loop.

[0040] Furthermore, when viewed from the first switching element and the second switching element, portions 36A and 36B of the control wiring portion are located farther from the control junction point 35. This allows the control junction point 35 to be closer to the first switching element and the second switching element. This shortens the length from the first main pad 11A to the control junction point 35. Furthermore, portions 26A and 26B of the gate wiring portion are located closer to the gate junction point 25. This allows the gate junction point 25 to be farther from the first switching element and the second switching element. This lengthens the length of the gate wiring portion from the first gate pad 10A to the gate junction point 25. This increases the partial inductance of the gate wiring portion between the first chip 1A and the second chip 1B connected in parallel (this is referred to as the "parallel chips") while reducing the partial inductance of the control wiring portion between the parallel chips, thereby suppressing gate oscillation.

[0041] As shown in FIG. 1, the power semiconductor module 100 has a layout that is symmetrical with respect to a line that passes through the center of the X-axis direction and is parallel to the Y-axis. Therefore, the length of the gate wiring portion from the first gate pad 10A to the gate junction point 25 is approximately the same as the length of the gate wiring portion from the second gate pad 10B to the gate junction point 25. The length of the control wiring portion from the first main pad 11A to the control junction point 35 is approximately the same as the length of the control wiring portion from the second main pad 11B to the control junction point 35. This can suppress deviations in switching timing due to differences in wiring length, and can suppress current nonuniformity during switching. "Similar lengths" means that the wiring portions are designed to be the same length, and does not take into account differences in wiring length due to manufacturing errors.

[0042] In the first embodiment, a cooler may be connected to the lower part of the insulating substrate 42 or to the lower part of a conductor provided on the lower part of the insulating substrate 42 using grease, solder, silver or copper paste, or a sintered material thereof, thereby reducing the thermal resistance of the power semiconductor module 100.

[0043] The power semiconductor module 100 may be entirely or partially sealed with a sealing material such as silicone gel or resin. In this case, a case may be used to fill the sealing material and to fix the external control terminals 34 and the external gate terminals 24.

[0044] (Second embodiment) The configuration of a power semiconductor module 101 according to the second embodiment will be described with reference to Fig. 3. The difference compared to the gate pattern 22 in Fig. 1 is that the gate pattern of the power semiconductor module 101 is divided into two.

[0045] The power semiconductor module 101 has a first gate pattern 22A and a second gate pattern 22B. When the first gate pattern 22A and the second gate pattern 22B are collectively referred to without distinction, they are referred to as "gate patterns 22." One end of the first gate pattern 22A is electrically connected to the other end of the conductor wiring 21A. The other end of the first gate pattern 22A is electrically connected to one end of the conductor wiring 23A. The other end of the conductor wiring 23A is electrically connected to a gate external terminal 24.

[0046] The other end of the conductor wiring 21B is electrically connected to one end of the second gate pattern 22B. The other end of the second gate pattern 22B is electrically connected to one end of the conductor wiring 23B. The other end of the conductor wiring 23B is electrically connected to the gate external terminal 24.

[0047] The first gate pattern 22A to which the conductor wiring 21A is connected and the second gate pattern 22B to which the conductor wiring 21B is connected join at a gate joining point 25. The gate joining point 25 is disposed on the gate external terminal 24. As described above, the power semiconductor module 101 differs from the power semiconductor module 100 of FIG. 1 in that the gate pattern 22 is divided into two and the gate joining point 25 is formed on the gate external terminal 24. The other configurations of the power semiconductor module 101 are the same as those of the power semiconductor module 100 of FIG. 1, and therefore will not be described again.

[0048] According to the second embodiment, the gate junction point 25 can be further away from the first switching element and the second switching element, and therefore the length of the gate wiring portion from the first gate pad 10A to the gate junction point 25 can be further increased, thereby increasing the partial inductance of the gate wiring portion.

[0049] (Third embodiment) 4A and 4B, the configuration of a power semiconductor module 102 according to the third embodiment will be described. The power semiconductor module 102 differs in that a control wiring section and a part of a gate wiring section are arranged on a control substrate 46 that is different from the insulating substrate 42. Specifically, a control source pattern 32 as a part of the control wiring section and a gate pattern 22 as a part of the gate wiring section are arranged on the control substrate 46.

[0050] Gate pattern 22 is divided into a plurality of individual gate patterns 22A1, 22A2, 22A3, 22B1, 22B2, 22B3, and 22C. These multiple patterns are arranged on the front and back surfaces of control substrate 46 and connected in series. Fig. 4A shows the overall configuration of power semiconductor module 102 including the front surface of control substrate 46, and Fig. 4B shows the back surface of control substrate 46.

[0051] The control board 46 is a board for mounting control system circuits and is mounted on the insulating board 42 or the conductor plate 41. The control board 46 is made of glass epoxy or ceramic such as silicon nitride, aluminum nitride, or alumina. The control source pattern 32 and some of the individual gate patterns 22A1, 22A2, 22B1, 22B2, and 22C are arranged on the front surface of the control board 46. The control source pattern 32 is the same as in the first embodiment, so its description will be omitted. The remaining individual gate patterns 22A3 and 22B3 are arranged on the back surface of the control board 46.

[0052] The other end of the conductor wiring 21A is electrically connected to the individual gate pattern 22A1. The individual gate pattern 22A1 is electrically connected to the individual gate pattern 22A2 via a first gate resistor 28A. The first gate resistor 28A is electrically connected to the individual gate patterns 22A1 and 22A2 using a bonding material such as solder. The individual gate pattern 22A2 is electrically connected to the individual gate pattern 22A3 via a conductive via 27A1 that penetrates the front and back surfaces of the control substrate 46. The individual gate pattern 22A3 is electrically connected to the individual gate pattern 22C via a conductive via 27A2 that penetrates the front and back surfaces of the control substrate 46.

[0053] The other end of the conductor wiring 21B is electrically connected to an individual gate pattern 22B1. The individual gate pattern 22B1 is electrically connected to an individual gate pattern 22B2 via a second gate resistor 28B. The second gate resistor 28B is electrically connected to the individual gate patterns 22B1 and 22B2 using a bonding material such as solder. The individual gate pattern 22B2 is electrically connected to an individual gate pattern 22B3 via a conductive via 27B1 that penetrates the front and back surfaces of the control substrate 46. The individual gate pattern 22B3 is electrically connected to an individual gate pattern 22C via a conductive via 27B2 that penetrates the front and back surfaces of the control substrate 46.

[0054] In the third embodiment, the "gate wiring portion" further includes conductive vias 27A1, 27A2, 27B1, and 27B2.

[0055] The power semiconductor module 102 has gate resistors (first gate resistor 28A and second gate resistor 28B) electrically connected to the gate wiring portion closer to the first switching element and the second switching element than the gate junction point 25. By disposing the first gate resistor 28A and the second gate resistor 28B individually outside the first chip 1A and the second chip 1B, the partial inductance of the gate wiring portion can be further increased and gate oscillation can be further suppressed.

[0056] The power semiconductor module 102 further includes a control substrate 46 having a first main surface (front surface) on which portions 36A and 36B of the control wiring portion are formed, and a second main surface (back surface) facing in the opposite direction to the first main surface on which portions 26A and 26B of the gate wiring portion are formed. When viewed from the first switching element and the second switching element, the portions 36A and 36B of the control wiring portion farther from the control junction point 35 and the portions 26A and 26B of the gate wiring portion closer to the gate junction point 25 are adjacent to each other in parallel via the control substrate 46. Specifically, the portions 36A and 36B of the control source pattern arranged on the front surface of the control substrate 46 face the portions 26A and 26B of the individual gate patterns 22A3 and 22B3 arranged on the back surface of the control substrate 46, respectively. As a result, the magnetic fields of the control source pattern 32 (partial inductances L4a and L4b) and the individual gate patterns 22A3 and 22B3 (partial inductances L2a and L2b) cancel each other out, reducing the inductance of the gate-source loop passing through the gate driver IC 44 and suppressing a decrease in switching speed and gate oscillation caused by the gate-source loop.

[0057] Furthermore, a portion 26A of the individual gate pattern 22A3 and a portion 26B of the individual gate pattern 22B3 are adjacent in parallel at a gate pattern opposing portion 26X. When viewed from the first switching element and the second switching element, the gate patterns closer to each other than the gate junction point 25 are adjacent in parallel. The parallel adjacent gate patterns strengthen the magnetic fields of each other, which can increase the partial inductance of the gate wiring portion between the parallel chips.

[0058] (Modification of the third embodiment) The configuration of a power semiconductor module 102A according to a modification of the third embodiment will be described with reference to Fig. 5. The power semiconductor module 102A differs from the power semiconductor module 102 in that it further includes a first control source resistor 38A and a second control source resistor 38B, respectively, outside the first chip 1A and the second chip 1B. The configuration of the back side of the control substrate 46 is the same as that in Fig. 4B, and is not shown in the figure.

[0059] The control source pattern 32 is divided into a plurality of individual control source patterns 32 A, 32 B, and 32 C. These multiple patterns are arranged on the surface of a control board 46 and connected in series.

[0060] The other end of the conductor wiring 31A is electrically connected to the individual control source pattern 32A. The individual control source pattern 32A is electrically connected to the individual control source pattern 32C via a first control source resistor 38A. The first control source resistor 38A is electrically connected to each of the individual control source patterns 32A and 32C using a bonding material such as solder. The other end of the conductor wiring 31B is electrically connected to the individual control source pattern 32B. The individual control source pattern 32B is electrically connected to the individual control source pattern 32C via a second control source resistor 38B. The second control source resistor 38B is electrically connected to each of the individual control source patterns 32B and 32C using a bonding material such as solder.

[0061] Power semiconductor module 102A has control resistors (first control source resistor 38A and second control source resistor 38B) electrically connected to the control wiring portion closer to the first switching element and the second switching element than control junction point 35. By providing first control source resistor 38A and second control source resistor 38B individually outside first chip 1A and second chip 1B, it is possible to prevent main currents from flowing from first main pad 11A and second main pad 11B to the control wiring portion, thereby further suppressing gate oscillation.

[0062] (Fourth embodiment) The configuration of a power semiconductor module 103 according to the fourth embodiment will be described with reference to Fig. 6. In the power semiconductor modules 100 to 102 already described, the gate pattern 22 is formed so as to detour around the outside of the control source pattern 32. In contrast, in the power semiconductor module 103, the control source pattern 32 is formed so as to detour around the outside of the gate pattern 22.

[0063] The control source pattern 32 is formed so that the connection points between the conductor wiring 31A and the conductor wiring 31B and the control source pattern 32 are connected by straight lines at the control junction point 35. That is, the connection points are connected to the control junction point 35 over the shortest distance. This shortens the length of the control wiring portion from the first main pad 11A to the control junction point 35. Therefore, the partial inductance parasitic on the control wiring portion from the first main pad 11A to the control junction point 35 is reduced. The same applies to the control wiring portion on the second chip 1B side. Note that the control source pattern 32 differs from the power semiconductor modules 100 to 102 in that it extends from the connection points toward the control external terminals 34, rather than from the control junction point 35.

[0064] The gate pattern 22 is not formed so that the connection points between the conductor wiring 21A and the conductor wiring 21B and the gate pattern 22 are connected by straight lines. The gate pattern 22 extends from the connection points toward the control external terminal 34 and merges at the outer periphery of the insulating substrate 42. That is, the gate pattern 22 has a gate junction point 25 located at the outer periphery of the insulating substrate 42. This increases the length of the gate wiring portion from the first gate pad 10A to the gate junction point 25. Therefore, the partial inductance parasitic on the gate wiring portion from the first gate pad 10A to the gate junction point 25 increases. The same applies to the gate wiring portion on the second chip 1B side.

[0065] In this way, the length of the gate wiring portion from first gate pad 10A to gate junction point 25 is longer than the length of the control wiring portion from first main pad 11A to control junction point 35. This increases the partial inductance of the gate wiring portion between first chip 1A and second chip 1B connected in parallel, while reducing the partial inductance of the control wiring portion between the parallel chips, thereby suppressing gate oscillation.

[0066] When viewed from the first switching element and the second switching element, portions 36A and 36B of the control wiring portion farther from the control junction point 35 and portions 26A and 26B of the gate wiring portion closer to the gate junction point 25 are adjacent and parallel to each other. This allows the control source pattern 32 and the gate pattern 22 to cancel each other's magnetic fields. This reduces the inductance of the gate-source loop passing through the gate driver IC 44 in FIG. 2, making it possible to suppress a decrease in switching speed and gate oscillation caused by the gate-source loop.

[0067] When viewed from the first switching element and the second switching element, parts of the gate wiring portions closer to each other than the gate junction point 25 are adjacent to each other in parallel at the gate pattern opposing portion 26X, which further increases the partial inductance of the gate wiring portions between the parallel chips.

[0068] (Fifth embodiment) 7A, the configuration of a power semiconductor module 104 according to the fifth embodiment will be described. The power semiconductor module 104 differs from the power semiconductor module 100 in that the power semiconductor module 104 further includes a third chip 1C mounted on the conductor plate 41.

[0069] A third switching element (not shown) is formed on the third chip 1C. A third main pad 11C connected to one main electrode (not shown) of the third switching element and a third gate pad 10C connected to the gate (not shown) of the third switching element are formed on the front surface of the third chip 1C. The other main electrode (not shown) of the third switching element is formed on the back surface of the third chip 1C. In other respects, the third chip 1C and the third switching element are the same as the first chip 1A and the first switching element, and therefore a description thereof will be omitted.

[0070] A conductor wiring 43C is electrically connected to the third main pad 11C. A main current controlled by the third switching element flows through the conductor wiring 43C. A control wiring section is electrically connected to the third main pad 11C. Specifically, one end of a conductor wiring 31C made of a wire is electrically connected to the third main pad 11C. The other end of the conductor wiring 31C is electrically connected to the control source pattern 32.

[0071] In the power semiconductor module 104, three control junction points 35A, 35B, and 36C exist on the control source pattern 32. The control source pattern 32 has a junction point 35A where the conductor wiring 31A and the conductor wiring 31B meet, a junction point 35B where the conductor wiring 31B and the conductor wiring 31C meet, and a junction point 35C where the conductor wiring 31A and the conductor wiring 31C meet. At each of the junction points 35A, 35B, and 35C, the connection points between the conductor wirings 31A, 31B, and 31C and the control source pattern 32 are connected by the shortest distance on the control source pattern 32. Therefore, the length of the control wiring portion from the main pads 11A, 11B, 11C to the control junction points 35A, 35B, 36C is shortened, and the partial inductance parasitic on the control wiring portion from the main pads 11A, 11B, 11C to the control junction points 35A, 35B, 36C is reduced.

[0072] In contrast, gate pattern 22 is not formed so as to connect the connection points of conductor wirings 21A, 21B, and 21C with gate pattern 22 by straight lines. Gate pattern 22 is formed so as to detour around the outside of control source pattern 32. Therefore, the distance between each of the connection points and gate junction point 25 is longer than the similar distance on the source side.

[0073] In this way, the partial inductance of the gate wiring section between the first chip 1A, second chip 1B, and third chip 1C connected in parallel (between the parallel chips) can be increased while the partial inductance of the control wiring section between the parallel chips can be reduced, thereby suppressing gate oscillation.

[0074] 7A and 7B, when viewed from the first switching element, the second switching element, and the third switching element, portions 36A1, 36A2, 36B1, and 36B2 of the control wiring portion farther from control junction points 35A, 35B, and 35C are adjacent in parallel to portions 26A1, 26A2, 26B1, and 26B2 of the gate wiring portion closer to gate junction point 25. This allows the control source pattern 32 and the gate pattern 22 to cancel out each other's magnetic fields. This reduces the inductance of the gate-source loop passing through the gate driver IC 44, suppressing a decrease in switching speed and gate oscillation caused by the gate-source loop.

[0075] Furthermore, when viewed from the first switching element, the second switching element, and the third switching element, portions 36A1, 36A2, 36B1, and 36B2 of the control wiring portion are located farther from the control junction point 35A, 35B, and 35C. This allows the control junction point 35 to be closer to the first switching element, the second switching element, and the third switching element. This shortens the length from the main pads 11A, 11B, and 11C to the control junction point 35A, 35B, and 35C. Furthermore, portions 26A1, 26A2, 26B1, and 26B2 of the gate wiring portion are located closer to the gate junction point 25. This allows the gate junction point 25 to be farther from the first switching element, the second switching element, and the third switching element. This lengthens the length of the gate wiring portion from the gate pads 10A, 10B, and 10C to the gate junction point 25. These features suppress gate oscillation.

[0076] In this way, the same effect can be obtained even if the number of chips included in power semiconductor module 104 is increased to 3. Specifically, by increasing the number of chips corresponding to second chip 1B and increasing the number of extensions connected to conductive wiring 21B of gate pattern 22, four or more chips can be mounted.

[0077] Although the embodiments of the present invention have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure. [Explanation of symbols]

[0078] 1A First Chip 1B Second chip 1C 3rd chip 10A 1st gate pad 10B Second gate pad 10C 3rd gate pad 11A 1st main pad 11B Second main pad 11C 3rd main pad 12A First switching element 12B Second switching element 21A, 21B, 21C, 23, 23A, 23B, 31A, 31B, 31C, 43A, 43B, 43C Conductor wiring 22 Gate Pattern 22A First gate pattern 22A1, 22A2, 22A3, 22B1, 22B2, 22B3, 22C Individual gate patterns 22B Second gate pattern 24 Gate external terminal Gate 25 junction 26X Gate pattern facing area 28A 1st gate resistor 28B Second gate resistor 32 Control Source Patterns 32A, 32B, 32C Individual control source patterns 34 External control terminal 35, 35A, 35B, 35C Controlled Junction 38A First Control Source Resistor 38B Second Control Source Resistor 41 Conductor plate 44 Gate driver IC (gate drive circuit) 45 Gate resistor 46 Control board 100, 101, 102, 102A, 103, 104 Power semiconductor modules L1a, L1b, L2a, L2b, L3a, L3b, L4a, L4b partial inductance

Claims

1. a first chip including a first switching element, a first main pad connected to one main electrode of the first switching element, and a first gate pad connected to a gate of the first switching element; a second chip including a second switching element, a second main pad connected to one main electrode of the second switching element, and a second gate pad connected to a gate of the second switching element; a gate wiring portion electrically connected to the first gate pad and the second gate pad; a control wiring portion electrically connected to the first main pad and the second main pad, the gate wiring portion and the control wiring portion are electrically connectable to a gate drive circuit that controls on / off of the first switching element and the second switching element, the gate wiring portion has a gate junction point where the gate wiring portion connected to the first gate pad and the gate wiring portion connected to the second gate pad join together, the control wiring portion has a control junction point where the control wiring portion connected to the first main pad and the control wiring portion connected to the second main pad join together, a length of the gate wiring portion from the first gate pad to the gate junction point is longer than a length of the control wiring portion from the first main pad to the control junction point; a part of the control wiring portion on a side farther from the control junction point and a part of the gate wiring portion on a side closer to the gate junction point are adjacent to each other in parallel when viewed from the first switching element and the second switching element; Power semiconductor module.

2. 2. The power semiconductor module according to claim 1, further comprising a gate resistor electrically connected to the gate wiring portion closer to the first switching element and the second switching element than the gate junction point.

3. 2. The power semiconductor module according to claim 1, further comprising a control resistor electrically connected to the control wiring portion closer to the first switching element and the second switching element than the control junction point.

4. 2 . The power semiconductor module according to claim 1 , wherein parts of the gate wiring portions closer to the first switching element and the second switching element than the gate junction point are adjacent to each other in parallel.

5. 2. The power semiconductor module according to claim 1, wherein a length of the gate wiring portion from the first gate pad to the gate junction point is approximately the same as a length of the gate wiring portion from the second gate pad to the gate junction point.

6. 2. The power semiconductor module according to claim 1, wherein the length of the control wiring portion from the first main pad to the control junction point is approximately the same as the length of the control wiring portion from the second main pad to the control junction point.

7. a substrate having a first main surface on which a part of the control wiring portion is formed, and a second main surface facing in a direction opposite to the first main surface on which a part of the gate wiring portion is formed, The power semiconductor module according to claim 1 , wherein a portion of the control wiring portion and a portion of the gate wiring portion are adjacent to each other in parallel with the substrate interposed therebetween.

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