Switched capacitor power supply circuit

Abstract

To provide a switched capacitor power supply circuit capable of reducing a BOX capacitance even when an integrated circuit is formed by a general-purpose process.SOLUTION: In a switched capacitor power supply circuit 1 configured by an integrated circuit, an N-well layer NW located below each of capacitive elements C1 to C5 is connected to the same potential point as a potential of a semiconductor substrate via resistive elements R1 to R5.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a switched capacitor power supply circuit that is configured with an integrated circuit, charges and discharges a plurality of capacitance elements via a plurality of switching elements in response to a plurality of clock signals with different phases, and converts an input voltage into a predetermined output voltage. [Background technology]

[0002] In recent years, there has been a demand for the development of high-step-down DC / DC converters capable of converting power from high-voltage power sources (over 400V, such as automotive batteries) to low-voltage power sources (around 12V). To achieve high conversion efficiency, these DC / DC converters often use switching power supplies with transformers. However, power conversion at high step-down ratios requires a reduced PWM signal duty cycle. This means that the control signal pulses become narrower, making timing design more difficult and resulting in poor conversion efficiency. Furthermore, transformers are generally large and heavy. Because these switching power supplies are unsuitable for high step-down ratios and compact size, switched-capacitor power supplies, implemented only with capacitance and switches, have been attracting attention.

[0003] For example, Non-Patent Document 1 proposes a fully integrated switched-capacitor power supply circuit with a Dickson star topology. When a switched-capacitor power supply circuit is configured as an integrated circuit, a so-called box capacitance occurs as a capacitive component in a BOX (Buried-Oxide) layer located below the capacitive element. This box capacitance is connected in series with the capacitive element, which reduces the power conversion efficiency of the switched-capacitor power supply circuit. This will be explained with reference to Figures 7 to 12. In these figures, S1 and S2 represent clock signals with different phases and switches driven by the respective clock signals.

[0004] Figure 7 shows a Dickson star switched capacitor power supply circuit. As shown in Figure 8, in phase 1 when switch S2 is at a high level, the box capacitance CBOX is charged by the output voltage Vout via the capacitance elements C1, C3, and C5. At this time, the bottom plates of the capacitance elements C2 and C4 are connected to ground, so the charge stored in these box capacitances CBOX is discharged, resulting in loss. Conversely, as shown in Figure 9, in phase 2 when switch S1 is at a high level, the box capacitance CBOX is charged by the output voltage Vout via the capacitance elements C2 and C4, and the charge stored in the box capacitance CBOX of the capacitance elements C1, C3, and C5 is discharged, resulting in loss.

[0005] Fig. 10 shows a ladder-type switched capacitor power supply circuit. As shown in Fig. 11, in phase 1 when switch S2 is at a high level, each box capacitance CBOX is charged via capacitance elements C5, C6, and C7 with output voltage Vout, voltage VT0 at the common connection point of capacitance elements C2 and C3, and voltage VT1 at the common connection point of capacitance elements C3 and C4, respectively. Also, as shown in Fig. 12, in phase 2 when switch S1 is at a high level, the charge in box capacitance CBOX5 is discharged, box capacitance CBOX6 is charged with output voltage Vout, and box capacitance CBOX7 is charged with voltage VT0.

[0006] In this way, the loss is the difference ΔQ in the charge of each BOX capacitance between Phase 1 and Phase 2. Specifically, since VT1≒3VOUT and VT0≒2VOUT, C5:ΔQ5=CBOX(VOUT-GND)≒CBOX×Vout C6:ΔQ6=CBOX(VT0-Vout)≒CBOX×Vout C7:ΔQ7=CBOX(VT1-VT0)≒CBOX×Vout And ΔQ=ΔQ5+ΔQ6+ΔQ7 This becomes:

[0007] FIG. 12 of Non-Patent Document 1 discloses a configuration that employs a special process to form an n-Buried layer on a p-substrate layer and apply a high voltage as a countermeasure against the BOX capacitance. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] IEEE JOURNAL OF SOLID-STATE CIRCUITS,Fully Integrating a 400 V-to-12 V DC-DC Converter in High-Voltage CMOS Tuur Van Daele,and Filip Tavernier. Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the measure such as that in Non-Patent Document 1, the circuit area increases due to the addition of an n-Buried layer, which increases manufacturing costs. The present invention has been made in view of the above circumstances, and its object is to provide a switched capacitor power supply circuit that can reduce the BOX capacitance even when an integrated circuit is formed using a general-purpose process. [Means for solving the problem]

[0010] According to the switched capacitor power supply circuit of claim 1, the well layer (15) located below the capacitance elements (C1 to C5) in the integrated circuit is connected to a potential point lower than the potential of the semiconductor substrate (11) via a load circuit (R). Note that the "load circuit" is a circuit having at least a resistance component and includes a single element. Here, the capacitance of the well layer in the capacitance element is defined as C W , BOX capacity is C BOX ,s=jω, and the resistance of the load circuit is R. The impedance Z1 of the BOX capacitance alone is Z1=1 / (sC BOX) is. On the premise that one end of the BOX capacitance is also connected to the electric potential point, when the well layer is connected to the electric potential point via a load circuit, the impedance Z2 of the well layer is the capacitance C W to the capacitance C BOX and the value obtained by connecting the parallel circuit of the load circuit R in series.

[0011] Therefore, if sC BOX ≫1 / R is set, the value of 1 / R can be ignored in the calculation of the impedance Z2. Thus. Substantially, the capacitance C W to the capacitance C BOX connected in series Z2 = 1 / (sC BOX [[ID=1十八]]) + 1 / (sC W ), and Z2 < Z1. Thus, by simply adding a load circuit, the influence of the BOX capacitance (12) can be reduced and a decrease in power conversion efficiency can be prevented.

[0012] According to the switched capacitor power circuit described in claim 2, a load circuit is connected to the well layer corresponding to all of the plurality of capacitor elements. Thereby, the influence of the BOX capacitance can be reduced for all of the capacitor elements.

[0013] According to the switched capacitor power circuit described in claim 3, wiring is performed such that the well layers corresponding to the capacitor element groups having the same charge and discharge timing among the plurality of capacitor elements have the same potential, and a load circuit is connected for each capacitor element group. Thereby, the number of load circuits can be reduced, an increase in the circuit area can be suppressed, and an increase in the manufacturing cost can be suppressed.

Brief Description of the Drawings

[0014] [Figure 1] The first embodiment, a diagram showing the configuration of a switched capacitor power circuit [Figure 2] A cross-sectional view schematically showing the semiconductor configuration of a capacitor element [Figure 3] A cross-sectional view schematically showing the semiconductor configuration of a conventional capacitor element [Figure 4] ​​​FIG. 10 is a diagram illustrating a configuration of a switched-capacitor power supply circuit according to a second embodiment. [Figure 6] FIG. 10 is a diagram illustrating a configuration of a switched-capacitor power supply circuit according to a third embodiment. [Figure 7] A diagram showing the configuration of a conventional Dickson star switched capacitor power supply circuit. [Figure 8] Diagram showing the connection state in phase 1 where switch S2 is at high level [Figure 9] Diagram showing the connection state in phase 2 when switch S1 is at high level [Figure 10] A diagram showing the configuration of a conventional ladder-type switched-capacitor power supply circuit. [Figure 11] Diagram showing the connection state in phase 1 where switch S2 is at high level [Figure 12] Diagram showing the connection state in phase 2 when switch S1 is at high level DETAILED DESCRIPTION OF THE INVENTION

[0015] (First embodiment) As shown in Fig. 1, the switched-capacitor power supply circuit 1 of this embodiment is a Dickson type and is configured as an integrated circuit. For example, five sets of series-connected P-channel MOSFET 2 and N-channel MOSFET 3 are connected in series between the input terminal Vin and the output terminal Vout. S1 and S2 attached to the gates of each of the FETs 2 and 3 are the same clock signals as those shown in Fig. 7, etc.

[0016] The top plates of the capacitance elements C1 to C5 are connected to the drains, which are the common connection points of the FETs 2 (1 to 5) and 3 (1 to 5). The bottom plates of the capacitance elements C2 and C4 are connected to the drains of the P-channel MOSFET 4 and N-channel MOSFET 5, and the bottom plates of the capacitance elements C1, C3, and C5 are connected to the drains of the P-channel MOSFET 6 and N-channel MOSFET 7. The sources of the FETs 4 and 7 are connected to the output terminal Vout, and the sources of the FETs 5 and 6 are connected to ground. The N-well layers (NW) formed below the capacitance elements C1 to C5 are connected to ground, which is also the substrate potential, via the resistance elements R1 to R5, respectively. The resistance element R, which is a passive element, is an example of a load circuit.

[0017] 2, a BOX layer 12 is formed on an N-type semiconductor substrate 11, and a deep N-well layer 14 and an N-well layer 15 are formed on the BOX layer 12 in a region separated by a trench 13 filled with an insulator. A capacitance element C is formed in a wiring layer, which is the surface of the N-well layer 15, using, for example, a comb-shaped electrode. In the figure, Vin on the top plate side and Vout on the bottom plate side indicate the input and output sides of one capacitance element C. The N-well layer 15 is connected to ground via a resistance element R formed in the wiring layer, and is therefore at the same potential as the semiconductor substrate 11.

[0018] With the above-described semiconductor configuration, as shown in the equivalent circuit in the figure, the bottom plate of each capacitance element C is connected to the ground parasitic capacitance C NW and resistor R. The capacitor C NW The common connection point of the resistor element R is the BOX capacitance C BOX is connected to ground via

[0019] As shown in Figure 3, in a conventional capacitor, the N-well layer is directly connected to the bottom plate of the capacitor, resulting in a parasitic capacitance to ground, C NWis short-circuited. Therefore, the impedance Z1 of the N-well layer is Z1 = 1 / (sC BOX ) when s = jω.

[0020] On the other hand, for the capacitive element C of this embodiment, the impedance Z2 of the N-well layer 15 is Z2 = 1 / (sC BOX ) + 1 / (sC[[ID=ll]] W + 1 / R) Thus, if sC BOX ≫ 1 / R is set, the value of 1 / R can be ignored in the calculation of the impedance Z2. Therefore, the impedance Z2 is substantially the value obtained by connecting the capacitor C W in series with the capacitor C BOX Z2 ≒ 1 / (sC BOX ) + 1 / (sC W ) [[ID=2Z]] and thus Z2 < Z1. Thereby, the influence of the BOX capacitance can be reduced and the decrease in the power conversion efficiency can be prevented. [[ID=SO]]

[0021] Fig. 4 shows the simulation results. The horizontal axis is the ratio of the BOX capacitance to the main capacitance which is the capacitance of the capacitive element C itself. As this ratio increases, the power conversion efficiency of the switch capacitor power supply circuit tends to decrease. In the conventional configuration, the efficiency at the maximum ratio is 34.51%, whereas in the configuration of this embodiment, the efficiency has increased to 44.22%, and the effect of improving the power conversion efficiency has been confirmed. [[ID=JO]]

[0022] As described above, according to this embodiment, in the switch capacitor power supply circuit 1 constituted by an integrated circuit, the N-well layer 15 located below each of the capacitive elements C1 to C5 is connected to the same potential point as the potential of the semiconductor substrate 11 via the resistance element R. In this way, by simply adding the resistance element R, the influence of the BOX capacitance can be reduced and the decrease in the power conversion efficiency can be prevented.

[0023] [[ID=JO]](Second Embodiment) ​In the following, the same parts as in the first embodiment are denoted by the same reference numerals and their explanations are omitted, and only the different parts are explained. In a switched capacitor power supply circuit 21 of the second embodiment shown in Fig. 5, the resistance elements R1 to R3 are eliminated. The upper end of the resistance element R4 is commonly connected to the N well layers 15 corresponding to the capacitance elements C2 and C4, and the upper end of the resistance element R5 is commonly connected to the N well layers 15 corresponding to the capacitance elements C1, C3, and C5.

[0024] That is, the capacitance elements C1, C3, and C5, and the capacitance elements C2 and C4 are charged and discharged by clock signals of the same phase, respectively. Therefore, the potential of the corresponding N-well layers 15 can be made common, and the number of resistance elements can be reduced to only R4 and R5.

[0025] (Third embodiment) The switched capacitor power supply circuit 22 of the third embodiment shown in Figure 6 is applied to a ladder-type 4:1 step-down converter, and the series-connected sets of FETs 2 and 3 are connected in series, for example, four sets. A capacitance element C7 is connected between the drains of FETs 2(4) and 3(4) and the drains of FETs 2(3) and 3(3). A capacitance element C6 is connected between the drains of FETs 2(3) and 3(3) and the drains of FETs 2(2) and 3(2). A capacitance element C5 is connected between the drains of FETs 2(2) and 3(2) and the drains of FETs 2(1) and 3(1). The N-well layers corresponding to the capacitance elements C5 to C7 are connected to ground via resistance elements R5 to R7, respectively.

[0026] The third embodiment configured as above can also be applied to a ladder-type switched capacitor power supply circuit 22.

[0027] In addition to the inventions described in the claims, this case also includes the following inventions: [1] A switched capacitor power supply circuit is configured with an integrated circuit and converts an input voltage into a predetermined output voltage by charging and discharging a plurality of capacitance elements (C1 to C5) via a plurality of switching elements (2 to 7) using a plurality of clock signals with different phases, A switched capacitor power supply circuit in which a well layer (15) located below the capacitance element is connected via a load circuit (R) to a point of potential equal to or lower than the potential of a semiconductor substrate (11) constituting the integrated circuit. [2] 10. The switched-capacitor power supply circuit according to claim 1, wherein the load circuit is connected to well layers corresponding to all of the plurality of capacitance elements. [3] Among the plurality of capacitance elements, well layers corresponding to capacitance element groups that are charged and discharged at the same timing are wired to have the same potential, The switched-capacitor power supply circuit according to [1] or [2], wherein the load circuit is connected to each of the capacitive element groups. [4] The switched capacitor power supply circuit according to any one of [1] to [3], wherein the load circuit is a passive element formed in a wiring layer.

[0028] (Other embodiments) In each embodiment, the number of series-connected FETs 2 and 3 may be changed as appropriate according to the individual design. It can also be applied to a series-parallel type. The well layer may be a P-well layer, in which case the semiconductor substrate may also be P-type. The electrode shape of the capacitance element is not limited to the comb-tooth shape. The load circuit may be a polysilicon resistor element, a metal resistor element, or a reverse-connected diode, and may be any passive element that has at least a resistance component. The potential of the potential point to which the load circuit is connected may be lower than the potential of the semiconductor substrate. The switching element is not limited to a MOSFET.

[0029] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0030] In the drawing, 1 is a switched capacitor power supply circuit, 2, 5 and 7 are P-channel MOSFETs, 3, 4 and 7 are N-channel MOSFETs, 11 is a semiconductor substrate, 12 is a BOX layer, 15 is an N-well layer, C1 to C5 are capacitance elements, and R is a resistance element.

Claims

1. A switched capacitor power supply circuit is configured with an integrated circuit and converts an input voltage into a predetermined output voltage by charging and discharging a plurality of capacitance elements (C1 to C5) via a plurality of switching elements (2 to 7) using a plurality of clock signals with different phases, A switched capacitor power supply circuit in which a well layer (15) located below the capacitance element is connected via a load circuit (R) to a point of potential equal to or lower than the potential of a semiconductor substrate (11) constituting the integrated circuit.

2. 2. The switched-capacitor power supply circuit according to claim 1, wherein the load circuit is connected to well layers corresponding to all of the plurality of capacitance elements.

3. Among the plurality of capacitance elements, well layers corresponding to capacitance element groups that are charged and discharged at the same timing are wired to have the same potential, 2. The switched-capacitor power supply circuit according to claim 1, wherein the load circuit is connected to each of the capacitance element groups.

4. 4. The switched-capacitor power supply circuit according to claim 1, wherein the load circuit is a passive element formed in a wiring layer.

Images