Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device including an SOI substrate, in which the variation in element characteristic can be reduced.SOLUTION: A semiconductor device 100 includes an SOI substrate 110 including a semiconductor support substrate 111, an insulating layer 112, and an N-type active layer 113, a source electrode 120 and a drain electrode 130, and a gate electrode 140 disposed through a gate insulating film 150. The SOI substrate 110 includes high-concentration N-type semiconductor regions 114a and 114b formed in a part of a surface of the active layer 113 at the depth that does not reach the insulating layer 112 and having the higher impurity concentration than the active layer 113, a P-type semiconductor region 115 formed apart from the active layer 113 on surfaces of the high-concentration N-type semiconductor regions 114a and 114b, and an N-channel formation region 116 formed right below the gate insulating film 150, provided in contact with the P-type semiconductor region 115, and having the lower impurity concentration than the high-concentration N-type semiconductor regions 114a and 114b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices (P-type MOSFETs) using SOI substrates have been known. One such semiconductor device is shown in FIG. 5 (hereinafter referred to as a conventional semiconductor device 800).

[0003] As shown in FIG. 5 , a conventional semiconductor device 800 includes an SOI substrate 810 having a semiconductor support substrate 811, an insulating layer 812 disposed on the semiconductor support substrate 811, and an N-type active layer 813 disposed on the insulating layer 812, a source electrode 820 and a drain electrode 830 disposed spaced apart on the active layer 813, a gate electrode 840 disposed between the source electrode 820 and the drain electrode 830 on the active layer 813 via a gate insulating film 850, an interlayer insulating film 852, and a surface protective film 860.

[0004] The SOI substrate 810 further includes a P-type semiconductor region 815 formed on the surface of the active layer 813 at a distance therefrom and connected to a source electrode 820 or a drain electrode 830 .

[0005] According to the conventional semiconductor device 800, an insulating layer 812 is disposed between a semiconductor support substrate 811 and an active layer 813, thereby reducing the parasitic capacitance of the transistor and reducing excess power consumption and leakage current.

[0006] A semiconductor device using such an SOI substrate 810 is used, for example, for controlling a high-side switch, and the active layer 813 is used at a higher potential than the semiconductor support substrate 811. In this case, however, holes gather near the interface between the insulating layer 812 and the active layer 813 (see the area surrounded by the dashed line A in FIG. 5 ), forming a P-type inversion layer, which may cause conduction between the source electrode 820 and the drain electrode 830 through the P-type inversion layer. This problem becomes more pronounced when the active layer 813 is thinned to achieve a high breakdown voltage element, since the P-type semiconductor region 815 and the P-type inversion layer become close to each other.

[0007] Therefore, for example, a semiconductor device is known in which a boundary high-concentration N-type semiconductor region 918 is formed at the boundary between an insulating layer 912 and an active layer 913 of an SOI substrate 910, as in the semiconductor device described in Patent Document 1 (another conventional semiconductor device 900, see FIG. 6). According to the other conventional semiconductor device 900, since the boundary high-concentration N-type semiconductor region 918 is included, a P-type inversion layer is unlikely to be formed, and electrical continuity between the source electrode 920 and the drain electrode 930 is unlikely to occur.

[0008] The other conventional semiconductor device 900 can be manufactured by, for example, the following method. That is, the manufacturing method of the other conventional semiconductor device 900 includes the steps of preparing an SOI substrate 910 having a semiconductor support substrate 911, an insulating layer 912 disposed on the semiconductor support substrate 911, and an N-type layer 913'' disposed on the insulating layer 912 (see FIG. 7(a)), introducing N-type impurities into the surface of the N-type layer 913'' (see FIG. 7(b)), and thermally diffusing the N-type impurities to form a high-concentration N + a step of forming a mold layer 913' (see FIG. 7(c)); +A step of introducing a P-type impurity into a part of the surface of the mold layer 913′ (see FIG. 7(d)), a step of thermally diffusing the P-type impurity so as not to reach the insulating layer 912 to form an active layer 913 and a boundary high-concentration N-type semiconductor region 918 (see FIG. 7(e)), a step of forming insulating films 950 and 951 on the surface of the active layer 913 and forming a gate electrode 940 made of polysilicon on the gate insulating film 950 (see FIG. 7(f)), and a step of applying a mask (not shown) having openings at predetermined positions to the insulating film 951. and introducing P-type impurities into the active layer 913 to form a plurality of P-type semiconductor regions 915 (see FIG. 7(g)); forming an interlayer insulating film 952 and opening the interlayer insulating film 952 and the insulating film 950 to form a source electrode 920 and a drain electrode 930 connected to the P-type semiconductor regions 915; and forming a surface protective film 960 to protect the interlayer insulating film 952, the source electrode 920, the drain electrode 930, and the gate electrode 940 (see FIG. 7(h)). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 10-303426 Summary of the Invention [Problem to be solved by the invention]

[0010] However, when manufacturing SOI substrates, there is generally a problem in that the concentrations of N-type and P-type impurities in the active layer fluctuate due to relatively large variations in the thickness of the active layer, resulting in large variations in the characteristics (e.g., threshold voltage) of the semiconductor device (MOSFET) (see Figure 3). Note that hereinafter, "characteristics of the semiconductor device" may also be referred to as "characteristics of the element."

[0011] Specifically, in the conventional manufacturing method of another semiconductor device 900, a fixed amount of N-type impurities is introduced into the entire N-type layer (active layer) (see FIG. 7(b)), so that when the N-type layer (active layer) is thicker than a predetermined thickness, the N-type impurity concentration in the N-type layer becomes low, and when the N-type layer (active layer) is thinner than the predetermined thickness, the N-type impurity concentration in the N-type layer becomes high. If P-type impurities are introduced to offset the N-type impurities (see FIG. 7(d)), when the N-type layer (active layer) is thicker than a predetermined thickness, the P-type impurities are more likely to thermally diffuse due to the low N-type impurity concentration in the N-type layer. Therefore, the P-type impurity concentration in the channel region directly below the gate electrode decreases, resulting in a high N-type impurity concentration in the channel region. On the other hand, when the N-type layer (active layer) is thinner than a predetermined thickness, the N-type impurity concentration in the N-type layer increases. Therefore, even if a certain amount of P-type impurities is introduced and thermally diffused, it is not possible to sufficiently offset the N-type impurity in the channel region directly below the gate electrode, and the N-type impurity concentration in the channel region increases. Therefore, the threshold voltage Vth also increases in this case.

[0012] In other words, variations in the thickness of the active layer 913 change the impurity concentration in the channel region in the active layer 913 directly below the gate electrode 940, causing variations in the characteristics (e.g., threshold voltage) of the semiconductor device (MOSFET). For this reason, there has been a demand for a semiconductor device having an SOI substrate, whose characteristics do not depend on variations in the thickness of the active layer and which can reduce variations in the characteristics of the elements.

[0013] The present invention has been made in view of the above circumstances, and has an object to provide a semiconductor device using an SOI substrate that can reduce variations in the characteristics of the semiconductor device, and a method for manufacturing such a semiconductor device. [Means for solving the problem]

[0014] The semiconductor device of the present invention comprises an SOI substrate having a semiconductor support substrate, an insulating layer disposed on the semiconductor support substrate, and an N-type active layer disposed on the insulating layer; a source electrode and a drain electrode disposed at a distance from each other on the active layer; and a gate electrode disposed on the active layer between the source electrode and the drain electrode with a gate insulating film interposed therebetween, wherein the SOI substrate further comprises: a heavily doped N-type semiconductor region formed in a part of a surface of the active layer to a depth that does not reach the insulating layer and having a higher impurity concentration than the active layer; a P-type semiconductor region formed on the surface of the heavily doped N-type semiconductor region at a distance from the active layer and connected to the source electrode or the drain electrode; and an N-type channel formation region formed directly below the gate insulating film and having a lower impurity concentration than the heavily doped N-type semiconductor region, the N-type channel formation region having an end in contact with the P-type semiconductor region.

[0015] a step of forming a gate electrode on a region of the active layer overlapping with the region where the P-type impurity has been introduced, via a gate insulating film; a step of introducing an N-type impurity into a peripheral region of the gate electrode in the active layer; a step of forming an N-type channel formation region directly below the gate insulating film, the N-type channel formation region having an impurity concentration lower than that of the N-type semiconductor region formed in a region where the P-type impurity and the N-type impurity overlap, by heating the SOI substrate and thermally diffusing the N-type impurity; a step of introducing a P-type impurity into a surface of the N-type semiconductor region, the P-type impurity being introduced into a surface of the N-type semiconductor region, to form a plurality of P-type semiconductor regions formed apart from the active layer; and a step of forming source electrodes and drain electrodes connected to the plurality of P-type semiconductor regions. [Effects of the Invention]

[0016] The semiconductor device of the present invention has a high-concentration N-type semiconductor region formed in a portion of the surface of the active layer at a depth not reaching the insulating layer and having a higher impurity concentration than the active layer. This eliminates the need to form a high-concentration N-type semiconductor region between the active layer and the insulating layer as in other conventional semiconductor devices 900. Therefore, it is not necessary to diffuse N-type impurities throughout the active layer to form the high-concentration N-type semiconductor region, and the impurity concentrations of the P-type impurity region and the channel formation region do not depend on the thickness of the SOI substrate (active layer). As a result, even if the thickness of the active layer of the SOI substrate varies, the impurity concentrations of the P-type impurity region and the channel formation region are less likely to change, thereby reducing variations in the characteristics of the semiconductor device due to variations in the thickness of the active layer of the SOI substrate.

[0017] According to the semiconductor device of the present invention, a high-concentration N-type semiconductor region is formed in a part of the surface of the active layer to a depth that does not reach the insulating layer and has a higher impurity concentration than the active layer. Therefore, even if a P-type inversion layer is formed between the active layer and the insulating layer, the high-concentration N-type semiconductor region can prevent electrical conduction between the P-type semiconductor region and the active layer, and ultimately between the source electrode and the drain electrode.

[0018] Furthermore, the method for manufacturing a semiconductor device of the present invention includes a step of introducing P-type impurities into the surface of a heavily doped N-type semiconductor region to form two P-type semiconductor regions spaced apart from the active layer, eliminating the need to form a heavily doped N-type semiconductor region between the active layer and the insulating layer as in other conventional semiconductor devices 900. Therefore, it is not necessary to diffuse N-type impurities throughout the active layer to form the heavily doped N-type semiconductor region, and the impurity concentrations of the P-type impurity region and the channel formation region do not depend on the thickness of the active layer of the SOI substrate. As a result, even if variations in the thickness of the active layer of the SOI substrate occur, the impurity concentrations of the P-type impurity region and the channel formation region are less likely to change. This reduces variations in the characteristics of the manufactured semiconductor device due to variations in the thickness of the active layer of the SOI substrate.

[0019] The method for manufacturing a semiconductor device of the present invention includes a step of introducing P-type impurities into the surface of a heavily doped N-type semiconductor region to form two P-type semiconductor regions spaced apart from the active layer. Therefore, the manufactured semiconductor device can prevent electrical continuity between the source electrode and the drain electrode due to the heavily doped N-type semiconductor region even if a P-type inversion layer is formed between the active layer and the insulating layer. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a diagram illustrating a semiconductor device 100 according to a first embodiment. [Figure 2] 2(a) to 2(g) are diagrams showing the steps of a method for manufacturing a semiconductor device according to embodiment 1. [Figure 3] 3 is a graph showing the relationship between the thickness of the active layer and the threshold voltage of the semiconductor device in the semiconductor device 100 according to the first embodiment and another conventional semiconductor device 900. In FIG. 3, the graph labeled "Conventional" shows the relationship between the thickness of the active layer and the threshold voltage of the semiconductor device in the other conventional semiconductor device 900, while the graph labeled "Present Invention" shows the relationship between the thickness of the active layer and the threshold voltage of the semiconductor device in the semiconductor device 100 according to the first embodiment. [Figure 4] FIG. 1 is a diagram showing a semiconductor device 101 according to a second embodiment. [Figure 5] 1 is a diagram illustrating a conventional semiconductor device 800. Reference numeral 851 denotes an insulating film. [Figure 6] FIG. 10 is a diagram illustrating another conventional semiconductor device 900. [Figure 7] 7(a) to 7(h) are diagrams illustrating the steps of a method for manufacturing another conventional semiconductor device 900. DETAILED DESCRIPTION OF THE INVENTION

[0021] The semiconductor device and the method for manufacturing the semiconductor device of the present invention will be described below based on the embodiments shown in the drawings. Note that the embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention. Furthermore, for components having the exact same or substantially the same function, common reference numerals are used in each embodiment even if the shape, etc., is slightly different, and descriptions already given may be omitted.

[0022] [Embodiment 1] 1. Configuration of the semiconductor device 100 according to the first embodiment 1, the semiconductor device 100 according to the first embodiment is a P-type field effect transistor (MOSFET) including an SOI substrate 110, a source electrode 120, a drain electrode 130, a gate electrode 140, a gate insulating film 150, an insulating film 151, an interlayer insulating film 152, and a surface protective film 160. The semiconductor device 100 is a planar semiconductor device.

[0023] The SOI substrate 110 includes a semiconductor support substrate 111, an insulating layer 112 disposed on the semiconductor support substrate 111, and an N-type (N - It has an active layer 113 of the GaN type.

[0024] The semiconductor support substrate 111 is, for example, a single crystal silicon substrate having a resistance of 10 Ωcm. The insulating layer 112 is made of, for example, a silicon dioxide (SiO2) film. The insulating layer 112 has a thickness that prevents parasitic capacitance from occurring between the semiconductor support substrate 111 and the active layer 113. The internal structure of the active layer 113 will be described later.

[0025] The source electrode 120 and the drain electrode 130 are disposed apart from each other on the active layer 113. The source electrode 120 and the drain electrode 130 are made of an aluminum-based material (e.g., an Al-Si-based alloy) having a thickness of, for example, 3 μm and formed by, for example, a sputtering method. An insulating film 151 and an interlayer insulating film 152 having openings at predetermined positions are formed on the surface of the SOI substrate 110, and the source electrode 120 and the drain electrode 130 are formed in the openings and are electrically connected to the active layer 113 (a P-type semiconductor region 115 described later).

[0026] The gate electrode 140 is disposed between the source electrode 120 and the drain electrode 130 on the active layer 113 via a gate insulating film 150. The gate insulating film 150 is made of, for example, a silicon dioxide film formed by thermal oxidation to a thickness of, for example, 50 nm. The gate electrode 140 is made of, for example, low-resistance polysilicon formed by CVD and ion implantation. When a voltage is applied to the gate electrode 140, a channel is formed in a channel formation region 116 (described later), and the semiconductor device is turned on. The insulating film 151 has the same thickness and composition as the gate insulating film 150 and is formed on the active layer 113. In the first embodiment, of the insulating films formed collectively, the insulating film directly below the gate electrode 140 is the gate insulating film 150, and the insulating film in the other region is the insulating film 151.

[0027] The interlayer insulating film 152 is formed on the surface of the insulating film 151 .

[0028] The surface protective film 160 is formed so as to cover the interlayer insulating film 152, the source electrode 120, and the drain electrode 130. The surface protective film 160 is a passivation film formed by, for example, a CVD method and having a thickness of, for example, 1000 nm.

[0029] Next, the internal structure of the active layer 113 will be described. The active layer 113 is made of, for example, N single crystal silicon. -The active layer 113 has a thickness in the range of, for example, 1 to 2 μm, and has high-concentration N-type semiconductor regions 114 a and 114 b, a P-type semiconductor region 115, a channel formation region 116, and a second P-type semiconductor region 117 formed on the surface.

[0030] The high-concentration N-type semiconductor regions 114a and 114b are formed in a part of the surface of the active layer 113 to a depth that does not reach the insulating layer 112. - N-type (N type) semiconductor layer) with a higher impurity concentration + The first heavily doped N-type semiconductor region 114a is electrically connected to the source electrode 120, and the second heavily doped N-type semiconductor region 114b is electrically connected to the drain electrode 130. The first heavily doped N-type semiconductor region 114a and the second heavily doped N-type semiconductor region 114b are separated from each other directly below the gate insulating film 150.

[0031] The P-type semiconductor region 115 is formed on the surface of the high-concentration N-type semiconductor regions 114a and 114b. - The active layer 113 (N - The P-type (P + The P-type semiconductor region 115 is formed by introducing P-type impurities (for example, boron) into an N-type semiconductor layer.

[0032] The channel formation region 116 is formed directly below the gate insulating film 150, with its end portion in contact with the P-type semiconductor region 115. The channel formation region 116 is an N-type semiconductor region having an impurity concentration lower than that of the high-concentration N-type semiconductor regions 114a and 114b and higher than that of the active layer 113. In the semiconductor device 100, when a voltage is applied to the gate electrode 140, a channel is formed in the channel formation region 116, the P-type semiconductor region 115 and the second P-type semiconductor region 117 are electrically connected, and the source electrode 120 (or the drain electrode 130) and the active layer 113 are electrically connected.

[0033] The second P-type semiconductor region 117 is a P-type (P- The second P-type semiconductor region 117 is formed in a region sandwiched between the first heavily doped N-type semiconductor region 114a and the second heavily doped N-type semiconductor region 114b (specifically, channel formation regions 116 formed in the first heavily doped N-type semiconductor region 114a and the second heavily doped N-type semiconductor region 114b, respectively). The thickness and impurity concentration of the second P-type semiconductor region 117 are different from the thickness and impurity concentration of the P-type semiconductor region 115.

[0034] 2. Manufacturing method of semiconductor device according to embodiment 1 Next, a method for manufacturing the semiconductor device 100 according to the first embodiment (a method for manufacturing the semiconductor device according to the first embodiment) will be described. As shown in Fig. 2, the method for manufacturing the semiconductor device according to the first embodiment includes, in this order, an SOI substrate preparation step, a first P-type impurity introduction step, a gate electrode formation step, an N-type impurity introduction step, a thermal diffusion step, a second P-type impurity introduction step, and an electrode, an interlayer insulating film, and a surface protection film formation step.

[0035] (1) SOI substrate preparation process First, an SOI substrate is prepared, which includes a semiconductor support substrate 111, an insulating layer 112 disposed on the semiconductor support substrate 111, and an N-type active layer 113 disposed on the insulating layer 112 (see FIG. 2(a)).

[0036] (2) First P-type impurity introduction process Next, a P-type impurity is introduced into a part of the surface of the active layer 113 (see FIG. 2(b)). Specifically, a photomask (not shown) having openings at predetermined positions is placed on the active layer 113, and a P-type impurity (e.g., boron) is introduced into the surface of the active layer 113 from above the active layer 113 through the openings by, for example, ion implantation.

[0037] (3) Gate electrode formation process Next, a gate electrode 140 is formed on the active layer 113 in a region overlapping the region 117′ into which the P-type impurity has been introduced, with a gate insulating film 150 interposed therebetween (see FIG. 2(c)). Specifically, first, the entire surface of the active layer 113 is thermally oxidized to form insulating films (gate insulating film 150 and insulating film 151). Next, low-resistance polysilicon is formed on the entire surface of the insulating film by, for example, CVD and ion implantation, and the low-resistance polysilicon is etched away, leaving behind a region overlapping the region into which the P-type impurity has been introduced. The low-resistance polysilicon remaining on the insulating film becomes the gate electrode 140. In this way, the gate electrode 140 is formed on the insulating film (gate insulating film 150) in a region overlapping the region 117′ into which the P-type impurity has been introduced. The insulating film directly below the gate electrode 140 constitutes the gate insulating film 150, and the insulating film in the other region constitutes the insulating film 151.

[0038] (4) N-type impurity introduction process Next, an N-type impurity is introduced into the peripheral region of the gate electrode 140 in the active layer 113 (see FIG. 2(d)). Specifically, a photomask (not shown) having an opening at a predetermined position (for example, a region 114' adjacent to a region 117' into which the P-type impurity was introduced in the first P-type impurity introduction step) is placed on the insulating film 151, and an N-type impurity (for example, phosphorus) is introduced into the surface of the active layer 113 from above through the opening by, for example, ion implantation.

[0039] (5) Thermal diffusion process Next, the SOI substrate 110 is heated to thermally diffuse the N-type impurities, thereby forming high-concentration N-type semiconductor regions 114a and 114b in a part of the surface of the active layer 113 to a depth not reaching the insulating layer 112 and having a higher impurity concentration than the active layer 113, and also forming N-type (N - In this case, a channel formation region 116 of high concentration N-type semiconductor material 114a and high concentration N-type semiconductor material 114b is formed (see FIG. 2(e)). The high concentration N-type semiconductor regions 114a and 114b are separated from each other, and the P-type impurities and the N-type impurities do not cancel each other out, so the region where the P-type impurities remain becomes a second P-type semiconductor region 117.

[0040] (6) Second P-type impurity introduction process Next, P-type impurities are introduced into the surfaces of the high-concentration N-type semiconductor regions 114a and 114b to form a plurality of P-type semiconductor regions 115 separated from the active layer 113 (see FIG. 2(f)). Specifically, a photomask (not shown) having openings at predetermined positions is placed on the insulating film 151, and P-type impurities (e.g., boron) are introduced from above through the openings by, for example, ion implantation into the surfaces of the high-concentration N-type semiconductor regions 114a and 114b to activate them. This forms a plurality of P-type semiconductor regions 115.

[0041] (7) Electrode, interlayer insulating film, and surface protection film formation process Next, an interlayer insulating film 152 is deposited, and a photomask having openings at predetermined positions (above the P-type semiconductor regions 115) is placed on the interlayer insulating film 152, and etching is performed to open the insulating film 151 and the interlayer insulating film 152. Next, a metal film is formed in the openings to form the source electrode 120 and the drain electrode 130. Next, a surface protective film 160 is formed so as to cover the interlayer insulating film 152, the source electrode 120, and the drain electrode 130 (see FIG. 2(g)).

[0042] In this manner, the semiconductor device 100 according to the first embodiment can be manufactured.

[0043] 3. Relationship between active layer thickness and threshold voltage of semiconductor device 100 according to embodiment 1 Next, the relationship between the active layer thickness and the threshold voltage in the semiconductor device 100 according to the first embodiment and another conventional semiconductor device 900 will be described.

[0044] In another conventional semiconductor device 900, as shown in the "Conventional" graph in FIG. 3, when the active layer thickness is near the target value of 1.4 μm, the threshold voltage Vth is approximately −1.5 V, which is within a predetermined range of −1.4 to −1.6 V. However, when the active layer thickness is thinner than 1.3 μm, the magnitude (absolute value) of the threshold voltage Vth is greater than −1.6 V; for example, when the active layer thickness is 1.2 μm, the threshold voltage Vth is approximately −1.65 V. On the other hand, when the active layer thickness is thicker than 1.6 μm, the magnitude (absolute value) of the threshold voltage Vth is greater than −1.6 V; for example, when the active layer thickness is 1.8 μm, the threshold voltage Vth is approximately −1.8 V.

[0045] This shows that in the other conventional semiconductor device 900, variations in the thickness of the active layer 113 of the SOI substrate 110 can cause variations in the characteristics of the semiconductor device (variations in threshold voltage).

[0046] This is thought to be because when the active layer thickness is thinner than 1.3 μm, a certain amount of N-type impurities diffuse into the thin active layer, making it difficult to form a channel due to the high N-type impurity concentration, and therefore increasing the threshold voltage Vth. On the other hand, when the active layer thickness is thicker than 1.6 μm, the low N-type impurity concentration in the N-type layer makes it easier for P-type impurities to thermally diffuse, reducing the P-type impurity concentration in the channel region directly below the gate electrode. As a result, the N-type impurity concentration in the channel region increases, making it difficult to form a channel and increasing the threshold voltage Vth.

[0047] In contrast, in the semiconductor device 100 according to the first embodiment, when the active layer thickness was near the target value of 1.4 μm, the threshold voltage Vth was a slightly low voltage close to approximately −1.6 V, as can be seen from the graph of “present invention” in Fig. 3. Furthermore, within the active layer thickness range of 1.0 μm to 2.0 μm, the threshold voltage remained within the predetermined range of −1.4 V to −1.6 V even when the active layer thickness was thinner than 1.3 μm or thicker than 1.6 μm.

[0048] From this, it was found that in the semiconductor device 100 according to the first embodiment, variations in the characteristics of the semiconductor device due to variations in the thickness of the active layer 113 of the SOI substrate 110 can be reduced.

[0049] This is thought to be because the high concentration N-type semiconductor regions 114a and 114b make the impurity concentrations of the P-type impurity region and the channel formation region independent of the thickness of the active layer of the SOI substrate.

[0050] 4. Effects of the semiconductor device 100 and the semiconductor device manufacturing method according to the first embodiment The semiconductor device 100 according to the first embodiment has high-concentration N-type semiconductor regions 114a and 114b formed in a portion of the surface of the active layer 113 to a depth not reaching the insulating layer 112 and having a higher impurity concentration than the active layer 113. This eliminates the need to form a boundary high-concentration N-type semiconductor region between the active layer and the insulating layer as in other conventional semiconductor devices 900. Therefore, it is not necessary to diffuse N-type impurities throughout the active layer 113 to form the boundary high-concentration N-type semiconductor region 918, and the impurity concentrations of the P-type semiconductor region 115 and the channel formation region 116 do not depend on the thickness of the active layer 113 of the SOI substrate 110 (see FIG. 3 ). As a result, even if the thickness of the active layer of the SOI substrate varies, the impurity concentrations of the P-type impurity region and the channel formation region are less likely to change, thereby reducing variations in the characteristics of the semiconductor device due to variations in the thickness of the active layer 113 of the SOI substrate 110.

[0051] Furthermore, according to the semiconductor device 100 of the first embodiment, the active layer 113 has high-concentration N-type semiconductor regions 114a and 114b formed in a part of the surface thereof at a depth not reaching the insulating layer 112 and having a higher impurity concentration than the active layer 113. Therefore, even if a P-type inversion layer is formed between the active layer 113 and the insulating layer 112, the high-concentration N-type semiconductor regions 114a and 114b can effectively separate the P-type semiconductor region 115 from the active layer 113 (N - This can prevent conduction between the source electrode 120 and the drain electrode 130, and hence between the gate electrode 120 and the drain electrode 130.

[0052] Furthermore, the method for manufacturing the semiconductor device according to the first embodiment includes a step of introducing P-type impurities into the surfaces of the high-concentration N-type semiconductor regions 114a and 114b to form two P-type semiconductor regions 115 spaced apart from the active layer 113. Therefore, even if a P-type inversion layer is formed between the active layer 113 and the insulating layer 112, the high-concentration N-type semiconductor regions 114a and 114b can prevent electrical continuity between the P-type semiconductor region 115 and the active layer 113, and further between the source electrode 120 and the drain electrode 130.

[0053] Furthermore, the method for manufacturing the semiconductor device according to the first embodiment includes a step of introducing P-type impurities into the surfaces of the heavily doped N-type semiconductor regions 114a and 114b to form two P-type semiconductor regions 115 spaced apart from the active layer 113. This eliminates the need to form a boundary heavily doped N-type semiconductor region between the active layer 113 and the insulating layer 112 as in other conventional semiconductor devices 900. Therefore, it is not necessary to diffuse N-type impurities throughout the active layer 113 to form the boundary heavily doped N-type semiconductor region, and the impurity concentrations of the P-type semiconductor region 115 and the channel formation region 116 do not depend on the thickness of the active layer 113 of the SOI substrate 110. As a result, the manufactured semiconductor device can reduce variations in the characteristics of the semiconductor device due to variations in the thickness of the active layer 113 of the SOI substrate 110.

[0054] Furthermore, according to the semiconductor device 100 of the first embodiment, the SOI substrate 110 has the second P-type semiconductor region 117 formed on the surface of the active layer 113 immediately below the gate insulating film 150, so that the impurity concentration of the channel formation region 116 can be adjusted to obtain a desired threshold voltage Vth, and furthermore, the P-type impurity immediately below the gate insulating film 150 results in a semiconductor device with a further reduced on-resistance.

[0055] Furthermore, according to the semiconductor device 100 of embodiment 1, the thickness of the active layer 113 is within a range of 1 to 2 μm, and therefore, a semiconductor device with high breakdown voltage can be obtained. In particular, by forming other electronic elements and the like on the same SOI substrate 110 and forming the semiconductor device 100 of embodiment 1, which is a high breakdown voltage element, a high breakdown voltage IC or semiconductor module can be obtained.

[0056] The semiconductor device 100 according to the first embodiment is a P-type field effect transistor, and this configuration makes it suitable for use at high potentials, such as for controlling a high-side switch.

[0057] [Embodiment 2] The semiconductor device 101 according to the second embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but differs from the semiconductor device 100 according to the first embodiment in that the second P-type semiconductor region 117 is not formed. - The gate insulating film 150 extends to the surface of the SOI substrate 110 (directly below the gate insulating film 150) (see FIG. 4).

[0058] The first heavily doped N-type semiconductor region 114a and the second heavily doped N-type semiconductor region 114b are separated from each other directly under the gate insulating film 150, and the channel forming region 116 is formed by the active layer 113 (N - The P-type semiconductor layer is formed between the P-type semiconductor region 115 and the P-type semiconductor layer.

[0059] As described above, the semiconductor device 101 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment in that the second P-type semiconductor region 117 is not formed. However, like the semiconductor device 100 according to the first embodiment, the semiconductor device 101 has high-concentration N-type semiconductor regions 114a and 114b formed in a part of the surface of the active layer 113 to a depth that does not reach the insulating layer 112 and having a higher impurity concentration than the active layer 113. Therefore, it is not necessary to form a boundary high-concentration N-type semiconductor region 918 between the active layer and the insulating layer as in other conventional semiconductor devices 900. Therefore, it is not necessary to diffuse N-type impurities throughout the active layer 113 to form the boundary high-concentration N-type semiconductor region 918, and the impurity concentrations of the P-type semiconductor region 115 and the channel formation region 116 do not depend on the thickness of the active layer 113 of the SOI substrate 110. As a result, it is possible to reduce variations in the characteristics of the semiconductor device due to variations in the thickness of the active layer 113 of the SOI substrate 110.

[0060] Furthermore, according to the semiconductor device 101 of the second embodiment, the active layer 113 has high-concentration N-type semiconductor regions 114a, 114b formed in a part of the surface thereof at a depth not reaching the insulating layer 112 and having a higher impurity concentration than the active layer 113. Therefore, even if a P-type inversion layer is formed between the active layer 113 and the insulating layer 112, the high-concentration N-type semiconductor regions 114a, 114b can prevent electrical conduction between the P-type semiconductor region 115 and the active layer 113, and further between the source electrode 120 and the drain electrode 130.

[0061] Furthermore, in the semiconductor device 101 according to the second embodiment, the first heavily doped N-type semiconductor region 114a and the second heavily doped N-type semiconductor region 114b are separated from each other directly below the gate insulating film 150, and no P-type semiconductor region is formed, resulting in a semiconductor device with high breakdown voltage.

[0062] The semiconductor device 101 according to the second embodiment has the same configuration as the semiconductor device 100 according to the first embodiment except that the second P-type semiconductor region 117 is not formed, and therefore has the corresponding effects of the semiconductor device 100 according to the first embodiment.

[0063] Although the present invention has been described above based on the above embodiment, the present invention is not limited to the above embodiment and can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0064] (1) The positions, connections, numbers, etc. described in the above embodiments (including each modified example; the same applies below) are examples and can be changed within the scope that does not impair the effects of the present invention.

[0065] (2) In the above embodiments, the thickness of the active layer is in the range of 1 to 2 μm, but the present invention is not limited to this. As long as a device can be formed, the thickness of the active layer may be less than 1 μm, or may be more than 2 μm as long as the breakdown voltage allows.

[0066] (3) In the above embodiments, the semiconductor device is manufactured using the method for manufacturing the semiconductor device according to embodiment 1, but the present invention is not limited to this. The semiconductor device according to embodiment 1 may be manufactured using a method other than the method for manufacturing the semiconductor device according to embodiment 1. [Explanation of symbols]

[0067] 100, 101... semiconductor device, 110... SOI substrate, 111... semiconductor support substrate, 112... insulating layer, 113... active layer, 114a... first heavily doped N-type semiconductor region, 114b... second heavily doped N-type semiconductor region, 115... P-type semiconductor region, 116... channel formation region, 117... second P-type semiconductor region, 120... source electrode, 130... drain electrode, 140... gate electrode, 150... gate insulating film, 152... interlayer insulating film, 160... surface protection film

Claims

1. an SOI substrate having a semiconductor support substrate, an insulating layer disposed on the semiconductor support substrate, and an N-type active layer disposed on the insulating layer; a source electrode and a drain electrode spaced apart from each other and disposed on the active layer; a gate electrode disposed on the active layer between the source electrode and the drain electrode via a gate insulating film; The SOI substrate is a high-concentration N-type semiconductor region formed in a part of the surface of the active layer to a depth not reaching the insulating layer, the high-concentration N-type semiconductor region having a higher impurity concentration than the active layer; a P-type semiconductor region formed on a surface of the high-concentration N-type semiconductor region, spaced apart from the active layer, and connected to the source electrode or the drain electrode; an N-type channel formation region formed directly under the gate insulating film, with an end portion in contact with the P-type semiconductor region, and having an impurity concentration lower than that of the high-concentration N-type semiconductor region.

2. the high-concentration N-type semiconductor region has a first high-concentration N-type semiconductor region surrounding the P-type semiconductor region connected to the source electrode, and a second high-concentration N-type semiconductor region surrounding the P-type semiconductor region connected to the drain electrode; the first heavily doped N-type semiconductor region and the second heavily doped N-type semiconductor region are spaced apart from each other directly below the gate insulating film, the SOI substrate further includes a second P-type semiconductor region formed on a surface of the active layer directly below the gate insulating film; 2. The semiconductor device according to claim 1, wherein the channel formation region is formed between the second P-type semiconductor region and the P-type semiconductor region.

3. the high-concentration N-type semiconductor region has a first high-concentration N-type semiconductor region surrounding the P-type semiconductor region connected to the source electrode, and a second high-concentration N-type semiconductor region surrounding the P-type semiconductor region connected to the drain electrode; the first heavily doped N-type semiconductor region and the second heavily doped N-type semiconductor region are spaced apart from each other directly below the gate insulating film, 2. The semiconductor device according to claim 1, wherein the channel formation region is formed between the active layer and the P-type semiconductor region immediately below the gate insulating film.

4. 4. The semiconductor device according to claim 1, wherein the thickness of the active layer is in the range of 1 to 2 μm.

5. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a P-type field effect transistor.

6. an SOI substrate including a semiconductor support substrate, an insulating layer disposed on the semiconductor support substrate, and an N-type active layer disposed on the insulating layer; and a step of introducing a P-type impurity into a part of a surface of the active layer; forming a gate electrode via a gate insulating film in a region on the active layer overlapping the region into which the P-type impurity is introduced; doping an N-type impurity into a peripheral region of the gate electrode in the active layer; a step of heating the SOI substrate to thermally diffuse the N-type impurity, thereby forming a high-concentration N-type semiconductor region in a part of the surface of the active layer, the high-concentration N-type semiconductor region being formed to a depth not reaching the insulating layer and having a higher impurity concentration than the active layer, and forming an N-type channel formation region having a lower impurity concentration than the high-concentration N-type semiconductor region formed in a region where the P-type impurity and the N-type impurity overlap directly below the gate insulating film; a step of introducing a P-type impurity into a surface of the high-concentration N-type semiconductor region to form a plurality of P-type semiconductor regions formed apart from the active layer; and forming a source electrode and a drain electrode connected to each of the plurality of P-type semiconductor regions.

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