Memory and manufacturing method for the same

Abstract

To provide a manufacturing method for a memory, and the memory, in which control capability for a semiconductor channel of a gate is improved and the contact resistance between source-drain and the semiconductor chanel is reduced.SOLUTION: A manufacturing method for a memory provides a semiconductor substrate. In a semiconductor substrate 10, at least one memory cell is manufactured. The memory cell includes at least one transistor 11. In each transistor, a semiconductor channel 112 surrounds an outer peripheral side of at least a gate 110. A gate dielectric 111 is formed between the semiconductor channel and the gate. An upper electrode 113 and a lower electrode 114 both are located on the outside of the semiconductor channel, and are in contact with the semiconductor channel. The lower electrode is provided while being insulated below the upper electrode. By oxidizing a region to be oxidized in an effective semiconductor channel in at least one transistor in the memory cell, the region to be oxidized is formed in an oxide channel 1120.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] TECHNICAL FIELD The present disclosure relates to the field of semiconductor technology, and more particularly to memories and methods for manufacturing the same. [Background technology]

[0002] As technology nodes shrink, capacitorless memory has become a research focus. Currently, capacitorless memory structures tend to be three-dimensional. When defects are repaired in the channel of a three-dimensional capacitorless memory by oxidation, the entire channel is easily oxidized, which increases the resistance of the entire channel and is detrimental to improving electrical performance. Summary of the Invention

[0003] The embodiments of the present disclosure provide a memory and a method for fabricating the same that can improve the controllability of the gate over the semiconductor channel and reduce the contact resistance between the source / drain and the semiconductor channel.

[0004] A first aspect of the present disclosure provides a method for manufacturing a memory, the method comprising: providing a semiconductor substrate; fabricating at least one memory cell on the semiconductor substrate, the memory cell including at least one transistor, each transistor including a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel surrounding at least an outer periphery of the gate, the gate dielectric being formed between the semiconductor channel and the gate, the upper electrode and the lower electrode both being located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode being provided below and insulated from the upper electrode, one of the upper electrode and the lower electrode being a source and the other being a drain; and forming an oxidation channel by oxidizing a region to be oxidized of an effective semiconductor channel of at least one of the transistors of the memory cells, the region to be oxidized being at least a part of the effective semiconductor channel, and neither the upper electrode nor the lower electrode being in contact with the oxidation channel, the effective semiconductor channel being a portion of the semiconductor channel located between the upper electrode and the lower electrode.

[0005] A second aspect of the present disclosure provides a memory, the memory including a semiconductor substrate and at least one memory cell; the at least one memory cell is formed on the semiconductor substrate, the memory cell includes at least one transistor, each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel surrounds at least the outer periphery of the gate, the gate dielectric is formed between the semiconductor channel and the gate, both the upper electrode and the lower electrode are located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is provided below the upper electrode and insulated, one of the upper electrode and the lower electrode is a source and the other is a drain, In the memory cell, a portion of the effective semiconductor channel of at least one of the transistors is formed into an oxide channel by an oxidation process, and the effective semiconductor channel is a portion of the semiconductor channel located between the upper electrode and the lower electrode, and neither the upper electrode nor the lower electrode contacts the oxide channel.

[0006] The technical solution according to the embodiments of the present disclosure has at least the following advantages:

[0007] By oxidizing only the effective semiconductor channel located between the source and drain, the gate's controllability over the semiconductor channel is improved, increasing the on-current. In addition, because the region of the semiconductor channel that comes into contact with the source and drain is not oxidized, the contact resistance between the source and drain and the semiconductor channel can be reduced. [Brief explanation of the drawings]

[0008] The drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are merely some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without creative work. [Figure 1] 1 shows a schematic diagram of a structure formed corresponding to step S100 in a memory manufacturing method according to an embodiment of the present disclosure. [Figure 2] 1 shows a schematic diagram of a structure formed corresponding to step S102 in a memory manufacturing method according to an embodiment of the present disclosure. [Figure 3] 10 shows a schematic diagram of a structure formed corresponding to step S104 in the memory manufacturing method according to the embodiment of the present disclosure. [Figure 4] 10A and 10B show schematic diagrams of the structure after correspondingly forming gas channels in a method for manufacturing a memory according to an embodiment of the present disclosure; [Figure 5] 10A and 10B are schematic diagrams illustrating a structure after an oxidation channel is formed by introducing an oxidation gas into a gas passage in a memory manufacturing method according to an embodiment of the present disclosure. [Figure 6] 10A and 10B are schematic diagrams illustrating a structure after a filler is formed by employing a partial filling method for a gas passage in a memory manufacturing method according to an embodiment of the present disclosure. [Figure 7] 1 shows a schematic diagram of a memory cell structure including a read transistor and a write transistor in a memory according to an embodiment of the present disclosure. [Figure 8]10A and 10B are schematic diagrams illustrating a structure after an oxidation channel is formed by oxidizing only the region to be oxidized of the read transistor in a memory manufacturing method according to an embodiment of the present disclosure. [Figure 9] 10A and 10B are schematic diagrams illustrating a structure after an oxidation channel is formed by oxidizing only the region to be oxidized of the write transistor in the memory manufacturing method according to the embodiment of the present disclosure. [Figure 10] 10A and 10B are schematic diagrams illustrating a structure after an oxidation channel is formed by oxidizing the region to be oxidized of the read transistor and the region to be oxidized of the write transistor in a memory manufacturing method according to an embodiment of the present disclosure. [Figure 11] FIG. 10 is a schematic diagram of the structure after gas passages are correspondingly formed in the method for manufacturing the memory according to the first embodiment of the present disclosure. [Figure 12] 3 is a schematic diagram showing a structure after a first oxidized channel and a second oxidized channel are simultaneously formed by introducing an oxidizing gas into a gas passage in the memory manufacturing method according to the first embodiment of the present invention; FIG. [Figure 13] 10 is a schematic diagram of a structure after a filler is formed by employing a complete filling method for a gas flow path in a manufacturing method of a memory according to the first embodiment of the present invention. FIG. [Figure 14] 10 is a schematic diagram of a structure after a filler is formed in a gas passage by employing a partial filling method in a memory manufacturing method according to the first embodiment of the present invention. FIG. [Figure 15] 2 shows a schematic diagram of a structure formed in accordance with step S200 of the memory manufacturing method according to the embodiment of the present invention. [Figure 16] 10A and 10B are schematic diagrams showing a structure formed in accordance with step S200 in the memory manufacturing method according to the embodiment of the present invention, viewed from different viewpoints. [Figure 17] 10A and 10B are schematic diagrams showing a structure formed in accordance with step S200 in the memory manufacturing method according to the embodiment of the present invention, viewed from different viewpoints. [Figure 18] 2 shows a schematic diagram of a structure formed in accordance with step S202 of the memory manufacturing method according to the embodiment of the present invention. [Figure 19] 1A and 1B are schematic diagrams illustrating a structure for correspondingly forming a read transistor in a memory manufacturing method according to an embodiment of the present invention; [Figure 20] 2 shows a schematic diagram of a structure formed corresponding to step S2041 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 21] 10 shows a schematic diagram of another structure formed corresponding to step S2041 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 22] 10 shows a schematic diagram of yet another structure formed corresponding to step S2041 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 23] 10 is a schematic diagram of a structure formed in accordance with step S206 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 24] 10 is a schematic diagram of another structure formed corresponding to step S206 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 25] 10 is a schematic diagram of a structure formed in accordance with step S208 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 26] 10A and 10B are schematic diagrams illustrating a structure formed in step S208 in a memory manufacturing method according to an embodiment of the present disclosure, viewed from different perspectives. [Figure 27] 10A and 10B are schematic diagrams illustrating a structure formed in step S208 in a memory manufacturing method according to an embodiment of the present disclosure, viewed from different perspectives. [Figure 28] 1 shows a schematic diagram of a structure formed in accordance with step S210 in the method for manufacturing a memory according to an embodiment of the present invention. [Figure 29] 10A and 10B are schematic diagrams illustrating a structure for correspondingly forming a write transistor in a memory manufacturing method according to an embodiment of the present disclosure; [Figure 30] 2 shows a schematic diagram of a structure formed corresponding to step S2121 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 31]10 shows a schematic diagram of another structure formed corresponding to step S2121 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 32] 2 shows a schematic diagram of a structure formed corresponding to step S2131 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 33] 21A and 21B are schematic diagrams illustrating a structure formed in accordance with step S2132 in the method for manufacturing a memory according to an embodiment of the present invention, as viewed from a different perspective. [Figure 34] 21A and 21B are schematic diagrams illustrating a structure formed in accordance with step S2132 in the method for manufacturing a memory according to an embodiment of the present invention, as viewed from a different perspective. [Figure 35] 10 shows a schematic diagram of a structure formed corresponding to step S2133 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 36] 10 is a schematic diagram of a structure formed in accordance with step S214 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 37] 10 is a schematic diagram of another structure formed corresponding to step S214 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 38] 10A and 10B are schematic diagrams illustrating the arrangement of memory cells and second portions of gas passages in a horizontal plane according to an embodiment of the present disclosure. [Figure 39] 10 shows a schematic diagram of a structure formed in accordance with step S216 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 40] 10 is a schematic view of the structure after correspondingly forming second gas passages in the method for manufacturing a memory according to the second embodiment of the present invention; FIG. [Figure 41] 10 is a schematic view of a structure after correspondingly forming first gas passages in a method for manufacturing a memory according to a second embodiment of the present invention; FIG. [Figure 42] FIG. 10 shows a schematic diagram of the structure after correspondingly forming a second oxidation channel in the method for manufacturing a memory according to the second embodiment of the present invention; [Figure 43] 10 is a schematic diagram of a structure after a second filling material is correspondingly formed in the manufacturing method of a memory according to the second embodiment of the present invention; FIG. [Figure 44] FIG. 10 shows a schematic diagram of the structure after correspondingly forming a first oxidation channel in the manufacturing method of the memory according to the second embodiment of the present invention; [Figure 45] 10 is a schematic diagram of a structure after a first filling material is correspondingly formed in the manufacturing method of a memory according to the second embodiment of the present invention; FIG. [Figure 46] 10 shows a schematic diagram of a structure formed in accordance with step S308 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 47] FIG. 10 is a schematic diagram of a structure after a second filler is formed by employing a partial filling method for a second gas passage in a memory manufacturing method according to a second embodiment of the present invention. [Figure 48] 10 shows a schematic diagram of a structure formed in accordance with step S406 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 49] 10 shows a schematic diagram of another structure formed corresponding to step S406 in the method for manufacturing a memory according to the embodiment of the present invention. [Figure 50] 10 shows a schematic diagram of a structure formed in accordance with step S408 in the method for manufacturing a memory according to an embodiment of the present invention. [Figure 51] FIG. 10 is a schematic diagram of a structure after a first filler is formed by employing a partial filling method in a first gas passage in a manufacturing method of a memory according to a second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, exemplary embodiments may be implemented in various forms and should not be limited to the examples described herein. On the contrary, by providing these embodiments, the present application will be more thorough and complete and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0010] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to thoroughly understand the embodiments of the present application. However, those skilled in the art will recognize that the technical solutions of the present application can be implemented without one or more of the specific details, or that other methods, components, devices, steps, etc. can be used. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0011] The present application will be described in more detail below with reference to the drawings and specific examples. The technical features of each embodiment of the present application described below can be combined with each other as long as they are not inconsistent. The embodiments described below with reference to the drawings are illustrative and are intended to explain the present application, but should not be construed as limiting the present application.

[0012] The present disclosure provides a method for manufacturing a memory, which includes steps S100, S102, and S104.

[0013] In step S100, a semiconductor substrate 10 is provided. As shown in FIG. 1, for example, the semiconductor substrate 10 may be, but is not limited to, a silicon (Si) substrate, and may also be a germanium (Ge) substrate, etc., which is determined according to specific circumstances.

[0014] In step S102, at least one memory cell is fabricated on the semiconductor substrate 10, and the memory cell may include at least one transistor 11. As shown in FIG. 2, the transistor 11 may have a three-dimensional structure. Specifically, each transistor 11 may include a gate 110, a gate dielectric 111, a semiconductor channel 112, an upper electrode 113, and a lower electrode 114. The semiconductor channel 112 surrounds at least the outer periphery of the gate 110, and the gate dielectric 111 is formed between the semiconductor channel 112 and the gate 110 to avoid direct contact between the semiconductor channel 112 and the gate 110. The upper electrode 113 and the lower electrode 114 are both located outside the semiconductor channel 112 and contact the semiconductor channel 112.

[0015] Here, the lower electrode 114 is provided below and insulated from the upper electrode 113, i.e., the lower electrode 114 is closer to the semiconductor substrate 10 than the upper electrode 113. Furthermore, one of the upper electrode 113 and the lower electrode 114 is the source and the other is the drain, and the portion of the semiconductor channel 112 located between the upper electrode 113 and the lower electrode 114 can be defined as an effective semiconductor channel.

[0016] For example, a plurality of memory cells may be provided and arranged in a horizontal plane to form a memory array structure. Here, the memory array structure may include one layer or multiple layers stacked in a vertical direction. Note that the horizontal plane referred to in this embodiment refers to a plane parallel or approximately parallel to the semiconductor substrate 10, and the vertical direction refers to a direction perpendicular or approximately perpendicular to the semiconductor substrate 10.

[0017] In step S104, the region to be oxidized of the effective semiconductor channel of at least one transistor 11 of the memory cell is oxidized to form the oxidized channel 1120, where the region to be oxidized is at least a portion of the effective semiconductor channel, and neither the upper electrode 113 nor the lower electrode 114 contacts the oxidized channel 1120, as shown in FIG. 3.

[0018] In this embodiment, by performing oxidation treatment only on the effective semiconductor channel located between the source and drain of the semiconductor channel 112, an oxide channel 1120 having oxygen vacancies is formed in the region located between the source and drain of the semiconductor channel 112, thereby improving the controllability of the gate 110 over the semiconductor channel 112 and increasing the on-current.In addition, since oxidation treatment is not performed on the region of the semiconductor channel 112 that contacts the source and drain, the contact resistance between the source and drain and the semiconductor channel 112 can be reduced.

[0019] In addition, step S104 in this embodiment may belong to one of the substeps in step S102, but is not limited to this, and step S104 may be a step performed after completing the manufacturing of the entire memory cell in step S102, and can then be explained in detail according to the actual manufacturing situation, so the explanation will be omitted here.

[0020] Here, before performing oxidation treatment on the region to be oxidized in the semiconductor channel 112, the manufacturing method of this embodiment further includes a step of manufacturing a gas passage 12. As shown in FIG. 4, the gas passage 12 includes a first portion 120 arranged around the outer periphery of the region to be oxidized, and a second portion 121 connected to the first portion 120 and extending vertically upward. After the gas passage 12 is formed, oxidizing gas introduced from above the second portion 121 acts on the region to be oxidized. That is, when performing oxidation treatment on the region to be oxidized in the semiconductor channel 112, oxidizing gas can be introduced from the opening above the second portion 121, as shown in FIG. 5. This oxidizing gas flows sequentially through the second portion 121 and the first portion 120 and acts on the region to be oxidized, thereby oxidizing the region to be oxidized into an oxidation channel 1120. Here, the thick dotted line with an arrow in the gas passage 12 in FIG. 5 indicates the flow path of the oxidizing gas.

[0021] In this embodiment, an oxide channel 1120 is formed in the effective semiconductor channel of the semiconductor channel 112 to improve the electrical performance of the transistor 11 and to achieve a desired threshold voltage control of the semiconductor channel 112. For example, the oxidizing gas in this embodiment may include at least oxygen gas.

[0022] Here, since the first portion 120 of the gas passage 12 is arranged around the outer periphery of the area to be oxidized, the oxidation channel 1120 formed in this embodiment may be arranged in a ring shape, specifically, may be arranged so as to surround the gate 110 of the transistor 11.

[0023] In an optional embodiment, after forming the gas passage 12 and before introducing the target gas from above the second portion 121, the manufacturing method of this embodiment may further include a step of performing a repair treatment on the surface of the area to be oxidized by introducing a repair agent from above the second portion 121 and allowing it to act on the area to be oxidized.

[0024] For example, if the semiconductor channel 112 is fabricated using a metal oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide), the repair agent may include at least hydrogen gas, but is not limited thereto. Other types of repair agents may also be used, and the repair agent will be determined according to the actual situation.

[0025] Here, after forming the oxidation channel 1120, the manufacturing method of this embodiment may further include a step of filling the gas passage 12 with an insulating material to prevent subsequent processing processes from affecting the oxidation channel 1120.

[0026] In some embodiments, filling the gas passage 12 with insulating material may include completely filling the gas passage 12 with insulating material to form a filler 13 within the gas passage 12. To completely fill the gas passage 12, the first and second portions 120 and 121 of the gas passage 12 are filled with insulating material, respectively, as shown in FIG. 3 . This design ensures structural stability. The top surface of the filler 13 is flush with the top surface of the gas passage 12, ensuring flatness of the top surface of the structure, which is advantageous for forming other structural layers above it.

[0027] It should be noted that the upper surface referred to in this disclosure refers to the surface of the object away from the semiconductor substrate 10, and will not be described again below.

[0028] In some other embodiments, filling the gas passage 12 with insulating material may include partially or completely filling the second portion 121 of the gas passage 12 with insulating material to form a filler 13 within the second portion 121, and as shown in FIG. 6, the top surface of the filler 13 is flush with the top surface of the gas passage 12, thereby ensuring flatness of the top surface of the structure and advantageously forming other structural layers above it.

[0029] As shown in FIG. 6, the region of the gas passage 12 other than the region filled with the filler 13 is a void. For example, when the filler 13 only partially fills the second portion 121, the first portion 120 of the gas passage 12 and the second portion 121 of the gas passage 12 that are not filled with the filler 13 are both void regions. When the filler 13 completely fills the second portion 121, the first portion 120 of the gas passage 12 is a void region. That is, by partially and completely filling the second portion 121 of the gas passage 12 with an insulating material, the subsequent processing steps can be prevented from affecting the oxidation channel, and the first portion 120 of the gas passage 12 can be formed in the void region. That is, there is a void between the upper electrode 113 and the lower electrode 114 of the transistor 11. In this way, the parasitic capacitance between the upper electrode 113 and the lower electrode 114 of the transistor 11 can be reduced, as shown in FIG. 6.

[0030] In addition, when the second portion 121 of the gas passage 12 is partially filled with an insulating material, the filled area should be the upper portion of the second portion 121, so that the upper surface of the filler 13 is flush with the upper surface of the gas passage 12, as shown in Figure 6. Specifically, the filler 13 is formed using an insulating material in a quick sealing manner, and the filler 13 is formed in the upper portion of the second portion 121, and the lower portion of the second portion 121 and the first portion 120 are both void areas.

[0031] Hereinafter, a method for manufacturing a memory will be described in detail with reference to the drawings and the specific structure of the memory cell. In the embodiment of the present disclosure, the memory cell may have a 2T0C structure, that is, the memory cell has a structure including two transistors 11 and no storage capacitance, where one of the two transistors 11 of each memory cell is a read transistor 11R and the other is a write transistor 11W.

[0032] For ease of subsequent description, in the embodiments of the present disclosure, the gate 110, gate dielectric 111, semiconductor channel 112, upper electrode 113, and lower electrode 114 of the write transistor 11W are defined as a first gate 110W, a first gate dielectric 111W, a first semiconductor channel 112W, a first upper electrode 113W, and a first lower electrode 114W, respectively, and the gate 110, gate dielectric 111, semiconductor channel 112, upper electrode 113, and lower electrode 114 of the read transistor 11R are defined as a second gate 110R, a second gate dielectric 111R, a second semiconductor channel 112R, a second upper electrode 113R, and a second lower electrode 114R, respectively.

[0033] As shown in FIG. 7, in the memory cell, the write transistor 11W is located above the read transistor 11R, and the first bottom electrode 114W of the write transistor 11W is electrically connected to the second gate 110R of the read transistor 11R.

[0034] Here, the step of forming the region to be oxidized into an oxidized channel by oxidizing the region to be oxidized of the effective semiconductor channel of at least one transistor 11 of the memory cells mentioned in step S104 above may specifically include a step of oxidizing the region to be oxidized of the effective semiconductor channel of at least one of the write transistor 11W and the read transistor 11R, that is, the effective semiconductor channel of at least one of the write transistor 11W and the read transistor 11R includes an oxidized channel 1120.

[0035] In some embodiments, the memory manufacturing method of the present disclosure may include a step of oxidizing a region to be oxidized of an effective semiconductor channel of one of the write transistor 11W and the read transistor 11R to form an oxide channel 1120, where the gas passage 12 is manufactured after the manufacturing of the transistor 11 corresponding to the region to be oxidized is completed, in this way, structures such as the gate dielectric 111 and the gate 110 inside the semiconductor channel 112 can protect it and reduce damage to the semiconductor channel 112 during the manufacturing process of the gas passage 12.

[0036] For example, as shown in FIG. 8, in this embodiment, the step of oxidizing the region to be oxidized of the transistor 11 in the memory cell may include a step of oxidizing only the region to be oxidized of the read transistor 11R in the memory cell, so that the effective semiconductor channel of the read transistor 11R includes an oxidized channel 1120, in which the gas passage 12 is fabricated after the fabrication of the read transistor 11R is completed, and the filling of the gas passage 12 is completed before the fabrication of the write transistor 11W begins.

[0037] Alternatively, as shown in FIG. 9, in this embodiment, the step of oxidizing the region to be oxidized of the transistor 11 in the memory cell may include a step of oxidizing only the region to be oxidized of the write transistor 11W in the memory cell, so that the effective semiconductor channel of the write transistor 11W includes an oxidized channel 1120, and the gas passage 12 is fabricated after the fabrication of the write transistor 11W is completed.

[0038] In some other embodiments, the manufacturing method of the present disclosure may include a step of forming both the regions to be oxidized of the effective semiconductor channels of the write transistor 11W and the read transistor 11R into the oxidized channel 1120 by oxidizing both the regions to be oxidized of the write transistor 11W and the read transistor 11R.

[0039] Here, for ease of subsequent description, the effective semiconductor channel of the first semiconductor channel 112W in the write transistor 11W may be defined as the first effective semiconductor channel, the region to be oxidized of the first effective semiconductor channel in the write transistor 11W may be defined as the first region to be oxidized, the effective semiconductor channel of the second semiconductor channel 112R in the read transistor 11R may be defined as the second effective semiconductor channel, and the region to be oxidized of the second effective semiconductor channel in the read transistor 11R may be defined as the second region to be oxidized.

[0040] Specifically, as shown in FIG. 10 , the step of oxidizing both the regions to be oxidized of the effective semiconductor channels of the write transistor 11W and the read transistor 11R to form both the regions to be oxidized of the write transistor 11W and the read transistor 11R into the oxidation channel 1120 may include the steps of oxidizing a first region to be oxidized of a first effective semiconductor channel of the write transistor 11W to form the first region to be oxidized into the first oxidation channel 1120W, and oxidizing a second region to be oxidized of a second effective semiconductor channel of the read transistor 11R to form the second region to be oxidized into the second oxidation channel 1120R. By oxidizing both the regions to be oxidized of the write transistor 11W and the read transistor 11R, the oxidation channel 1120 is formed in the write transistor 11W and the read transistor 11R, which improves the electrical performance of the read transistor 11R and the write transistor 11W and enhances the memory performance of the memory cell.

[0041] Here, in this embodiment, the embodiment in which the regions to be oxidized of the effective semiconductor channels of the write transistor 11W and the read transistor 11R are both oxidized may include the following types.

[0042] [Embodiment 1] In an embodiment of the present disclosure, the first oxidation channel 1120W of the write transistor 11W and the second oxidation channel 1120R of the read transistor 11R may be formed simultaneously, that is, the first oxidation channel 1120W and the second oxidation channel 1120R are formed in the same manufacturing step, thereby improving manufacturing efficiency and reducing manufacturing costs.

[0043] Here, if the first oxidation channel 1120W and the second oxidation channel 1120R need to be formed simultaneously, the gas passage 12 is manufactured after the completion of the manufacturing of the write transistor 11W. In this embodiment, as shown in FIG. 11, the first portion 120 of the manufactured gas passage 12 may include an upper first portion 120W and a lower first portion 120R, where the upper first portion 120W refers to the upper region of the first portion 120 away from the semiconductor substrate 10, and the upper first portion 120W surrounds the outer periphery of the region to be first oxidized, and the lower first portion 120R refers to the lower region of the first portion 120 close to the semiconductor substrate 10, and the lower first portion 120R surrounds the outer periphery of the region to be second oxidized.

[0044] As shown in FIG. 11 , the upper first portion 120W and the lower first portion 120R of the gas passage 12 in this embodiment are spaced apart in the vertical direction Z and communicate with each other through the second portion 121. Specifically, the second portion 121 extends vertically upward to the top surface of the memory cell to communicate with the upper first portion 120W and the lower first portion 120R. This allows the oxidizing gas introduced from above the second portion 121 to act simultaneously on the first oxidation target region and the second oxidation target region to perform oxidation processing. That is, As shown in Figure 12, the oxidizing gas enters the second part 121 through the intake port of the second part 121, and a portion of the oxidizing gas is diverted into the upper first part 120W to act on the first oxidation target area and perform an oxidation process, and another portion of the oxidizing gas is diverted into the lower first part 120R to act on the second oxidation target area and perform an oxidation process, thereby simultaneously forming the first oxidation channel 1120W and the second oxidation channel 1120R, and the thick dashed lines with arrows in Figure 12 indicate the flow paths of the oxidizing gas.

[0045] For example, after the first oxidation channel 1120W and the second oxidation channel 1120R are formed simultaneously, as shown in FIG. 13, the gas passage 12 can be completely filled with an insulating material to form a filler 13 in the gas passage 12. That is, the upper first portion 120W, the lower first portion 120R and the second portion 121 of the gas passage 12 are all filled with the filler 13 made of an insulating material, which ensures the stability of the memory cell structure. Here, the upper surface of the filler 13 can be flush with the upper surface of the memory cell, thereby ensuring the flatness of the upper surface of the memory array structure and facilitating the fabrication of subsequent structural layers.

[0046] After the first oxidation channel 1120W and the second oxidation channel 1120R are simultaneously formed, the gas passage 12 is not limited to being filled by the above-mentioned complete filling method, but may be filled by an incomplete filling method. For example, the second portion 121 is divided into an upper main region and a lower communication region along the vertical direction Z, and the upper main region extends from the top surface of the memory cell to the upper first portion 120W and communicates with the upper first portion 120W, and the lower communication region is The region connects the upper first portion 120W and the lower first portion 120R, and here, in order to form a filler 13 in the upper main region of the second portion 121, a quick sealing method is adopted to fill the upper main region with an insulating material, and as shown in Figure 14, the upper surface of this filler 13 is flush with the upper surface of the memory cell, and the filler 13 may completely fill the upper main region of the second portion 121 or may fill the upper half of the upper main region.

[0047] Here, after filling the gas passage 12 using the incomplete filling method described above, as shown in FIG. 14, the upper first portion 120W and the lower first portion 120R are both void regions that are not filled with the filler 13. That is, there is a void between the first upper electrode 113W and the first lower electrode 114W and between the second upper electrode 113R and the second lower electrode 114R. In this way, the parasitic capacitance between the first upper electrode 113W and the first lower electrode 114W and between the second upper electrode 113R and the second lower electrode 114R can be reduced.

[0048] In one specific example of an embodiment of the present disclosure, the manufacturing method of the gas passage 12 including the upper first portion 120W, the lower first portion 120R and the second portion 121 may include at least steps S200, S202, S204, S206, S208, S210, S212, S214 and S216.

[0049] In step S200, a lower stacked film layer is formed on the semiconductor substrate 10, and as shown in FIG. 15, the lower stacked film layer includes a second lower electrode 114R, a lower sacrificial insulating film layer 141R, a second upper electrode 113R and a lower partition insulating film layer 142R sequentially stacked at least along the vertical direction Z, wherein the material of the lower partition insulating film layer 142R may be different from the material of the lower sacrificial insulating film layer 141R and the subsequent upper sacrificial insulating film layer so as to avoid the risk of the lower partition insulating film layer 142R also being removed in the subsequent removal step of the upper sacrificial insulating film layer and the lower sacrificial insulating film layer 141R.

[0050] In some embodiments, as shown in FIG. 15, the lower stacked film layer may further include a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, where the first lower interlayer dielectric layer 143R is formed between the second upper electrode 113R and the lower sacrificial insulating film layer 141R, and the second lower interlayer dielectric layer 144R is formed between the second lower electrode 114R and the lower sacrificial insulating film layer 141R.

[0051] Here, the material of the first lower inter-layer dielectric layer 143R and the second lower inter-layer dielectric layer 144R is different from the material of the lower sacrificial insulating layer 141R so as to avoid the risk of the first lower inter-layer dielectric layer 143R and the second lower inter-layer dielectric layer 144R also being removed in the subsequent removal step of the lower sacrificial insulating layer 141R, thereby allowing the first lower inter-layer dielectric layer 143R and the second lower inter-layer dielectric layer 144R to protect the second upper electrode 113R and the second lower electrode 114R.

[0052] For example, the insulating materials of the first lower interlayer dielectric layer 143R, the second lower interlayer dielectric layer 144R and the lower partition insulating layer 142R may be the same, for example, silicon oxide, and the insulating material of the lower sacrificial insulating layer 141R may be silicon nitride, silicon oxynitride, silicon carbonitride, etc., but is not limited to these and can be determined according to actual conditions.

[0053] In some embodiments of the present disclosure, step S200 may specifically include step S2001, step S2002, step S2003, and step S2004.

[0054] In step S2001, a plurality of second down signal lines 145R are formed on the semiconductor substrate 10. The second down signal lines 145R are arranged side by side at intervals in the first horizontal direction X and extend in the second horizontal direction Y. Second lower partition insulating portions 146R are also formed between adjacent second down signal lines 145R. Referring to FIGS. 16 and 17, in this embodiment, the second lower partition insulating portions 146R insulate adjacent second down signal lines 145R from each other. Here, the second down signal lines 145R may be formed on the semiconductor substrate 10 before the second lower partition insulating portions 146R. However, this is not limited thereto, and the second lower partition insulating portions 146R may be formed first, and then the plurality of second down signal lines 145R may be formed.

[0055] It should be noted that the first horizontal direction X and the second horizontal direction Y mentioned at any position in this disclosure are defined as directions parallel or approximately parallel to the semiconductor substrate 10, where the first horizontal direction X intersects with the second horizontal direction Y, and further, the first horizontal direction X and the second horizontal direction Y are vertical or approximately vertical, thereby reducing the difficulty of design and saving space.

[0056] In step S2002, as shown in Figures 16 and 17, a second lower interlayer dielectric layer 144R, a lower sacrificial insulating film layer 141R and a first lower interlayer dielectric layer 143R are formed on the upper surfaces (i.e., the surfaces away from the semiconductor substrate 10) of the second down signal line 145R and the second lower partition insulating portion 146R, sequentially stacked along the vertical direction Z.

[0057] In step S2003, as shown in FIGS. 16 and 17 , a plurality of second UP signal lines 147R are formed in the first lower inter-layer dielectric layer 143R. The second UP signal lines 147R are arranged side by side at intervals in the second horizontal direction Y and extend in the first horizontal direction X, and second upper partition insulating portions 148R are located between adjacent second UP signal lines 147R. In this embodiment, the second upper partition insulating portions 148R insulate the adjacent second UP signal lines 147R from each other. Here, the second UP signal lines 147R are formed in the first lower inter-layer dielectric layer 143R before the second upper partition insulating portions 148R are formed. However, this is not limited to this. The second upper partition insulating portions 148R are formed first, and then the plurality of second UP signal lines 147R are formed.

[0058] In the disclosed embodiment, one of the second up signal line 147R and the second down signal line 145R is a read bit line, and the other is a read word line. As shown in FIGS. 16 and 17 , there is an overlapping region between the orthogonal projection of the second up signal line 147R onto the semiconductor substrate 10 and the orthogonal projection of the second down signal line 145R onto the semiconductor substrate 10. Here, the portion of the second up signal line 147R corresponding to the overlapping region is defined as the second upper electrode 113R, and the portion of the second down signal line 145R corresponding to the overlapping region is defined as the second lower electrode 114R.

[0059] For example, the second up signal line 147R and the second down signal line 145R may include one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and polysilicon, but are not limited thereto, and other conductive materials may be used as long as the performance of the second up signal line 147R and the second down signal line 145R can be ensured.

[0060] In step S2004, as shown in FIGS. 16 and 17, a lower partition insulating film layer 142R is formed to entirely cover the second UP signal line 147R and the second upper partition insulating portion 148R.

[0061] The lower partition insulating layer 142R may be integrally formed with the second upper partition insulating portion 148R, but is not limited to this and may be manufactured separately depending on specific circumstances.

[0062] In some other embodiments, the lower stacked film layer may not include the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R shown in FIGS. 15 to 17, depending on specific circumstances.

[0063] In step S202, a lower through-hole 149R is formed penetrating at least the lower partition insulating film layer 142R, the second upper electrode 113R, and the lower sacrificial insulating film layer 141R. As shown in FIG. 18, the second lower electrode 114R is exposed from the lower through-hole 149R. Note that the second upper electrode 113R belongs to a portion of the second up signal line 147R that overlaps with the second down signal line 145R, and the second lower electrode 114R belongs to a portion of the second down signal line 145R that overlaps with the second up signal line 147R. Therefore, it may be understood that the lower through-hole 149R in this embodiment is opened in the region where the second up signal line 147R and the second down signal line 145R overlap.

[0064] Here, if the lower stacked film layer further includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, as shown in FIG. 18, the lower through-hole 149R may further penetrate the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R.

[0065] For example, the lower surface of the lower through-hole 149R can extend into the second lower electrode 114R, as shown in FIG. 18, thereby increasing the exposed area of ​​the second lower electrode 114R and increasing the contact area with the subsequent semiconductor channel 112. This also ensures that the second lower electrode 114R is exposed, while reducing the etching accuracy and reducing the etching cost. However, the lower surface of the lower through-hole 149R is not limited to extending into the second lower electrode 114R, and may extend just up to the upper surface of the second lower electrode 114R, or the lower through-hole 149R may penetrate the second lower electrode 114R, etc. (i.e., the lower surface of the lower through-hole 149R is flush with or lower than the lower surface of the second lower electrode 114R).

[0066] In step S204, a second semiconductor channel 112R, a second gate dielectric 111R and a second gate 110R are formed in the lower through-hole 149R, thereby forming a read transistor 11R. As shown in FIG. 19, the second oxidation target region of the second semiconductor channel 112R corresponds to the lower sacrificial insulating layer 141R, that is, the second oxidation target region of the second semiconductor channel 112R is located in a position surrounded by the lower sacrificial insulating layer 141R.

[0067] In addition, if the lower stacked film layer includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, after performing step S204, the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R are both arranged to surround the second effective semiconductor channel. Specifically, the first lower interlayer dielectric layer 143R may surround a region located above the second region to be oxidized in the second effective semiconductor channel, and the second lower interlayer dielectric layer 144R may surround a region located below the second region to be oxidized in the second effective semiconductor channel.

[0068] In some embodiments of the present disclosure, step S204 may include at least step S2041 and step S2042.

[0069] In step S2041, after the lower through-hole 149R is formed, a lower semiconductor thin film layer 151R, a lower gate dielectric thin film layer 152R and a lower gate thin film layer 153R are sequentially deposited on the lower stacked film layer. As shown in FIG. 20, the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R and the lower gate thin film layer 153R all cover the lower stacked film layer. That is, the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R and the lower gate thin film layer 153R are It may be deposited on the upper surface of the lower partition insulating film layer 142R and in the lower through-hole 149R, where, as shown in FIG. 20, the portions of the lower semiconductor thin-film layer 151R and the lower gate dielectric thin-film layer 152R located in the lower through-hole 149R may be U-shaped, and the portion of the lower gate thin-film layer 153R located in the lower through-hole 149R may be U-shaped, or as shown in FIG. 21, the lower gate thin-film layer 153R fills the lower through-hole 149R.

[0070] For example, the material of the lower semiconductor thin film layer 151R may be a semiconductor material such as IGZO, but is not limited to this, and may be other semiconductor materials; the material of the lower gate dielectric thin film layer 152R may be a high-dielectric insulating material such as silicon oxide, but is not limited to this, and may be a low-dielectric material, etc.; and the material of the lower gate thin film layer 153R may be a conductive material with good gate control ability, such as ZnO (zinc oxide), ITO (indium tin oxide), IZO (indium zinc oxide), but is not limited to this, and may be other conductive materials.

[0071] In addition, if the portion of the lower gate thin film layer 153R located in the lower through-hole 149R is U-shaped as shown in Figure 20, step S2041 may further include a step of depositing a lower conductive filling thin film layer 154R to completely cover the lower gate thin film layer 153R after depositing the lower gate thin film layer 153R, as shown in Figure 22, where the portion of the lower conductive filling thin film layer 154R located in the lower through-hole 149R fills the lower through-hole 149R. In this embodiment, the lower conductive filling thin film layer 154R can be made of a conductive material with good conductivity and lower cost than the lower gate thin film layer 153R.

[0072] In step S2042, as shown in FIG. 19, the portions of the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R that are beyond the target distance value from the hole boundary of the lower through-hole 149R are etched and removed, thereby forming a second semiconductor channel 112R, a second gate dielectric 111R, and a second gate 110R in the lower through-hole 149R, thereby forming the read transistor 11R.

[0073] Here, the obtained target distance value mentioned in step S2042 may be 0, that is, all portions of the lower semiconductor thin film layer 151R, the lower gate dielectric thin film layer 152R, and the lower gate thin film layer 153R that exceed the boundary of the lower through-hole 149R are etched and removed, but is not limited thereto. The obtained target distance value mentioned in step S2042 may be greater than 0, but must be less than half the distance between adjacent lower through-holes 149R. In addition to the portions of the second semiconductor channel 112R, the second gate dielectric 111R, and the second gate 110R fabricated in this manner that are located within the lower through-hole 149R, they also have portions that extend away from the hole axis and are mounted on the upper surface of the lower partition insulating film layer 142R, as shown in Figure 19, when forming a plurality of readout transistors 11R arranged in an array in this manner, the difficulty of etching can be reduced and the quality of the product can be guaranteed.

[0074] It should be understood that if step S2041 includes a lower conductive filling thin-film layer 154R covering the entire lower gate thin-film layer 153R, then step S2042, in the process of etching and removing the portions of the lower semiconductor thin-film layer 151R, the lower gate dielectric thin-film layer 152R, and the lower gate thin-film layer 153R that are beyond a target distance value from the hole boundary, further includes etching and removing the portion of the lower conductive filling thin-film layer 154R that is beyond a target distance value from the hole boundary. Here, the remaining unetched portion of the lower conductive filling thin-film layer 154R is defined as a lower conductive filling portion 115R, and the lower conductive filling portion 115R may be included in the readout transistor 11R. A portion of the lower conductive filling portion 115R fills the lower through-hole 149R and contacts the second gate 110R, and another portion is mounted on the upper surface of the second gate 110R. Note that the upper surface of the second gate 110 referred to in this disclosure refers to the surface of the second gate 110 that is farthest from the semiconductor substrate 10.

[0075] In step S206, an intermediate partition insulating film layer 16 is formed on the lower stacked film layer, and as shown in Figure 23, the intermediate partition insulating film layer 16 covers at least the area on the upper surface of the lower partition insulating film layer 142R that is not covered by the read transistor 11R, and the orthogonal projection of at least a portion of the second gate 110R onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the intermediate partition insulating film layer 16 onto the semiconductor substrate 10, that is, at least a portion of the second gate 110R is not shielded by the intermediate partition insulating film layer 16 so as to be connected to the first lower electrode 114W of the write transistor 11W to be formed later.

[0076] 23, the portion of the second gate 110R located in the lower through-hole 149R is U-shaped, and when the lower through-hole 149R is filled with the lower conductive filling 115R, the upper surface of the intermediate partition insulating layer 16 may be higher than the upper surface of the lower conductive filling 115R, and the intermediate partition insulating layer 16 has a plurality of intermediate vias 160 that correspond one-to-one to the lower conductive filling 115R, and the intermediate vias 160 expose at least a partial region of the upper surface of the lower conductive filling 115R. 24, when the second gate 110R fills the lower through-hole 149R, the upper surface of the intermediate partition insulating layer 16 may be higher than the upper surface of the second gate 110R, and the intermediate partition insulating layer 16 has a plurality of intermediate vias 160 that correspond one-to-one to the second gate 110R of the read transistor 11R, and the intermediate vias 160 expose at least a partial region of the upper surface of the second gate 110R.

[0077] In step S208, an upper stacked film layer is formed, and as shown in Figure 25, the upper stacked film layer includes a first lower electrode 114W, an upper sacrificial insulating film layer 171W, a first upper electrode 113W and an upper partition insulating film layer 172W stacked sequentially at least along the vertical direction Z, wherein the first lower electrode 114W is connected to the second gate 110R, and the upper surface of the first lower electrode 114W is flush with the upper surface of the intermediate partition insulating film layer 16.

[0078] For example, by making the material of the upper partition insulating film layer 172W different from the materials of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, the risk of the upper partition insulating film layer 172W also being removed in the subsequent step of removing the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R is avoided.

[0079] In some embodiments, as shown in FIG. 25, the upper stacked film layer may further include a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, where the first upper interlayer dielectric layer 173W is formed between the first upper electrode 113W and the upper sacrificial insulating film layer 171W, and the second upper interlayer dielectric layer 174W is formed between the intermediate partition insulating film layer 16 and the upper sacrificial insulating film layer 171W.

[0080] For example, since the material of the first inter-layer dielectric layer (173W) and the second inter-layer dielectric layer (174W) is different from the material of the upper sacrificial insulating layer (171W) and the lower sacrificial insulating layer (141R), the risk of the first inter-layer dielectric layer (173W) and the second inter-layer dielectric layer (174W) also being removed in the subsequent removal step of the upper sacrificial insulating layer (171W) and the lower sacrificial insulating layer (141R) can be avoided, and the first upper electrode (113W) and the first lower electrode (114W) can be protected using the first inter-layer dielectric layer (173W) and the second inter-layer dielectric layer (174W).

[0081] For example, the insulating material of the first upper interlayer dielectric layer 173W, the second upper interlayer dielectric layer 174W, the upper partition insulating film layer 172W, the middle partition insulating film layer 16 and the lower partition insulating film layer 142R may be the same, for example, they may all be silicon oxide, and the insulating material of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R may be the same, for example, they may all be silicon nitride, silicon oxynitride or silicon carbonitride, etc. It can be understood that the insulating materials of each interlayer dielectric layer, partition insulating film layer and sacrificial insulating film layer are not limited to those exemplified above and may be other insulating materials in some cases.

[0082] In some embodiments of the present disclosure, step S208 may specifically include step S2081, step S2082, and step S2083.

[0083] In step S2081, as shown in FIGS. 26 and 27, a plurality of first lower electrodes 114W are formed in an array along the first horizontal direction X and the second horizontal direction Y, and the first lower electrodes 114W correspond one-to-one to the intermediate vias 160, that is, each first lower electrode 114W is connected to one second gate 110R.

[0084] When the second gate 110R fills the lower through-hole 149R, the lower surface of the first lower electrode 114W is in direct contact with the upper surface of the second gate 110R, thereby realizing a direct connection between the first lower electrode 114W and the second gate 110R. Here, the first lower electrode 114W and the second gate 110R may be integrally formed, but are not limited to this. The second gate 110R and the first lower electrode 114W may be manufactured separately, that is, the second gate 110R is manufactured first, and then the first lower electrode 114W is manufactured. It should be understood that the first lower electrode 114W and the second gate 110R may be manufactured using the same conductive material, but are not limited to this. They may be manufactured using different conductive materials, and this should be determined according to specific circumstances.

[0085] When the portion of the second gate 110R located within the lower through-hole 149R is U-shaped and the lower through-hole 149R is filled with the lower conductive filling 115R, the lower surface of the first lower electrode 114W directly contacts the upper surface of the lower conductive filling 115R, thereby realizing an indirect connection with the second electrode through the lower conductive filling 115R. Here, the first lower electrode 114W may be integrally formed with the lower conductive filling 115R, but is not limited to this. The lower conductive filling 115R and the first lower electrode 114W may be manufactured separately, that is, the lower conductive filling 115R may be manufactured first, and then the first lower electrode 114W may be manufactured. Furthermore, the first lower electrode 114W and the lower conductive filling 115R may be manufactured using the same conductive material, but is not limited to this. They may be manufactured using different conductive materials, and this can be determined according to specific circumstances.

[0086] For example, when the first lower electrode 114W and the second gate 110R are integrally formed, or when the first lower electrode 114W and the lower conductive filling 115R are integrally formed, the intermediate partition insulating layer 16 may be selected as an integrally formed entire layer structure. For example, after the first lower electrode 114W is integrally formed with the second gate 110R or the lower conductive filling 115R, step S206 may specifically include first forming an intermediate partition insulating thin film that completely covers the lower partition insulating layer 142R, the second gate 110R (or the lower conductive filling 115R) and the first lower electrode 114W, and then removing the entire portion of the intermediate partition insulating thin film that is higher than the upper surface of the first lower electrode 114W to form the intermediate partition insulating layer 16, and the upper surface of this intermediate partition insulating layer 16 may be flush with the upper surface of the first lower electrode 114W.

[0087] In addition, when the first bottom electrode 114W is fabricated separately from the second gate 110R or the lower conductive filling 115R, the intermediate partition insulating film layer 16 may be an integrally formed whole layer structure. For example, after the second gate 110R or the lower conductive filling 115R is formed and before the first bottom electrode 114W is formed, step S206 may be performed to completely cover the lower partition insulating film layer 142R and the second gate 110R (or the lower conductive filling 115R). The method may include a step of first forming an intermediate partition insulating thin film, and then removing a portion of the intermediate partition insulating thin film that is higher than the top surface of the second gate 110R (or the lower conductive filling 115R) to form an intermediate partition insulating film layer 16 including the intermediate via 160, and then performing step S2081. However, this is not limited thereto. If the first lower electrode 114W is manufactured separately from the second gate 110R or the lower conductive filling 115R, the intermediate partition insulating film layer 16 may be formed. The partition insulating layer 16 may be manufactured in two layers. For example, after forming the second gate 110R or the lower conductive filling portion 115R, first a first intermediate insulating thin film is formed that completely covers the lower partition insulating layer 142R and the second gate 110R (or the lower conductive filling portion 115R). Then, the entire portion of the first intermediate insulating thin film that is higher than the upper surface of the second gate 110R (or the lower conductive filling portion 115R) is removed to form a first intermediate insulating layer. This first intermediate insulating layer covers the area on the upper surface of the lower partition insulating layer 142R that is not covered by the read transistor 11R. Then, a second intermediate insulating thin film is formed that completely covers the second intermediate insulating layer and the second gate 110R (or the lower conductive filling portion 115R). Then, a hole is drilled in the second intermediate insulating thin film to form a second intermediate insulating layer including an intermediate via. This second intermediate insulating film layer and the first intermediate insulating film layer together constitute the intermediate partition insulating layer 16.

[0088] In addition, the manufacturing step of the second intermediate insulating film layer may be performed after the step of manufacturing the first lower electrode 114W, or may be performed before the step of manufacturing the first lower electrode 114W, or may be decided in some cases, and explanation will be omitted here.

[0089] In step S2082, as shown in Figures 26 and 27, a second upper interlayer dielectric layer 174W, an upper sacrificial insulating film layer 171W and a first upper interlayer dielectric layer 173W are sequentially stacked on the upper surfaces of the intermediate partition insulating film layer 16 and the first lower electrode 114W.

[0090] In step S2083, the first upper inter-layer dielectric layer 173W is formed with a plurality of write bit lines 175W arranged side by side at intervals in the second horizontal direction Y and extending in the first horizontal direction X, and first lower partition insulating portions 176W located between adjacent write bit lines 175W. As shown in FIGS. 26 and 27, in this embodiment, the first lower partition insulating portions 176W can insulate the adjacent write bit lines 175W from each other. Here, the write bit lines 175W are formed on the first upper inter-layer dielectric layer 173W before the first lower partition insulating portions 176W are formed. However, this is not limited to this, and the first lower partition insulating portions 176W may be formed first, and then the plurality of write bit lines 175W may be formed.

[0091] In an embodiment of the present disclosure, the write bit line 175W may include a first upper electrode 113, and the orthogonal projection of the first upper electrode 113 onto the semiconductor substrate 10 has an overlapping area with the orthogonal projection of the first lower electrode 114W onto the semiconductor substrate 10.

[0092] In step S2084, as shown in FIGS. 26 and 27, an upper partition insulating film layer 172W is formed to entirely cover the write bit line 175W and the first lower partition insulating portion 176W.

[0093] In some other embodiments, the upper stacked film layer may not include the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W, depending on specific circumstances.

[0094] In step S210, an upper through-hole 177W is formed penetrating at least the upper partition insulating layer 172W, the first upper electrode 113W and the upper sacrificial insulating layer 171W, and as shown in FIG. 28, the first lower electrode 114W is exposed through the upper through-hole 177W, that is, the upper through-hole 177W may be opened in the area where the first upper electrode 113W and the first lower electrode 114W correspond to and overlap with each other.

[0095] For example, the orthogonal projections of the upper through-hole 177W and the lower through-hole 149R onto the semiconductor substrate 10 can overlap so that the write transistor 11W and the read transistor 11R of the memory cell overlap as much as possible in the vertical direction Z, thereby ensuring the performance of the memory cell and reducing the horizontal area occupied by the memory cell, thereby allowing more memory cells to be placed within a unit area and improving the storage density of the memory.

[0096] In some embodiments, as shown in FIG. 28, when the upper stacked film layer further includes a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, the upper through hole 177W may further penetrate the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W.

[0097] For example, as shown in FIG. 28, the orthogonal projection of the upper through-hole 177W onto the semiconductor substrate 10 can completely cover the orthogonal projection of the first lower electrode 114W onto the semiconductor substrate 10. In this case, the lower surface of the upper through-hole 177W extends exactly up to the upper surface of the first lower electrode 114W, thereby preventing subsequent etching from being prone to defects due to the difference in material between the first lower electrode 114W and the intermediate partition insulating film layer 16.

[0098] In addition, the orthogonal projection of the upper through-hole 177W onto the semiconductor substrate 10 may be located within the orthogonal projection of the first lower electrode 114W onto the semiconductor substrate 10. In this case, the lower surface of the upper through-hole 177W may extend into the interior of the first lower electrode 114W. In this way, the exposed area of ​​the first lower electrode 114W can be increased, thereby increasing the contact area with the subsequent semiconductor channel 112. Furthermore, while ensuring that the first lower electrode 114W is exposed, the etching accuracy can be reduced and the etching cost can be reduced. However, it should be understood that the lower surface of the upper through-hole 177W is not limited to extending into the first lower electrode 114W, but may extend just to the upper surface of the first lower electrode 114W.

[0099] In step S212, as shown in FIG. 29, a first semiconductor channel 112W, a first gate dielectric 111W, and a first gate 110W are sequentially formed in the upper through-hole 177W to form a write transistor 11W, where the first oxidation target region of the first semiconductor channel 112W corresponds to the upper sacrificial insulating film layer 171W, i.e., the first oxidation target region of the first semiconductor channel 112W is located in a position surrounded by the upper sacrificial insulating film layer 171W.

[0100] In addition, if the upper stacked film layer includes a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, after performing step S212, as shown in FIG. 29, the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W may both be arranged to surround the first effective semiconductor channel. Specifically, the first upper interlayer dielectric layer 173W may surround a region located above the first oxidation target region in the first effective semiconductor channel, and the second upper interlayer dielectric layer 174W may surround a region located below the first oxidation target region in the first effective semiconductor channel.

[0101] In some embodiments of the present disclosure, step S212 may include at least step S2121 and step S2122.

[0102] In step S2121, after the upper through-hole 177W is formed, an upper semiconductor thin film layer 181W, an upper gate dielectric thin film layer 182W, and an upper gate thin film layer 183W are sequentially deposited on the upper stacked film layer, and as shown in FIG. 30, the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W all completely cover the upper stacked film layer, that is, the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W may be deposited on the upper surface of the upper partition insulating film layer 172W and in the upper through-hole 177W.

[0103] Here, as shown in FIG. 31, the portions of the upper semiconductor thin film layer 181W and the upper gate dielectric thin film layer 182W located within the upper through-hole 177W may be U-shaped, and the portion of the upper gate thin film layer 183W located within the upper through-hole 177W may be U-shaped, or as shown in FIG. 30, the upper gate thin film layer 183W may fill the upper through-hole 177W.

[0104] For example, the material of the upper semiconductor thin film layer 181W may be a semiconductor material such as, but not limited to, IGZO, or other semiconductor materials; the material of the upper gate dielectric thin film layer 182W may be a high-dielectric insulating material such as, but not limited to, silicon oxide, or other low-dielectric material; and the material of the upper gate thin film layer 183W may be a conductive material with good gate control ability such as, but not limited to, ZnO (zinc oxide), ITO (indium tin oxide), IZO (indium zinc oxide), or other conductive materials.

[0105] In step S2122, the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W and the upper gate thin film layer 183W are etched and removed in portions that exceed the target distance value from the hole boundary of the upper through-hole 177W, thereby forming a first semiconductor channel 112W, a first gate dielectric 111W and a first gate 110W in the upper through-hole 177W, thereby forming the write transistor 11W.

[0106] In the embodiment of the present disclosure, the obtained target distance value referred to in step S2122 may be 0, that is, the portions of the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W that exceed the boundary of the upper through-hole 177W are all etched and removed, but is not limited thereto. The obtained target distance value referred to in step S2122 may be greater than 0, but must be less than half the distance between adjacent upper through-holes 177W. In addition to the portions of the first semiconductor channel 112W, first gate dielectric 111W, and first gate 110W fabricated in this manner that are located within the upper through-hole 177W, they also have portions that extend away from the hole axis and are mounted on the upper surface of the upper partition insulating film layer 172W, as shown in FIG. 29, when forming a plurality of write transistors 11W arranged in an array in this manner, the difficulty of etching can be reduced and product quality can be ensured.

[0107] Here, if the portion of the first gate 110W located within the upper through-hole 177W is U-shaped, as shown in FIG. 29, the write transistor 11W of this embodiment may further include an upper conductive filling portion 115W that fills at least the upper through-hole 177W, and in this embodiment, the upper conductive filling portion 115W may be made of a conductive material that has good conductive performance and is cheaper than the first gate 110W.

[0108] For example, in this embodiment, the upper conductive filling 115W may be columnar, and the upper surface of the columnar upper conductive filling 115W may be flush with the upper surface of the first gate 110W, but is not limited to this. The upper conductive filling 115W may be T-shaped, and as shown in FIG. 29, the T-shaped upper conductive filling 115W may fill the upper through-hole 177W and cover the upper surface of the first gate 110W, and the upper surface of this first gate 110W may be the surface of the first gate 110W that is farthest from the semiconductor substrate 10.

[0109] In some embodiments, the manufacturing method of the upper conductive filling 115W may include the following steps: in step S2121, after depositing the upper gate thin film layer 183W, as shown in FIG. 31 , further deposit an upper conductive filling thin film layer 184W to completely cover the upper gate thin film layer 183W; then, perform step S2112 to etch away the portions of the upper semiconductor thin film layer 181W, the upper gate dielectric thin film layer 182W, and the upper gate thin film layer 183W that are beyond a target distance value from the hole boundary, and etch away the portions of the upper conductive filling thin film layer 184W that are beyond the target distance value from the hole boundary, thereby forming a T-shaped upper conductive filling; here, if a pillar-shaped upper conductive filling is desired, after performing step S2112, the portion of the T-shaped upper conductive filling that is beyond the top surface of the first gate 110W may be removed to form a pillar-shaped upper conductive filling.

[0110] It should be noted that the pillar-shaped upper conductive filling portion is not limited to being manufactured in the above manner. For example, after performing step S2122 to form the first gate 110W, the first gate dielectric 111W, and the first semiconductor channel 112W of the write transistor 11W, an upper conductive filling thin-film layer 184W is first deposited, and this upper conductive filling thin-film layer 184W not only completely covers the structural layer located below it but also fills the upper through-holes 177W. Then, a patterning process is performed on the upper conductive filling thin-film layer 184W, thereby forming a filled pillar-shaped upper conductive filling portion in each upper through-hole 177W.

[0111] In some embodiments of the present disclosure, after forming the write transistor 11W, step S212 may further include step S2131, step S2132, and step S2133.

[0112] In step S2131, a filled partition insulating portion 178W is formed on the upper surface of the upper partition insulating film layer 172W. As shown in FIG. 32, the filled partition insulating portion 178W can cover the upper surface of the upper partition insulating film layer 172W that is not covered by the write transistor 11W. Furthermore, when the first gate 110W itself fills the upper through-hole 177W or a manufactured pillar-shaped upper conductive filling fills the upper through-hole 177W, the upper surface of the filled partition insulating portion 178W formed here can be flush with the upper surfaces of the first gate 110W and the pillar-shaped upper conductive filling. When the manufactured T-shaped upper conductive filling fills the upper through-hole 177W, the upper surface of the filled partition insulating portion 178W formed here can be flush with the T-shaped upper conductive filling, thereby ensuring that the subsequent write word line is formed flush.

[0113] In step S2132, as shown in Figures 33 and 34, a plurality of write word lines 179W are formed, arranged side by side at intervals in the first horizontal direction X and extending in the second horizontal direction Y, and first upper partition insulating portions 180W are formed, each located between adjacent write word lines 179W.

[0114] Here, the write word line 179W may be connected to the first gates 110W of the plurality of write transistors 11W arranged side by side at intervals in the second horizontal direction Y. Here, when the first gate 110W itself fills the upper through-hole 177W, the write word line 179W may be in direct contact with the first gate 110W, thereby realizing a direct connection between the two; when the upper through-hole 177W is filled by a T-shaped upper conductive filling, the write word line 179W may be in direct contact with an upper surface of the T-shaped upper conductive filling, thereby realizing an indirect connection with the first gate 110W via the T-shaped upper conductive filling; and when the upper through-hole 177W is filled by a pillar-shaped upper conductive filling, the write word line 179W may be in direct contact with the first gate 110W and the upper surface of the pillar-shaped upper conductive filling at the same time, thereby realizing a connection between the three.

[0115] In step S2133, as shown in FIG. 35, a cap insulating layer 19 is formed to cover the entire surface, and the cap insulating layer 19 covers the write word line 179W and the filling partition insulating portion 178W, and the upper surface of the cap insulating layer 19 is a plane parallel or approximately parallel to the semiconductor substrate 10.

[0116] In this embodiment, adjacent write word lines 179W are insulated from each other by a first upper partition insulating portion 180W. Specifically, the write word lines 179W may be formed before the first upper partition insulating portion 180W, but this is not limited to this. The first upper partition insulating portion 180W may be formed first, and then multiple write word lines 179W may be formed.

[0117] In some embodiments, when the write word line 179W is formed first and then the first upper partition insulating portion 180W is formed, the first upper partition insulating portion 180W may be integrally formed with the cap insulating layer 19, but this is not limited thereto, and the first upper partition insulating portion 180W may be manufactured separately from the cap insulating layer 19, that is, the first upper partition insulating portion 180W may be formed first and then the cap insulating layer 19 may be manufactured.

[0118] In another embodiment, when the first upper partition insulating portion 180W is formed first and then the write word line 179W is formed, the first upper partition insulating portion 180W may be integrally formed with the filling partition insulating portion 178W, but is not limited to this, and the first upper partition insulating portion 180W may be manufactured separately from the filling partition insulating portion 178W, that is, the filling partition insulating portion 178W is formed first and then the first upper partition insulating portion 180W is manufactured.

[0119] In addition, the write word line 179W in the present disclosure is not limited to being formed after the first gate 110W or the upper conductive filling 115W, and may be integrally formed with the first gate 110W or the upper conductive filling 115W, or may be determined according to specific circumstances, and description thereof will be omitted here. In addition, in the present disclosure, the write bit line 175W is not limited to extending in the first horizontal direction X, and the write word line 179W is extended in the second horizontal direction Y, and the write bit line 175W may extend in the second horizontal direction Y, and the write word line 179W may extend in the first horizontal direction X, as long as the extending directions of the write word line 179W and the write bit line 175W intersect.

[0120] In step S214, after forming the write transistor 11W, the second portion 121 of the gas passage 12 is formed. The orthogonal projection of the second portion 121 onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the lower through-hole 149R and the upper through-hole 177W onto the semiconductor substrate 10. As shown in FIGS. 36 and 37, the second portion 121 penetrates at least the upper partition insulating film layer 172W, the upper sacrificial insulating film layer 171W, the middle partition insulating film layer 16, and the lower partition insulating film layer 142R to expose the lower sacrificial insulating film layer 141R. The second portion 121 of the gas passage 12 may extend along the vertical direction Z into the interior of the lower sacrificial insulating layer 141R, thereby reducing the difficulty of the process and increasing the area of ​​the lower sacrificial insulating layer 141R that is exposed, thereby accelerating the rate at which the lower sacrificial insulating layer 141R is subsequently etched and removed, but is not limited to this. The second portion 121 of the gas passage 12 may extend just to the top surface of the lower sacrificial insulating layer 141R, or may penetrate the lower sacrificial insulating layer 141R.

[0121] In some embodiments, as shown in FIG. 36 , the second portion 121 of the gas passage 12 may be manufactured after the cap insulating layer 19 is formed. In this case, the “upper surface of the memory cell” in the above-mentioned “second portion 121 extends vertically upward to the upper surface of the memory cell” refers to the upper surface of the cap insulating layer 19. That is, after the cap insulating layer 19 is formed, hole etching is performed vertically downward from the upper surface of the cap insulating layer 19 until etching reaches the lower sacrificial insulating film layer 141R. By manufacturing the second portion 121 of the gas passage 12 after the formation of the cap insulating layer 19 is completed, the cap insulating layer 19 is used to protect the write transistor 11W and the write word line 179W, and it is possible to avoid damaging the write transistor 11W and the write word line 179W during subsequent hole etching.

[0122] In some other embodiments, the second portion 121 of the gas passage 12 may be fabricated after the write transistor 11W (or the upper conductive filling 115W) is formed and before the write word line 179W is formed. In this case, the write transistor 11W can be protected. As shown in FIG. 37, after the write transistor 11W (or the upper conductive filling 115W) is formed, a first upper partition insulating thin film layer 180 covering the entire surface may be formed. In this case, the "upper surface of the memory cell" in the above description of "the second portion 121 extending vertically upward to the upper surface of the memory cell" may be the first upper partition insulating thin film layer 180. This refers to the upper surface of the insulating thin film layer 180, and then vertically downward hole etching is performed from the upper surface of the first upper partition insulating thin film layer 180 to the lower sacrificial insulating film layer 141R, and then subsequent steps are performed, in which the formation of the first oxidation channel 1120W and the second oxidation channel 1120R is completed and the second part 121 of the gas passage 12 is partially or completely filled with insulating material, and then the first upper partition insulating thin film layer 180 is etched to form the first upper partition insulating part 180W, and then the write word line 179W and the cap insulating layer 19, etc. are formed.

[0123] In some embodiments, as shown in Figures 36 and 37, when the lower stacked film layer includes a first lower inter-layer dielectric layer 143R and a second lower inter-layer dielectric layer 144R and the upper stacked film layer includes a first upper inter-layer dielectric layer 173W and a second upper inter-layer dielectric layer 174W, the second portion 121 of the gas passage 12 may further penetrate the first upper inter-layer dielectric layer 173W, the second upper inter-layer dielectric layer 174W and the first lower inter-layer dielectric layer 143R.

[0124] In some embodiments, as shown in FIG. 38 , the orthogonal projection of the second portion 121 of the gas passage 12 onto the semiconductor substrate 10 does not overlap with the orthogonal projections of the write word line 179W, the write bit line 175W, the second down signal line 145R, and the second up signal line 147R onto the semiconductor substrate 10, thereby ensuring the performance of the write word line 179W, the write bit line 175W, the second down signal line 145R, and the second up signal line 147R. Here, as shown in FIG. 36, the orthogonal projection of the second portion 121 of the gas passage 12 onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the write word line 179W, the write bit line 175W, the second down signal line 145R, and the second up signal line 147R onto the semiconductor substrate 10, so the second portion 121 of the gas passage 12 may penetrate the first upper partition insulating portion 180W, the first lower partition insulating portion 176W, and the second upper partition insulating portion 148R in addition to penetrating the above-mentioned film layers.

[0125] In some embodiments, as shown in FIG. 38, the second portion 121 of the gas passage 12 may be provided in plurality, and the outer periphery of each memory cell C may be surrounded by a plurality of second portions 121, which not only increases the etching rate of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, but also ensures uniformity of the etching.

[0126] In step S216, as shown in FIG. 39, an etching agent is introduced into the second portion 121 to remove the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, thereby forming an upper first portion 120W that is arranged to surround the region to be first oxidized and a lower first portion 120R that is arranged to surround the region to be second oxidized.

[0127] Here, in the process of removing the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R using an etching agent, the first lower interlayer dielectric layer 143R, the second lower interlayer dielectric layer 144R, the first upper interlayer dielectric layer 173W, and the second upper interlayer dielectric layer 174W are retained, i.e., are not etched or are etched very little by the etching agent.

[0128] For example, the etching agent in this embodiment may be a liquid, but is not limited to this, and may also be a gas. Here, when the insulating material of the interlayer dielectric layer, partition insulating layer, and partition insulating portion mentioned above is silicon oxide, and the insulating material of the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R is silicon nitride, silicon oxynitride, silicon carbonitride, or the like, this embodiment may use chlorine gas or liquid phosphoric acid to completely etch the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R, but is not limited to this. This embodiment ensures that the etching agent etches and removes the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R while having little or no effect on the interlayer dielectric layer, partition insulating layer, and partition insulating portion mentioned above. As long as the interlayer dielectric layer, partition insulating layer, and partition insulating portion mentioned above are preserved, other etching agents may be used to etch the upper sacrificial insulating layer 171W and the lower sacrificial insulating layer 141R.

[0129] [Embodiment 2] In an embodiment of the present disclosure, the first oxide channel 1120W of the write transistor 11W and the second oxide channel 1120R of the read transistor 11R may be fabricated respectively, specifically, first form the second oxide channel 1120R of the read transistor 11R, and then form the first oxide channel 1120W of the write transistor 11W, thereby ensuring the quality of the first oxide channel 1120W and the second oxide channel 1120R.

[0130] Here, when the first oxidation channel 1120W of the write transistor 11W and the second oxidation channel 1120R of the read transistor 11R are formed by separate manufacturing processes, the above-mentioned gas passage 12 needs to include two passages manufactured in succession, that is, the gas passage 12 can include a first gas passage 12W shown in FIG. 41 and a second gas passage 12R shown in FIG. 40, where the first gas passage 12W and the second gas passage 12R are manufactured separately, and the second gas passage 12R is manufactured before the first gas passage 12W.

[0131] Here, as shown in FIG. 40, the second gas passage 12R includes a first portion 120 arranged around the region to be second oxidized, and a second portion 121 that is connected to the first portion 120 of the second gas passage 12 and extends vertically upward to the upper surface of the read transistor 11R, and as shown in FIG. 41, the first gas passage 12W includes a first portion 120 arranged around the region to be first oxidized, and a second portion 121 that is connected to the first portion 120 of the first gas passage 12W and extends vertically upward to the upper surface of the memory cell.

[0132] Based on this, the manufacturing method of this embodiment includes the following steps. As shown in FIG. 42, first, a second oxidation target region of the second effective semiconductor channel of the read transistor 11R is oxidized to form a second oxidation channel 1120R. After the second oxidation channel 1120R is formed, the second gas passage 12R is filled with an insulating material to form a second filler 13R. As shown in FIG. 43, the upper surface of the second filler 13R is flush with the upper surface of the second gas passage 12R, thereby ensuring the flatness of the upper surface of the structural layer. As shown in FIG. 44, a first oxidation target region of the first effective semiconductor channel of the write transistor 11W is oxidized to form a first oxidation channel 1120W. As shown in FIG. 45, after the first oxidation channel 1120W is formed, the first gas passage 12W is filled with an insulating material to form a first filler 13. The upper surface of the first filler 13 is flush with the upper surface of the first gas passage 12W, which ensures the flatness of the upper surface of the memory array structure and is advantageous for the fabrication of subsequent structural layers.

[0133] In a specific embodiment of the present disclosure, the manufacturing method of the first gas passage 12W may include steps S300, S302, S304, S306, S308, and S310.

[0134] Here, for step S300, the explanation of step S200 described above can be referred to, for step S302, the explanation of step S202 described above can be referred to, and for step S304, the explanation of step S204 described above can be referred to. Here, detailed explanations of the contents of step S300, step S302, and step S304 will be omitted.

[0135] In step S306, an intermediate partition insulating film layer 16 is formed on the lower laminated film layer, and the intermediate partition insulating film layer 16 covers at least the region on the upper surface of the lower partition insulating film layer 142R that is not covered by the read transistor 11R. Here, the intermediate partition insulating film layer 16 formed in step S306 completely covers the read transistor 11R, thereby protecting the read transistor 11R. Note that when a lower conductive filling 115R is formed in the read transistor 11R, the intermediate partition insulating film layer 16 formed in step S306 The insulating film layer 16 may completely cover the read transistor 11 and the lower conductive filling portion 115R, thereby protecting the read transistor 11 and the lower conductive filling portion 115R at the same time, but is not limited to this. At least a part of the second gate 110R or the lower conductive filling portion 115R may not be shielded by the intermediate partition insulating film layer 16, thereby facilitating the subsequent direct connection, indirect connection or integral molding of the first lower electrode 114W and the second gate 110R, and the specific details are determined according to actual circumstances.

[0136] In step S308, the second portion 121 of the second gas passage 12R is formed, and as shown in FIG. 46, the orthogonal projections of the second portion 121 of the second gas passage 12R and the lower through-hole 149R onto the semiconductor substrate 10 do not overlap, and the second portion 121 of the second gas passage 12R penetrates at least the middle partition insulating film layer 16 and the lower partition insulating film layer 142R to expose the lower sacrificial insulating film layer 141R.

[0137] Here, the orthogonal projection of the second portion 121 of the second gas passage 12R onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the read word line and the read bit line onto the semiconductor substrate 10, thereby ensuring the performance of the read word line and the read bit line. Since the orthogonal projection of the second portion 121 of the second gas passage 12R onto the semiconductor substrate 10 does not overlap with the orthogonal projection of the read word line and the read bit line onto the semiconductor substrate 10, the second portion 121 of the second gas passage 12R may further penetrate the second upper partition insulating portion 148R in addition to penetrating the above-mentioned film layers. Note that, when the lower stacked film layer includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, the second portion 121 of the second gas passage 12R may further penetrate the first lower interlayer dielectric layer 143R.

[0138] As shown in FIG. 41, the second portion 121 of the second gas passage 12R extends vertically upward to the upper surface of the readout transistor 11R, and the "upper surface of the readout transistor 11R" here may be understood as the upper surface of the structural layer in which the readout transistor 11R is located. Here, the structural layer in which the readout transistor 11R is located includes a lower stacked film layer and an intermediate partition insulating film layer 16 located above the lower stacked film layer. Therefore, the "upper surface of the readout transistor 11R" may be understood as the upper surface of the intermediate partition insulating film layer 16. In other words, the second portion 121 of the second gas passage 12R may extend vertically downward from the upper surface of the intermediate partition insulating film layer 16 to the lower sacrificial insulating film layer 141R.

[0139] In some embodiments, the second portion 121 of the second gas passage 12R may extend along the vertical direction Z into the lower sacrificial insulating layer 141R, thereby reducing the difficulty of the process and increasing the area of ​​the lower sacrificial insulating layer 141R exposed, thereby accelerating the rate at which the lower sacrificial insulating layer 141R is subsequently etched and removed. However, this is not limited thereto, and as shown in FIG. 46, the second portion 121 of the second gas passage 12R may extend just to the top surface of the lower sacrificial insulating layer 141R or may penetrate the lower sacrificial insulating layer 141R.

[0140] In some embodiments, the second portion 121 of the second gas passage 12R may be provided in plurality, and the periphery of each read transistor 11R may be surrounded by the second portion 121 of the second gas passage 12R in plurality, which not only increases the etching rate of the lower sacrificial insulating film layer 141R but also ensures uniformity of the etching.

[0141] 42, in step S310, an etching agent is introduced into the second portion 121 of the second gas passage 12R to remove the lower sacrificial insulating film layer 141R, thereby forming the first portion 120 of the second gas passage 12R that is provided so as to surround the region to be subjected to the second oxidation. Here, the limitations on the etching agent can be found in the above description, and therefore will not be described here.

[0142] Here, after performing step S310, an oxidizing gas is introduced through the second portion 121 of the second gas passage 12R, and the oxidizing gas acts on the second oxidation target region through the first portion 120 of the second gas passage 12R, thereby performing an oxidation process on the second oxidation target region and forming a second oxidation channel 1120R. After forming the second oxidation channel 1120R, the second gas passage 12R is further filled with an insulating material to form a second filler 13R. As shown in FIG. 43, the upper surface of this second filler 13R is flush with the upper surface of the intermediate partition insulating film layer 16, which facilitates the subsequent formation of the write transistor 11W and the structural layer in which it is located. In some embodiments, when filling the second gas passage 12R with the insulating material, a complete filling method may be used, i.e., as shown in Fig. 43, the formed second filler 13R completely fills the first portion 120 and the second portion 121 of the second gas passage 12R, thereby ensuring structural stability. However, without being limited thereto, in other embodiments, as shown in Fig. 47, the second gas passage 12R may be partially filled with the insulating material, i.e., the formed second filler 13R may partially or completely fill the second portion 121 of the second gas passage 12R. For example, the second filler 13R may be formed in the second portion 121 of the second gas passage 12R by filling the second portion 121 of the second gas passage 12R with the insulating material using a quick-filling method.

[0143] When the second filler 13R partially or completely fills the second portion 121 of the second gas passage 12R, the area in the second gas passage 12R other than the area filled by the second filler 13R is a void area. Specifically, as shown in FIG. 47, at least the first portion 120 in the second gas passage 12R may be a void area that is not filled by the second filler 13R, thereby reducing the parasitic capacitance between the second upper electrode 113R and the second lower electrode 114R in the read transistor 11R.

[0144] In a specific embodiment of the present disclosure, the manufacturing method of the first gas passage 12W may include step S400, step S402, step S404, step S406, and step S408.

[0145] Here, for step S400, please refer to the explanation of step S208 mentioned above, for step S402, please refer to the explanation of step S210 mentioned above, and for step S404, please refer to the explanation of step S212 mentioned above, and the contents of steps S400, S402, and S404 will not be explained in detail here.

[0146] In step S406, after forming the write transistor 11W, the second portion 121 of the first gas passage 12W is formed, and as shown in FIG. 48, the orthogonal projections of the second portion 121 of the first gas passage 12W and the upper through-hole 177W onto the semiconductor substrate 10 do not overlap, and the second portion 121 of the first gas passage 12W penetrates at least the upper partition insulating film layer 172W to expose the upper sacrificial insulating film layer 171W.

[0147] Here, the second portion 121 of the first gas passage 12W may extend into the upper sacrificial insulating film 171W along the vertical direction Z, thereby reducing the difficulty of the process and increasing the area of ​​the upper sacrificial insulating film 171W exposed, thereby accelerating the rate at which the upper sacrificial insulating film 171W is subsequently etched and removed. However, this is not limited to this, and as shown in FIG. 48, the second portion 121 of the first gas passage 12W may extend just to the top surface of the upper sacrificial insulating film or may penetrate the upper sacrificial insulating film.

[0148] In addition, multiple second portions 121 of the first gas passage 12W may be provided, and the outer periphery of each write transistor 11W may be surrounded by multiple second portions 121 of the first gas passage 12W, which not only increases the etching rate of the upper sacrificial insulating film layer 171W but also ensures uniformity of the etching.

[0149] In some embodiments, the manufacturing method of the first gas passage 12W may further include step S4051, step S4052, and step S4053, in which step S4051 may refer to the description of step S2131, step S4052 may refer to the description of step S2132, and step S4053 may refer to the description of step S2133, and the contents of steps S4051, S4052, and S4053 will not be described in detail here.

[0150] Here, the orthogonal projection of the second portion 121 of the first gas passage 12W onto the semiconductor substrate 10 may not overlap with the orthogonal projection of the write word line 179W and the write bit line 175W onto the semiconductor substrate 10, thereby ensuring the performance of the write word line 179W and the write bit line 175W. Since it does not overlap with the orthogonal projection onto the conductive substrate 10, the second portion 121 of the first gas passage 12W may penetrate not only the above-mentioned film layers but also the first upper partition insulating portion 180W and the first lower partition insulating portion 176W, and when the upper stacked film layer includes the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W, the second portion 121 of the first gas passage 12W may further penetrate the first upper interlayer dielectric layer 173W. In addition, the second portion 121 of the first gas passage 12W extends vertically upward to the upper surface of the memory cell, and here, the "upper surface of the memory cell" may be understood as the upper surface of the cap insulating layer 19. That is, after the cap insulating layer 19 is formed, hole etching is performed vertically downward from the upper surface of the cap insulating layer 19 to etching into the upper sacrificial insulating film layer 171W, as shown in FIG. 49. By manufacturing the second portion 121 of the first gas passage 12W after forming the cap insulating layer 19, the cap insulating layer 19 can be used to protect the write transistor 11W and the write word line 179W, thereby avoiding damage to the write transistor 11W and the write word line 179W when performing hole etching later. However, without being limited thereto, the second portion 121 of the first gas channel 12W may be manufactured after forming the write transistor 11W (or the upper conductive filling portion 115W) and before forming the write word line 179W. In this case, protection of the write transistor 11W is realized. After forming the write transistor 11W (or the upper conductive filling portion 115W), the first upper partition insulating thin film layer 180 may be formed to cover the entire surface. In this case, the above-mentioned "upper surface of the memory cell" refers to the first upper partition insulating thin film layer 180. As shown in FIG. 48, hole etching is performed vertically downward from the top surface of the first upper partition insulating thin film layer 180 until the upper sacrificial insulating film layer 171W is etched, and then subsequent steps are performed, in which the formation of the first oxidation channel 1120W is completed and the first gas passage 12W is filled with an insulating material, and then the first upper partition insulating thin film layer 180 is etched to form the first upper partition insulating portion 180W, and then the write word line 179W, the cap insulating layer 19, etc. are formed.

[0151] In step S408, an etching agent is introduced into the second portion 121 of the first gas passage 12W to remove the upper sacrificial insulating film layer 171W and form the first portion 120 of the first gas passage 12W, which is arranged to surround the first oxidation target area, as shown in FIG. 50. Here, the limitations on the etching agent can be referred to the above description, and the explanation will be omitted here.

[0152] After step S408, an oxidizing gas is introduced through the second portion 121 of the first gas passage 12W. The oxidizing gas acts on the first oxidation target region through the first portion 120 of the first gas passage 12W, thereby oxidizing the first oxidation target region and forming a first oxidation channel 1120W. After forming the first oxidation channel 1120W, the first gas passage 12W is further filled with an insulating material to form a first filler 13W. As shown in FIG. 51, the top surface of the first filler 13W may be flush with the top surface of the memory cell to facilitate the formation of subsequent structural layers. In some embodiments, when filling the first gas passage 12W with an insulating material, a complete filling method may be used, as shown in FIG. 45. That is, the formed first filler 13W can completely fill the first portion 120 and the second portion 121 of the first gas passage 12W, ensuring structural stability. However, this is not limiting, and in other embodiments, a portion of the first gas passage 12W may be filled with an insulating material. That is, as shown in FIG. 51, the formed first filler 13W may partially or completely fill the second portion 121 of the first gas passage 12W. For example, the first filler 13W may be formed in the second portion 121 of the first gas passage 12W by quickly filling the second portion 121 of the first gas passage 12W with an insulating material using a sealing method.

[0153] When the first filler 13W partially or completely fills the second portion 121 of the first gas passage 12W, the area in the first gas passage 12W other than the area filled by the first filler 13W is a void area. Specifically, as shown in FIG. 51, at least the first portion 120 in the first gas passage 12W is a void area that is not filled by the first filler 13W, thereby reducing the parasitic capacitance between the first upper electrode 113W and the first lower electrode 114W in the write transistor 11W.

[0154] An embodiment of the present disclosure provides a memory, which includes a semiconductor substrate 10 and at least one memory cell. The memory cell is formed on the semiconductor substrate 10, and the memory cell includes at least one transistor 11, each transistor 11 including a gate 110, a gate dielectric 111, a semiconductor channel 112, an upper electrode 113, and a lower electrode 114, the semiconductor channel 112 surrounding at least the outer periphery of the gate 110, the gate dielectric 111 being formed between the semiconductor channel 112 and the gate 110, the upper electrode 113 and the lower electrode 114 both being located outside the semiconductor channel 112 and in contact with the semiconductor channel 112, the lower electrode 114 being provided below and insulated from the upper electrode 113, one of the upper electrode 113 and the lower electrode 114 being a source and the other being a drain.

[0155] Here, in the memory cell, as shown in Figure 8, Figure 9 or Figure 10, a portion of the effective semiconductor channel of at least one transistor 11 is formed into an oxidized channel by oxidation treatment, and the effective semiconductor channel is the portion of the semiconductor channel 112 located between the upper electrode 113 and the lower electrode 114, and neither the upper electrode 113 nor the lower electrode 114 contacts the oxidized channel.

[0156] It should be noted that the memory of the embodiments of the present disclosure may be manufactured by the manufacturing method described in any of the above-mentioned embodiments, and although not repeated here, is not limited to this, and the memory of the present embodiment may be formed by other manufacturing methods.

[0157] In an embodiment of the present disclosure, as shown in FIG. 8, FIG. 9 or FIG. 10, there are multiple memory cells, which are arranged in a memory array structure in a horizontal plane, and each memory cell includes two transistors 11, which are a read transistor 11R and a write transistor 11W, respectively. The write transistor 11W includes a first gate 110W, a first gate dielectric 111W, a first semiconductor channel 112W, a first upper electrode 113W, and a first lower electrode 114W. The read transistor 11R includes a second gate 110R, a second gate dielectric 111R, a second semiconductor channel 112R, a second upper electrode 113R, and a second lower electrode 114R. The write transistor 11W is located above the read transistor 11R, and the first lower electrode 114W and the second gate 110R are electrically connected. Here, a portion of the effective semiconductor channel 112 of the write transistor 11W and the read transistor 11R is formed into an oxide channel 1120 by an oxidation process.

[0158] 38, in the memory array structure, a plurality of memory cells are arranged in an array in a first horizontal direction X and a second horizontal direction Y, and the first horizontal direction X and the second horizontal direction Y intersect. For example, the first horizontal direction X and the second horizontal direction Y are perpendicular or approximately perpendicular.

[0159] 26, 27, 33, 34, and 38, the memory further includes a second down signal line 145R, a second up signal line 147R, a write word line 179W, and a write bit line 175W. The second down signal line 145R extends in a second horizontal direction Y. A plurality of second down signal lines 145R are provided and arranged side by side at intervals in the first horizontal direction X. Each second down signal line 145R is arranged in a row arranged side by side in the second horizontal direction Y. The second up signal line 147R is connected to the second lower electrodes 114 of the readout transistors 11R in one column, the second up signal line 147R extends in the first horizontal direction X, and a plurality of the second up signal lines 147R are provided and arranged side by side at intervals in the second horizontal direction Y, the second up signal line 147R is located on the side of the second down signal line 145R away from the semiconductor substrate 10, and each second up signal line 147R is connected to the second lower electrodes 114 of the readout transistors 11R in one column arranged side by side in the first horizontal direction X. The second upper electrode 113 of the second up signal line 147R is connected to the second upper electrode 113 of the second down signal line 145R, one of which is a read word line and the other is a read bit line, the write bit line 175W is formed on the side of the second up signal line 147R that is farther from the semiconductor substrate 10, and the write word line 179W is formed on the side of the write bit line 175W that is farther from the semiconductor substrate 10, and here, one of the write word line 179W and the write bit line 175W The write bit lines 175W extend in the first horizontal direction X and are provided at intervals in the second horizontal direction Y, and the other write word lines 179W extend in the second horizontal direction Y and are provided at intervals in the first horizontal direction X. Each write bit line 175W is connected to the first upper electrodes 113 of the write transistors 11W in a row arranged side by side in the extension direction, and each write word line 179W is connected to the first gates 110W of the write transistors 11W in a row arranged side by side in the extension direction.

[0160] In some embodiments, as shown in Figures 14 and 51, a portion of the first effective semiconductor channel 112 of the write transistor 11W is formed into a first oxide channel 1120W by an oxidation process, and a first void region is formed between the first upper electrode 113 and the first lower electrode 114, and the first void region is arranged to surround the first oxide channel 1120W.

[0161] Furthermore, as shown in Figures 14 and 51, a first interlayer dielectric layer 173W is formed between the first upper electrode 113 and the first gap region, and a second interlayer dielectric layer 174W is formed between the first lower electrode 114 and the first gap region, and both the first interlayer dielectric layer 173W and the second interlayer dielectric layer 174W are arranged to surround the first effective semiconductor channel 112 and do not contact the first oxide channel 1120W.

[0162] In some other embodiments, as shown in Figures 9, 10, 13 or 45, a portion of the first effective semiconductor channel 112 of the write transistor 11W is formed into a first oxidized channel 1120W by oxidation, and a first insulating layer is formed between the first upper electrode 113 and the first lower electrode 114. The first insulating layer is arranged to surround the first oxidized channel 1120W and is in contact with the lower surface of the first upper electrode 113 and the upper surface of the first lower electrode 114 without any gaps.

[0163] For example, the first insulating layer may be a composite film layer including first upper interlayer dielectric layer (173W), second upper interlayer dielectric layer (174W) and first filling material (13W).

[0164] In some embodiments, as shown in FIG. 14 or FIGS. 47 to 51, a portion of the second effective semiconductor channel 112 of the read transistor 11R is formed into a second oxide channel 1120R by an oxidation process, and a second gap region is formed between the second upper electrode 113 and the second lower electrode 114, and the second gap region is arranged to surround the second oxide channel 1120R.

[0165] Furthermore, a first lower interlayer dielectric layer 143R is formed between the second upper electrode 113 and the second gap region, and a second lower interlayer dielectric layer 144R is formed between the second lower electrode 114 and the second gap region, and both the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R are arranged to surround the second effective semiconductor channel 112 and do not contact the second oxide channel 1120R.

[0166] In another embodiment, as shown in FIG. 8, FIG. 10, FIG. 13 or FIG. 44, a portion of the second effective semiconductor channel 112 of the read transistor 11R is formed into a second oxide channel 1120R by oxidation, and a second insulating layer is formed between the second upper electrode 113 and the second lower electrode 114. The second insulating layer is arranged to surround the second oxide channel 1120R and is in contact with the lower surface of the second upper electrode 113 and the upper surface of the second lower electrode 114 without any gaps.

[0167] For example, the second insulating layer may be a composite film layer including a first lower inter-layer dielectric layer 143R, a second lower inter-layer dielectric layer 144R, and a second filler 13R.

[0168] Furthermore, the terms "first," "second," etc. are for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly specifying the number of the indicated technical features. Thus, a feature qualified as "first" or "second" can explicitly or implicitly include one or more of the feature. In the description of this application, "plurality" means two or more, unless otherwise specifically limited.

[0169] In the description herein, references to terms such as "some embodiments," "exemplary," and the like mean that the specific features, structures, materials, or characteristics described with reference to the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, general expressions using the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, if not mutually inconsistent, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described herein.

[0170] Although the embodiments of the present application have been shown and described above, the above embodiments are illustrative and should not be understood as limiting the present invention. Those skilled in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application. Any changes or modifications made based on the claims and specification of the present application should fall within the scope of the present application. [Explanation of symbols]

[0171] 10. Semiconductor substrate; 11, transistor, 110, gate, 111, gate dielectric, 112, semiconductor channel, 1120, oxide channel, 113, upper electrode, 114, lower electrode, 11W, write transistor; 110W, first gate; 111W, first gate dielectric; 112W, first semiconductor channel; 1120W, first oxide channel; 113W, first top electrode; 114W, first bottom electrode; 115W, top conductive fill; 11R, readout transistor; 110R, second gate; 111R, second gate dielectric; 112R, second semiconductor channel; 1120R, second oxide channel; 113R, second top electrode; 114R, second bottom electrode; 115R, bottom conductive fill; 12, gas passage, 12W, first gas passage, 12R, second gas passage, 120, first portion, 120W, upper first portion, 120R, lower first portion, 121, second portion, 13, filler, 13W, first filler, 13R, second filler, 141R, lower sacrificial insulating film layer, 142R, lower partition insulating film layer, 143R, first lower interlayer dielectric layer, 144R, second lower interlayer dielectric layer, 145R, second down signal line, 146R, second lower partition insulating portion, 147R, second up signal line, 148R, second upper partition insulating portion, 149R, lower through hole, 151R, lower semiconductor thin film layer; 152R, lower gate dielectric thin film layer; 153R, lower gate thin film layer; 154R, lower conductive filling thin film layer; 16, intermediate partition insulating film layer; 160, intermediate via; 171W, upper sacrificial insulating film layer, 172W, upper partition insulating film layer, 173W, first upper interlayer dielectric layer, 174W, second upper interlayer dielectric layer, 175W, write bit line, 176W, first lower partition insulating portion, 177W, upper through hole, 178W, filled partition insulating portion, 179W, write word line, 180, first upper partition insulating thin film layer; 180W, first upper partition insulating part; 181W, upper semiconductor thin film layer, 182W, upper gate dielectric thin film layer, 183W, upper gate thin film layer, 184W, upper conductive filling thin film layer, 19, cap insulating layer; C, memory cell, X, first horizontal direction, Y, second horizontal direction, Z, vertical direction

Claims

1. providing a semiconductor substrate; fabricating at least one memory cell on the semiconductor substrate, the memory cell including at least one transistor, each transistor including a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel surrounding at least an outer periphery of the gate, the gate dielectric being formed between the semiconductor channel and the gate, the upper electrode and the lower electrode both being located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode being provided below and insulated from the upper electrode, one of the upper electrode and the lower electrode being a source and the other being a drain; and oxidizing a region to be oxidized of an effective semiconductor channel of at least one of the transistors of the memory cells, thereby forming the region to be oxidized into an oxidation channel, the region to be oxidized being at least a part of the effective semiconductor channel, and neither the upper electrode nor the lower electrode being in contact with the oxidation channel, the effective semiconductor channel being a portion of the semiconductor channel located between the upper electrode and the lower electrode. A method for manufacturing a memory comprising the steps of:

2. The method further includes a step of heat-treating the oxidized region to be oxidized after oxidizing the region to be oxidized, or The oxidation treatment of the region to be oxidized is performed simultaneously with a step of heat-treating the region to be oxidized.

2. The method for manufacturing a memory according to claim 1.

3. The method for manufacturing a memory further includes, before oxidizing the region to be oxidized, a step of manufacturing a gas passage, the gas passage including a first portion provided around the outer periphery of the region to be oxidized and a second portion communicating with the first portion and extending vertically upward, so that an oxidizing gas introduced from above the second portion acts on the region to be oxidized.

3. The method for manufacturing a memory according to claim 1 or 2.

4. After forming the oxide channel, the method for manufacturing a memory further includes filling the gas passage with an insulating material.

4. The method for manufacturing a memory according to claim 3.

5. filling the gas passage with insulating material includes completely filling the gas passage with insulating material to form a filler body within the gas passage, wherein a top surface of the filler body is flush with a top surface of the gas passage.

5. The method for manufacturing a memory according to claim 4.

6. the step of filling the gas passage with insulating material includes a step of partially or completely filling the second portion of the gas passage with insulating material to form a filler body in the second portion, wherein an upper surface of the filler body is flush with an upper surface of the gas passage, and a region of the gas passage other than the region filled with the filler body is a void region.

5. The method for manufacturing a memory according to claim 4.

7. The number of the memory cells is plural, and the memory array structure is arranged in a horizontal plane, and each of the memory cells includes two of the transistors, and the two transistors are a read transistor and a write transistor, respectively; the write transistor includes a first gate, a first gate dielectric, a first semiconductor channel, a first top electrode, and a first bottom electrode; the readout transistor includes a second gate, a second gate dielectric, a second semiconductor channel, a second top electrode, and a second bottom electrode; the write transistor is located above the read transistor, and the first bottom electrode and the second gate are electrically connected to each other; The method for manufacturing the memory includes a step of oxidizing a region to be oxidized of an effective semiconductor channel of at least one of the write transistor and the read transistor.

5. The method for manufacturing a memory according to claim 4.

8. The method for manufacturing the memory includes a step of oxidizing a region to be oxidized of an effective semiconductor channel of one of the write transistor and the read transistor to form an oxide channel; the gas passage is fabricated after fabrication of the transistor corresponding to the region to be oxidized is completed; 8. The method for manufacturing a memory according to claim 7.

9. oxidizing a first region to be oxidized, the first region to be oxidized being a first effective semiconductor channel of the write transistor, to form the first region to be oxidized into a first oxidation channel; oxidizing a second region to be oxidized, the second region to be oxidized being a second effective semiconductor channel of the readout transistor, so as to form the second region to be oxidized into a second oxidized channel; 8. The method for manufacturing a memory according to claim 7.

10. the first oxide channel and the second oxide channel are formed simultaneously, and the gas passage is fabricated after fabrication of the write transistor is completed; the first portion of the gas passage includes an upper first portion surrounding the outer periphery of the first region to be oxidized and a lower first portion surrounding the outer periphery of the second region to be oxidized, the upper first portion and the lower first portion being spaced apart in the vertical direction, the second portion extending vertically upward to the top surface of the memory cell to connect the upper first portion and the lower first portion, and an oxidation gas introduced from above the second portion simultaneously acts on the first region to be oxidized and the second region to be oxidized, thereby realizing oxidation processing.

10. The method for manufacturing a memory according to claim 9.

11. The method for manufacturing the gas passage comprises: forming a lower stacked film layer on the semiconductor substrate, the lower stacked film layer including the second lower electrode, a lower sacrificial insulating film layer, the second upper electrode, and a lower partition insulating film layer stacked in order at least along a vertical direction; forming a lower through-hole penetrating at least the lower partition insulating layer, the second upper electrode, and the lower sacrificial insulating layer, wherein the second lower electrode is exposed through the lower through-hole; forming the second semiconductor channel, the second gate dielectric, and the second gate in the lower through-hole to form the readout transistor, wherein the second region to be oxidized of the second semiconductor channel is located in a position surrounded by the lower sacrificial insulating film; a step of forming an intermediate partition insulating film layer on the lower stacked film layer, the intermediate partition insulating film layer covering at least a region on the upper surface of the lower partition insulating film layer that is not covered by the read transistor, and a step of orthogonal projections of at least a part of the second gate and the intermediate partition insulating film layer onto the semiconductor substrate not overlapping each other; forming an upper stacked film layer, the upper stacked film layer including the first lower electrode, an upper sacrificial insulating film layer, a first upper electrode, and an upper partition insulating film layer stacked in order at least along a vertical direction, the first lower electrode being connected to the second gate, and an upper surface of the first lower electrode being flush with an upper surface of the intermediate partition insulating film layer; forming an upper through-hole penetrating at least the upper partition insulating layer, the first upper electrode, and the upper sacrificial insulating layer, wherein the first lower electrode is exposed through the upper through-hole; forming the write transistor by sequentially forming the first semiconductor channel, the first gate dielectric, and the first gate in the upper through-hole, wherein the first region to be oxidized of the first semiconductor channel is located in a position surrounded by the upper sacrificial insulating film; forming the second portion of the gas passage after forming the write transistor, wherein an orthogonal projection of the second portion onto the semiconductor substrate does not overlap with orthogonal projections of the lower through-hole and the upper through-hole onto the semiconductor substrate, and the second portion penetrates at least the upper partition insulating film layer, the upper sacrificial insulating film layer, the intermediate partition insulating film layer, and the lower partition insulating film layer to expose the lower sacrificial insulating film; introducing an etchant into the second portion to remove the upper sacrificial insulating film layer and the lower sacrificial insulating film layer, thereby forming an upper first portion provided to surround the first region to be oxidized and a lower first portion provided to surround the second region to be oxidized; 11. The method for manufacturing a memory according to claim 10.

12. the gas passage includes a first gas passage and a second gas passage, the first gas passage includes a first portion surrounding the first oxidation target region and a second portion communicating with the first portion of the first gas passage and extending vertically upward to an upper surface of the memory cell, the second gas passage includes a first portion surrounding the second oxidation target region and a second portion communicating with the first portion of the second gas passage and extending vertically upward to an upper surface of the read transistor, and the method for manufacturing the memory includes: First, a second oxidation target region of a second effective semiconductor channel of the read transistor is oxidized to form a second oxidized channel, and after the second oxidized channel is formed, a second filler is formed by filling the second gas passage with an insulating material, wherein an upper surface of the second filler is flush with an upper surface of the second gas passage; Next, a first oxidation target region of a first effective semiconductor channel of the write transistor is oxidized to form a first oxidized channel, and after the first oxidized channel is formed, the first gas passage is filled with an insulating material to form a first filler, wherein an upper surface of the first filler is flush with an upper surface of the first gas passage.

10. The method for manufacturing a memory according to claim 9.

13. the second filler completely fills the first portion and the second portion of the second gas passage; Alternatively, the second filler partially or completely fills the second portion of the second gas passage, and a region of the second gas passage other than the region filled with the second filler is a void region.

13. The method for manufacturing a memory according to claim 12.

14. the first filler completely fills the first portion and the second portion of the first gas passage; Alternatively, the first filling material partially or completely fills the second portion of the first gas passage, and a region of the first gas passage other than the region filled with the first filling material is a void region.

13. The method for manufacturing a memory according to claim 12.

15. The method for manufacturing the first gas passage includes the steps of: forming a lower stacked film layer on the semiconductor substrate, the lower stacked film layer including at least the second lower electrode, a lower sacrificial insulating film layer, the second upper electrode, and a lower partition insulating film layer, which are sequentially stacked; forming a lower through-hole penetrating at least the lower partition insulating layer, the second upper electrode, and the lower sacrificial insulating layer, wherein the second lower electrode is exposed through the lower through-hole; forming the second semiconductor channel, the second gate dielectric, and the second gate in the lower through-hole to form the readout transistor, wherein the second region to be oxidized of the second semiconductor channel is located in a position surrounded by the lower sacrificial insulating film; forming an intermediate partition insulating film layer on the lower stacked film layer, the intermediate partition insulating film layer covering at least a region on the upper surface of the lower partition insulating film layer that is not covered by the readout transistor, and forming a second portion of a second gas passage, the second portion of the second gas passage and the lower through-hole being orthogonally projected onto the semiconductor substrate and not overlapping with each other, and the second portion of the second gas passage penetrating at least the intermediate partition insulating film layer and the lower partition insulating film layer and being exposed to the lower sacrificial insulating film layer; and removing the lower sacrificial insulating film layer by introducing an etchant into the second portion of the second gas passage, thereby forming the first portion of the second gas passage provided to surround the second region to be oxidized.

13. The method for manufacturing a memory according to claim 12.

16. The method for manufacturing the first gas passage includes the steps of: forming an upper stacked film layer, the upper stacked film layer including at least the first lower electrode, an upper sacrificial insulating film layer, a first upper electrode, and an upper partition insulating film layer, which are sequentially stacked, the first lower electrode being connected to the second gate, and an upper surface of the first lower electrode being flush with an upper surface of the intermediate partition insulating film layer; forming an upper through-hole penetrating at least the upper partition insulating layer, the first upper electrode, and the upper sacrificial insulating layer, wherein the first lower electrode is exposed through the upper through-hole; forming the write transistor by sequentially forming the first semiconductor channel, the first gate dielectric, and the first gate in the upper through-hole, wherein the first region to be oxidized of the first semiconductor channel is located in a position surrounded by the upper sacrificial insulating film; forming the second portion of the first gas passage after forming the write transistor, so that the second portion of the first gas passage and the upper through-hole are not overlapped in orthogonal projection onto the semiconductor substrate, and the second portion of the first gas passage penetrates at least the upper partition insulating film layer and is exposed to the upper sacrificial insulating film layer; and introducing an etchant into the second portion of the first gas passage to remove the upper sacrificial insulating film layer and form the first portion of the first gas passage surrounding the first region to be oxidized.

16. The method for manufacturing a memory according to claim 15.

17. the lower stacked film layer further includes a first lower interlayer dielectric layer and a second lower interlayer dielectric layer made of a material different from that of the lower sacrificial insulating film layer, the first lower interlayer dielectric layer being formed between the second upper electrode and the lower sacrificial insulating film layer to surround the second effective semiconductor channel, and the second lower interlayer dielectric layer being formed between the second lower electrode and the lower sacrificial insulating film layer to surround the second effective semiconductor channel; the upper stacked film layer further includes a first upper interlayer dielectric layer and a second upper interlayer dielectric layer made of a material different from that of the upper sacrificial insulating film layer, the first upper interlayer dielectric layer being formed between the first upper electrode and the upper sacrificial insulating film layer to surround the first effective semiconductor channel, and the second upper interlayer dielectric layer being formed between the first lower electrode and the upper sacrificial insulating film layer to surround the first effective semiconductor channel; In the process of removing the upper sacrificial insulating layer and the lower sacrificial insulating layer using the etchant, the first lower interlayer dielectric layer, the second lower interlayer dielectric layer, the first upper interlayer dielectric layer, and the second upper interlayer dielectric layer are left unremoved.

12. The method for manufacturing a memory according to claim 11.

18. the lower stacked film layer further includes a first lower interlayer dielectric layer and a second lower interlayer dielectric layer made of a material different from that of the lower sacrificial insulating film layer, the first lower interlayer dielectric layer being formed between the second upper electrode and the lower sacrificial insulating film layer to surround the second effective semiconductor channel, and the second lower interlayer dielectric layer being formed between the second lower electrode and the lower sacrificial insulating film layer to surround the second effective semiconductor channel; the upper stacked film layer further includes a first upper interlayer dielectric layer and a second upper interlayer dielectric layer made of a material different from that of the upper sacrificial insulating film layer, the first upper interlayer dielectric layer being formed between the first upper electrode and the upper sacrificial insulating film layer to surround the first effective semiconductor channel, and the second upper interlayer dielectric layer being formed between the first lower electrode and the upper sacrificial insulating film layer to surround the first effective semiconductor channel; In the process of removing the upper sacrificial insulating layer and the lower sacrificial insulating layer using the etchant, the first lower interlayer dielectric layer, the second lower interlayer dielectric layer, the first upper interlayer dielectric layer, and the second upper interlayer dielectric layer are left unremoved.

17. The method of manufacturing a memory according to claim 16.

19. A memory including a semiconductor substrate and at least one memory cell, the at least one memory cell is formed on the semiconductor substrate, the memory cell includes at least one transistor, each transistor includes a gate, a gate dielectric, a semiconductor channel, an upper electrode, and a lower electrode, the semiconductor channel surrounds at least the outer periphery of the gate, the gate dielectric is formed between the semiconductor channel and the gate, both the upper electrode and the lower electrode are located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is provided below the upper electrode and insulated, one of the upper electrode and the lower electrode is a source and the other is a drain, In the memory cell, a part of an effective semiconductor channel of at least one of the transistors is formed into an oxide channel by oxidation, the effective semiconductor channel being a part of the semiconductor channel located between the upper electrode and the lower electrode, and neither the upper electrode nor the lower electrode contacts the oxide channel; A memory characterized by:

20. The number of the memory cells is plural, and the memory array structure is arranged in a horizontal plane, and each of the memory cells includes two of the transistors, and the two transistors are a read transistor and a write transistor, respectively; the write transistor includes a first gate, a first gate dielectric, a first semiconductor channel, a first top electrode, and a first bottom electrode; the readout transistor includes a second gate, a second gate dielectric, a second semiconductor channel, a second top electrode, and a second bottom electrode; the write transistor is located above the read transistor, and the first bottom electrode and the second gate are electrically connected to each other; a portion of the effective semiconductor channel of at least one of the write transistor and the read transistor is formed into the oxide channel by an oxidation process; 20. The memory of claim 19.

21. In the memory array structure, the memory cells are arranged in an array in a first horizontal direction and a second horizontal direction, and the first horizontal direction intersects with the second horizontal direction.

21. The memory of claim 20.

22. a memory further including a plurality of second down signal lines arranged in a row at intervals in a first horizontal direction and extending in a second horizontal direction, a plurality of second up signal lines arranged in a row at intervals in the second horizontal direction and extending in the first horizontal direction, a write word line, and a write bit line, each of the second down signal lines is connected to a second lower electrode of each of the readout transistors in one column arranged side by side in a second horizontal direction; the second up signal line is located on a side of the second down signal line that is farther from the semiconductor substrate, each of the second up signal lines is connected to a second upper electrode of each of the read transistors in one column that are arranged side by side in a first horizontal direction, one of the second up signal line and the second down signal line is a read word line, and the other is a read bit line; the write bit line is formed on a side of the second up signal line remote from the semiconductor substrate, the write word line is formed on a side of the write bit line remote from the semiconductor substrate, one of the write word line and the write bit line extends in a first horizontal direction and is arranged in a line at intervals in a second horizontal direction, and the other extends in a second horizontal direction and is arranged in a line at intervals in the first horizontal direction, each write bit line is connected to a first upper electrode of each write transistor in a row arranged in a line at intervals in the extension direction, and each write word line is connected to a first gate of each write transistor in a row arranged in a line at intervals in the extension direction.

22. The memory of claim 21 .

23. a first oxidized channel is formed by oxidizing a portion of the first effective semiconductor channel of the write transistor; a first gap region is formed between the first upper electrode and the first lower electrode; and the first gap region is disposed to surround the first oxidized channel; a second oxide channel is formed by oxidizing a portion of the second effective semiconductor channel of the readout transistor; a second gap region is formed between the second upper electrode and the second lower electrode; and the second gap region is disposed to surround the second oxide channel.

21. The memory of claim 20.

24. a first upper interlayer dielectric layer is formed between the first upper electrode and the first gap region, and a second upper interlayer dielectric layer is formed between the first lower electrode and the first gap region, and both the first upper interlayer dielectric layer and the second upper interlayer dielectric layer are formed to surround the first effective semiconductor channel and do not contact the first oxide channel; a first lower interlayer dielectric layer is formed between the second upper electrode and the second gap region, and a second lower interlayer dielectric layer is formed between the second lower electrode and the second gap region, and both the first lower interlayer dielectric layer and the second lower interlayer dielectric layer are disposed to surround the second effective semiconductor channel and do not contact the second oxide channel; 24. The memory of claim 23.

25. a first oxide channel is formed by oxidizing a portion of a first effective semiconductor channel of the write transistor; a first insulating layer is formed between the first upper electrode and the first lower electrode; the first insulating layer is formed to surround the first oxide channel and is in contact with a lower surface of the first upper electrode and an upper surface of the first lower electrode without a gap; a second oxide channel is formed by oxidizing a portion of the second effective semiconductor channel of the readout transistor; a second insulating layer is formed between the second upper electrode and the second lower electrode; the second insulating layer is formed to surround the second oxide channel and is in contact with a lower surface of the second upper electrode and an upper surface of the second lower electrode without any gap; 21. The memory of claim 20.

Images