Power supply control device, and switching power supply

Abstract

To arbitrarily switch validity / invalidity of a load line function.SOLUTION: A power supply control device 1 comprises: an error amplifier 10 which generates an error signal EOUT corresponding to an error between a feedback voltage FB corresponding to an output voltage VOUT of a switching power supply A and a reference voltage REF; a current sensor 20 which generates a current detection signal ISNS corresponding to a coil current IL; a duty signal generation circuit 30 which receives input of the error signal EOUT and the current detection signal ISNS and generates a duty signal PWM; and a drive signal generation circuit 40 which receives input of the duty signal PWM and generates drive signals GH and GL of an output circuit 2. The error amplifier 10 is switched between a first mode and a second mode in response to a mode switching signal MODE. In the first mode, the error signal EOUT is generated using an integration voltage (Vcal) of a differential value (REF-FB) and in the second mode, the error signal EOUT is generated without using the integration voltage (Vcal).SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device and a switching power supply. [Background technology]

[0002] 2. Description of the Related Art Conventionally, switching power supplies have been used as power supply means for various applications, which generate a desired output voltage from an input voltage by turning an output transistor on and off.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-153079

[0005] [overview] In conventional switching power supplies, it was difficult to arbitrarily enable or disable the function that changes the output voltage according to the load current, the so-called load line function.

[0006] A power supply control device according to the present disclosure is configured to control an output circuit of a switching power supply that generates an output voltage from an input voltage, and includes: an error amplifier configured to generate an error signal corresponding to the error between a feedback voltage corresponding to the output voltage and a predetermined reference voltage; a current sensor configured to generate a current detection signal corresponding to a coil current flowing through the output circuit; a duty signal generation circuit configured to generate a duty signal upon receiving the error signal and the current detection signal; and a drive signal generation circuit configured to generate a drive signal for the output circuit upon receiving the duty signal, wherein the error amplifier is switched between a first mode and a second mode upon a mode switching signal; in the first mode, the error amplifier generates the error signal using an integrated voltage obtained by integrating the difference value obtained by subtracting the reference voltage from the feedback voltage; and in the second mode, the error amplifier generates the error signal without using the integrated voltage. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a comparative example of a switching power supply. [Figure 2] FIG. 2 is a diagram showing a load response waveform when the load line function is disabled. [Figure 3] FIG. 3 is a diagram showing a load response waveform when the load line function is enabled. [Figure 4] FIG. 4 is a diagram showing the overall configuration of a switching power supply according to the present disclosure. [Figure 5] FIG. 5 is a diagram showing the relationship between the error signal and the coil current. [Figure 6] FIG. 6 is a diagram illustrating a first embodiment of the error amplifier. [Figure 7] FIG. 7 is a diagram showing a load response waveform when the error amplifier of the first embodiment is in the first mode. [Figure 8] FIG. 8 is a diagram showing a load response waveform when the error amplifier of the first embodiment is in the second mode. [Figure 9] FIG. 9 is a diagram illustrating a second embodiment of the error amplifier. [Figure 10] FIG. 10 is a diagram showing a load response waveform when the error amplifier of the second embodiment is in the first mode. [Figure 11] FIG. 11 is a diagram showing a load response waveform when the error amplifier of the second embodiment is in the second mode. [Figure 12] FIG. 12 is a diagram illustrating a first example of the soft start function. [Figure 13] FIG. 13 is a diagram illustrating a second example of the soft start function. [Figure 14] FIG. 14 is a diagram showing a modified example of the switching power supply according to the present disclosure.

[0008] [Detailed explanation] <Switching power supply (comparison example)> 1 is a diagram showing a comparative example of a switching power supply A (= a configuration to be compared with the present disclosure described later). The switching power supply A of this comparative example is a DC / DC converter that generates an output voltage VOUT and a load current Iload from an input voltage VIN and supplies them to a load (not shown). Referring to this diagram, the switching power supply A includes a power supply control device 1 and an output circuit 2.

[0009] The power supply control device 1 receives feedback inputs of an output voltage VOUT and a coil current IL and performs current mode control of an output circuit 2. Referring to the figure, the power supply control device 1 includes an error amplifier 10, a current sensor 20, a duty signal generation circuit 30, a drive signal generation circuit 40, and a load line function circuit 100. The power supply control device 1 may also include other components (such as a protection circuit). The power supply control device 1 may be provided as a semiconductor integrated circuit device such as a power supply control IC (integrated circuit) or a PMIC (power management IC).

[0010] The error amplifier 10 generates an error signal EOUT corresponding to the error between a feedback voltage FB (=VOUT+Vofs) applied to the inverting input terminal (-) and a reference voltage REF applied to the non-inverting input terminal (+). The error signal EOUT increases when the feedback voltage FB is lower than the reference voltage REF, and decreases when the feedback voltage FB is higher than the reference voltage REF.

[0011] The current sensor 20 generates a current detection signal ISNS corresponding to the coil current IL flowing through the output circuit 2.

[0012] The duty signal generating circuit 30 receives the error signal EOUT and generates the duty signal PWM. The duty signal generating circuit 30 can be implemented with a well-known circuit configuration, and therefore a detailed description thereof will be omitted.

[0013] The drive signal generation circuit 40 receives the duty signal PWM as an input and generates an upper drive signal GH and a lower drive signal GL for the output circuit 2. Referring to the figure, the drive signal generation circuit 40 includes a controller 41, a level shifter 42, a buffer 43, and an inverter 44.

[0014] The controller 41 receives the duty signal PWM and generates the upper control signal SH and the lower control signal SL. For example, the controller 41 may set the upper control signal SH and the lower control signal SL to a high level when the duty signal PWM is at a high level. Alternatively, the controller 41 may set the upper control signal SH and the lower control signal SL to a low level when the duty signal PWM is at a low level.

[0015] The level shifter 42 generates the high-side control signal SHx by level-shifting the high-side control signal SH. The high-side control signal SH may be pulse-driven by a drive voltage of the controller 41. On the other hand, the level-shifted high-side control signal SHx may be pulse-driven by a drive voltage of the buffer 43.

[0016] The buffer 43 buffers and amplifies the high-side control signal SHx to generate the high-side drive signal GH. Therefore, the high-side drive signal GH goes high when the high-side control signal SHx is high. Also, the high-side drive signal GH goes low when the high-side control signal SHx is low.

[0017] The inverter 44 inverts the logic level (high level / low level) of the low-side control signal SL to generate the low-side drive signal GL. Therefore, the low-side drive signal GL is at a low level when the low-side control signal SL is at a high level. Also, the low-side drive signal GL is at a high level when the low-side control signal SL is at a low level.

[0018] The output circuit 2 steps down the input voltage VIN to generate the output voltage VOUT. Referring to the figure, the output circuit 2 includes transistors MH and ML (e.g., N-channel MOSFETs [metal oxide semiconductor field effect transistors]), a capacitor C1, and a coil L1.

[0019] The drain of transistor MH is connected to a terminal to which an input voltage VIN is applied. The source and back gate of transistor MH are connected to a terminal to which a switch voltage SW is applied. The gate of transistor MH is connected to a terminal to which an upper drive signal GH is applied. Transistor MH is turned on when the upper drive signal GH is at a high level, and turned off when the upper drive signal GH is at a low level. Transistor MH connected in this manner functions as the upper switch of the half-bridge output stage, i.e., as an output transistor. Note that transistor MH may be replaced with a P-channel MOSFET.

[0020] The drain of the transistor ML is connected to the application terminal of the switch voltage SW. The source and back gate of the transistor ML are connected to the reference potential terminal. The reference potential terminal may be, for example, the ground terminal. The gate of the transistor ML is connected to the application terminal of the low-side drive signal GL. The transistor ML is turned on when the low-side drive signal GL is at a high level, and turned off when the low-side drive signal GL is at a low level. The transistor ML connected in this manner functions as the lower switch of the half-bridge output stage, i.e., as a synchronous rectification transistor.

[0021] The transistors MH and ML are complementarily turned on / off in response to the high-side drive signal GH and the low-side drive signal GL. This on / off operation generates a square-wave switch voltage SW. The term "complementary" above should be understood in a broad sense to include not only the case where the on / off states of the transistors MH and ML are completely reversed, but also the case where a period (dead time) during which the transistors MH and ML are simultaneously off is provided.

[0022] The transistors MH and ML may be Si devices, SiC devices, or GaN devices. The transistors MH and ML may be replaced with, for example, IGBTs (insulated gate bipolar transistors). When the power supply control device 1 is provided as a semiconductor integrated circuit device, the transistors MH and ML may be integrated into the power supply control device 1. Alternatively, the transistors MH and ML may be external to the power supply control device 1.

[0023] A first end of the coil L1 is connected to an application terminal of the switch voltage SW. A second end of the coil L1 and a first end of the capacitor C1 are connected to an application terminal of the output voltage VOUT. A second end of the capacitor C1 is connected to a reference potential terminal. The coil L1 and capacitor C1 connected in this manner function as an LC filter that rectifies and smoothes the switch voltage SW to generate the output voltage VOUT. When the power supply control device 1 is provided as a semiconductor integrated circuit device, the coil L1 and the capacitor C1 may be externally attached to the power supply control device 1.

[0024] The output format of the output circuit 2 is not limited to a step-down type, but may be a step-up type, a step-up / step-down type, or an inverting type. The rectification method of the output circuit 2 is not limited to a synchronous rectification type, but may be a diode rectification type using a rectifier diode as a lower switch of a half-bridge output stage.

[0025] The load line function circuit 100 realizes a function of changing the output voltage VOUT in accordance with the load current Iload, that is, a so-called load line function. Referring to this figure, the load line function circuit 100 includes a current source CS and a resistor R0.

[0026] The current source CS is connected between the feedback voltage FB application terminal and the reference potential terminal, and generates a variable current I0 according to the current detection signal ISNS. The variable current I0 may be a current proportional to the average value of the coil current IL, and therefore to the load current Iload (I0 ∝ Iload).

[0027] The resistor R0 is connected between the application terminal of the output voltage VOUT and the application terminal of the feedback voltage FB. An offset voltage Vofs (=I0×R0) corresponding to the variable current I0 is generated across the resistor R0.

[0028] As a result, the feedback voltage FB becomes the sum of the output voltage VOUT and the offset voltage Vofs (=VOUT+Vofs). Therefore, the feedback voltage FB increases as the load current Iload increases.

[0029] The power supply control device 1 performs output feedback control so that the feedback voltage FB matches the reference voltage REF. Therefore, by implementing the load line function circuit 100, output feedback control is applied so that the output voltage VOUT decreases as the load current Iload increases.

[0030] 2 is a diagram showing a load response waveform when the load line function is disabled, that is, a load response waveform when the load line function circuit 100 is not implemented in the power supply control device 1. In this diagram, from top to bottom, the load current Iload and the output voltage VOUT (which may also be understood as the feedback voltage FB) are depicted.

[0031] As shown in this figure, when the load line function is disabled, fluctuations in the load current Iload cause overshoot and undershoot in the output voltage VOUT, which deteriorates the accuracy of the output voltage VOUT.

[0032] 3 is a diagram showing a load response waveform when the load line function is enabled, that is, a load response waveform when the load line function circuit 100 is implemented in the power supply control device 1. In this diagram, from top to bottom, the load current Iload, the output voltage VOUT (solid line), and the feedback voltage FB (dashed line) are depicted.

[0033] As shown in this diagram, when the load line function is enabled, as the load current Iload increases, the output voltage VOUT is reduced in a DC manner by the same amount as the undershoot, making it less likely that the output voltage VOUT will overshoot. It is recommended that the target value VOUT_target of the output voltage VOUT be set in advance to be half the amount of undershoot. This setting makes it possible to improve the accuracy of the output voltage VOUT (for example, from ±6% to ±3%).

[0034] <Considerations regarding roadline functions> The purpose of implementing the load line function circuit 100 in the power supply control device 1 is to equalize the transient overshoot and undershoot of the output voltage VOUT during load fluctuations with the DC fluctuation component. However, with the switching power supply A of this comparative example, it is not necessarily easy to achieve this purpose.

[0035] A specific problem is that the overshoot and undershoot of the output voltage VOUT during load fluctuations are determined by the respective circuit configurations of the error amplifier 10 and the duty signal generating circuit 30. On the other hand, the DC fluctuation component of the output voltage VOUT during load fluctuations is determined by the voltage value of the offset voltage Vofs, i.e., the current value of the variable current I0 and the resistance value of the resistor R0. Therefore, it is difficult to set the overshoot and undershoot of the output voltage VOUT during load fluctuations and the DC fluctuation component independently.

[0036] Furthermore, in the switching power supply A of this comparative example, in order to enable / disable the load line function, it is necessary to switch whether or not to incorporate the load line function circuit 100 into the output feedback system of the power supply control device 1. Therefore, it is necessary to adjust other control circuits that form the output feedback system depending on whether the load line function is enabled / disabled. For this reason, it is difficult to arbitrarily enable / disable the load line function while sharing control circuits other than the load line function circuit 100.

[0037] In view of the above considerations, the following discloses a switching power supply A that can arbitrarily switch between enabling and disabling the load line function and can also arbitrarily adjust the load response characteristics and load line characteristics.

[0038] <Switching power supply (overall configuration)> FIG. 4 is a diagram showing the overall configuration of a switching power supply A according to the present disclosure. The switching power supply A according to the present disclosure is based on the comparative example (FIG. 1) described above, but the load line function circuit 100 is omitted and the error amplifier 10 is modified. In addition, in this figure, the current sensor 20 is of a differential output type, and accordingly, the internal configuration of the duty signal generation circuit 30 is clearly shown. The switching power supply A according to the present disclosure also includes an output feedback circuit 50. The above modifications will be described in detail below.

[0039] The current sensor 20 differentially outputs a positive-phase current detection signal ISNSP and a negative-phase current detection signal ISNSN as the current detection signal ISNS. For example, the current sensor 20 converts the average value of the coil current IL into a differential voltage (ISNSP-ISNSN) between the positive-phase current detection signal ISNSP and the negative-phase current detection signal ISNSN.

[0040] The current sensor 20 may sample the coil current IL during an on-period of the output circuit 2, i.e., the center timing of the period when the transistor MH is on and the transistor ML is off. Alternatively, the current sensor 20 may sample the coil current IL during an off-period of the output circuit 2, i.e., the center timing of the period when the transistor MH is off and the transistor ML is on.

[0041] When such sampling is performed, output feedback control is applied to the switching power supply A so as to maintain the average value of the coil current IL, and therefore the load current Iload, constant. However, the method for detecting the coil current IL is not limited to the above.

[0042] The duty signal generating circuit 30 receives the error signal EOUT and the current detection signal ISNS as inputs and generates the duty signal PWM. Referring to the figure, the duty signal generating circuit 30 includes an output feedback amplifier 31 and a comparator 32.

[0043] The output feedback amplifier 31 receives the error signal EOUT and the current detection signal ISNS as inputs and generates a control voltage VC according to them. For example, the first non-inverting input terminal (+) of the output feedback amplifier 31 is connected to the application terminal of the error signal EOUT. The first inverting input terminal (-) of the output feedback amplifier 31 is connected to the application terminal of the bias voltage EOUT_REF. The second non-inverting input terminal (+) of the output feedback amplifier 31 is connected to the application terminal of the negative-phase current detection signal ISNSN. The second inverting input terminal (-) of the output feedback amplifier 31 is connected to the application terminal of the positive-phase current detection signal ISNSP.

[0044] The output feedback amplifier 31 connected in this manner generates a control voltage VC so that the difference value (EOUT-EOUT_REF) between the error signal EOUT and the bias voltage EOUT_REF matches the difference value (ISNSP-ISNSN) between the positive-phase current detection signal ISNSP and the negative-phase current detection signal ISNSN.

[0045] The comparator 32 compares the control voltage VC with the ramp voltage VR to generate the duty signal PWM. The ramp voltage VR may be, for example, a triangular wave, a sawtooth wave, or an n-th order slope wave (e.g., n=2) that rises during the on-period Ton of the transistor MH.

[0046] The duty signal PWM is at a high level when the ramp voltage VR is lower than the control voltage VC, and is at a low level when the ramp voltage VR is higher than the control voltage VC. The duty signal PWM can be understood as a signal that determines the off-timing of the transistor MH. The on-duty D (= Ton / Tsw) of the duty signal PWM, i.e., the ratio of the on-period Ton to the switching period Tsw, increases as the control voltage VC increases and decreases as the control voltage VC decreases.

[0047] In this way, in the switching power supply A according to the present disclosure, output feedback control is applied so that the difference (EOUT-EOUT_REF) between the error signal EOUT and the bias voltage EOUT_REF coincides with the difference (ISNSP-ISNSN) between the positive-phase current detection signal ISNSP and the negative-phase current detection signal ISNSN. As a result, the coil current IL is controlled in accordance with the difference (EOUT-EOUT_REF) between the error signal EOUT and the bias voltage EOUT_REF.

[0048] 5 is a diagram showing the relationship between the error signal EOUT and the coil current IL. The horizontal axis of this diagram represents the error signal EOUT. The vertical axis of this diagram represents the coil current IL.

[0049] When the error signal EOUT is higher than the bias voltage EOUT_REF, the greater the absolute value of the error signal EOUT, the greater the coil current IL flowing in the positive direction (= from the output circuit 2 to the load). On the other hand, when the error signal EOUT is lower than the bias voltage EOUT_REF, the greater the absolute value of the error signal EOUT, the greater the coil current IL flowing in the negative direction (= from the load to the output circuit 2). When the error signal EOUT and the bias voltage EOUT_REF are equal, the coil current IL is 0 A. In other words, the error signal EOUT matches the bias voltage EOUT_REF when the coil current IL is 0 A.

[0050] In this way, the switching power supply A according to the present disclosure can achieve current mode control, which has better load response characteristics than voltage control mode.

[0051] Returning to Figure 4, the description of the power supply control device 1 will continue. The output feedback circuit 50 includes resistors 51 and 52 connected in series between the application terminal of the output voltage VOUT and the ground terminal. The output feedback circuit 50 outputs a feedback voltage FB (= a divided voltage of the output voltage VOUT) according to the output voltage VOUT from the connection node of the resistors 51 and 52. However, if the output voltage VOUT falls within the input dynamic range of the error amplifier 10, the output feedback circuit 50 may be omitted and the output voltage VOUT may be input directly to the error amplifier 10.

[0052] The error amplifier 10 is switched between the first mode and the second mode in response to a mode switching signal MODE, which may be set, for example, by an external input to a dedicated terminal, serial communication, or writing to a memory or a register.

[0053] In the first mode, the error amplifier 10 generates an error signal EOUT using an integrated voltage Vcal obtained by integrating a difference (REF-FB) obtained by subtracting a reference voltage REF from a feedback voltage FB. In the first mode, output feedback control is applied so that the output voltage VOUT matches the target value VOUT_target regardless of the load current Iload. In other words, the first mode can be understood as a mode in which the load line function is disabled.

[0054] On the other hand, in the second mode, the error amplifier 10 generates the error signal EOUT without using the integrated voltage Vcal. In the second mode, output feedback control is applied so as to shift the output voltage VOUT in accordance with the load current Iload. That is, the second mode can be understood as a mode in which the load line function is enabled.

[0055] In this way, in the switching power supply A according to the present disclosure, the load line function is enabled / disabled depending on whether or not the integral voltage Vcal generated inside the error amplifier 10 is used when the error signal EOUT is generated. Therefore, it is easy to arbitrarily enable / disable the load line function while sharing most of the control circuits that form the output feedback system.

[0056] <Error Amplifier (First Embodiment)> 6 is a diagram showing a first embodiment of the error amplifier 10. The error amplifier 10 of this embodiment includes amplifiers 11 and 12, resistors 13 and 14, a capacitor 15, and a switch 16.

[0057] The non-inverting input terminal (+) of the amplifier 11 is connected to a terminal to which a reference voltage REF is applied. The inverting input terminal (-) of the amplifier 11 is connected to a terminal to which a feedback voltage FB is applied. The output terminal of the amplifier 11 is connected to a terminal to which an integrated voltage Vcal is applied. The amplifier 11 may be a transconductance amplifier, a so-called gm amplifier, that generates a current signal I11 corresponding to the difference value (REF-FB) between the reference voltage REF and the feedback voltage FB.

[0058] The first non-inverting input terminal (+) of the amplifier 12 is connected to the terminal to which the reference voltage REF is applied. The first inverting input terminal (-) of the amplifier 12 is connected to the terminal to which the feedback voltage FB is applied. The second non-inverting input terminal (+) of the amplifier 12 is connected to the terminal to which the integral voltage Vcal is applied. The second inverting input terminal (-) of the amplifier 12 is connected to the terminal to which the node voltage INN2 is applied. The output terminal of the amplifier 12 is connected to the terminal to which the error signal EOUT is applied. The resistor 13 is connected between the terminal to which the bias voltage EOUT_REF is applied and the terminal to which the node voltage INN2 is applied. The resistor 14 is connected between the terminal to which the node voltage INN2 is applied and the terminal to which the error signal EOUT is applied.

[0059] The amplifier 12 and resistors 13 and 14 connected in this manner generate an error signal EOUT so that the difference (REF-FB) between the reference voltage REF and the feedback voltage FB matches the difference (Vcal-INN2) between the integral voltage Vcal and the node voltage INN2. In other words, the amplifier 12 and resistors 13 and 14 can be understood as a circuit that adds the difference (REF-FB) between the reference voltage REF and the feedback voltage FB and the difference (Vcal-EOUT_REF) between the integral voltage Vcal and the bias voltage EOUT_REF and amplifies the sum by a constant factor.

[0060] The capacitor 15 is connected between the application terminal of the integral voltage Vcal and the reference potential terminal. The capacitor 15 is charged and discharged by the current signal output from the amplifier 11. The charged voltage of the capacitor 15 is extracted as the integral voltage Vcal. The amplifier 11 and the capacitor 15 connected in this manner can be understood as a circuit that amplifies and integrates the difference value (REF-FB) between the reference voltage REF and the feedback voltage FB. The capacitor 15 may also be connected between the application terminal of the integral voltage Vcal and the application terminal of the bias voltage EOUT_REF. In other words, the capacitor 15 may be connected across the switch 16.

[0061] The switch 16 is connected between the application terminal of the integral voltage Vcal and the application terminal of the bias voltage EOUT_REF. The switch 16 is turned on / off in response to the mode switching signal MODE. When the error amplifier 10 is in the first mode, the switch 16 is turned off. At this time, the integral voltage Vcal is input to the amplifier 12 without being fixed by the bias voltage EOUT_REF. Therefore, the error signal EOUT is generated using the integral voltage Vcal. On the other hand, when the error amplifier 10 is in the second mode, the switch 16 is turned on. At this time, the integral voltage Vcal is fixed by the bias voltage EOUT_REF. Therefore, the error signal EOUT is generated without using the integral voltage Vcal.

[0062] 7 is a diagram showing a load response waveform when the error amplifier 10 of the first embodiment is in the first mode, i.e., when the load line function is disabled. From top to bottom, the diagram depicts the load current Iload, the feedback voltage FB, the integral voltage Vcal, the error signal EOUT, and the coil current IL.

[0063] When the switch 16 is in the OFF state, the following equation (1) holds: R13 and R14 in equation (1) are the resistance values ​​of the resistors 13 and 14, respectively.

[0064]

number

[0065] In the initial state, Iload=Iload1, FB=REF, and Vcal=EOUT_REF. In this initial state, EOUT-EOUT_REF=0 according to equation (1).

[0066] Consider a case where, from the initial state described above, the load current Iload suddenly increases to the set value Iload2 (> Iload1), causing the feedback voltage FB to drop. In this case, the integral voltage Vcal does not immediately follow the feedback voltage FB. Therefore, Vcal is maintained at EOUT_REF. Therefore, the following equation (2) holds true:

[0067]

number

[0068] As a result, the difference value (EOUT-EOUT_REF) between the error signal EOUT and the bias voltage EOUT_REF becomes a voltage obtained by multiplying the difference value (REF-FB) between the reference voltage REF and the feedback voltage FB by a constant.

[0069] The coil current IL is increased according to the difference (EOUT-EOUT_REF) between the error signal EOUT and the bias voltage EOUT_REF. When the coil current IL reaches the load current Iload (=Iload2), the decrease in the output voltage VOUT stops.

[0070] As time passes, the integral voltage Vcal gradually increases. The error signal EOUT increases in accordance with the integral voltage Vcal. When the coil current IL becomes larger than the load current Iload (=Iload2), the output voltage VOUT and, by extension, the feedback voltage FB increase.

[0071] After that, when FB converges to REF, the increase in the integral voltage Vcal stops. At this time, REF=FB, so the following equation (3) holds:

[0072]

number

[0073] The coil current IL and the load current Iload (=Iload2) are then balanced when they are equal. As can be seen from equation (3), the difference between the error signal EOUT and the bias voltage EOUT_REF (EOUT-EOUT_REF) does not depend on the feedback voltage FB. In other words, the coil current IL (≒ load current Iload) does not depend on the output voltage VOUT.

[0074] The case where the load current Iload suddenly decreases to the set value Iload1 from this state and the feedback voltage FB rises can also be understood in the same way as above.

[0075] 8 is a diagram showing a load response waveform when the error amplifier 10 of the first embodiment is in the second mode, i.e., when the load line function is enabled. In this diagram, as in the above-mentioned FIG. 7, the load current Iload, the feedback voltage FB, the integral voltage Vcal, the error signal EOUT, and the coil current IL are depicted from top to bottom.

[0076] When the switch 16 is in the on state, Vcal = EOUT_REF. Therefore, the above-mentioned equation (2) holds. That is, the difference between the error signal EOUT and the bias voltage EOUT_REF (EOUT - EOUT_REF) is always a voltage obtained by multiplying the difference between the reference voltage REF and the feedback voltage FB (REF - FB) by a constant.

[0077] Therefore, when Iload=Iload1, FB=REF, and the output voltage VOUT matches the target value VOUT_target. Also, when Iload=Iload2, the feedback voltage FB balances and stabilizes at a voltage value lower than the reference voltage REF. The load line function is realized by the output feedback operation described above.

[0078] As described above, with the error amplifier 10 of the first embodiment, it is possible to arbitrarily switch the load line function between enabled and disabled by controlling the switch 16 on and off. Furthermore, by changing the resistance ratio between the resistors 13 and 14, it is possible to adjust the gain of the error amplifier 10 that receives the feedback voltage FB and generates the error signal EOUT, i.e., the relationship between the amount of decrease in the feedback voltage FB and the amount of increase in the coil current IL. As a result, it is possible to arbitrarily adjust the load response characteristics and load line characteristics of the switching power supply A.

[0079] <Error Amplifier (Second Embodiment)> 9 is a diagram showing a second embodiment of the error amplifier 10. The error amplifier 10 of this embodiment includes an amplifier 17, a resistor 18, a capacitor 19, and a switch 1A.

[0080] The non-inverting input terminal (+) of amplifier 17 is connected to the terminal to which the reference voltage REF is applied. The inverting input terminal (-) of amplifier 17 is connected to the terminal to which the feedback voltage FB is applied. The output terminal of amplifier 17 is connected to the terminal to which the error signal EOUT is applied. Resistor 18 is connected between the terminal to which the feedback voltage FB is applied and the terminal to which the node voltage V1 is applied. Capacitor 19 is connected between the terminal to which the node voltage V1 is applied and the terminal to which the error signal EOUT is applied. The charging voltage of capacitor 19 can be understood as the aforementioned integral voltage Vcal. As described above, the error amplifier 10 of this embodiment employs a configuration known as Miller compensation.

[0081] The switch 1A is connected between the application terminal of the node voltage V1 and the application terminal of the error signal EOUT. The switch 1A is turned on / off in response to the mode switching signal MODE. When the error amplifier 10 is in the first mode, the switch 1A is turned off. At this time, both ends of the capacitor 19 are opened. Therefore, the error signal EOUT is generated using the integral voltage Vcal. On the other hand, when the error amplifier 10 is in the second mode, the switch 1A is turned on. At this time, both ends of the capacitor 19 are shorted. Therefore, the error signal EOUT is generated without using the integral voltage Vcal.

[0082] The capacitor 19 and the switch 1A may be connected in parallel between the application terminal of the error signal EOUT and the reference potential terminal.

[0083] 10 is a diagram showing a load response waveform when the error amplifier 10 of the second embodiment is in the first mode, i.e., when the load line function is disabled. In this diagram, from top to bottom, the load current Iload, the output voltage VOUT (which may be understood as the feedback voltage FB), the error signal EOUT, and the coil current IL are depicted.

[0084] Thus, when the error amplifier 10 is in the first mode, the component obtained by integrating the difference (REF-FB) between the reference voltage REF and the feedback voltage FB is added to the error signal EOUT. Therefore, when the load current Iload increases, the output voltage VOUT initially drops, but then returns to the target value VOUT_target over time. The same is true when the load current Iload decreases; the output voltage VOUT initially rises before converging to the target value VOUT_target.

[0085] 11 is a diagram showing a load response waveform when the error amplifier 10 of the second embodiment is in the second mode, i.e., when the load line function is enabled. In this diagram, as in the above-mentioned FIG. 10, from top to bottom, the load current Iload, the output voltage VOUT (which may be understood as the feedback voltage FB), the error signal EOUT, and the coil current IL are depicted.

[0086] When the switch 1A is in the on state, the following equation (4) holds.

[0087]

number

[0088] That is, the error signal EOUT is a voltage obtained by multiplying the difference (VOUT-target-VOUT) between the output voltage VOUT and the target value VOUT_target by a constant.

[0089] Unlike the above-mentioned equation (2), the left side of equation (5) is EOUT-REF. Therefore, when the error amplifier 10 of the second embodiment is employed, it is preferable to set the power supply control device 1 in FIG. 4 so that EOUT_REF=REF. With this setting, as shown in this figure, output feedback control is applied so as to shift the output voltage VOUT in accordance with the load current Iload. In other words, the load line function is enabled.

[0090] In this way, with the error amplifier 10 of the second embodiment, it is possible to arbitrarily switch between enabling and disabling the load line function by controlling the on / off of the switch 1A.

[0091] <Soft start function> The power supply control device 1 has a so-called soft start function, which is a function for gradually increasing the output voltage VOUT at startup. For example, the soft start function can be realized by gradually increasing the reference voltage REF from 0 V to a predetermined value over an appropriate soft start time Tss at startup of the power supply control device 1.

[0092] However, as described above, when the error amplifier 10 of the second embodiment is adopted, it is necessary to set EOUT_REF=REF. Therefore, it is necessary to pay attention to compatibility (coexistence) with the soft start function.

[0093] 12 is a diagram showing a first example of the soft-start function in the power supply control device 1. In this diagram, from top to bottom, the output voltage VOUT, the reference voltage REF, the error signal EOUT (which may also be understood as the current detection signal ISNS), and the coil current IL are depicted.

[0094] This diagram depicts the behavior when the reference voltage REF is gradually increased from 0V over the soft start time Tss when the power supply control device 1 is started up, and EOUT_REF=REF after the power supply control device 1 has completed starting up.

[0095] In this case, it takes a relatively long time until the error signal EOUT exceeds the bias voltage EOUT_REF. To describe this in accordance with this figure, when REF = 0.5 × EOUT_REF, the positive coil current IL finally starts to flow, and the output voltage VOUT starts to rise. Also, when EOUT < EOUT_REF, the coil current IL can flow in the negative direction. Therefore, in the power supply control device 1, measures such as waiting for the driving of the output circuit 2 until EOUT ≥ EOUT_REF are necessary.

[0096] FIG. 13 is a diagram showing a second example of the soft start function in the power supply control device 1. In this figure, similar to the previous FIG. 12, the output voltage VOUT, the reference voltage REF, the error signal EOUT (which may be understood as the current detection signal ISNS), and the coil current IL are depicted in order from the top.

[0097] In this figure, the behavior when both the reference voltage REF and the bias voltage EOUT_REF gradually rise from 0V to a predetermined value with a soft start time Tss at the start of the power supply control device 1 is depicted. In this case, as the reference voltage REF rises, the output voltage VOUT also starts to rise without delay. Therefore, in principle, an ideal start-up operation is realized. However, it should be noted that it is not always easy to start the error signal EOUT generated by the error amplifier 10 from 0V.

[0098] <Switching power supply (modified example)> FIG. 14 is a diagram showing a modified example of the switching power supply A according to the present disclosure. The switching power supply A of this modified example is based on the previous FIG. 3, but the current sensor 20 has been changed to a single-phase output. Also, along with this change, the output feedback amplifier 31 of the duty signal generation circuit 30 has also been changed.

[0099] The current sensor 20 outputs the current detection signal ISNS as a single phase with the bias voltage EOUT_REF as a reference value. For example, when the coil current IL is flowing in the positive direction, ISNS > EOUT_REF. On the other hand, when the coil current IL is flowing in the negative direction, ISNS < EOUT_REF.

[0100] The output feedback amplifier 31 generates a control voltage VC so that the error signal EOUT input to the non-inverting input terminal (+) coincides with the current detection signal ISNS input to the inverting input terminal (-). In this way, the output feedback amplifier 31 is changed from a four-input type to a two-input type, unlike the output feedback amplifier 31 shown in FIG.

[0101] Even when this modification is adopted, the relationship between the error signal EOUT and the coil current IL remains the same as before (see FIG. 5). Therefore, by using the error amplifier 10 of the first embodiment (FIG. 6) or the second embodiment (FIG. 9), it is possible to easily switch between enabling and disabling the load line function in accordance with the mode switching signal MODE.

[0102] <Additional Notes> In the switching power supply according to the present disclosure, it is possible to arbitrarily switch between enabling and disabling a function that changes the output voltage according to the load current, that is, a so-called load line function.

[0103] [Appendix 1] A power supply control device (1) configured to control an output circuit (2) of a switching power supply (A) that generates an output voltage (VOUT) from an input voltage (VIN), an error amplifier (10) configured to generate an error signal (EOUT) corresponding to an error between a feedback voltage (FB) corresponding to the output voltage (VOUT) and a predetermined reference voltage (REF); a current sensor (20) configured to generate a current detection signal (ISNS) corresponding to a coil current (IL) flowing through the output circuit (2); a duty signal generating circuit (30) configured to receive the error signal (EOUT) and the current detection signal (ISNS) as inputs and generate a duty signal (PWM); a drive signal generating circuit (40) configured to receive the duty signal (PWM) and generate drive signals (GH, GL) for the output circuit (2); Equipped with The error amplifier (10) is switched between a first mode and a second mode in response to a mode switching signal (MODE), and in the first mode, generates the error signal (EOUT) using an integrated voltage (Vcal) obtained by integrating a difference value (REF-FB) obtained by subtracting the reference voltage (REF) from the feedback voltage (FB), and in the second mode, generates the error signal (EOUT) without using the integrated voltage (Vcal).

[0104] [Appendix 2] The duty signal generating circuit (30) an output feedback amplifier (31) configured to receive the error signal (EOUT) and the current detection signal (ISNS) as inputs and generate a control voltage (VC) in response thereto; a comparator (32) configured to compare the control voltage (VC) with a ramp voltage (VR) to generate the duty signal (PWM); The power supply control device (1) according to appendix 1, comprising:

[0105] [Appendix 3] The error amplifier (10) a first amplifier (11) having a non-inverting input terminal (+) connected to a terminal to which the reference voltage (REF) is applied, an inverting input terminal (-) connected to a terminal to which the feedback voltage (FB) is applied, and an output terminal connected to a terminal to which an integral voltage (Vcal) is applied; a second amplifier (12) having a first non-inverting input terminal (+) connected to the reference voltage (REF) application terminal, a first inverting input terminal (-) connected to the feedback voltage (FB) application terminal, a second non-inverting input terminal (+) connected to the integration voltage (Vcal) application terminal, a second inverting input terminal (-) connected to the node voltage (INN2) application terminal, and an output terminal connected to the error signal (EOUT) application terminal; a first resistor (13) connected between an application terminal of a bias voltage (EOUT_REF) and an application terminal of the node voltage (INN2); a second resistor (14) connected between the node voltage (INN2) application terminal and the error signal (EOUT) application terminal; a capacitor (15) connected between an application terminal of the integral voltage (Vcal) and a reference potential terminal or an application terminal of the bias voltage; a switch (16) connected between an application terminal of the integral voltage (Vcal) and an application terminal of the bias voltage (EOUT_REF) and configured to be turned on / off in response to the mode switching signal (MODE); The power supply control device (1) according to appendix 1 or 2, comprising:

[0106] [Appendix 4] 4. The power supply control device (1) according to claim 3, wherein the error signal (EOUT) coincides with the bias voltage (EOUT_REF) when the coil current (IL) is zero.

[0107] [Appendix 5] The error amplifier (10) an amplifier (17) having a non-inverting input terminal (+) connected to a terminal to which the reference voltage (REF) is applied, an inverting input terminal (-) connected to a terminal to which the feedback voltage (FB) is applied, and an output terminal connected to a terminal to which the error signal (EOUT) is applied; a resistor (18) connected between an application terminal of the feedback voltage (FB) and an application terminal of the node voltage (V1); a capacitor (19) connected between an application terminal of the node voltage (V1) and an application terminal of the error signal (EOUT); a switch (1A) connected between an application terminal of the node voltage (V1) and an application terminal of the error signal (EOUT) and configured to be turned on / off in response to the mode switching signal (MODE); The power supply control device (1) according to appendix 1 or 2, comprising:

[0108] [Appendix 6] The power supply control device (1) according to appendix 3 or 4, wherein the reference voltage (REF) and the bias voltage (EOUT_REF) rise to a predetermined value over a soft start time (Tss) when the power supply control device (1) is started up.

[0109] [Appendix 7] The current sensor (20) differentially outputs a positive-phase current detection signal (ISNSP) and a negative-phase current detection signal (ISNSN) as the current detection signal (ISNS), The power supply control device (1) according to any one of appendices 3, 4 and 6, wherein the output feedback amplifier (31) generates the control voltage (VC) so that a difference value (EOUT-EOUT_REF) between the error signal (EOUT) and the bias voltage (EOUT_REF) matches a difference value (ISNSP-ISNSN) between the positive-phase current detection signal (ISNSP) and the negative-phase current detection signal (ISNSN).

[0110] [Appendix 8] The current sensor (20) outputs the current detection signal (ISNS) in a single phase using the bias voltage (EOUT_REF) as a reference value, 7. The power supply control device (1) according to any one of appendices 3, 4, and 6, wherein the output feedback amplifier (31) generates the control voltage (VC) so that the error signal (EOUT) coincides with the current detection signal (ISNS).

[0111] [Appendix 9] The power supply control device (1) according to any one of appendices 1 to 8, wherein the mode switching signal (MODE) is set by an external input to a dedicated terminal, serial communication, or writing to a memory or a register.

[0112] [Appendix 10] A power supply control device (1) according to any one of appendices 1 to 9; The output circuit (2); A switching power supply (A).

[0113] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0114] 1 Output circuit 2 Power supply control device 10 Error Amplifier 11, 12 Amplifier 13, 14 Resistor 15 Capacitor 16 Switch 17 Amplifier 18 Resistance 19 Capacitor 1A switch 20 Current Sensor 30 Duty signal generation circuit 31 Output Feedback Amplifier 32 Comparator 40 Drive signal generation circuit 41 Controller 42 Level Shifter 43 buffers 44 inverter 50 Output feedback circuit 51, 52 Resistor 100 Load Line Function Circuit A Switching Power Supply C1 capacitor CS current source L1 coil MH, ML transistor (N-channel MOSFET) R0 resistance

Claims

1. A power supply control device configured to control an output circuit of a switching power supply that generates an output voltage from an input voltage, an error amplifier configured to generate an error signal corresponding to an error between a feedback voltage corresponding to the output voltage and a predetermined reference voltage; a current sensor configured to generate a current detection signal corresponding to a coil current flowing through the output circuit; a duty signal generating circuit configured to receive the error signal and the current detection signal and generate a duty signal; a drive signal generating circuit configured to receive the duty signal and generate a drive signal for the output circuit; Equipped with the error amplifier is switched between a first mode and a second mode in response to a mode switching signal, and in the first mode, generates the error signal using an integrated voltage obtained by integrating a difference value obtained by subtracting the reference voltage from the feedback voltage, and in the second mode, generates the error signal without using the integrated voltage.

2. The duty signal generating circuit an output feedback amplifier configured to receive the error signal and the current detection signal and generate a control voltage in response thereto; a comparator configured to compare the control voltage with a ramp voltage to generate the duty signal; The power control device of claim 1 , comprising:

3. The error amplifier a first amplifier having a non-inverting input terminal connected to a terminal to which the reference voltage is applied, an inverting input terminal connected to a terminal to which the feedback voltage is applied, and an output terminal connected to a terminal to which an integrating voltage is applied; a second amplifier having a first non-inverting input terminal connected to the reference voltage application terminal, a first inverting input terminal connected to the feedback voltage application terminal, a second non-inverting input terminal connected to the integration voltage application terminal, a second inverting input terminal connected to the node voltage application terminal, and an output terminal connected to the error signal application terminal; a first resistor connected between a bias voltage application terminal and the node voltage application terminal; a second resistor connected between the node voltage application terminal and the error signal application terminal; a capacitor connected between the application terminal of the integrated voltage and a reference potential terminal or the application terminal of the bias voltage; a switch connected between the application terminal of the integral voltage and the application terminal of the bias voltage, and configured to be turned on / off in response to the mode switching signal; The power control device of claim 1 , comprising:

4. 4. The power supply control device according to claim 3, wherein the error signal coincides with the bias voltage when the coil current is zero.

5. The error amplifier an amplifier having a non-inverting input terminal connected to a terminal to which the reference voltage is applied, an inverting input terminal connected to a terminal to which the feedback voltage is applied, and an output terminal connected to a terminal to which the error signal is applied; a resistor connected between the feedback voltage application terminal and the node voltage application terminal; a capacitor connected between an application terminal of the node voltage and an application terminal of the error signal; a switch connected between an application terminal of the node voltage and an application terminal of the error signal, the switch being configured to be turned on / off in response to the mode switching signal; The power control device of claim 1 , comprising:

6. 4. The power supply control device according to claim 3, wherein the reference voltage and the bias voltage are increased to predetermined values ​​over a soft start time when the power supply control device is started.

7. the current sensor differentially outputs a positive-phase current detection signal and a negative-phase current detection signal as the current detection signal; 4. The power supply control device according to claim 3, wherein the output feedback amplifier generates the control voltage so that a difference value between the error signal and the bias voltage coincides with a difference value between the positive-phase current detection signal and the negative-phase current detection signal.

8. the current sensor outputs the current detection signal in a single phase using the bias voltage as a reference value; 4. The power supply control device according to claim 3, wherein the output feedback amplifier generates the control voltage so that the error signal coincides with the current detection signal.

9. 2. The power supply control device according to claim 1, wherein the mode switching signal is set by an external input to a dedicated terminal, serial communication, or writing to a memory or a register.

10. A power supply control device according to any one of claims 1 to 9; the output circuit; A switching power supply comprising:

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