Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device that can prevent a contact barrier metal film from peeling off from a trench gate extraction electrode.SOLUTION: In a gate wiring lead-out region MGR defined in a semiconductor substrate SUB, a protrusion PRT protruding toward a gate lead-out contact member GCN is formed in a trench gate lead-out electrode TGI. The protrusion PRT is formed of a native oxide film SSM and a polysilicon film PSF. The gate lead-out contact member GCN is formed to cover the protrusion PRT with a barrier metal film BME interposed therebetween at the protrusion PRT.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, in a semiconductor device including an electron injection enhanced trench insulated gate bipolar transistor. [Background technology]

[0002] Among power semiconductor devices, there are semiconductor devices equipped with trench insulated gate bipolar transistors (IGBTs) as switching elements, and some of these semiconductor devices have an enhanced injection enhancement (IE) effect to reduce on-state voltage.

[0003] In this type of semiconductor device, a region is formed that prevents holes injected from the collector side from escaping to the emitter (electrode) side. This increases the concentration of holes accumulated in the drift layer in the semiconductor substrate, promoting the injection of electrons from the emitter side and increasing the electron concentration. The increased concentration of carriers (electrons and holes) causes conductivity modulation, which can reduce the on-state voltage. For this type of semiconductor device, various arrangement patterns of trench gate electrodes and the like have been proposed depending on the application.

[0004] The IGBT is formed in the cell region. A trench gate extraction electrode electrically connected to the trench gate electrode of the IGBT is formed in an area outside the cell region. The trench gate extraction electrode is formed to have a width (wide portion) wider than the width of the trench gate electrode. The trench gate extraction electrode is electrically connected to the gate electrode via a gate extraction contact member connected to the wide portion and a gate extraction wiring.

[0005] The gate lead contact member is formed in a contact opening formed in an interlayer insulating film covering the main surface of the semiconductor substrate. The gate lead contact member is electrically connected to the trench gate lead electrode via a contact barrier metal film. The gate lead wiring is formed on the interlayer insulating film with an interlayer barrier metal film interposed therebetween (Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2022-82244 Summary of the Invention [Problem to be solved by the invention]

[0007] In the semiconductor device described above, a heat treatment is performed to improve adhesion between the interlayer insulating film and the interlayer barrier metal film, and it has been confirmed that during this heat treatment, the contact barrier metal film peels off from the trench gate extraction electrode.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes a semiconductor substrate of a first conductivity type, a plurality of trench conductors, an interlayer insulating film, a contact barrier metal film, a plurality of contact members, and an interlayer barrier metal film. The semiconductor substrate of the first conductivity type has opposing first and second main surfaces, and a plurality of trenches are formed from the first main surface toward the second main surface. The plurality of trench conductors are formed in each of the trenches. An interlayer insulating film is formed to cover the first main surface of the semiconductor substrate, and a plurality of contact holes are formed therein, each reaching the plurality of trench conductors. The contact barrier metal film is formed on the inner wall of each of the plurality of contact holes. A plurality of contact members are formed in each of the plurality of contact holes, with the contact barrier metal film interposed therebetween, and are electrically connected to each of the plurality of trench conductors. The interlayer barrier metal film is formed in contact with the interlayer insulating film. The plurality of trenches formed in the semiconductor substrate include a first trench. The plurality of trench conductors include a first trench conductor formed in the first trench. The plurality of contact holes formed in the interlayer insulating film include a first contact hole reaching a first trench conductor. The plurality of contact members include a first contact member electrically connected to the first trench conductor. A convex portion protruding toward the first contact member is formed in the first trench conductor located at the bottom of the first contact hole. In the first contact hole, a contact barrier metal film is formed so as to cover the convex portion. The first contact member is formed in the first contact hole so as to cover the convex portion, with the contact barrier metal film interposed between the convex portion.

[0010] A method for manufacturing a semiconductor device according to another embodiment includes the following steps: preparing a semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposing each other; forming a plurality of trenches from the first main surface toward the second main surface in the semiconductor substrate; forming a trench conductor in each of the plurality of trenches; forming an interlayer insulating film to cover the first main surface of the semiconductor substrate; performing a first etching process on the interlayer insulating film to form a plurality of contact holes exposing each of the trench conductors; performing a second etching process on the exposed trench conductor; forming a contact barrier metal film on each of the inner walls of the plurality of contact holes; forming a plurality of contact members in each of the plurality of contact holes with the contact barrier metal film interposed therebetween; forming an interlayer barrier metal film to contact the interlayer insulating film and the plurality of contact members; performing a heat treatment after the interlayer barrier metal film is formed; forming the plurality of trenches includes forming a first trench; and forming the trench conductors includes forming the first trench conductor in the first trench. The step of forming the plurality of contact holes by a first etching process includes a step of forming the first contact holes exposing the first trench conductor. The step of forming a contact barrier metal film includes a step of forming a first contact barrier metal film on the inner walls of the first contact holes including the first trench conductor exposed at the bottom of the first contact hole. The step of forming the plurality of contact members includes forming the first contact members in the first contact holes with the first contact barrier metal film interposed therebetween. The step of performing a second etching process includes forming convex portions on the first trench conductor that protrude toward the first contact members. The step of forming the first contact barrier metal film includes forming the first contact members in the first contact holes with the first contact barrier metal film interposed therebetween so as to cover the convex portions. The step of forming the first contact members includes forming the first contact members in the first contact holes with the first contact barrier metal film interposed therebetween so as to cover the convex portions. [Effects of the Invention]

[0011] According to the semiconductor device of the embodiment, it is possible to prevent the contact barrier metal film from peeling off from the trench gate extraction electrode.

[0012] According to the method for manufacturing a semiconductor device according to another embodiment, it is possible to manufacture a semiconductor device that can prevent the contact barrier metal film from peeling off from the trench gate extraction electrode. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view illustrating an example of a semiconductor device according to each embodiment. [Figure 2] 1 is a partial plan view showing an example of a planar structure of a semiconductor device according to a first embodiment. [Figure 3] 3 is a cross-sectional view showing the cross-sectional structures along the cross-sectional lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc shown in FIG. 2 in the embodiment. [Figure 4] FIG. 10 is a partially enlarged cross-sectional view of a gate wiring lead-out region in the embodiment. [Figure 5] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 6] 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the embodiment. [Figure 7] 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the embodiment. [Figure 8] 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the embodiment. [Figure 9] 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the embodiment. [Figure 10] 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the embodiment. [Figure 11] 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the embodiment. [Figure 12] 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the embodiment. [Figure 13] 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the embodiment. [Figure 14] 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the embodiment. [Figure 15] 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the embodiment. [Figure 16] 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the embodiment. [Figure 17] FIG. 17 is a partially enlarged cross-sectional view of the step shown in FIG. 16 in the embodiment. [Figure 18] 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the embodiment. [Figure 19] FIG. 19 is a partially enlarged cross-sectional view of the step shown in FIG. 18 in the embodiment. [Figure 20] 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the embodiment. [Figure 21] FIG. 21 is a partially enlarged cross-sectional view of the step shown in FIG. 20 in the embodiment. [Figure 22] 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the embodiment. [Figure 23] 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the embodiment. [Figure 24] 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the embodiment. [Figure 25] 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the embodiment. [Figure 26] 10A and 10B are diagrams showing simulation results of film stress acting on a barrier metal film interposed between a trench gate lead electrode and a gate lead contact member in a semiconductor device according to a comparative example; [Figure 27]10A and 10B are diagrams showing the results of a simulation of film stress acting on a barrier metal film interposed between a trench gate extraction electrode and a gate extraction contact member in the embodiment; [Figure 28] FIG. 10 is a partial plan view showing an example of the planar structure of a semiconductor device according to a second embodiment. [Figure 29] 29 is a cross-sectional view showing the cross-sectional structures along the cross-sectional lines XXIXa-XXIXa, XXIXb-XXIXb, and XXIXc-XXIXc shown in FIG. 28 in the embodiment. [Figure 30] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 31] 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the embodiment. [Figure 32] 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in this embodiment. [Figure 33] 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in this embodiment. [Figure 34] FIG. 34 is a cross-sectional view showing a step performed after the step shown in FIG. 33 in this embodiment. [Figure 35] FIG. 35 is a cross-sectional view showing a step performed after the step shown in FIG. 34 in this embodiment. [Figure 36] FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in this embodiment. [Figure 37] FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36 in this embodiment. [Figure 38] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] As mentioned above, semiconductor devices with IE-type trench insulated gate bipolar transistors have various trench gate electrode arrangement patterns depending on the application. For example, there is a GE-type semiconductor device that prioritizes reducing on-state voltage. The GE-type has a structure in which a trench gate electrode electrically connected to the gate electrode and a trench emitter electrode electrically connected to the emitter electrode are arranged at a distance from each other.

[0015] Furthermore, a semiconductor device that emphasizes operational stability and balance is the GGEE type semiconductor device. The GGEE type has a structure in which one trench emitter electrode and another trench emitter electrode are arranged at a distance from each other, and one trench gate electrode and another trench gate electrode are arranged at a distance from each other. The one trench emitter electrode and another trench emitter electrode, and the one trench gate electrode and another trench gate electrode are arranged at a predetermined distance from each other.

[0016] Furthermore, semiconductor devices that prioritize high-speed performance include EGE type semiconductor devices. The EGE type has a structure in which one trench emitter electrode, a trench gate electrode, and another trench emitter electrode are arranged with a gap between them. This will be explained in detail below.

[0017] First, an example of the overall structure of a semiconductor device including an IE-type trench insulated gate bipolar transistor will be described. As shown in Figure 1, a semiconductor device SED (semiconductor substrate SUB) includes a cell region CER and a gate wiring lead-out region MGR.

[0018] An IE-type trench insulated gate bipolar transistor is formed in the cell region CER. An emitter electrode MEE is formed in the cell region CER so as to cover the cell region CER. The emitter electrode MEE is exposed at the bottom of an opening HK1 formed in an insulating film (not shown) covering the emitter electrode MEE (semiconductor substrate SUB).

[0019] The gate wiring lead-out region MGR is arranged to surround the cell region CER. Gate wiring lead-out lines MGI and gate electrodes MGE are formed in the gate wiring lead-out region MGR. The gate wiring lead-out lines MGI are electrically connected to the gate electrodes MGE. The gate electrodes MGE are exposed at the bottom of openings HK2 formed in an insulating film (not shown) covering the gate electrodes MGE (semiconductor substrate SUB).

[0020] Furthermore, the semiconductor device SED (semiconductor substrate SUB) has defined therein a peripheral element region PDR in which peripheral elements such as protection diodes or temperature sensing diodes are formed.

[0021] Embodiment 1 Here, an example of a GGEE type semiconductor device will be described. The GGEE type semiconductor device is applied to applications that require stable operation, etc. First, the cell region CER will be described.

[0022] (Cell Area CER) 2 and 3, in the cell region CER on the first main surface side of the semiconductor substrate SUB, one trench emitter electrode TEE (third trench conductor) and another trench emitter electrode TEE (fourth trench conductor) are arranged at a distance in one direction. The distance between the one trench emitter electrode TEE and the other trench emitter electrode TEE is distance L1. The one trench emitter electrode TEE and the other trench emitter electrode TEE each extend in another direction intersecting the one direction.

[0023] One trench gate electrode TGE (second trench conductor) and another trench gate electrode TGE are arranged at a distance in one direction. The distance between the one trench gate electrode TGE and the other trench gate electrode TGE is distance L2. Distance L2 is larger than distance L1. The one trench gate electrode TGE and the other trench gate electrode TGE each extend in another direction intersecting the one direction.

[0024] The one trench emitter electrode TEE and the other trench emitter electrode TEE, and the one trench gate electrode TGE and the other trench gate electrode TGE are arranged at a distance in one direction. An N+ type source diffusion layer SDR is formed in a region of the semiconductor substrate SUB located between the one trench gate electrode TGE and the other trench gate electrode TGE.

[0025] A P-type base diffusion layer BDR is formed from the bottom of the source diffusion layer SDR to a predetermined depth. A P+ layer PPR having a higher P-type impurity concentration is formed in the base diffusion layer BDR. An N-type hole barrier layer HBR is formed from the bottom of the base diffusion layer BDR to a predetermined depth. The hole barrier layer HBR is formed to reach the bottoms (lower ends) of one trench gate electrode TGE and the other trench gate electrode TGE. The region where the hole barrier layer HBR is formed is called the active region.

[0026] A P-type base diffusion layer BDR is formed from the first main surface to a predetermined depth in a region of the semiconductor substrate SUB located between the one trench emitter electrode TEE and the other trench emitter electrode TEE. A P+ layer PPR having a higher P-type impurity concentration is formed in the base diffusion layer BDR. An N-type hole barrier layer HBR is formed from the bottom of the base diffusion layer BDR to a further predetermined depth. The hole barrier layer HBR is formed to reach the bottoms (lower ends) of the one trench emitter electrode TEE and the other trench emitter electrode TEE. The region where the hole barrier layer HBR is formed is called an active region.

[0027] In a region of the semiconductor substrate SUB where the one trench emitter electrode TEE and the other trench emitter electrode TEE are arranged relative to the one trench gate electrode TGE and the other trench gate electrode TGE, a P-type floating diffusion layer FPR is formed from the first main surface to a position deeper than the bottoms (lower ends) of the one trench emitter electrode TEE and the other trench emitter electrode TEE. The floating diffusion layer FPR is called an inactive region.

[0028] (Gate wiring lead-out area MGR) In the gate wiring lead-out region MGR, a trench gate lead-out electrode TGI (first trench conductor) is formed. The trench gate lead-out electrode TGI is formed in the trench TRCW (first trench) with an insulating film GIF interposed therebetween. As will be described later, the trench gate lead-out electrode TGI has a protrusion PRT protruding toward the gate lead-out contact member GCN. The height H of the protrusion PRT is at least 50 nm or more.

[0029] 2 and 3, the trench gate extraction electrode TGI is electrically connected to the trench gate electrode TGE. The trench gate extraction electrode TGI (trench TRCW) has a first part TGN set to a first width W1 that is the same as the width of the trench gate electrode TGE (trench TRC), and a second part TGW set to a second width W2 that is wider than the first width W1.

[0030] (Peripheral Device Region PDR) In the peripheral element region PDR, wirings PIC are formed on the first main surface of the semiconductor substrate SUB with an insulating film IF and a silicon oxide film HDL interposed therebetween. The wirings PIC are electrically connected to peripheral elements (not shown), such as protection diodes or temperature sensing diodes.

[0031] (Structure on semiconductor substrate SUB) Next, the structure on the semiconductor substrate SUB will be described. An interlayer insulating film CIL is formed on the semiconductor substrate SUB so as to cover the trench gate electrodes TGE, trench emitter electrodes TEE, trench gate extraction electrodes TGI, and the like.

[0032] In the cell region CER, a contact opening CH2 and a contact opening CH3 are formed so as to penetrate the interlayer insulating film CIL. A gate contact member GDC is formed in the contact opening CH2 with a barrier metal film BME interposed therebetween. A common contact member CCN (second contact member) is formed in the contact opening CH3 with a barrier metal film BME interposed therebetween.

[0033] An emitter electrode MEE is formed on the surface of the interlayer insulating film CIL with an interlayer barrier metal film ABM interposed therebetween. The gate contact member GDC and the common contact member CCN are electrically connected to the emitter electrode MEE. The emitter electrode MEE is formed of, for example, an aluminum film or the like.

[0034] In the gate wiring lead-out region MGR, a contact opening CH1 is formed so as to penetrate the interlayer insulating film CIL. In the contact opening CH1, a gate lead-out contact member GCN (first contact member) is formed with a barrier metal film BME interposed therebetween. On the surface of the interlayer insulating film CIL, a gate lead-out wiring MGI is formed with an interlayer barrier metal film ABM interposed therebetween. The gate lead-out wiring MGI is formed of, for example, an aluminum film or the like.

[0035] In the peripheral element region PDR, a contact opening CH4 is formed so as to penetrate the interlayer insulating film CIL. In the contact opening CH4, a contact member DCN is formed with a barrier metal film BME interposed therebetween, the contact member DCN being in contact with the wiring PIC. On the surface of the interlayer insulating film CIL, a conductive layer MPL is formed with an interlayer barrier metal film ABM interposed therebetween. The contact member DCN is electrically connected to the conductive layer MPL.

[0036] The barrier metal film BME is formed as a laminated film of a titanium film TF (lower layer) and a titanium nitride film TNF (upper layer). The barrier metal film BME also includes titanium silicide TSF, which is formed by silicidizing a part of the titanium film TF (see FIG. 4). As the interlayer barrier metal film ABM, for example, a titanium tungsten film is formed.

[0037] Next, the structure of the trench gate lead electrode TGI in the gate wiring lead region MGR will be described. As shown in Fig. 4, the trench gate lead electrode TGI has a protrusion PRT that protrudes toward the gate lead contact member GCN.

[0038] A native oxide film SSM protruding toward the gate lead contact member GCN is formed on the trench gate lead electrode TGI. A polysilicon film PSF constituting the trench gate lead electrode TGI is formed so as to cover the side surfaces of the native oxide film SSM. The protrusion PRT is formed by the native oxide film SSM and the polysilicon film PSF. The protrusion PRT is formed along the direction in which the trench gate lead electrode TGI extends.

[0039] The gate lead contact member GCN is formed so as to cover the protrusion PRT with a barrier metal film BME interposed therebetween. As will be described later, the barrier metal film BME is formed so as to cover the protrusion PRT of the gate lead contact member GCN, thereby making it possible to suppress peeling of the barrier metal film BME.

[0040] On the other hand, a P-type collector diffusion layer CDR and an N-type buffer layer NBR are formed on the second main surface side of the semiconductor substrate SUB. An N-type region NSR serving as a drift layer is located between the floating diffusion layer FPR and the buffer layer NBR. A collector electrode BEL (back electrode) is formed so as to be in contact with the collector diffusion layer CDR (the second main surface of the semiconductor substrate SUB). The GGEE-type semiconductor device SED is configured as described above.

[0041] (Manufacturing method) Next, an example of a method for manufacturing the above-mentioned semiconductor device SED will be described. As shown in Fig. 5, a silicon oxide film SOF1 is formed so as to cover the first main surface of the semiconductor substrate SUB. Next, with the silicon oxide film SOF1 formed, a P-type region PR that will become a floating diffusion layer is formed by injecting P-type impurities. Furthermore, an N-type region NR that will become a hole barrier layer is formed by injecting N-type impurities.

[0042] Next, a hard mask (not shown) is formed to form trenches. Next, the semiconductor substrate SUB is etched using the hard mask as an etching mask to form trenches TRC (second trench, third trench, fourth trench) and trench TRCW (first trench) (see FIG. 6). Thereafter, the hard mask is removed. As a result, as shown in FIG. 6, the first main surface of the semiconductor substrate SUB in which the trenches TRC and TRCW are formed is exposed. The trenches TRCW are formed to have a width wider than the width of the trenches TRC.

[0043] Next, a predetermined heat treatment is performed to diffuse the P-type impurities in the P-type region PR, thereby forming a floating diffusion layer FPR. Also, the N-type impurities in the N-type region NR are diffused to form a hole barrier layer HBR (see FIG. 7). Next, as shown in FIG. 7, a thermal oxidation treatment is performed to form an insulating film IF on the first main surface of the semiconductor substrate SUB, including the inner wall surfaces of the trenches TRC and TRCW.

[0044] Next, a polysilicon film PSF (see FIG. 9) is formed so as to cover the semiconductor substrate SUB and to fill the trenches TRC and TRCW, respectively. Here, the polysilicon film PSF is formed in two steps.

[0045] As shown in FIG. 8, first, a first-layer polysilicon film PS1 is formed. The semiconductor substrate SUB on which the polysilicon film PS1 is formed is removed from a film-forming apparatus (not shown) and temporarily exposed to the atmosphere. At this time, a natural oxide film SSM is formed on the surface of the polysilicon film PS1. Furthermore, the polysilicon film PS1 may be subjected to thermal oxidation treatment or oxygen plasma treatment (ashing treatment) to promote oxidation of the surface of the polysilicon film PS1, making it easier to form the protrusion PRT (see FIG. 4) by the natural oxide film SSM. Next, as shown in FIG. 9, a second-layer polysilicon film PS2 is formed to cover the polysilicon film PS1.

[0046] In this way, a polysilicon film PSF consisting of two layers, the polysilicon film PS1 and the polysilicon film PS2, is formed. At this time, the position of the upper surface of the polysilicon film PSF covering the relatively wide trench TRCW is lower than the position of the upper surface of the polysilicon film PSF covering the relatively narrow trench TRC.

[0047] 10, an etching process is performed on the entire surface of the polysilicon film PSF, thereby removing the portion of the polysilicon film PSF located on the first main surface of the semiconductor substrate SUB. At this time, the native oxide film SSM formed on the surface of the first-layer polysilicon film PS1 is exposed.

[0048] 11, the polysilicon film PSF is further subjected to an over-etching process. As a result, the upper surfaces of the polysilicon film PSF left in the trenches TRC and TRCW are positioned lower than the first main surface of the semiconductor substrate SUB. Furthermore, the position of the upper surface of the polysilicon film PSF left in the trenches TRCW is lower than the position of the upper surface of the polysilicon film PSF left in the trenches TRC.

[0049] 12, a silicon oxide film HDL is formed to cover the insulating film IF. Next, a polysilicon film PSF2 is formed to cover the silicon oxide film HDL. Next, a photolithography process is performed to form a photoresist pattern PHR1 for patterning wiring.

[0050] 13, the polysilicon film PSF2 is etched using the photoresist pattern PHR1 as an etching mask, thereby forming the wiring PIC. Next, as shown in Fig. 14, the silicon oxide film HDL is etched using the photoresist pattern PHR1 as an etching mask, and further the insulating film IF is etched, thereby removing the portions of the silicon oxide film HDL and the insulating film IF located on the first main surface of the semiconductor substrate SUB.

[0051] At this time, the native oxide film SSM protruding from the upper surface of the polysilicon film PSF is also removed together with the insulating film IF. Thereafter, the photoresist pattern PHR1 is removed. As a result, a trench emitter electrode TEE (third trench conductor, fourth trench conductor) is formed in the trench TRC with the trench insulating film EIF (insulating film IF) interposed therebetween. A trench gate electrode TGE (second trench conductor) is formed in the trench TRC with the insulating film GIF (insulating film IF) interposed therebetween. A trench gate lead electrode TGI (first trench conductor) is formed in the trench TRCW with the insulating film GIF (insulating film IF) interposed therebetween.

[0052] 15, a silicon oxide film SOF2 is formed to cover the first main surface of the semiconductor substrate SUB. Next, a predetermined photolithography process is performed to form a photoresist pattern (not shown) for forming a source diffusion layer and a base diffusion layer. Next, P-type impurities are implanted using the photoresist pattern as an implantation mask. Furthermore, N-type impurities are implanted. Thereafter, the photoresist pattern is removed.

[0053] As a result, a source diffusion layer SDR and a base diffusion layer BDR are formed in a region of the semiconductor substrate SUB located between the one trench gate electrode TGE and the other trench gate electrode TGE. A base diffusion layer BDR is formed in a region of the semiconductor substrate SUB located between the one trench emitter electrode TEE and the other trench emitter electrode TEE. The source diffusion layer SDR is formed to a predetermined depth from the first main surface. The base diffusion layer BDR is formed to an even deeper position from the bottom of the base diffusion layer BDR. Thereafter, the silicon oxide film SOF2 is removed.

[0054] Next, an interlayer insulating film CIL is formed so as to cover the first main surface of the semiconductor substrate SUB (see FIG. 16). As the interlayer insulating film CIL, for example, a PSG film (Phospho Silicate Glass) is formed. Next, a predetermined photolithography process is performed to form a photoresist pattern PHR2 for forming contact openings in the interlayer insulating film CIL (see FIG. 16).

[0055] 16, the interlayer insulating film CIL is subjected to an etching process (first etching process) using the photoresist pattern PHR2 as an etching mask. This etching process simultaneously forms contact openings CH1 (first contact openings), CH2, CH3 (second contact openings), and CH4. At this time, the contact opening CH3 is formed so as to straddle the trench emitter electrode TEE and the region of the semiconductor substrate SUB.

[0056] This etching process is performed using an etching gas (first gas) containing fluorocarbon (first fluorocarbon). In this etching process, the etching rate of the silicon oxide film becomes sufficiently higher than the etching rate of silicon. As a result, as shown in FIG. 17, in the contact opening CH3, the trench insulating film EIF located between the trench emitter electrode TEE and the region of the semiconductor substrate SUB is receded by over-etching. At this time, part of the trench insulating film EIF is left as residue on the sidewall surface of the trench emitter electrode TEE. On the other hand, in the contact opening CH1, the native oxide film SSM is thin (narrow), and therefore is hardly etched.

[0057] 18, the exposed portions at the bottoms of the contact openings CH1, CH2, and CH3 are subjected to an etching process (second etching process). This etching process is performed using an etching gas (second gas) containing at least one of chlorine and hydrogen bromide. In this etching process, the etching rate of silicon is made sufficiently higher than the etching rate of the silicon oxide film.

[0058] 19, the polysilicon film of the exposed trench gate extraction electrode TGI is etched in the contact opening CH1. At this time, a portion of the polysilicon film is left on the sidewall surface of the native oxide film SSM, and the remaining portion of the polysilicon film and the native oxide film SSM form a protrusion PRT. The polysilicon film is etched so that the height H of the protrusion PRT is finally at least 50 nm or more. The upper limit of the height H of the protrusion PRT is set to a height that allows the protrusion PRT to be satisfactorily covered by the barrier metal film BME.

[0059] In the contact opening CH3, the exposed polysilicon film of the trench emitter electrode TEE and the semiconductor substrate SUB are etched. At this time, residues RES of the trench insulating film EIF appear as thorns.

[0060] 20, the exposed portions at the bottoms of the contact openings CH1, CH2, and CH3 are further etched (third etching process). This etching process is performed using an etching gas (third gas) containing a fluorocarbon (second fluorocarbon). In this etching process, the etching rate of the silicon oxide film is made sufficiently higher than the etching rate of silicon.

[0061] 21, the residue RES of the trench insulating film EIF is removed at the bottom of the contact opening CH3. At the bottom of the contact opening CH1, the polysilicon film is formed on the sidewall surface of the protruding native oxide film SSM, and therefore the native oxide film SSM cannot be completely removed and remains as a protrusion PRT.

[0062] Next, P+ type impurities are injected through the contact openings CH1 to CH3. As a result, a P+ layer PPR having a higher impurity concentration than the impurity concentration of the base diffusion layer BDR is formed in the P type base diffusion layer BDR exposed at the bottom of the contact opening CH3. Also, a P+ layer PPR having a higher impurity concentration than the impurity concentration of the base diffusion layer BDR is formed in the P type base diffusion layer BDR exposed at the bottom of the contact opening CH2.

[0063] At this time, the P+ type impurities are also implanted into the exposed side surface of the N-type source diffusion layer SDR at the bottom of the contact opening CH2, which may result in the N-type impurities in the source diffusion layer SDR, which comes into contact with the gate contact member GDC, being neutralized by the P+ type impurities, resulting in an increase in contact resistance between the source diffusion layer SDR and the gate contact member GDC.

[0064] 22, the interlayer insulating film CIL is subjected to a wet etching process to widen the opening width of the contact opening CH2 and the like. Widening the opening width of the contact opening CH2 exposes the upper surface of the source diffusion layer SDR into which P+ type impurities are not implanted. This reduces the contact resistance between the gate contact member GDC and the source diffusion layer SDR. At this time, the protrusion PRT exposed at the bottom of the contact opening CH1 is not removed because the sidewall surface of the native oxide film SSM is covered with a polysilicon film (see FIG. 21).

[0065] 23, a barrier metal film BME is formed so as to cover the interlayer insulating film CIL including the inner wall surfaces of the contact openings CH1 to CH3. As the barrier metal film BME, for example, a stacked film of a titanium nitride film TNF (TiN: upper layer) and a titanium film TF (Ti: lower layer) is formed. Next, a tungsten film WF is formed so as to cover the barrier metal film BME. Next, the tungsten film WF etc. is subjected to an etch-back process on the entire surface, thereby removing the tungsten film WF and the barrier metal film BME located on the upper surface of the interlayer insulating film CIL.

[0066] 24, a gate lead-out contact member GCN is formed in the contact opening CHI. In the contact opening CHI, the barrier metal film BME is formed so as to cover the protrusion portion PRT. The gate lead-out contact member GCN is formed with the barrier metal film BME covering the protrusion portion PRT interposed therebetween. In the contact opening CH2, a gate contact member GDC is formed. In the contact opening CH3, a shared contact member CCN is formed.

[0067] 25, an interlayer barrier metal film ABM is formed to cover the interlayer insulating film CIL. As the interlayer barrier metal film ABM, for example, a titanium tungsten (TiW) film is formed. Next, in order to improve the adhesion between the interlayer barrier metal film ABM and the interlayer insulating film CIL, the interlayer barrier metal film ABM is subjected to a heat treatment by, for example, lamp annealing at a temperature of 650° C. or higher.

[0068] Thereafter, for example, an aluminum film (not shown) is formed so as to cover the interlayer barrier metal film ABM, and the aluminum film is patterned to form an emitter electrode MEE, a gate lead-out wiring MGI, a gate electrode MGE, etc. (See FIG. 3, etc.). Next, an N-type buffer layer NBR and a P-type collector diffusion layer CDR are formed on the second main surface side of the semiconductor substrate SUB. Furthermore, a collector electrode BEL (back surface electrode) is formed, thereby completing the semiconductor device SED shown in FIGS. 1 to 3.

[0069] Next, the operation of the semiconductor device SED described above will be explained. First, when the trench insulated gate bipolar transistor is turned on, a voltage equal to or higher than the threshold voltage is applied to the gate electrode MGE. As a result, electrons are injected from the source diffusion layer SDR through the channel into the N-type region NSR (drift layer) in the semiconductor substrate SUB, the PN junction between the N-type region NSR and the collector diffusion layer CDR is forward biased, and holes are injected from the collector diffusion layer CDR into the N-type region NSR.

[0070] The injected holes are prevented from escaping to the source diffusion layer SDR (emitter) side by the P-type floating diffusion layer FPR, and holes accumulate in the N-type region NSR and floating diffusion layer FPR, increasing the hole concentration. When the hole concentration in the N-type region NSR etc. increases, the injection of electrons from the source diffusion layer SDR is promoted, and the electron concentration also increases. In this way, the increase in the carrier concentration in the N-type region NSR etc. causes conductivity modulation, resulting in an on-state.

[0071] Next, to turn off the trench insulated gate bipolar transistor, a voltage lower than the threshold voltage is applied to the gate electrode MGE. This causes the channel to disappear. The carriers (holes) accumulated in the N-type region NSR and other regions are discharged to the emitter electrode MEE by the parasitic P-channel MOSFET (floating diffusion layer FPR, trench emitter electrode TEE at the emitter potential, base diffusion layer BDR, etc.) formed on the trench emitter electrode TEE side, turning the transistor off.

[0072] In the above-mentioned semiconductor device SED, the inventors have confirmed that when heat treatment (at a temperature of 650°C or higher) is performed on the interlayer barrier metal film ABM, a portion of the barrier metal film BME formed on the trench gate extraction electrode TGI is metal silicided, causing voids to occur in the barrier metal film BME.

[0073] The barrier metal film BME is formed as a stacked film of a titanium film TF (lower layer) and a titanium nitride film TNF (upper layer). In particular, at the bottom of the contact opening CH1, the titanium film TF is formed so as to be in contact with the trench gate lead-out electrode TGI. The trench gate lead-out electrode TGI is formed of a polysilicon film PSF (see FIG. 9). Therefore, when the interlayer barrier metal film ABM is subjected to a heat treatment, the titanium film TF reacts with silicon (Si) to form titanium silicide TSF (TiSi).

[0074] The inventors suspected that the generation of voids was due to the formation of titanium silicide in part of the barrier metal film BME during heat treatment, and evaluated the film stress through simulation.

[0075] 26 shows a simulation result according to a comparative example. In the comparative example, the portion of the trench gate extraction electrode TGI located on the bottom surface of the contact opening CH1 is a flat surface. In addition, the titanium film TF of the barrier metal film BME is formed so as to be in contact with the trench gate extraction electrode TGI (polysilicon film PSF).

[0076] The titanium film TF is converted into titanium silicide by heat treatment to form titanium silicide TSF, which generates film stress in the titanium film TF. In particular, it was found that film stress is concentrated on the titanium nitride film TNF side in the portion of the titanium film TF (including titanium silicide TSF) located on the bottom surface of the contact opening CH1. The inventors believed that the film stress concentrated in this portion was the cause of the generation of voids between the titanium film and the titanium nitride film TNF.

[0077] Therefore, the inventors evaluated and investigated a structure for alleviating the film stress occurring on the titanium nitride film TNF side for the portion of the titanium film TF (including titanium silicide) located on the bottom surface of the contact opening CH1. As a result, it was found that the film stress occurring on the titanium nitride film TNF side can be alleviated by forming a convex portion having a predetermined height in the portion of the trench gate extraction electrode TGI located on the bottom surface of the contact opening CH1. In other words, it was found that the film stress can be alleviated if the height H of the convex portion PRT is at least 50 nm or more.

[0078] 27 shows a simulation result according to the embodiment. In the embodiment, a protrusion PRT is formed in a portion of the trench gate lead electrode TGI located on the bottom surface of the contact opening CH1. In addition, of the barrier metal film BME, the titanium film TF is formed so as to cover the protrusion PRT and to be in contact with the trench gate lead electrode TGI (polysilicon film PSF).

[0079] As shown in Figure 27, in the titanium film TF formed to cover the protrusion PRT, film stress is concentrated on the trench gate extraction electrode TGI side at the corner of the bottom surface of the contact opening CH1, and it has been found that in the part of the titanium film TF covering the protrusion PRT, the film stress occurring on the titanium nitride film TNF side is reduced.

[0080] Based on this evaluation result, the inventors first formed a protrusion PRT using the natural oxide film SSM formed when forming the trench gate extraction electrode TGI, etc. They confirmed that by forming a barrier metal film BME so as to cover the protrusion PRT, it is possible to suppress the generation of voids between the titanium film TF (including titanium silicide) and the titanium nitride film TNF.

[0081] Suppressing the generation of voids can reduce the leakage current (ICES), which is the leakage current that flows between the collector electrode BEL and the emitter electrode MEE when a predetermined voltage is applied between the collector electrode BEL and the emitter electrode MEE with the gate electrode MGE and the emitter electrode MEE short-circuited.

[0082] Furthermore, in a structure in which the trench gate lead-out electrode TGI is formed in the contact opening CH1, the generation of voids can be suppressed, thereby reducing the density of the current flowing through the gate lead-out contact member GCN.

[0083] In the above-described semiconductor device SED, a laminated film of a titanium film Ti and a titanium nitride film TNF is taken as an example of the barrier metal film BME. The barrier metal film BME may be a titanium tungsten film (TiW). In this case, tungsten silicide is formed in the titanium tungsten film by heat treatment. The barrier metal film BME may also be a laminated film of a tungsten film (W) and a tungsten nitride film (WN). In this case, tungsten silicide is formed in the tungsten film by heat treatment.

[0084] Furthermore, a titanium film may be used. In this case, titanium nitride (TiN) and titanium silicide (TiSi) are formed by annealing in a nitrogen atmosphere. A tungsten (W) film may also be used. In this case, tungsten nitride (WN) and tungsten silicide (WSi) are formed by annealing in a nitrogen atmosphere.

[0085] Also, a tungsten film WF was formed as a gate lead contact member GCN etc. Alternatively, a tungsten nitride film (WN) may be used.

[0086] Embodiment 2 Here, an example of a GE type semiconductor device will be described. First, the cell region CER will be described.

[0087] (Cell Area CER) 28 and 29, a trench gate electrode TGE (second trench conductor) and a trench emitter electrode TEE (third trench conductor) are arranged in one direction with an interval L3 therebetween, and the trench gate electrode TGE and the trench emitter electrode TEE each extend in another direction intersecting the one direction.

[0088] In a region of the semiconductor substrate SUB located between the trench gate electrode TGE and the trench emitter electrode TEE, an N+ type source diffusion layer SDR is formed from the first main surface to a predetermined depth. A P-type base diffusion layer BDR is formed from the bottom of the source diffusion layer SDR to a further predetermined depth. A P+ layer PPR having a higher P-type impurity concentration is formed in the base diffusion layer BDR.

[0089] An interlayer insulating film CIL is formed on the semiconductor substrate SUB so as to cover the trench gate electrode TGE, the trench emitter electrode TEE, etc. A contact opening CH5 is formed so as to penetrate the interlayer insulating film CIL. A common contact member CCN (second contact member) is formed in the contact opening CH5 with a barrier metal film BME interposed therebetween.

[0090] In addition, the structure of the gate wiring pull-out region MGR in which a trench gate pull-out electrode TGI (first trench conductor) having a protrusion PRT is formed, and the structure of the peripheral element region PDR, etc. other than the cell region CER are the same as the structures shown in Figures 2, 3 and 4, so the same symbols are used for the same components and their descriptions will not be repeated unless necessary.

[0091] (Manufacturing method) Next, an example of a manufacturing method of the above-mentioned semiconductor device SED will be described. The semiconductor device SED is manufactured by substantially the same manufacturing method as the manufacturing method of the above-mentioned semiconductor device SED, except that the arrangement pattern of the trench gate electrode TGE (trench TRC) and the trench emitter electrode TEE (trench TRC) is different from the arrangement pattern of the trench gate electrode TGE and the trench emitter electrode TEE in the above-mentioned semiconductor device SED.

[0092] 5 to 14, a silicon oxide film SOF2 is formed so as to cover the first main surface of the semiconductor substrate SUB, as shown in Fig. 30. Next, a predetermined photolithography process is performed to form a photoresist pattern (not shown) for forming the base diffusion layer BDR.

[0093] Next, using the photoresist pattern as an implantation mask, P-type impurities are implanted to form a base diffusion layer BDR. Furthermore, N-type impurities are implanted to form a source diffusion layer SDR. Thereafter, the photoresist pattern is removed. Furthermore, the silicon oxide film SOF2 is removed. As a result, the base diffusion layer BDR and the source diffusion layer SDR are formed in the region of the semiconductor substrate SUB located between the trench gate electrode TGE and the trench emitter electrode TEE adjacent to each other.

[0094] Next, an interlayer insulating film CIL (see FIG. 31) is formed so as to cover the first main surface of the semiconductor substrate SUB. Next, a predetermined photolithography process is performed to form a photoresist pattern PHR2 (see FIG. 31) for forming contact openings in the interlayer insulating film CIL. Next, as shown in FIG. 31, an etching process (first etching process) is performed on the interlayer insulating film CIL using the photoresist pattern PHR2 as an etching mask.

[0095] This etching process simultaneously forms the contact opening CH1 (first contact opening), the contact opening CH5 (second contact opening), and the contact opening CH4. At this time, the contact opening CH5 is formed so as to straddle the trench emitter electrode TEE and the region of the semiconductor substrate SUB.

[0096] As described above, this etching process is performed using an etching gas (first gas) containing a fluorocarbon (first fluorocarbon). At this time, the native oxide film SSM is hardly etched, particularly at the contact opening CH1, because the contact opening CH1 is narrow.

[0097] 32, the portions exposed at the bottoms of the contact openings CH1 and CH5 are subjected to an etching process (second etching process). As described above, this etching process is performed using an etching gas (second gas) containing at least one of chlorine and hydrogen bromide.

[0098] This etching process etches the exposed polysilicon film of the trench gate extraction electrode TGI at the contact opening CH1. At this time, a portion of the polysilicon film remains on the sidewall surface of the native oxide film SSM (see FIG. 19). At the contact opening CH5, the exposed polysilicon film of the trench emitter electrode TEE and a portion of the semiconductor substrate SUB are etched. Furthermore, residues RES of the trench insulating film EIF appear as spikes (see FIG. 19).

[0099] 33, the portions exposed at the bottoms of the contact openings CH1 and CH5 are further etched (third etching process). As described above, this etching process is performed using an etching gas (third gas) containing a fluorocarbon (second fluorocarbon).

[0100] This etching process removes residues RES of the trench insulating film EIF at the bottom of the contact opening CH5. At the bottom of the contact opening CH1, the native oxide film SSM cannot be completely removed because a polysilicon film is formed on the sidewall surface of the protruding native oxide film SSM, and the native oxide film SSM remains as a protrusion PRT.

[0101] Next, P+ type impurities are injected through the contact opening CH5 etc. As a result, a P+ layer PPR having an impurity concentration higher than the impurity concentration of the base diffusion layer BDR is formed in the P type base diffusion layer BDR exposed at the bottom of the contact opening CH3.

[0102] 34, the interlayer insulating film CIL is subjected to a wet etching process to widen the opening width of the contact opening CH5 and the like. This exposes the upper surface of the source diffusion layer SDR into which P+ type impurities are not implanted. At this time, the protrusion PRT exposed at the bottom of the contact opening CH1 is not removed because the sidewall surface of the native oxide film SSM is covered with a polysilicon film (see FIG. 21).

[0103] Next, a process similar to that shown in Fig. 23 is performed. As a result, a barrier metal film BME is formed so as to cover the interlayer insulating film CIL including the inner wall surfaces of the contact openings CH1 and CH5, etc., as shown in Fig. 35. Next, a tungsten film WF is formed so as to cover the barrier metal film BME.

[0104] Next, a process similar to that shown in FIG. 24 is performed. As a result, as shown in FIG. 36, a gate lead-out contact member GCN is formed in the contact opening CHI. In the contact opening CHI, a barrier metal film BME is formed so as to cover the protrusion portion PRT. The gate lead-out contact member GCN is formed with the barrier metal film BME covering the protrusion portion PRT interposed therebetween. In the contact opening CH5, a shared contact member CCN is formed.

[0105] 25 is performed. As a result, an interlayer barrier metal film ABM is formed so as to cover the interlayer insulating film CIL. Next, in order to improve the adhesion between the interlayer barrier metal film ABM and the interlayer insulating film CIL, the interlayer barrier metal film ABM is subjected to a heat treatment, for example, by lamp annealing at a temperature of 650° C. or higher.

[0106] Thereafter, an emitter electrode MEE, a gate lead wiring MGI, a gate electrode MGE, etc. are formed on the interlayer barrier metal film ABM (see FIG. 29, etc.). Furthermore, an N-type buffer layer NBR, a P-type collector diffusion layer CDR, and a collector electrode BEL (rear electrode) are formed on the second main surface side of the semiconductor substrate SUB, thereby completing the semiconductor device SED shown in FIGS. 28 and 29.

[0107] In the semiconductor device SED described above, a protrusion PRT is formed on the trench gate extraction electrode TGI. The barrier metal film BME is formed so as to cover the protrusion PRT. As a result, as described in the first embodiment, in the titanium film TF, film stress is concentrated on the trench gate extraction electrode TGI side at the corner of the bottom surface of the contact opening CH1, and in the portion of the titanium film TF covering the protrusion PRT, film stress occurring on the titanium nitride film TNF side is reduced.

[0108] As a result, it is possible to suppress the generation of voids between the titanium film TF (including titanium silicide) and the titanium nitride film TNF. By suppressing the generation of voids, it is possible to reduce leakage current (ICES). In addition, it is possible to reduce the density of the current flowing through the gate lead contact member GCN.

[0109] Embodiment 3 Here, an example of an EGE type semiconductor device will be described. The EGE type semiconductor device SED is used for applications requiring high speed. The cell region CER will be described.

[0110] (Cell Area CER) As shown in FIG. 38, in the cell region CER, one trench emitter electrode TEE (third trench conductor), a trench gate electrode TGE (second trench conductor), and another trench emitter electrode TEE are formed.

[0111] The one trench emitter electrode TEE, the trench gate electrode TGE and the other trench emitter electrode TEE are formed at an interval L3 from one another in such a manner that the trench gate electrode TGE is located between the one trench emitter electrode TEE and the other trench emitter electrode TEE.

[0112] In addition, the structure of the gate wiring pull-out region MGR in which a trench gate pull-out electrode TGI (first trench conductor) having a protrusion PRT is formed, and the structure of the peripheral element region PDR, etc. other than the cell region CER are the same as the structures shown in Figures 2, 3 and 4, so the same symbols are used for the same components and their descriptions will not be repeated unless necessary.

[0113] Next, an example of a manufacturing method of the semiconductor device SED described above will be described. The semiconductor device SED can be manufactured by substantially the same manufacturing method as the manufacturing method of the semiconductor device SED described in the first embodiment, except that the layout pattern of the trench gate electrode TGE (trench TRC) and the trench emitter electrode TEE (trench TRC) is different from the layout pattern of the trench gate electrode TGE and the trench emitter electrode TEE in the semiconductor device SED shown in FIG. 3 etc.

[0114] In the semiconductor device SED described above, a protrusion PRT is formed on the trench gate extraction electrode TGI. The barrier metal film BME is formed so as to cover the protrusion PRT. As a result, as described in the first embodiment, in the titanium film TF, film stress is concentrated on the trench gate extraction electrode TGI side at the corner of the bottom surface of the contact opening CH1, and in the portion of the titanium film TF covering the protrusion PRT, film stress occurring on the titanium nitride film TNF side is reduced.

[0115] As a result, it is possible to suppress the generation of voids between the titanium film TF (including titanium silicide TSF) and the titanium nitride film TNF. By suppressing the generation of voids, it is possible to reduce leakage current (ICES). In addition, it is possible to reduce the density of the current flowing through the gate extraction contact member GCN.

[0116] The semiconductor devices and manufacturing methods thereof described in the respective embodiments can be combined in various ways as required.

[0117] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0118] SED semiconductor device, CER cell region, MGR gate wiring lead region, PDR peripheral element region, MEE emitter electrode, MGE gate electrode, MGI gate lead wiring, CH1 contact opening, GCN gate lead contact material, BME barrier metal, TRCW trench, GIF insulating film, TGI trench gate lead electrode, TGN part 1, TGW part 2, SUB semiconductor substrate, TRC trench, GIF trench insulating film, TGE trench gate electrode, EIF trench insulating film, TEE trench emitter electrode, SDR source diffusion layer, BDR base diffusion layer, PPR P+ layer, HBR hole barrier layer, FPR floating diffusion layer, NBR N buffer layer, CDR collector diffusion layer, NSR N-type region, BEL collector electrode, CIL interlayer insulating film, ABM interlayer barrier metal film, CH2 contact opening, GDC gate contact material, CH3 contact opening, CCN common contact material, BME barrier metal film, TNF Titanium nitride film, TF titanium film, TSF titanium silicide, PRT convex portion, CH4 contact opening, DCN contact material, PIC wiring, MPL conductive layer, CH5 contact opening, SOF1 silicon oxide film, NR N-type region, PR P-type region, IF insulating film, PSF, PS1, PS2 polysilicon film, SSM native oxide film, HLD silicon oxide film, PSF2 polysilicon film, PHR1 photoresist, SOF2 silicon oxide film, PHR2 photoresist, RES residue, WF tungsten film, W1 first width, W2 second width, L1, L2, L3 spacing, H height.

Claims

1. a semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposed to each other, and a plurality of trenches formed from the first main surface toward the second main surface; a plurality of trench conductors formed in each of the plurality of trenches; an interlayer insulating film formed to cover the first main surface of the semiconductor substrate, the interlayer insulating film having a plurality of contact holes formed therein that reach the plurality of trench conductors, respectively; a contact barrier metal film formed on an inner wall of each of the plurality of contact holes; a plurality of contact members formed in each of the plurality of contact holes with the contact barrier metal film interposed therebetween and electrically connected to each of the plurality of trench conductors; an interlayer barrier metal film formed in contact with the interlayer insulating film; Equipped with the plurality of trenches formed in the semiconductor substrate include a first trench; the plurality of trench conductors include a first trench conductor formed in the first trench; the plurality of contact holes formed in the interlayer insulating film include a first contact hole reaching the first trench conductor; the plurality of contact members include a first contact member electrically connected to the first trench conductor; a protrusion protruding toward the first contact member is formed on the first trench conductor located at the bottom of the first contact hole; In the first contact hole, the contact barrier metal film is formed so as to cover the protrusion, The first contact member is formed in the first contact hole so as to cover the protruding portion with the contact barrier metal film interposed therebetween.

2. 2. The semiconductor device according to claim 1, wherein the height of said protrusion is at least 50 nm.

3. The semiconductor device according to claim 1 , wherein said protrusion includes an insulating film.

4. 2. The semiconductor device according to claim 1, wherein said contact barrier metal film contains a metal that can be silicided.

5. 5. The semiconductor device according to claim 4, wherein said contact barrier metal film comprises a laminate of titanium and titanium nitride.

6. 2. The semiconductor device according to claim 1, wherein said first contact member includes one of tungsten and tungsten nitride.

7. a trench insulated gate bipolar transistor having an emitter electrode and a gate electrode formed on the first main surface and a collector electrode formed on the second main surface; the first trench conductor is electrically connected to the gate electrode via the first contact member; the plurality of trenches includes a second trench; the plurality of trench conductors include second trench conductors formed in the second trenches and electrically connected to the first trench conductors; the first trench conductor has a first width; the second trench conductor has a second width; The semiconductor device according to claim 1 , wherein said first width is greater than said second width.

8. the plurality of trenches includes a third trench; the plurality of trench conductors include a third trench conductor formed in the third trench with a trench insulating film interposed therebetween; the plurality of contact holes include a second contact hole formed across the third trench conductor, the trench insulating film, and a region of the semiconductor substrate; 8. The semiconductor device according to claim 7, wherein the plurality of contact members include a second contact member formed in the second contact hole, electrically connected to the third trench conductor, and electrically connected to the emitter electrode.

9. the plurality of trenches include a fourth trench formed at a distance from the third trench; the plurality of trench conductors include a fourth trench conductor formed in the fourth trench and electrically connected to the emitter electrode; 9. The semiconductor device according to claim 8, wherein a first impurity region of the second conductivity type serving as a base is formed in the region of the semiconductor substrate located between the third trench conductor and the fourth trench conductor.

10. the second trench conductor is formed at a distance from the third trench conductor; 9. The semiconductor device according to claim 8, wherein a second impurity region of the first conductivity type serving as an emitter is formed in the region of the semiconductor substrate located between the third trench conductor and the second trench conductor.

11. providing a semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposed to each other; forming a plurality of trenches from the first main surface toward the second main surface in the semiconductor substrate; forming a trench conductor in each of the plurality of trenches; forming an interlayer insulating film so as to cover the first main surface of the semiconductor substrate; performing a first etching process on the interlayer insulating film to form a plurality of contact holes exposing the trench conductors; subjecting the exposed trench conductor to a second etching process; forming a contact barrier metal film on each of the inner walls of the plurality of contact holes; forming a plurality of contact members in each of the plurality of contact holes with the contact barrier metal film interposed therebetween; forming an interlayer barrier metal film so as to be in contact with the interlayer insulating film and the plurality of contact members; a step of performing a heat treatment after the interlayer barrier metal film is formed; Equipped with forming the plurality of trenches includes forming a first trench; forming the trench conductor includes forming a first trench conductor in the first trench; forming the plurality of contact holes by the first etching process includes forming first contact holes that expose the first trench conductor; the step of forming the contact barrier metal film includes the step of forming a first contact barrier metal film on an inner wall of the first contact hole including the first trench conductor exposed at a bottom of the first contact hole; the step of forming the plurality of contact members includes the step of forming the first contact members in the first contact holes with the first contact barrier metal film interposed therebetween; In the step of performing the second etching process, a protrusion that protrudes toward the first contact member is formed in the first trench conductor, In the step of forming the first contact barrier metal film, the first contact barrier metal film is formed in the first contact hole in a manner to cover the protrusion, A method for manufacturing a semiconductor device, wherein in the step of forming the first contact member, the first contact member is formed in the first contact hole with the first contact barrier metal film covering the convex portion interposed therebetween.

12. The step of forming the first trench conductor includes: forming a conductive film in the first trench with an insulating film interposed therebetween; removing the conductive film and the insulating film located on the first main surface of the semiconductor substrate, while leaving the conductive film and the insulating film located in the first trench; Including, 12. The method for manufacturing a semiconductor device according to claim 11, wherein the step of performing the second etching process includes a step of removing the conductive film while leaving the insulating film exposed at the bottom of the first contact hole, thereby forming the insulating film protruding from the conductive film as the convex portion.

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the step of forming the conductive film in the first trench with the insulating film therebetween includes the step of forming the insulating film as a native oxide film.

14. 12. The method for manufacturing a semiconductor device according to claim 11, wherein in the step of forming the contact barrier metal film, a material from which a metal silicide is formed by the heat treatment is used for the contact barrier metal film.

15. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the first etching process is performed using a first gas containing a first fluorocarbon.

16. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the second etching process is performed using a second gas containing at least one of chlorine and hydrogen bromide.

17. forming the plurality of trenches includes forming a second trench having a width narrower than a width of the first trench; 12. The method for manufacturing a semiconductor device according to claim 11, wherein the step of forming the trench conductor includes the step of forming a second trench conductor in the second trench, the second trench conductor having a width narrower than a width of the first trench conductor.

18. forming the plurality of trenches includes forming a third trench at a distance from the first trench; the step of forming the trench conductor includes a step of forming the third trench conductor with a trench insulating film interposed in the third trench; forming the plurality of contact holes by the first etching process includes forming second contact holes exposing the third trench conductor, the trench insulating film, and regions of the semiconductor substrate; the step of performing the second etching process includes a step of removing the third trench conductor and the region of the semiconductor substrate exposed at the bottom of the second contact hole while leaving the trench insulating film; 13. The method for manufacturing a semiconductor device according to claim 12, further comprising, after the second etching process, performing a third etching process to remove residues of the trench insulating film while leaving the convex portion protruding from the conductive film exposed at the bottom of the first contact hole.

19. 20. The method for manufacturing a semiconductor device according to claim 18, wherein the third etching process is performed using a third gas containing a second fluorocarbon.

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