Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing the decrease in electric connection reliability.SOLUTION: A semiconductor substrate 10 includes a lower substrate 20, a semiconductor element 30 having an electrode 32 provided on an upper surface and mounted on an upper surface of the lower substrate 20, and an upper substrate 40 provided on an upper surface of the semiconductor element 30. The semiconductor device 10 includes a plurality of via wires 80 connected to the electrode 32 penetrating the upper substrate 40 in a thickness direction, and a wiring layer 60 provided on an upper surface of the upper substrate 40 and electrically connected to the electrode 32 through the via wires 80. The via wires 80 include two or more kinds of via wires 81, 82, and 83 whose planar size is different from each other. The via wires 81, 82, and 83 are disposed so that the planar size is reduced from a peripheral part of the semiconductor element 30 toward a central part of the semiconductor element 30 in a plan view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, power semiconductor devices (power modules) that control and supply electric power have been known as semiconductor devices. One such semiconductor device includes a semiconductor element mounted between a lower substrate and an upper substrate, a sealing resin disposed between the lower substrate and the upper substrate and sealing the semiconductor element, and a wiring layer formed on the upper surface of the upper substrate. The wiring layer formed on the upper surface of the upper substrate is electrically connected to electrodes of the semiconductor element, for example, through a plurality of via wirings that penetrate the upper substrate in the thickness direction.

[0003] Incidentally, Patent Document 1 is disclosed as a prior art related to the above conventional technology. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-120902 Summary of the Invention [Problem to be solved by the invention]

[0005] In the above-mentioned semiconductor device, it is desirable to suppress a decrease in the reliability of electrical connection between the wiring layer formed on the upper surface of the upper substrate and the electrodes of the semiconductor element. [Means for solving the problem]

[0006] According to one aspect of the present invention, a semiconductor device includes a lower substrate, a semiconductor element having a first electrode provided on its upper surface and mounted on the upper surface of the lower substrate, an upper substrate provided on the upper surface of the semiconductor element, a plurality of via wirings penetrating the upper substrate in the thickness direction and connected to the first electrode, and a wiring layer provided on the upper surface of the upper substrate and electrically connected to the first electrode via the plurality of via wirings, wherein the plurality of via wirings include two or more types of via wirings having different planar sizes, and the plurality of via wirings are arranged so that, in a planar view, their planar sizes decrease from the periphery of the semiconductor element toward the center of the semiconductor element. [Effects of the Invention]

[0007] According to one aspect of the present invention, an effect is achieved in that a decrease in the reliability of electrical connection can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an enlarged portion of the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view (cross-sectional view taken along line 3-3 in FIG. 1) showing the semiconductor device of one embodiment. [Figure 4] FIG. 4 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 5] FIG. 5 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 6] FIG. 6 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment will be described below with reference to the accompanying drawings. For convenience, the accompanying drawings may show characteristic portions enlarged to make the features easier to understand, and the dimensional ratios of each component may differ from one drawing to another. Furthermore, in cross-sectional views, the hatching of some components is replaced with a matte finish, and some components are omitted, to make the cross-sectional structure of each component easier to understand. Each drawing illustrates mutually orthogonal X-, Y-, and Z-axes. In the following description, for convenience, the direction extending along the X-axis is referred to as the X-axis direction, the direction extending along the Y-axis is referred to as the Y-axis direction, and the direction extending along the Z-axis is referred to as the Z-axis direction. Furthermore, in this specification, "planar view" refers to viewing an object from the Z-axis direction, and "planar shape" refers to the shape of an object viewed from the Z-axis direction.

[0010] (Overall configuration of semiconductor device 10) First, the overall configuration of a semiconductor device 10 will be described with reference to FIGS. 1 to 3 is, for example, a power semiconductor device (power module) that controls and supplies power. An example of the semiconductor device 10 is a DC-DC converter.

[0011] As shown in FIG. 3 , the semiconductor device 10 includes a lower substrate 20, one or more semiconductor elements 30 (one in this embodiment) mounted on the upper surface of the lower substrate 20, and an upper substrate 40 provided on the upper surface of the semiconductor element 30. The lower substrate 20 includes a wiring layer 21 provided on its upper surface and a metal layer 25 provided on its lower surface. The semiconductor device 10 includes a sealing resin 50 provided between the lower substrate 20 and the upper substrate 40 and sealing the semiconductor element 30, and a wiring layer 60 electrically connected to the semiconductor element 30 and provided on the upper surface of the upper substrate 40. The semiconductor element 30 is provided between the upper surface of the lower substrate 20 and the lower surface of the upper substrate 40. In the semiconductor device 10, the semiconductor element 30 is embedded between the lower substrate 20 and the upper substrate 40.

[0012] (Configuration of semiconductor element 30) The semiconductor element 30 is formed of, for example, silicon (Si) or silicon carbide (SiC). The semiconductor element 30 is, for example, a power semiconductor element, i.e., a power semiconductor element. For example, the semiconductor element 30 may be an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, or the like. The semiconductor element 30 of this embodiment is a MOSFET. The planar shape of the semiconductor element 30 may be any shape and any size. The planar shape of the semiconductor element 30 is, for example, rectangular. The planar size of the semiconductor element 30 may be, for example, approximately 5 mm × 5 mm. The thickness of the semiconductor element 30 may be, for example, in the range of 50 μm to 775 μm.

[0013] The semiconductor element 30 has, for example, an electrode 31 provided on the bottom surface side and electrodes 32 and 33 provided on the top surface side. The semiconductor element 30 has, for example, a main body 34. The electrodes 32 and 33 are provided on the opposite side to the electrode 31. The electrode 31 is, for example, a drain electrode of a MOSFET. The electrode 32 is, for example, a source electrode of a MOSFET. The electrode 33 is, for example, a gate electrode of a MOSFET.

[0014] The electrodes 31, 32, and 33 may be made of a metal such as aluminum (Al) or copper (Cu), or an alloy containing at least one metal selected from these metals. If necessary, a surface treatment layer may be formed on the surfaces of the electrodes 31, 32, and 33. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated metal layer). The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

[0015] The electrode 31 is formed, for example, on the lower surface of the main body portion 34. For example, the electrode 31 is formed so as to cover the entire lower surface of the main body portion 34. As shown in FIG. 2, the electrodes 32 and 33 are formed, for example, on the upper surface of the main body 34. In this embodiment, two electrodes 32 and one electrode 33 are provided on the upper surface of the main body 34. The two electrodes 32 are provided spaced apart from each other on the upper surface of the main body 34. The two electrodes 32 are provided side by side, for example, along the Y-axis direction. Each electrode 32 has a recess 32X, for example, on the right side of the figure. The electrode 33 is provided, for example, spaced apart from the electrode 32 on the upper surface of the main body 34. The electrode 33 is provided, for example, so as to fit inside the two recesses 32X in a plan view.

[0016] (Configuration of lower substrate 20) As shown in Fig. 1, the lower substrate 20 is formed in a flat plate shape. The lower substrate 20 is a ceramic substrate made of ceramics such as oxide ceramics or non-oxide ceramics. Examples of oxide ceramics include aluminum oxide (Al2O3) and zirconia (ZrO2). Examples of non-oxide ceramics include aluminum nitride (AlN) and silicon nitride (Si3N4).

[0017] The planar shape of the lower substrate 20 can be any shape and any size. For example, the planar shape of the lower substrate 20 is formed into a rectangular shape. The thickness of the lower substrate 20 can be, for example, in the range of 200 μm to 400 μm. FIG. 1 is a plan view of the semiconductor device 10 shown in FIG. 3 as seen from above. In FIG. 1, the sealing resin 50 is drawn perspectively. FIG. 2 is an enlarged plan view of a portion of the semiconductor device 10 shown in FIG. 1. In FIG. 2, the upper substrate 40, the sealing resin 50, and the wiring layer 60 are drawn perspectively.

[0018] (Configuration of metal layer 25) As shown in FIG. 3, the metal layer 25 is provided on the lower surface of the lower substrate 20. The planar shape of the metal layer 25 can be any shape and any size. The planar shape of the metal layer 25 is formed, for example, in a rectangular shape. The metal layer 25 is formed, for example, in a solid shape. For example, the metal layer 25 is formed so as to extend over the entire lower surface of the lower substrate 20 except for the outer peripheral edge portion. The metal layer 25 functions, for example, as a reinforcing layer that suppresses warping of the lower substrate 20. The metal layer 25 can also function, for example, as a heat dissipation member.

[0019] The metal layer 25 may be made of, for example, copper or a copper alloy. If necessary, a surface treatment layer may be formed on the surface (bottom and side surfaces, or bottom surface only) of the metal layer 25. Examples of the surface treatment layer include an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer. The thickness of the metal layer 25 may be, for example, in the range of 100 μm to 800 μm.

[0020] (Configuration of wiring layer 21) 1, the wiring layer 21 has, for example, a large number of wiring patterns. The wiring layer 21 of this embodiment has a wiring pattern 22, a wiring pattern 23, and a wiring pattern 24.

[0021] The wiring patterns 22, 23, and 24 may be made of, for example, copper or a copper alloy. If necessary, a surface treatment layer may be formed on the surfaces (top and side surfaces, or only the top surfaces) of the wiring patterns 22, 23, and 24. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer. The thickness of the wiring patterns 22, 23, and 24 may be, for example, in the range of 100 μm to 800 μm.

[0022] The wiring patterns 22, 23, 24 are provided separately from each other on the upper surface of the lower substrate 20. The planar shapes of the wiring patterns 22, 23, 24 can be any shape and any size.

[0023] The planar shape of the wiring pattern 22 is, for example, L-shaped overall. The wiring pattern 22 has, for example, a first portion formed in a strip shape having a predetermined width in the Y-axis direction, which is one of the planar directions, and extending in the X-axis direction, which is also one of the planar directions. The wiring pattern 22 has, for example, a second portion extending from the first portion toward the Y-axis direction. The wiring pattern 22 is, for example, provided such that a portion of the wiring pattern 22 overlaps with the upper substrate 40 in a planar view, and the remaining portion of the wiring pattern 22 is exposed from the upper substrate 40. The wiring pattern 22 is, for example, provided such that it overlaps with the semiconductor element 30 in a planar view. As shown in FIG. 3 , the wiring pattern 22 is, for example, electrically connected to an electrode 31 of the semiconductor element 30. That is, the wiring pattern 22 is electrically connected to the electrode 31 serving as a drain electrode.

[0024] The wiring pattern 22 has, for example, a current input terminal 22A. The current input terminal 22A is provided, for example, on the upper surface of the wiring pattern 22 in a portion that does not overlap with the upper substrate 40 in a planar view. A first end of a connection terminal 72 is joined to the current input terminal 22A via, for example, a conductive joint 71. The current input terminal 22A is electrically connected to an external electrode provided outside the semiconductor device 10 via, for example, the joint 71 and the connection terminal 72. The current input terminal 22A is a terminal to which a current is input from, for example, a circuit or a power supply provided outside the semiconductor device 10. In this embodiment, the current input terminal 22A is a drain electrode terminal. Note that the connection terminal 72 is formed so that a first end is embedded in the sealing resin 50 and a second end opposite the first end is drawn out of the sealing resin 50.

[0025] 1, the planar shape of the wiring pattern 23 is formed, for example, in a rectangular shape. The wiring pattern 23 is formed, for example, in a strip shape having a predetermined width in the Y-axis direction and extending in the X-axis direction. The wiring pattern 23 is formed, for example, so as to face the wiring pattern 22 in the X-axis direction. The wiring pattern 23 is provided, for example, so that a portion of the wiring pattern 23 overlaps with the upper substrate 40 in a planar view, and the remaining portion of the wiring pattern 23 is exposed from the upper substrate 40. The wiring pattern 23 is electrically connected, for example, to the electrode 32 of the semiconductor element 30. That is, the wiring pattern 23 is electrically connected to the electrode 32 serving as a source electrode.

[0026] As shown in FIG. 3 , the wiring pattern 23 has, for example, a current output terminal 23A. The current output terminal 23A is provided, for example, on the upper surface of the wiring pattern 23 in a portion that does not overlap with the upper substrate 40 in a planar view. A first end of a connection terminal 74 is joined to the current output terminal 23A via, for example, a conductive joint 73. The current output terminal 23A is electrically connected to, for example, an external electrode provided outside the semiconductor device 10 via the joint 73 and the connection terminal 74. The current output terminal 23A is, for example, a terminal that outputs current to a circuit or the like provided outside the semiconductor device 10. In this embodiment, the current output terminal 23A is a source electrode terminal. Note that the connection terminal 74 is formed so that a first end is embedded in the sealing resin 50 and a second end opposite the first end is drawn out of the sealing resin 50.

[0027] As shown in FIG. 1 , the planar shape of the wiring pattern 24 is, for example, rectangular. The wiring pattern 24 is, for example, formed in a strip shape having a predetermined width in the Y-axis direction and extending in the X-axis direction. The wiring pattern 24 is, for example, provided above the wiring pattern 23 in the figure. The wiring pattern 24 is, for example, formed to extend parallel to the wiring pattern 23. The wiring pattern 24 is, for example, formed to be longer than the wiring pattern 23 in the X-axis direction. The wiring pattern 24 is, for example, provided so that a portion of the wiring pattern 24 overlaps with the upper substrate 40 in a planar view, and the remaining portion of the wiring pattern 24 is exposed from the upper substrate 40. The wiring pattern 24 is, for example, electrically connected to the electrode 33 of the semiconductor element 30. That is, the wiring pattern 24 is electrically connected to the electrode 33 serving as a gate electrode.

[0028] The wiring pattern 24 has, for example, a connection terminal 24A. The connection terminal 24A is provided on the upper surface of the wiring pattern 24 in a portion that does not overlap with the upper substrate 40 in a plan view. A first end of a connection terminal 75 is joined to the connection terminal 24A via, for example, a conductive joint (not shown). The connection terminal 24A is electrically connected to, for example, an external electrode provided outside the semiconductor device 10 via the connection terminal 75. The connection terminal 24A is, for example, a gate electrode terminal.

[0029] (Configuration of joint 76) 3, the semiconductor element 30 is bonded to the upper surface of the wiring pattern 22 via a conductive bonding portion 76. The bonding portion 76 is bonded to the wiring pattern 22 and also to the electrode 31. The bonding portion 76 electrically connects the wiring pattern 22 and the electrode 31 of the semiconductor element 30.

[0030] 1, the semiconductor element 30 is provided, for example, so that its entirety overlaps the wiring pattern 22 in a planar view. The semiconductor element 30 is provided, for example, so that its entirety overlaps the upper substrate 40 in a planar view.

[0031] (Configuration of joint 77) As shown in FIG. 3, a conductive joint 77 is formed on the upper surface of the wiring pattern 23. Although detailed illustration is omitted, a joint 77 is also formed on the upper surface of the wiring pattern 24 shown in FIG. 1. A connection member 78 is formed on the upper surface of each joint 77. The joint 77 is joined to the wiring pattern 23 or the wiring pattern 24 (see FIG. 1) and is also joined to the connection member 78. As shown in FIG. 3, the joint 77 electrically connects the wiring pattern 23 and the connection member 78. As shown in FIG. 1, the joint 77 electrically connects the wiring pattern 24 and the connection member 78.

[0032] The bonding portions 71, 73, 76, and 77 shown in Fig. 3 may be made of, for example, a metal sintered material. Examples of the sintered material include a sintered material (silver sintered material) primarily composed of silver (Ag) particles and a sintered material (copper sintered material) primarily composed of copper particles. The bonding portions 71, 73, 76, and 77 may also be made of, for example, solder, conductive paste such as silver paste, or a metal brazing material. The thickness of the bonding portions 71, 73, 76, and 77 may be, for example, in the range of 10 µm to 60 µm.

[0033] (Configuration of connecting member 78) The connection member 78 is electrically connected to the wiring layer 60 formed on the upper surface of the upper substrate 40. As a result, the wiring patterns 23, 24 are electrically connected to the wiring layer 60 via the joints 77 and the connection member 78. The connection member 78 is formed, for example, in a columnar shape extending along the stacking direction of the semiconductor device 10 (here, the Z-axis direction). The connection member 78 is, for example, a metal post. The connection member 78 is formed, for example, to have the same thickness as the semiconductor element 30. The thickness of the connection member 78 can be, for example, in the range of 50 μm to 775 μm. Note that the connection member 78 can be made of, for example, copper or a copper alloy.

[0034] (Configuration of upper substrate 40) As shown in FIG. 3, the upper substrate 40 is provided on the side of the electrodes 32 and 33 of the semiconductor element 30. That is, the upper substrate 40 is provided above the semiconductor element 30. The upper substrate 40 is provided on the upper surface of the semiconductor element 30 and the upper surface of the connecting member 78. The upper substrate 40 is formed in a flat plate shape. The planar shape of the upper substrate 40 can be any shape and any size. As shown in FIG. 1, the planar shape of the upper substrate 40 is formed, for example, in a rectangular shape. The planar shape of the upper substrate 40 is formed, for example, to be smaller than the planar shape of the lower substrate 20. For example, the dimension of the upper substrate 40 along the X-axis direction is formed smaller than the dimension of the lower substrate 20 along the X-axis direction. For example, the dimension of the upper substrate 40 along the Y-axis direction is formed smaller than the dimension of the lower substrate 20 along the Y-axis direction. The upper substrate 40 is provided, for example, so that its entirety overlaps with the lower substrate 20 in a planar view.

[0035] As shown in FIG. 3, the upper substrate 40 includes, for example, a substrate main body 41 and an adhesive layer 42 formed on the lower surface of the substrate main body 41. The substrate main body 41 may be made of an insulating resin such as a polyimide resin or a polyester resin. The adhesive layer 42 may be made of an epoxy, polyimide, or silicone adhesive. The thickness of the substrate main body 41 may be, for example, in the range of 30 μm to 50 μm. The thickness of the adhesive layer 42 may be, for example, in the range of 15 μm to 45 μm.

[0036] The substrate main body 41 is adhered to the semiconductor element 30 and the connecting member 78 by, for example, an adhesive layer 42. The adhesive layer 42 is adhered to the upper surface of the semiconductor element 30 and also to the lower surface of the substrate main body 41. The adhesive layer 42 is adhered to the upper surface of the connecting member 78 and also to the lower surface of the substrate main body 41. The adhesive layer 42 is provided, for example, to incorporate a portion of the semiconductor element 30. In other words, a portion of the semiconductor element 30 is embedded in the adhesive layer 42. For example, a portion of the electrodes 32, 33 of the semiconductor element 30 is embedded in the adhesive layer 42. The adhesive layer 42 is provided, for example, to incorporate an upper portion of the connecting member 78. In other words, the upper portion of the connecting member 78 is embedded in the adhesive layer 42.

[0037] The upper substrate 40 has a plurality of openings 43 formed therein, penetrating the upper substrate 40 in the thickness direction (here, the Z-axis direction). Each opening 43 is formed, for example, so as to penetrate the substrate main body 41 and the adhesive layer 42 in the thickness direction. Each opening 43 is formed, for example, in a tapered shape in which the opening width (opening diameter) decreases from the upper side (the upper surface side of the upper substrate 40) to the lower side (the lower substrate 20 side) in FIG. 3. For example, each opening 43 is formed in an inverted truncated cone shape in which the opening diameter at the lower opening end is smaller than the opening diameter at the upper opening end. Some of the openings 43 are formed, for example, so as to expose part of the upper surfaces of the electrodes 32, 33. Some of the openings 43 are formed, for example, so as to expose part of the upper surface of the connecting member 78.

[0038] (Configuration of wiring layer 60) The wiring layer 60 is formed on the upper surface of the upper substrate 40. The wiring layer 60 has, for example, a wiring pattern 61 and a wiring pattern 62. The wiring patterns 61 and 62 can be made of, for example, copper or a copper alloy. If necessary, a surface treatment layer may be formed on the surfaces (upper and side surfaces, or only the upper surfaces) of the wiring patterns 61 and 62. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer. The thickness of the wiring patterns 61 and 62 can be, for example, in the range of 50 μm to 200 μm.

[0039] The wiring patterns 61 and 62 are provided apart from each other on the upper surface of the upper substrate 40. The planar shapes of the wiring patterns 61 and 62 can be any shape and any size.

[0040] (Configuration of wiring pattern 61) The wiring pattern 61 is formed, for example, so as to electrically connect the wiring pattern 23 and the electrode 32 of the semiconductor element 30. The wiring pattern 61 is formed, for example, so as to electrically connect the current output terminal 23A of the wiring pattern 23 and the electrode 32 of the semiconductor element 30. As shown in Fig. 1 , the wiring pattern 61 is formed, for example, so as to extend from the electrode 32 toward the current output terminal 23A in the X-axis direction.

[0041] The wiring pattern 61 is formed, for example, to partially overlap the wiring pattern 23 in a plan view. The wiring pattern 61 is formed, for example, to overlap a portion of the wiring pattern 23 on the right side in the figure in a plan view. As shown in FIG. 3 , the wiring pattern 61 is electrically connected to a connection member 78 provided on the wiring pattern 23, for example, via one or more via wirings V1 that penetrate the upper substrate 40 in the thickness direction. The wiring pattern 61 is electrically connected to the wiring pattern 23, for example, via the via wirings V1, the connection member 78, and a joint 77. The wiring pattern 61 is formed, for example, integrally with the via wirings V1. Each via wiring V1 is formed, for example, in an opening 43 that exposes a portion of the upper surface of the connection member 78 provided on the wiring pattern 23. Each via wiring V1 is formed, for example, to fill the opening 43.

[0042] As shown in FIG. 1 , the wiring pattern 61 is formed, for example, to partially overlap the semiconductor element 30 in a planar view. The wiring pattern 61 is formed, for example, to overlap the electrode 32 of the semiconductor element 30 in a planar view. The wiring pattern 61 is formed, for example, to overlap two electrodes 32 in a planar view. As shown in FIG. 3 , the wiring pattern 61 is electrically connected to the electrode 32, for example, through a plurality of via wirings 80 that penetrate the upper substrate 40 in the thickness direction. As a result, the wiring pattern 61 is electrically connected to the electrode 32 through the via wirings 80, and is also electrically connected to the wiring pattern 23 through the via wiring V1, the connecting member 78, and the joint 77. In other words, the wiring pattern 23 having the current output terminal 23A is electrically connected to the electrode 32, which is the source electrode, through the joint 77, the connecting member 78, the via wiring V1, the wiring pattern 61, and the via wiring 80. The wiring pattern 61 is formed, for example, integrally with the via wiring 80. In FIG. 3, the number of via wirings 80 is reduced for the sake of simplicity.

[0043] (Configuration of via wiring 80) Each via wiring 80 penetrates the upper substrate 40 in the thickness direction and is connected to an electrode 32. Each via wiring 80 is formed, for example, in an opening 43 that exposes a portion of the upper surface of the electrode 32. Each via wiring 80 is formed, for example, so as to fill the opening 43. As shown in FIG. 2, for example, a plurality of via wirings 80 (30 in this embodiment) are connected to two electrodes 32. The 30 via wirings 80 in this embodiment are provided so that 15 via wirings 80 are connected to each of the two electrodes 32. The 30 via wirings 80 are provided, for example, lined up along the X-axis direction and lined up along the Y-axis direction.

[0044] The via wirings 80 include two or more types (three types in this embodiment) of via wirings 81, 82, and 83 that are different from each other in planar size. The planar shape of each of the via wirings 81, 82, and 83 can be formed into any shape. The planar shapes of the via wirings 81, 82, and 83 may be the same or different from each other. In this embodiment, the planar shapes of the via wirings 81, 82, and 83 are the same as each other, specifically, circular. The planar size of the via wiring 81 is larger than the planar size of the via wiring 82 and is also larger than the planar size of the via wiring 83. That is, the via diameter of the via wiring 81 is larger than the via diameters of each of the via wirings 82 and 83. The planar size of the via wiring 82 is larger than the planar size of the via wiring 83. That is, the via diameter of the via wiring 82 is larger than the planar size of the via wiring 83. Thus, the via wiring 81 is the via wiring 80 with the largest planar size among the via wirings 81, 82, and 83. The via wiring 82 is the via wiring 80 with the second largest planar size among the via wirings 81, 82, and 83. The via wiring 83 is the via wiring 80 with the smallest planar size among the via wirings 81, 82, and 83. The via diameter of the via wiring 81 can be, for example, in the range of 450 μm or more and less than 550 μm. The via diameter of the via wiring 82 can be, for example, in the range of 350 μm or more and less than 450 μm. The via diameter of the via wiring 83 can be, for example, in the range of 250 μm or more and less than 350 μm.

[0045] The 30 via wirings 80 in this embodiment include 14 via wirings 81, 12 via wirings 82, and 4 via wirings 83. In this embodiment, 7 via wirings 81, 6 via wirings 82, and 2 via wirings 81 are connected to each of the two electrodes 32.

[0046] Here, through intensive research by the present inventors, it has been found that the reliability of the electrical connection between the via wiring 80 and the electrode 32 is more likely to decrease in the via wiring 80 provided in the peripheral portion of the semiconductor element 30 than in the via wiring 80 provided in the central portion of the semiconductor element 30. Specifically, when a temperature cycle test, which is one of the reliability tests, is performed on the semiconductor device 10, the bonding area between the via wiring 80 and the electrode 32 decreases as the number of temperature cycles increases. It has been found that the bonding area between the via wiring 80 and the electrode 32 is more likely to decrease and the reliability of the electrical connection between the via wiring 80 and the electrode 32 decreases as the semiconductor element 30 approaches the peripheral portion (outer periphery) of the semiconductor element 30. In other words, it has been found that when the semiconductor device 10 is subjected to a temperature cycle test, the bonding area between the via wiring 80 and the electrode 32 gradually decreases from the peripheral portion of the semiconductor element 30. This is presumably because the amount of distortion caused by stress, etc., generated during the temperature cycle test is greater in the peripheral portion of the semiconductor element 30 than in the central portion of the semiconductor element 30. Furthermore, when a temperature cycle test was performed on the semiconductor device 10, it was found that the smaller the via diameter of the via wiring 80, the more likely it is that the junction area between the via wiring 80 and the electrode 32 will decrease, and the more likely it is that the reliability of the electrical connection between the via wiring 80 and the electrode 32 will decrease.

[0047] Therefore, in the semiconductor device 10 of this embodiment, the multiple types of via wirings 81, 82, and 83 are arranged so that their planar size decreases from the periphery toward the center of the semiconductor element 30 in a plan view. The via wirings 81, 82, and 83 of this embodiment are arranged so that their planar size decreases from the periphery toward the center of the semiconductor element 30 in both the X-axis direction and the Y-axis direction. The via wirings 81, 82, and 83 of this embodiment are arranged so that their planar size is smallest at the center of the semiconductor element 30 in a plan view and increases in planar size in a concentric rectangular shape toward the periphery of the semiconductor element 30.

[0048] More specifically, in a plan view, a via wiring 83 having the smallest planar size is provided in the center of the semiconductor element 30. In this embodiment, in a plan view, four via wirings 83 are arranged in a matrix in the central region of the semiconductor element 30. In a plan view, each of the four via wirings 83 is provided in a position overlapping with an electrode 32 in the central region of the semiconductor element 30. Two of the four via wirings 83 are provided for each of the two electrodes 32. The two via wirings 83 provided for each electrode 32 are arranged side by side along the X-axis direction.

[0049] The via wiring 82, which has the second largest planar size, is provided closer to the periphery of the semiconductor element 30 than the via wiring 83. In this embodiment, twelve via wirings 82 are arranged so as to surround the four via wirings 83 from the outside in a plan view. Each of the twelve via wirings 82 is provided in a region closer to the periphery than the via wiring 83 and at a position overlapping with an electrode 32. Six of the twelve via wirings 82 are provided for each of the two electrodes 32.

[0050] The via wiring 81 having the largest planar size is provided closer to the periphery of the semiconductor element 30 than the via wiring 82. In this embodiment, 14 via wirings 81 are arranged so as to surround the 12 via wirings 82 from the outside in a plan view. The 14 via wirings 81 are arranged peripherally in a plan view in the outer periphery region of the semiconductor element 30. That is, the 14 via wirings 81 are provided along the outer periphery of the semiconductor element 30. Each of the 14 via wirings 81 is provided in a region closer to the periphery than the via wiring 82, at a position overlapping with an electrode 32. Seven of the 14 via wirings 81 are provided for each of the two electrodes 32.

[0051] Two adjacent via wirings 80 are spaced apart by a predetermined distance L1 or more, regardless of the planar size of the two via wirings 80. More specifically, the distance between two adjacent via wirings 81 is the predetermined distance L1 or more, and the distance between two adjacent via wirings 81 and 82 is the predetermined distance L1 or more. Furthermore, the distance between two adjacent via wirings 82 is the predetermined distance L1 or more, the distance between two adjacent via wirings 82 and 83 is the predetermined distance L1 or more, and the distance between two adjacent via wirings 83 is the predetermined distance L1 or more.

[0052] (Configuration of wiring pattern 62) 1, the wiring pattern 62 is formed, for example, so as to electrically connect the wiring pattern 24 and the electrode 33 of the semiconductor element 30. The wiring pattern 62 is formed, for example, so as to extend from the wiring pattern 24 to the semiconductor element 30 in a plan view.

[0053] The wiring pattern 62 is formed, for example, to partially overlap the wiring pattern 24 in a plan view. The wiring pattern 62 is formed, for example, to overlap the right end of the wiring pattern 24 in a plan view. The wiring pattern 62 is electrically connected to a connection member 78 provided on the wiring pattern 24, for example, via one or more via wirings V2 that penetrate the upper substrate 40 in the thickness direction. The wiring pattern 62 of this embodiment is electrically connected to the connection member 78 provided on the wiring pattern 24 via the via wirings V2. The wiring pattern 62 is electrically connected to the wiring pattern 24, for example, via the via wirings V2, the connection member 78, and the joints 77. Although detailed illustration is omitted, the wiring pattern 62 is formed, for example, integrally with the via wirings V2.

[0054] The wiring pattern 62 is formed, for example, to partially overlap the semiconductor element 30 in a planar view. The wiring pattern 62 is formed, for example, to overlap the electrodes 33 of the semiconductor element 30 in a planar view. As shown in FIG. 3 , the wiring pattern 62 is electrically connected to the electrodes 33, for example, via one or more via wirings V3 that penetrate the upper substrate 40 in the thickness direction. The wiring pattern 62 is formed, for example, integrally with the via wirings V3. The via wirings V3 are formed, for example, in openings 43 that expose part of the upper surfaces of the electrodes 33. The via wirings V3 are formed, for example, to fill the openings 43.

[0055] 1, the wiring pattern 62 is electrically connected to the electrode 33 through the via wiring V3, and is also electrically connected to the wiring pattern 24 through the via wiring V2, the connection member 78, and the joint 77. In other words, the electrode 33, which is the gate electrode, is electrically connected to the wiring pattern 24 through the via wiring V3, the wiring pattern 62, the via wiring V2, the connection member 78, and the joint 77.

[0056] (Configuration of sealing resin 50) As shown in FIG. 3 , the sealing resin 50 is formed, for example, to seal the semiconductor element 30 provided between the lower substrate 20 and the upper substrate 40. The sealing resin 50 is formed to seal the connection member 78 and the bonding portions 71, 73, 76, and 77. The sealing resin 50 is formed, for example, to cover the entire side surfaces of the semiconductor element 30, the entire side surfaces of the connection member 78, and the entire side surfaces of the bonding portions 71, 73, 76, and 77. The sealing resin 50 is formed, for example, to cover the first ends of the connection terminals 72 and 74. The sealing resin 50 is formed, for example, to cover the entire upper surface of the wiring layer 21 exposed from the semiconductor element 30 and the connection member 78, etc. The sealing resin 50 is formed, for example, to cover the entire side surface of the wiring layer 21. The sealing resin 50 is formed, for example, to cover the entire upper surface of the lower substrate 20 exposed from the wiring layer 21. The sealing resin 50 is formed, for example, to cover the entire side surface of the lower substrate 20. The sealing resin 50 is formed, for example, to cover the entire lower surface of the lower substrate 20 exposed from the metal layer 25. The sealing resin 50 is formed, for example, to cover the entire side surfaces of the metal layer 25. The sealing resin 50 is formed, for example, to expose the entire lower surface of the metal layer 25. The sealing resin 50 is formed, for example, to cover the entire lower surface of the upper substrate 40 exposed from the semiconductor element 30 and the connecting member 78. The sealing resin 50 is formed, for example, to cover the entire side surfaces of the upper substrate 40. The sealing resin 50 is formed, for example, to cover the entire upper surface of the upper substrate 40 exposed from the wiring layer 60. The sealing resin 50 is formed, for example, to cover the entire side surfaces of the wiring layer 60. The sealing resin 50 is formed, for example, to cover the entire upper surface of the wiring layer 60.

[0057] The material for the sealing resin 50 may be, for example, a non-photosensitive insulating resin containing a thermosetting resin as its main component. The material for the sealing resin 50 may be, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which a filler such as silica or alumina is mixed into such a resin. The sealing resin 50 may be, for example, a mold resin.

[0058] In this embodiment, electrode 31 is an example of a second electrode, electrode 32 is an example of a first electrode, electrode 33 is an example of a third electrode, the X-axis direction is an example of a first direction, and the Y-axis direction is an example of a second direction.

[0059] (Effects of this embodiment) Next, the effects of this embodiment will be described. (1) The semiconductor device 10 includes a lower substrate 20, a semiconductor element 30 having electrodes 32 provided on its upper surface and mounted on the upper surface of the lower substrate 20, and an upper substrate 40 provided on the upper surface of the semiconductor element 30. The semiconductor device 10 includes a plurality of via wirings 80 that penetrate the upper substrate 40 in the thickness direction and are connected to the electrodes 32, and a wiring layer 60 that is provided on the upper surface of the upper substrate 40 and is electrically connected to the electrodes 32 via the plurality of via wirings 80. The plurality of via wirings 80 include two or more types of via wirings 81, 82, and 83 that differ from each other in planar size. The via wirings 81, 82, and 83 are arranged so that their planar size decreases from the periphery of the semiconductor element 30 toward the center of the semiconductor element 30 in a planar view.

[0060] According to this configuration, via wirings 81 with large planar sizes are arranged in the peripheral portion of the semiconductor element 30, and via wirings 83 with small planar sizes are arranged in the central portion of the semiconductor element 30. As a result, via wirings 81 with large planar sizes that are superior in terms of electrical connection reliability are provided in the peripheral portion of the semiconductor element 30 where the reliability of the electrical connection between the via wirings 80 and the electrodes 32 is likely to decrease. In other words, via wirings 81 with large planar sizes that are less likely to decrease in electrical connection reliability are provided in the peripheral portion of the semiconductor element 30 where the reliability of the electrical connection is likely to decrease. Therefore, it is possible to preferably prevent a decrease in the reliability of the electrical connection between the via wirings 81 and the electrodes 32 in the peripheral portion of the semiconductor element 30.

[0061] (2) Furthermore, the via wiring 83 having a small planar size is provided in the center of the semiconductor element 30, where the reliability of the electrical connection between the via wiring 80 and the electrode 32 is unlikely to decrease. By providing such a via wiring 83 having a small planar size, the via wiring 80 can be suitably arranged on the electrode 32 even in a small space. Therefore, compared to a case where the multiple via wirings 80 are composed of only the via wiring 81 having a large planar size, for example, it is possible to suitably arrange a large number of via wirings 81, 82, and 83 on the electrode 32 while reducing the dead space between adjacent via wirings 80. This makes it possible to increase the total bonding area of ​​the multiple via wirings 80 with respect to the electrode 32. As a result, the reliability of the electrical connection between the via wiring 80 and the electrode 32 can be improved.

[0062] (3) Here, the via wiring 83 having a small planar size is more likely to have a reduced reliability of electrical connection with the electrode 32 than the via wiring 81 having a large planar size. Such via wiring 83 is provided in the center of the semiconductor element 30, where the reliability of the electrical connection between the via wiring 80 and the electrode 32 is less likely to be reduced. Therefore, even when the via wiring 83 having a small planar size is provided, the reduction in the reliability of the electrical connection between the via wiring 83 and the electrode 32 can be suitably suppressed.

[0063] (4) The multiple via wirings 80 are arranged side by side along the X-axis direction, which is one of the planar directions, and are also arranged side by side along the Y-axis direction, which is one of the planar directions. The multiple via wirings 80 are arranged such that their planar size decreases from the periphery toward the center of the semiconductor element 30 in the X-axis direction. This makes it possible to preferably prevent a decrease in the reliability of the electrical connection between the via wirings 80 and the electrodes 32 in the peripheral portion of the semiconductor element 30 in the X-axis direction. Furthermore, the multiple via wirings 80 are arranged such that their planar size decreases from the periphery toward the center of the semiconductor element 30 in the Y-axis direction. This makes it possible to preferably prevent a decrease in the reliability of the electrical connection between the via wirings 80 and the electrodes 32 in the peripheral portion of the semiconductor element 30 in the Y-axis direction. As described above, the above configuration makes it possible to preferably prevent a decrease in the reliability of the electrical connection between the via wirings 80 and the electrodes 32 in the peripheral portion of the semiconductor element 30 in both the X-axis direction and the Y-axis direction.

[0064] (Example of change) The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0065] The number and arrangement of the via wirings 80 in the above embodiment can be changed as appropriate. 4, the via wirings 81, 82, and 83 may be arranged such that their planar size decreases in the X-axis direction from the periphery toward the center of the semiconductor element 30. In this modification, eight via wirings 81, twelve via wirings 82, and twenty-four via wirings 83 are arranged on two electrodes 32.

[0066] More specifically, the via wiring 83 with the smallest planar size is provided in the central portion in the X-axis direction of the semiconductor element 30. In this modified example, 24 via wirings 83 are arranged in a matrix in the central region in the X-axis direction of the semiconductor element 30. Twelve of the 24 via wirings 83 are provided for each of the two electrodes 32.

[0067] The via wiring 82, which has the second largest planar size, is provided closer to the periphery of the semiconductor element 30 in the X-axis direction than the via wiring 83. In this modified example, 12 via wirings 82 are arranged to sandwich the 24 via wirings 83 from both sides in the X-axis direction in plan view. Six of the 12 via wirings 82 are provided for each of the two electrodes 32.

[0068] The via wirings 81, which have the largest planar size, are provided closer to the peripheral edge of the semiconductor element 30 in the X-axis direction than the via wirings 82. In this modified example, eight via wirings 81 are arranged to sandwich the twelve via wirings 82 from both sides in the X-axis direction in a plan view. The eight via wirings 81 are provided along the sides of the electrodes 32 extending in the Y-axis direction. Four of the eight via wirings 81 are provided for each of the two electrodes 32.

[0069] 5, the via wirings 81, 82, and 83 may be arranged such that their planar size decreases in the Y-axis direction from the periphery toward the center of the semiconductor element 30. In this modification, 10 via wirings 81, 12 via wirings 82, and 16 via wirings 83 are arranged on two electrodes 32.

[0070] More specifically, the via wiring 83 with the smallest planar size is provided in the central portion in the Y-axis direction of the semiconductor element 30. In this modified example, 16 via wirings 83 are arranged in a matrix in the central region in the Y-axis direction of the semiconductor element 30. Of the 24 via wirings 83, eight are provided for each of the two electrodes 32.

[0071] The via wiring 82, which has the second largest planar size, is provided closer to the periphery of the semiconductor element 30 in the Y-axis direction than the via wiring 83. In this modified example, 12 via wirings 82 are arranged to sandwich the 16 via wirings 83 from both sides in the Y-axis direction in plan view. Six of the 12 via wirings 82 are provided for each of the two electrodes 32.

[0072] The via wirings 81 having the largest planar size are provided closer to the peripheral edge of the semiconductor element 30 in the Y-axis direction than the via wirings 82. In this modified example, ten via wirings 81 are arranged to sandwich the twelve via wirings 82 from both sides in the Y-axis direction in a plan view. The ten via wirings 81 are provided along the sides of the electrodes 32 extending in the X-axis direction. Five of the ten via wirings 81 are provided for each of the two electrodes 32.

[0073] As shown in FIG. 6 , multiple via wirings 81, 82, and 83 may be arranged so that their planar size is smallest at the center of the semiconductor element 30 in a plan view and increases concentrically toward the periphery of the semiconductor element 30. In this modification, four via wirings 81, 22 via wirings 82, and 18 via wirings 83 are arranged on two electrodes 32. Note that in FIG. 6 , three imaginary circles C1, C2, and C3 are illustrated by dashed dotted lines. The three imaginary circles C1, C2, and C3 are concentric circles centered on the planar center of the semiconductor element 30. The imaginary circle C1 has the largest diameter among the imaginary circles C1, C2, and C3. The imaginary circle C2 has a diameter smaller than the imaginary circle C1 but larger than the imaginary circle C3. The imaginary circle C3 has the smallest diameter among the imaginary circles C1, C2, and C3.

[0074] The via wiring 83 with the smallest planar size is provided in the planar center of the semiconductor element 30. Specifically, 18 via wirings 83 are arranged in the area inside the imaginary circle C3 in plan view. Of the 18 via wirings 83, nine are provided for each of the two electrodes 32.

[0075] The via wiring 82 having the second largest planar size is provided closer to the periphery of the semiconductor element 30 than the via wiring 83. In this modified example, 22 via wirings 82 are arranged so as to surround the 18 via wirings 83 from the outside in a plan view. Specifically, the 22 via wirings 82 are arranged in a region outside the imaginary circle C3 and inside the imaginary circle C2 and on the imaginary circle C2 in a plan view. Eleven of the 22 via wirings 82 are provided for each of the two electrodes 32.

[0076] The via wiring 81, which has the largest planar size, is provided closer to the periphery of the semiconductor element 30 than the via wiring 82. In this modified example, four via wirings 81 are arranged on an imaginary circle C1 in a planar view. Specifically, the four via wirings 81 are provided one at each of the four corners of the semiconductor element 30 in a planar view. Two of the four via wirings 81 are provided for each of the two electrodes 32.

[0077] In the above embodiment, the via wirings 80 include three types of via wirings 81, 82, and 83 that are different in planar size from each other, but the types of planar sizes of the via wirings 80 are not limited to three. For example, the types of planar sizes of the via wirings 80 may be changed to two or four or more types.

[0078] In the above embodiment, the current input terminal 22A is provided on the upper surface of the lower substrate 20, but the position where the current input terminal 22A is formed is not limited to this. For example, the current input terminal 22A may be provided on the upper surface of the upper substrate 40.

[0079] In the above embodiment, the current output terminal 23A is provided on the upper surface of the lower substrate 20, but the position where the current output terminal 23A is formed is not limited to this. For example, the current output terminal 23A may be provided on the upper surface of the upper substrate 40. For example, the wiring pattern 61 provided on the upper surface of the upper substrate 40 may have the current output terminal 23A.

[0080] In the above embodiment, the connection terminals 24A are provided on the upper surface of the lower substrate 20, but the formation position of the connection terminals 24A is not limited to this. For example, the connection terminals 24A may be provided on the upper surface of the upper substrate 40. For example, the wiring pattern 62 provided on the upper surface of the upper substrate 40 may have the connection terminals 24A.

[0081] The connection terminal 72 in the above embodiment may be omitted. The connection terminal 74 in the above embodiment may be omitted. The connection terminal 75 in the above embodiment may be omitted.

[0082] The area where the sealing resin 50 is formed in the above embodiment can be changed as appropriate. For example, the sealing resin 50 may be formed so as to expose the side surface of the lower substrate 20. For example, the sealing resin 50 may be formed so as to expose the upper surface of the wiring layer 60.

[0083] The sealing resin 50 in the above embodiment may be omitted. In the above embodiment, the upper substrate 40 is formed so that its planar shape is smaller than that of the lower substrate 20, but this is not limiting. For example, the planar shape of the upper substrate 40 may be formed so that it is larger than that of the lower substrate 20. For example, the planar shape of the upper substrate 40 may be formed so that it is the same size as that of the lower substrate 20.

[0084] The metal layer 25 in the above embodiment may be omitted. In the above embodiment, the substrate body 41 of the upper substrate 40 has a single-layer structure, but is not limited to this. For example, the substrate body 41 may have a laminated structure in which one or more wiring layers and multiple insulating layers are laminated.

[0085] In the above embodiment, the semiconductor element 30 is embodied as a MOSFET, but the present invention is not limited to this. For example, as shown in FIG. 7 , the semiconductor element 30 may be embodied as a diode having an electrode 91 serving as an anode electrode and an electrode 92 serving as a cathode electrode. The semiconductor element 30 has, for example, a main body 94. The electrode 91 is provided on, for example, the lower surface of the main body 94. The electrode 91 is formed, for example, so as to cover the entire lower surface of the main body 94. The electrode 92 is provided on, for example, the upper surface of the main body 94. The electrode 92 is formed, for example, so as to cover the entire upper surface of the main body 94. In this case, the wiring layer 60 is electrically connected to the electrode 92 through a plurality of via wirings 80 that penetrate the upper substrate 40 in the thickness direction. Even in this case, the plurality of via wirings 80 are arranged so that their planar size decreases from the periphery toward the center of the semiconductor element 30 in a plan view.

[0086] In the above embodiment, the semiconductor device 10 is embodied as a power semiconductor device, but is not limited to this. For example, the semiconductor device 10 may be embodied as various semiconductor devices other than power semiconductor devices.

[0087] In the above embodiment, the semiconductor element 30 is embodied as a power semiconductor element, but is not limited to this. For example, the semiconductor element 30 may be embodied as various semiconductor elements other than power semiconductor elements. [Explanation of symbols]

[0088] 10 Semiconductor device 20 Lower board 30 Semiconductor elements 31 electrode (second electrode) 32 electrodes (1st electrode) 33 electrode (3rd electrode) 40 Upper board 41 Board body 42 Adhesive layer 43 Opening 50 Sealing resin 60 wiring layer 80 via wiring 81, 82, 83 Via wiring 91 Electrode (2nd electrode) 92 electrode (1st electrode)

Claims

1. A lower substrate; a semiconductor element having a first electrode provided on an upper surface thereof and mounted on an upper surface of the lower substrate; an upper substrate provided on an upper surface of the semiconductor element; a plurality of via wirings that penetrate the upper substrate in a thickness direction and are connected to the first electrodes; a wiring layer provided on the upper surface of the upper substrate and electrically connected to the first electrode through the plurality of via wirings; the plurality of via wirings include two or more types of via wirings having different planar sizes; The semiconductor device, wherein the plurality of via wirings are arranged so that, in a plan view, their planar size decreases from the periphery of the semiconductor element toward the center of the semiconductor element.

2. the plurality of via wirings are arranged side by side along a first direction which is one of planar directions, 2 . The semiconductor device according to claim 1 , wherein said plurality of via wirings are arranged so that a planar size thereof decreases from said peripheral edge portion toward said central portion in said first direction.

3. the plurality of via wirings are arranged side by side along a second direction that is one of the planar directions and is perpendicular to the first direction, 3. The semiconductor device according to claim 2, wherein said plurality of via wirings are arranged so that a planar size thereof decreases from said peripheral edge portion toward said central portion in said second direction.

4. The semiconductor element has a rectangular planar shape, 4. The semiconductor device according to claim 3, wherein said plurality of via wirings are arranged so that, in a plan view, a planar size thereof is smallest at said central portion and increases in planar size in a concentric rectangular shape toward said peripheral portion.

5. The semiconductor element has a rectangular planar shape, 2. The semiconductor device according to claim 1, wherein said plurality of via wirings are arranged so that, in a plan view, a planar size thereof is smallest at said central portion and increases concentrically toward said peripheral portion.

6. 2. The semiconductor device according to claim 1, further comprising a sealing resin provided between said lower substrate and said upper substrate and sealing said semiconductor element.

7. The semiconductor device according to claim 1 , wherein the semiconductor element is a power semiconductor element.

8. 8. The semiconductor device according to claim 7, wherein the semiconductor element is a metal oxide semiconductor field effect transistor having the first electrode as a source electrode, a second electrode as a drain electrode, and a third electrode as a gate electrode.

9. 8. The semiconductor device according to claim 7, wherein the semiconductor element is a diode having the first electrode as a cathode electrode and a second electrode as an anode electrode.

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