Array substrate and display device

Abstract

To suppress the reduction in an aperture ratio and reduce a step that may occur on a surface of a light blocking portion.SOLUTION: An array substrate 21 includes: a transistor 24 having a semiconductor portion 24D disposed superposed on a first electrode 24A, a second electrode 24B provided on an upper layer side of the semiconductor portion 24D and connected to the semiconductor portion 24D, and a third electrode 24C provided on the upper layer side of the semiconductor portion 24D, spaced apart from the second electrode 24B, and connected to the semiconductor portion 24D; a first insulating film 31 provided on an upper layer side of the first electrode 24A and on a lower layer side of the semiconductor portion 24D; a second insulating film 32 provided on an upper layer side of the second electrode 24B and the third electrode 24C; a third insulating film 33 provided on an upper layer side of the second insulating film 32; and a light blocking portion 36 provided on an upper layer side of the third insulating film 33. The light blocking portion 36 is electrically isolated and overlaps at least a channel forming portion 24D1, which is a portion of the semiconductor portion 24D sandwiched between the second electrode 24B and the third electrode 24C.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an array substrate and a display device in which a decrease in aperture ratio is suppressed and steps that may occur on the surface of a light-shielding portion are alleviated. [Background technology]

[0002] Conventionally, an example of an array substrate and a display device including the array substrate is known, as described in Patent Document 1 below. The display device described in Patent Document 1 includes a plurality of pixels, each of which includes a TFT and a light-shielding layer that shields the TFT from light. The TFT includes a gate electrode provided on the substrate, a gate insulating film provided on the gate electrode, a semiconductor layer provided on the gate insulating film, and a source electrode and a drain electrode provided on the semiconductor layer. The gate electrode is connected to a scanning line. The source electrode is connected to a pixel electrode. The drain electrode is connected to a signal line. The width of the light-shielding layer is wider than the width of the semiconductor layer. The source electrode is configured to cover one corner of the semiconductor layer. The drain electrode is configured to cover one corner of the semiconductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-21842 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned Patent Document 1, the light-shielding layer is electrically connected to a common electrode and a common voltage is applied thereto. To connect the light-shielding layer to the common electrode, a connection structure for connecting the two must be provided near the TFT. There is a concern that this connection structure may reduce the aperture ratio of the pixel. Furthermore, as mentioned above, the light-shielding layer has an electrical function, and therefore is required to have a certain level of low electrical resistance so that the function can be fully exerted. This tends to increase the thickness of the light-shielding layer, which raises concerns about large steps occurring on the surface of the light-shielding layer.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to suppress a decrease in aperture ratio and reduce steps that may occur on the surface of the light-shielding portion. [Means for solving the problem]

[0006] (1) An array substrate related to the technology described in this specification includes a transistor having a first electrode, a semiconductor portion provided above the first electrode and overlapping the first electrode, a second electrode provided above the semiconductor portion and connected to the semiconductor portion, and a third electrode provided above the semiconductor portion, spaced apart from the second electrode and connected to the semiconductor portion; a first insulating film provided above the first electrode and below the semiconductor portion, a second insulating film provided above the second electrode and the third electrode, a third insulating film provided above the second insulating film, and a light-shielding portion provided above the third insulating film, wherein the third insulating film is thicker than the second insulating film, and the light-shielding portion is electrically isolated and overlaps at least a channel-forming portion that is a portion of the semiconductor portion sandwiched between the second electrode and the third electrode.

[0007] (2) In addition to the above (1), the array substrate may also be configured such that the third insulating film has a recess at least in an area overlapping the channel-forming portion, the peripheral portion of the recess is an inclined surface that slopes upward from the bottom surface of the recess, and the light-shielding portion has a bottom portion disposed on the bottom surface of the recess and an inclined portion disposed on the inclined surface of the recess.

[0008] (3) In addition to the above (2), the array substrate may be configured such that the inclined portion overlaps the second electrode and the third electrode.

[0009] (4) In addition to any one of (1) to (3), the array substrate may further include a fourth insulating film provided on the upper side of the third insulating film, and the light-shielding portion may be arranged on the upper side of the fourth insulating film.

[0010] (5) In addition to any one of (1) to (3), the array substrate may further include a fourth insulating film provided on the upper side of the third insulating film, and a fifth insulating film provided on the upper side of the fourth insulating film, and the light-shielding portion may be arranged on the upper side of the fifth insulating film.

[0011] (6) A display device according to the technology described in this specification includes an array substrate according to any one of (1) to (5) above, and an opposing substrate arranged opposite the array substrate with a gap therebetween. [Effects of the Invention]

[0012] According to the technology described in this specification, it is possible to suppress a decrease in aperture ratio and reduce steps that may occur on the surface of the light-shielding portion. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a plan view of a liquid crystal panel, a driver, and a flexible substrate according to a first embodiment; [Figure 2] 1 is a cross-sectional view of a liquid crystal panel, a driver, and a flexible substrate according to Embodiment 1. [Figure 3]1 is a plan view showing a pixel array of a liquid crystal panel according to a first embodiment; [Figure 4] 4 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line iv-iv in FIG. 3. [Figure 5] 4 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vv in FIG. 3. [Figure 6] 1 is a plan view of a liquid crystal panel, a driver, and a flexible substrate according to a second embodiment; [Figure 7] FIG. 10 is a plan view showing a pixel array of a liquid crystal panel according to a second embodiment. [Figure 8] 8 is a cross-sectional view of the liquid crystal panel according to the second embodiment taken along line VIII-VIII in FIG. 7. [Figure 9] 8 is a cross-sectional view of the liquid crystal panel according to the second embodiment taken along line ix-ix in FIG. 7. [Figure 10] 10 is a cross-sectional view of an array substrate provided in a liquid crystal panel according to a third embodiment, taken along the same cutting line as in FIG. 9; [Figure 11] 10 , taken along line xi-xi of the array substrate according to the third embodiment. [Figure 12] 10 is a cross-sectional view of an array substrate according to a fourth embodiment taken along the same cutting line as FIG. 9; [Figure 13] 10 is a cross-sectional view of an array substrate according to a fifth embodiment taken along the same cutting line as FIG. 9; [Figure 14] 10 is a cross-sectional view of an array substrate according to a sixth embodiment taken along the same line as FIG. 9; DETAILED DESCRIPTION OF THE INVENTION

[0014] <Embodiment 1> Embodiment 1 will be described with reference to Figures 1 to 5. In this embodiment, a liquid crystal display device 10 will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in parts of each drawing, and each axis direction is drawn to correspond to the direction shown in each drawing. Also, the upper side of Figures 2, 4, and 5 is the front side, and the lower side of each figure is the back side.

[0015] As shown in Fig. 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back surface) of the liquid crystal panel 11 and includes a light source (e.g., an LED) that emits white light and optical components that convert the light from the light source into planar light by applying an optical effect. The central portion of the main surface of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, a frame-shaped outer peripheral portion of the main surface of the liquid crystal panel 11 that surrounds the display area AA is a non-display area NAA where no image is displayed.

[0016] The liquid crystal panel 11 will be described with reference to FIG. 1 and FIG. 2. As shown in FIGS. 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20, 21 together. The front side of the pair of substrates 20, 21 is the counter substrate 20, and the back side is the array substrate 21. The counter substrate 20 and the array substrate 21 are both formed by laminating various films on the inner surface of glass substrates. A liquid crystal layer 22 containing liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied, is disposed between the pair of substrates 20, 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral edges of the pair of substrates 20, 21. The seal portion 23 is formed in a rectangular frame shape so as to surround the liquid crystal layer 22. A polarizing plate 14 is attached to the outer surface of each of the substrates 20, 21.

[0017] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 so that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally from the counter substrate 20 and is exposed. The entire exposed portion 21A is a non-display area NAA, and a driver 12 and a flexible substrate 13 for supplying various signals are mounted on the exposed portion 21A.

[0018] The driver 12 is an LSI chip with an internal drive circuit. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 using COG (Chip On Glass) technology. The driver 12 processes various signals transmitted by the flexible substrate 13. As shown in FIGS. 1 and 2, the driver 12 is disposed adjacent to one side of the display area AA in the Y-axis direction, sandwiched between the display area AA and the flexible substrate 13 (described below). The driver 12 has a horizontally elongated rectangular shape in plan view. The driver 12 can supply various signals to the source lines 27 and other signals provided on the array substrate 21. The flexible substrate 13 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). One end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (e.g., a control board).

[0019] Next, the configuration of the display area AA of the array substrate 21 will be described with reference to Fig. 3. As shown in Fig. 3, at least TFTs (transistors, switching elements) 24 and pixel electrodes 25 are provided on the inner surface of the display area AA of the array substrate 21. The TFTs 24 and pixel electrodes 25 are arranged in a matrix (rows and columns) with multiple TFTs 24 and multiple pixel electrodes 25 spaced apart along the X-axis and Y-axis directions. Gate wiring (scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 are arranged around these TFTs 24 and pixel electrodes 25, intersecting each other at right angles. The gate wiring 26 extends along the X-axis direction, with multiple gate wirings 26 arranged at intervals along the Y-axis direction. The source wiring 27 extends along the Y-axis direction, with multiple source wirings 27 arranged at intervals along the X-axis direction. The TFT 24 includes a gate electrode (first electrode) 24A connected to the gate line 26, a source electrode (second electrode) 24B connected to the source line 27, a drain electrode (third electrode) 24C connected to the pixel electrode 25, and a semiconductor portion 24D made of a semiconductor material and connected to the source electrode 24B and the drain electrode 24C. The TFT 24 is driven based on a scanning signal supplied to the gate electrode 24A by the gate line 26. This scanning signal includes a potential higher than the threshold voltage of the TFT 24. This generates a channel region in the semiconductor portion 24D, allowing charge to move between the source electrode 24B and the drain electrode 24C via the channel region. Therefore, a potential related to an image signal (data signal) supplied to the source electrode 24B by the source line 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential related to the image signal. The pixel electrode 25 is disposed in a region surrounded by the gate wiring 26 and the source wiring 27, and has a planar shape that is, for example, a vertically long, substantially rectangular shape. The pixel electrode 25 has a plurality of slits 25A (two in FIG. 3) formed therein, which extend along the longitudinal direction (Y-axis direction) of the pixel electrode 25.

[0020] As shown in FIG. 4, the display area AA of the counter substrate 20 constituting the liquid crystal panel 11 is provided with a large number of color filters 28 at positions overlapping the pixel electrodes 25 of the array substrate 21. The color filters 28 are arranged in an alternating pattern along the X-axis direction, with three colors—red (R), green (G), and blue (B)—alternating along the X-axis direction. Each of the three color filters 28 extends along the Y-axis direction, resulting in a generally striped arrangement overall. The overlapping color filters 28 and pixel electrodes 25 form a pixel PX, which is a display unit. The display area AA of the counter substrate 20 is provided with a black matrix 29 that separates (at the boundaries) adjacent pixels PX in the X-axis direction and the Y-axis direction. The black matrix 29 is provided in the non-display area NAA as well as the display area AA. The black matrix 29 is in a lattice pattern so as to overlap the TFTs 24, gate lines 26, and source lines 27 in the display area AA, but is generally solid in the non-display area NAA. An overcoat film 30 is provided on the upper layer side of the color filter 28 and the black matrix 29. The overcoat film 30 is provided in a solid state over almost the entire area of ​​the counter substrate 20. The overcoat film 30 is made of an organic material such as an acrylic resin (e.g., PMMA), and functions to flatten any steps that occur on the layer below it. Note that an alignment film for aligning liquid crystal molecules contained in the liquid crystal layer 22 is formed on the innermost surface (uppermost layer) of each of the substrates 20, 21 that contacts the liquid crystal layer 22.

[0021] Here, various films laminated on the inner surface of the array substrate 21 will be described with reference to FIG. 5. As shown in FIG. 5, the array substrate 21 is laminated with a base coat film BC, a first metal film, a gate insulating film (first insulating film) 31, a semiconductor film, a second metal film, a first interlayer insulating film (second insulating film) 32, a planarizing film (third insulating film) 33, a first transparent electrode film, a third metal film, a second interlayer insulating film (fourth insulating film) 34, a second transparent electrode film, and an alignment film, in this order from the bottom up. The first metal film, the second metal film, and the third metal film are each a single-layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, thereby providing electrical conductivity and light-shielding properties. The first metal film constitutes the gate wiring 26, the gate electrode 24A of the TFT 24, etc. The first metal film has a thickness of, for example, approximately 200 nm to 600 nm. The second metal film constitutes the source wiring 27, the source electrode 24B and the drain electrode 24C of the TFT 24, etc. The second metal film has a thickness of, for example, about 200 nm to 600 nm. The third metal film constitutes the light-shielding portion 36, which will be described later. The third metal film has a thickness of, for example, about 150 nm to 400 nm, which may be smaller than the thicknesses of the first metal film and the second metal film. The first transparent electrode film and the second transparent electrode film are made of a transparent electrode material (for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). The first transparent electrode film constitutes the common electrode 35, which will be described later, etc. The second transparent electrode film constitutes the pixel electrode 25, etc.

[0022] The semiconductor film is made of an oxide semiconductor material and constitutes the semiconductor portion 24D of the TFT 24. The semiconductor film may contain at least one metal element selected from the group consisting of In, Ga, and Zn, and may be, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). The In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and examples include In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, and In:Ga:Zn=1:1:2. The In-Ga-Zn-O-based semiconductor used in the semiconductor film may be amorphous or crystalline. Instead of the In-Ga-Zn-O-based semiconductor, the semiconductor film may contain other oxide semiconductors. For example, it may contain an In-Sn-Zn-O-based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In-W-Zn-O-based semiconductor containing W (tungsten), an In-W-Sn-Zn-O-based semiconductor, an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, or an In-Ga-Zn-Sn-O-based semiconductor. The oxide semiconductor material of the semiconductor film has a higher resistance value when no voltage is applied (off state) than polysilicon semiconductor material, and also has a higher electron mobility than amorphous silicon semiconductor material.

[0023] The base coat film BC, the gate insulating film 31, the first interlayer insulating film 32, and the second interlayer insulating film 34 are each made of silicon nitride (SiN xThe base coat film BC is made of an inorganic material such as silicon dioxide (SiO2). The base coat film BC has a thickness of, for example, about 200 nm to 500 nm. The gate insulating film 31 has a thickness of, for example, about 200 nm to 600 nm. The first interlayer insulating film 32 has a thickness of, for example, about 200 nm to 600 nm, which may be approximately the same as the thickness of the gate insulating film 31. The second interlayer insulating film 34 has a thickness of, for example, about 100 nm to 400 nm, which may be smaller than the thicknesses of the gate insulating film 31 and the first interlayer insulating film 32. The planarizing film 33 is made of an organic material such as PMMA (acrylic resin). The planarizing film 33 has a thickness of, for example, about 1.5 μm to 3 μm (preferably about 2 μm), which is much larger than the thicknesses of the gate insulating film 31, the first interlayer insulating film 32, and the second interlayer insulating film 34. The planarizing film 33 flattens the inner surface of the array substrate 21 (the surface on the liquid crystal layer 22 side).

[0024] The gate insulating film 31 insulates the first metal film on the lower layer from the semiconductor film and second metal film on the upper layer. For example, the gate insulating film 31 insulates the intersection of the gate line 26 made of the first metal film and the source line 27 made of the second metal film. In the TFT 24, the gate electrode 24A made of the first metal film and the semiconductor portion 24D made of the semiconductor film overlap each other. The first interlayer insulating film 32 and the planarizing film 33 insulate the semiconductor film and second metal film on the lower layer from the first transparent electrode film and third metal film on the upper layer. For example, the source line 27 made of the second metal film and the common electrode 35 made of the first transparent electrode film are insulated by the first interlayer insulating film 32 and the planarizing film 33. The second interlayer insulating film 34 insulates the first transparent electrode film and third metal film on the lower layer from the second transparent electrode film on the upper layer. For example, the common electrode 35 made of the first transparent electrode film and the pixel electrode 25 made of the second transparent electrode film are kept in an insulated state by the second interlayer insulating film .

[0025] The common electrode 35, which is made of the first transparent electrode film, has an overall size equivalent to the display area AA. As shown in FIG. 4, the common electrode 35 is disposed below all of the pixel electrodes 25, with the second interlayer insulating film 34 interposed therebetween. A common potential (reference potential) is supplied to the common electrode 35. When the pixel electrodes 25 are charged to a potential based on the image signals transmitted to the source lines 27 as the TFTs 24 are driven based on the scanning signals transmitted through the gate lines 26, a potential difference is generated between the pixel electrodes 25 and the common electrode 35. This generates a fringe electric field (oblique electric field) between the opening edge of the slit 25A in the pixel electrode 25 and the common electrode 35, which includes a component normal to the main surface of the array substrate 21 in addition to a component along the main surface of the array substrate 21. Therefore, the orientation of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by utilizing this fringe electric field, and a predetermined display can be produced based on the orientation of the liquid crystal molecules. That is, the liquid crystal panel 11 according to this embodiment operates in FFS (Fringe Field Switching) mode.

[0026] Next, the configuration of the TFT 24 will be described in detail. As shown in FIG. 3, the gate electrode 24A of the TFT 24 is formed by a portion of the gate wiring 26 near the intersection with the source wiring 27. The source electrode 24B is disposed at one end of the TFT 24 in the X-axis direction (the right end in FIG. 3). The source electrode 24B overlaps with a portion of the gate electrode 24A and is connected to the semiconductor portion 24D. The drain electrode 24C of the TFT 24 is disposed at a position spaced apart from the source electrode 24B in the X-axis direction (first direction), i.e., at the other end of the TFT 24 in the X-axis direction (the left end in FIG. 3). The drain electrode 24C has a vertically elongated, approximately rectangular shape extending along the Y-axis direction. The end of the drain electrode 24C on the source electrode 24B side (the upper side in FIG. 3) is disposed so as to overlap with a portion of the gate electrode 24A and is connected to the semiconductor portion 24D. An end of the drain electrode 24C on the opposite side to the source electrode 24B side (the lower side in FIG. 3) is disposed so as to overlap a part of the pixel electrode 25. A pixel contact hole CH is provided in communication with the first interlayer insulating film 32, the planarizing film 33, and the second interlayer insulating film 34, which are interposed between the drain electrode 24C and the pixel electrode 25, at a position that overlaps both the drain electrode 24C and the pixel electrode 25. The drain electrode 24C and the pixel electrode 25 are connected to each other through the pixel contact hole CH.

[0027] As shown in FIG. 3, the semiconductor portion 24D constituting the TFT 24 has a horizontally elongated shape extending along the X-axis direction. The semiconductor portion 24D is larger in dimension in the X-axis direction than the gate electrode 24A. The semiconductor portion 24D overlaps the gate electrode 24A via the gate insulating film 31. One end of the semiconductor portion 24D in the X-axis direction is connected to the source electrode 24B. The other end of the semiconductor portion 24D in the X-axis direction is connected to the drain electrode 24C. A portion of the semiconductor portion 24D sandwiched between the source electrode 24B and the drain electrode 24C in the X-axis direction is a channel-forming portion 24D1 in which a channel region is generated when the TFT 24 is driven. The channel-forming portion 24D1 is a portion of the semiconductor portion 24D that overlaps with the gate electrode 24A but does not overlap with the source electrode 24B or the drain electrode 24C.

[0028] As shown in FIGS. 3 and 5 , the array substrate 21 according to this embodiment includes a light-shielding portion 36 that is electrically isolated and overlaps a portion of the semiconductor portion 24D. The light-shielding portion 36 has a horizontally elongated, substantially rectangular shape extending along the X-axis direction. The light-shielding portion 36 overlaps at least a channel-forming portion 24D1, which is a portion of the semiconductor portion 24D sandwiched between the source electrode 24B and the drain electrode 24C. Specifically, a central portion of the light-shielding portion 36 in the X-axis direction overlaps the channel-forming portion 24D1, one end portion of the light-shielding portion 36 in the X-axis direction overlaps the end portion of the source electrode 24B connected to the semiconductor portion 24D, and the other end portion of the light-shielding portion 36 in the X-axis direction overlaps the end portion of the drain electrode 24C connected to the semiconductor portion 24D. The light-shielding portion 36 is wider in the Y-axis direction (a second direction intersecting the first direction) than the semiconductor portion 24D, and both ends of the light-shielding portion 36 in the Y-axis direction do not overlap the semiconductor portion 24D. The light-shielding portion 36 is made of a third metal film and is disposed on the upper layer side of the planarizing film 33.

[0029] As described above, the light-shielding portion 36 overlaps at least the channel-forming portion 24D1 of the semiconductor portion 24D, thereby blocking light that may be irradiated onto the channel-forming portion 24D1 of the semiconductor portion 24D during the manufacturing process of the array substrate 21. This reduces the likelihood of the threshold voltage of the TFT 24 shifting negatively due to light irradiation, thereby reducing the degradation of the characteristics of the TFT 24. Furthermore, because the light-shielding portion 36 is electrically isolated, a connection structure with other electrodes (e.g., the gate electrode 24A or the common electrode 35) is not required. This avoids a reduction in the aperture ratio of the pixel PX due to the connection structure, which is advantageous for achieving high resolution in the liquid crystal panel 11. Moreover, since the electrically isolated light-shielding portion 36 does not require any electrical function, high electrical resistance does not pose a problem. Therefore, for example, by making the thickness of the third metal film smaller than the thicknesses of the first and second metal films, the thickness of the light-shielding portion 36 can be made smaller than the thicknesses of the gate electrode 24A, the source electrode 24B, and the drain electrode 24C. This reduces steps that may occur on the surface of the light-shielding portion 36 disposed above the planarizing film 33, thereby improving the coverage of the second interlayer insulating film 34 laminated on the light-shielding portion 36 and, as a result, improving yields, etc. Furthermore, because the planarizing film 33, which is thicker than the first interlayer insulating film 32 and is in addition to the first interlayer insulating film 32, is interposed between the light-shielding portion 36 and the semiconductor portion 24D, it is possible to reduce parasitic capacitance that may occur between the light-shielding portion 36 and the semiconductor portion 24D. This makes it less likely that charges moving through the channel region of the semiconductor portion 24D will become dull as the TFT 24 is driven, increasing the reliability with which the pixel electrode 25 is charged to a desired potential.

[0030] As described above, the array substrate 21 of this embodiment includes a TFT (transistor) 24 having a gate electrode (first electrode) 24A, a semiconductor portion 24D provided above the gate electrode 24A and overlapping the gate electrode 24A, a source electrode (second electrode) 24B provided above the semiconductor portion 24D and connected to the semiconductor portion 24D, and a drain electrode (third electrode) 24C provided above the gate electrode 24A and arranged at an interval from the source electrode 24B and connected to the semiconductor portion 24D, and a TFT (transistor) 24 having a drain electrode (third electrode) 24C provided above the gate electrode 24A and below the semiconductor portion 24D. the semiconductor portion 24D includes a gate insulating film (first insulating film) 31 provided above the source electrode 24B and the drain electrode 24C, a first interlayer insulating film (second insulating film) 32 provided above the source electrode 24B and the drain electrode 24C, a planarization film (third insulating film) 33 provided above the first interlayer insulating film 32, and a light-shielding portion 36 provided above the planarization film 33, the planarization film 33 having a thickness greater than that of the first interlayer insulating film 32, and the light-shielding portion 36 being electrically isolated and arranged to overlap at least a channel-forming portion 24D1 which is a portion of the semiconductor portion 24D that is sandwiched between the source electrode 24B and the drain electrode 24C.

[0031] When a voltage equal to or greater than the threshold voltage of the TFT 24 is applied to the gate electrode 24A, a channel region is generated in the channel-forming portion 24D1, which is a portion of the semiconductor portion 24D that is disposed above the gate electrode 24A and overlaps the gate electrode 24A with the gate insulating film 31 interposed therebetween, and charge can move between the source electrode 24B and the drain electrode 24C through the channel region. The light-shielding portion 36 is disposed above at least the channel-forming portion 24D1 of the semiconductor portion 24D, and can therefore block light that may be irradiated onto the channel-forming portion 24D1 of the semiconductor portion 24D during the manufacturing process of the array substrate 21. This makes it difficult for the threshold voltage of the TFT 24 to shift in the negative direction due to light irradiation, thereby making it difficult for the characteristics of the TFT 24 to deteriorate.

[0032] Because the light-shielding portion 36 is electrically isolated, a connection structure with other electrodes or the like is not required. Therefore, a decrease in aperture ratio due to the connection structure can be avoided. Furthermore, because the electrically isolated light-shielding portion 36 is not required to have any electrical function, a high electrical resistance does not pose a problem. Therefore, the thickness of the light-shielding portion 36 can be reduced, thereby reducing steps that may occur on the surface of the light-shielding portion 36. Furthermore, because the planarization film 33, which is thicker than the first interlayer insulating film 32, is interposed between the light-shielding portion 36 and the semiconductor portion 24D in addition to the first interlayer insulating film 32, the parasitic capacitance that may occur between the light-shielding portion 36 and the semiconductor portion 24D can be reduced.

[0033] Furthermore, the liquid crystal panel (display device) 11 according to this embodiment includes the above-described array substrate 21 and a counter substrate 20 disposed opposite to and spaced apart from the array substrate 21. The liquid crystal panel 11 configured in this manner can achieve higher definition and improve yield.

[0034] <Embodiment 2> A second embodiment will be described with reference to Figures 6 to 9. In this second embodiment, a touch panel function is added. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0035] As shown in FIG. 6, the liquid crystal panel 111 according to this embodiment has both a display function for displaying an image and a touch panel function for detecting a position (input position) at which a user inputs information based on the displayed image. A touch panel pattern for achieving the touch panel function is integrated (in-cell) into the liquid crystal panel 111. This touch panel pattern is a so-called projected capacitive type, and its detection method is a self-capacitive type. The touch panel pattern is composed of a plurality of touch electrodes (position detection electrodes) 37 arranged in a matrix on the main surface of the liquid crystal panel 111. The touch electrodes 37 are arranged in a display area AA of the liquid crystal panel 111. Therefore, the display area AA of the liquid crystal panel 111 substantially coincides with a touch area (position input area) where an input position can be detected, and the non-display area NAA substantially coincides with a non-touch area (non-position input area) where an input position cannot be detected. When a user approaches a conductive finger (position input object) to the surface of liquid crystal panel 111 to input a position based on the image in display area AA of liquid crystal panel 111 that is visually recognized, a capacitance is formed between the finger and touch electrode 37. As a result, the capacitance detected at touch electrode 37 near the finger changes as the finger approaches, and becomes different from that of touch electrode 37 farther away from the finger, making it possible to detect the input position based on this.

[0036] As shown in FIG. 6 , the touch electrodes 37 are formed by dividing the common electrode 135. Specifically, the common electrode 135 has partition slits that form a grid in a plan view. The partition slits divide the common electrode 135 into a grid pattern, thereby forming a plurality of electrically independent touch electrodes 37. The plurality of touch electrodes 37 arranged in a grid pattern are separated by the partition slits. Note that the specific number of touch electrodes 37 can be changed as appropriate, in addition to the number shown in FIG. 6 . The touch electrode 37 has a substantially rectangular shape in a plan view, with each side measuring approximately several millimeters. Therefore, the size of the touch electrode 37 in a plan view is much larger than that of the pixel PX, and the touch electrode 37 is arranged in an area that spans multiple pixels PX in the X-axis direction and the Y-axis direction.

[0037] As shown in FIG. 7 , a plurality of touch wirings (position detection wirings) 38 connected to a plurality of touch electrodes 37 are provided on the inner surface of the display area AA of the array substrate 121. The touch wirings 38 extend along the Y-axis direction parallel to the source wirings 127 and are arranged so as to overlap the source wirings 127 in a plan view. The plurality of touch wirings 38 are individually connected to the plurality of touch electrodes 37. Ends of the plurality of touch wirings 38 opposite to the touch electrodes 37 to which they are connected are each connected to a driver 112 (see FIG. 6 ). A common signal (reference potential signal) related to the display function and a touch signal (position detection signal) related to the touch function are supplied to the touch wirings 38 from the driver 112 at different timings (in a time-division manner). The timing when the common signal is supplied from the driver 112 to the touch wirings 38 is a display period, and the timing when the touch signal is supplied from the driver 112 to the touch wirings 38 is a sensing period (position detection period). During the display period, a common signal is supplied to all the touch wirings 38, so that all the touch electrodes 37 have a reference potential and function as the common electrode 135.

[0038] As shown in FIGS. 8 and 9 , the touch wiring 38 is formed from a portion of the third metal film that is separate from the light-shielding portion 136. Therefore, a first interlayer insulating film 132 and a planarization film 133 are interposed between the touch wiring 38 and the overlapping source wiring 127. The light-shielding portion 136 is thinner than the touch wiring 38. This can be achieved by forming the third metal film and then processing the third metal film to partially thin it during the manufacturing process of the array substrate 121. The thickness of the touch wiring 38 can be approximately the same as the thickness of each of the gate wiring 126 and the source wiring 127, for example, which allows the wiring resistance of the touch wiring 38 to be kept sufficiently low.

[0039] <Embodiment 3> Embodiment 3 will be described with reference to Fig. 10 or 11. In this embodiment 3, the configurations of the planarization film 233 and the light-shielding portion 236 are changed from those of the above-mentioned embodiment 2. Note that redundant explanations of the structure, action, and effect similar to those of the above-mentioned embodiment 2 will be omitted.

[0040] As shown in FIGS. 10 and 11 , the planarization film 233 according to this embodiment has a recess 39 at least in a region overlapping the channel-forming portion 224D1 of the semiconductor portion 224D. The recess 39 is arranged in a horizontally elongated, substantially rectangular region in the planarization film 233 in a plan view, and is arranged to overlap the light-shielding portion 236. The recess 39 is generally mortar-shaped overall and has a bottom surface 39A that is lower than the upper surface (surface) of the planarization film 233, and an inclined surface 39B that forms the periphery of the recess 39 and slopes upward from the bottom surface 39A. The bottom surface 39A is a flat surface parallel to the upper surface of the planarization film 233. The inclined surface 39B is inclined at a predetermined angle with respect to the Z-axis direction (a third direction intersecting the first and second directions), which is the normal direction to the bottom surface 39A.

[0041] As shown in FIGS. 10 and 11 , the light-shielding portion 236 has a bottom portion 236A disposed on the bottom surface 39A of the recess 39 and an inclined portion 236B disposed on the inclined surface 39B of the recess 39. The bottom portion 236A is flat and parallel to the bottom surface 39A, and is disposed so as to overlap substantially the entire area of ​​the channel-forming portion 224D1. The inclined portion 236B is inclined at a predetermined angle with respect to the Z-axis direction, which is the normal direction of the bottom portion 236A. The inclined portion 236B extends radially from the bottom portion 236A and is disposed in a frame shape so as to surround the entire periphery of the bottom portion 236A. Therefore, portions of the inclined portion 236B are disposed so as to overlap portions of the source electrode 224B and the drain electrode 224C (portions of the semiconductor portion 224D connected to the source electrode 224B and the drain electrode 224C). The frame-shaped inclined portion 236B is inclined so that a main surface 236B1 on the back side (planarizing film 233 side) faces outward in the radial direction centered on the channel component 224D1 that overlaps the inclined portion 236B.

[0042] In this configuration, when light is irradiated from the backlight device onto the liquid crystal panel 11, the light travels from the gate electrode 224A side toward the light-shielding portion 236 side, and a portion of the light is reflected by the rear principal surface 236B1 of the inclined portion 236B. This reflected light travels in the direction of the rear principal surface 236B1 of the inclined portion 236B, that is, toward the outside of the radial direction centered on the channel-forming portion 224D1. As a result, the light reflected by the inclined portion 236B is directed outward from the semiconductor portion 224D, making it difficult for the light to irradiate the channel-forming portion 224D1 of the semiconductor portion 224D. Moreover, because the inclined portion 236B is arranged to overlap a portion of each of the source electrode 224B and the drain electrode 224C, it is more unlikely that the light reflected by the rear principal surface 236B1 of the inclined portion 236B will travel toward the channel-forming portion 224D1 of the semiconductor portion 224D.

[0043] As described above, according to this embodiment, the planarization film 233 is provided with the recess 39 in at least an area overlapping the channel-forming portion 224D1, and the peripheral portion of the recess 39 is formed as an inclined surface 39B that slopes upward from the bottom surface 39A of the recess 39. The light-shielding portion 236 has a bottom 236A disposed on the bottom surface 39A of the recess 39 and an inclined portion 236B disposed on the inclined surface 39B of the recess 39. Since the inclined portion 236B of the light-shielding portion 236 is disposed on the inclined surface 39B that slopes upward from the bottom surface 39A of the recess 39, light traveling from the gate electrode 224A side toward the light-shielding portion 236 side is reflected by the inclined portion 236B, making it easier to direct the reflected light out of the semiconductor portion 224D. This makes it difficult for light to be irradiated onto the channel-forming portion 224D1 of the semiconductor portion 224D.

[0044] Furthermore, the inclined portion 236B is disposed so as to overlap the source electrode 224B and the drain electrode 224C. By disposing the inclined portion 236B so as to overlap the source electrode 224B and the drain electrode 224C, it becomes more unlikely that light reflected by the inclined portion 236B will be directed toward the channel forming portion 224D1 of the semiconductor portion 224D.

[0045] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 12. In this fourth embodiment, the configuration of the array substrate 321 and the arrangement of the light-shielding portion 336 are changed from those in the second embodiment. Note that redundant explanations of the structure, actions, and effects similar to those in the second embodiment will be omitted.

[0046] As shown in FIG. 12 , the light-shielding portion 336 according to this embodiment is disposed above the second interlayer insulating film 334. Specifically, in the array substrate 321 according to this embodiment, a fourth metal film is formed above the second transparent electrode film during manufacturing, and the fourth metal film is patterned to provide the light-shielding portion 336. Like the first, second, and third metal films, the fourth metal film is a single-layer film made of one metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different metal materials, thereby providing electrical conductivity and light-shielding properties. With this configuration, the second interlayer insulating film 334, in addition to the first interlayer insulating film 332 and the planarizing film 333, is interposed between the light-shielding portion 336 made of the fourth metal film and the semiconductor portion 324D made of a semiconductor film. This further reduces parasitic capacitance that may occur between the light-shielding portion 336 and the semiconductor portion 324D. Furthermore, the light-shielding portion 336 made of the fourth metal film is disposed above the touch wiring 338 made of the third metal film via the second interlayer insulating film 334, thereby avoiding a short circuit with the touch wiring 338. This increases the degree of freedom in setting the formation range of the light-shielding portion 336.

[0047] As described above, according to this embodiment, the second interlayer insulating film (fourth insulating film) 334 is provided above the planarizing film 333, and the light-shielding portion 336 is disposed above the second interlayer insulating film 334. In this way, the second interlayer insulating film 334, in addition to the first interlayer insulating film 332 and the planarizing film 333, is interposed between the light-shielding portion 336 and the semiconductor portion 324D. This makes it possible to further reduce parasitic capacitance that may occur between the light-shielding portion 336 and the semiconductor portion 324D.

[0048] <Embodiment 5> A fifth embodiment will be described with reference to Fig. 13. In this fifth embodiment, the configuration of the array substrate 421 and the arrangement of the light-shielding portion 436 are changed from those in the fourth embodiment. Note that redundant explanations of the structure, actions, and effects similar to those in the fourth embodiment will be omitted.

[0049] 13, the array substrate 421 according to this embodiment has a third interlayer insulating film (fifth insulating film) 40 provided on the upper side of the second transparent electrode film. The third interlayer insulating film 40 is made of an inorganic material such as silicon nitride or silicon oxide, similar to the gate insulating film 431, the first interlayer insulating film 432, and the second interlayer insulating film 434. The third interlayer insulating film 40 has a thickness of, for example, about 100 nm to 400 nm. The light-shielding portion 436 is disposed on the upper side of the third interlayer insulating film 40. More specifically, in the manufacturing process of the array substrate 421 according to this embodiment, the third interlayer insulating film 40 is formed on the upper side of the second transparent electrode film, and then a fourth metal film is formed on the upper side of the third interlayer insulating film 40, and the fourth metal film is patterned to provide the light-shielding portion 436. According to this configuration, in addition to the first interlayer insulating film 432 and the planarizing film 433, the second interlayer insulating film 434 and the third interlayer insulating film 40 are interposed between the light-shielding portion 436 and the semiconductor portion 424D. This makes it possible to further reduce parasitic capacitance that may occur between the light-shielding portion 436 and the semiconductor portion 424D. Furthermore, the light-shielding portion 436 made of the fourth metal film is arranged above the touch wiring 438 made of the third metal film, with the second interlayer insulating film 434 and the third interlayer insulating film 40 interposed therebetween, thereby preventing a short circuit with the touch wiring 438. This increases the degree of freedom in setting the formation range of the light-shielding portion 436.

[0050] As described above, according to this embodiment, the second interlayer insulating film 434 is provided above the planarizing film 433, and the third interlayer insulating film (fifth insulating film) 40 is provided above the second interlayer insulating film 434, and the light-shielding portion 436 is disposed above the third interlayer insulating film 40. In this way, in addition to the first interlayer insulating film 432 and planarizing film 433, the second interlayer insulating film 434 and the third interlayer insulating film 40 are interposed between the light-shielding portion 436 and the semiconductor portion 424D. This makes it possible to further reduce parasitic capacitance that may occur between the light-shielding portion 436 and the semiconductor portion 424D.

[0051] <Embodiment 6> A sixth embodiment will be described with reference to Fig. 14. In this sixth embodiment, the arrangement of the pixel electrode 525, the common electrode 535, and the light-shielding portion 536 is changed from that of the fifth embodiment. Note that a redundant description of the structure, action, and effect similar to those of the fifth embodiment will be omitted.

[0052] As shown in FIG. 14 , the pixel electrode 525 according to this embodiment is disposed on the upper side of the third interlayer insulating film 540. Accordingly, the common electrode 535 is disposed below the third interlayer insulating film 540 and above the second interlayer insulating film 534. The light-shielding portion 536 is disposed below the third interlayer insulating film 540 and above the second interlayer insulating film 534. Specifically, in manufacturing the array substrate 521 according to this embodiment, after the second interlayer insulating film 534 is formed, the common electrode 535 is provided by forming and patterning a first transparent electrode film. Thereafter, the light-shielding portion 536 is provided by forming and patterning a fourth metal film. Thereafter, the third interlayer insulating film 540 is formed, and then the pixel electrode 525 is provided by forming and patterning a second transparent electrode film. According to this configuration, in addition to the first interlayer insulating film 532 and the planarizing film 533, the second interlayer insulating film 534 is interposed between the light-shielding portion 536 made of the fourth metal film and the semiconductor portion 524D made of the semiconductor film. This further reduces parasitic capacitance that may occur between the light-shielding portion 536 and the semiconductor portion 524D. Furthermore, the light-shielding portion 536 made of the fourth metal film is disposed above the touch wiring 538 made of the third metal film via the second interlayer insulating film 534, thereby preventing short-circuiting with the touch wiring 538. This increases the degree of freedom in determining the formation range of the light-shielding portion 536. In this embodiment, the pixel contact hole CH is provided in communication with the first interlayer insulating film 532, the planarizing film 533, the second interlayer insulating film 534, and the third interlayer insulating film 540.

[0053] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0054] (1) The specific formation range of the light-shielding portion 36, 136, 236, 336, 436, 536 in a plan view can be changed as appropriate to be other than that shown in the drawings. For example, the formation range of the light-shielding portion 36, 136, 236, 336, 436, 536 may be narrower than the formation range shown in each drawing. Specifically, the light-shielding portion 36, 136, 236, 336, 436, 536 may be formed in a range that overlaps with the channel constituent portions 24D1, 224D1 of the semiconductor portions 24D, 224D, 324D, 424D, 524D but does not overlap with portions of the semiconductor portions 24D, 224D, 324D, 424D, 524D other than the channel constituent portions 24D1, 224D1. Furthermore, the formation range of the light-shielding portions 36, 136, 236, 336, 436, and 536 may be wider than the formation range illustrated in each drawing.

[0055] (2) In the configurations described in the fourth to sixth embodiments, the touch wiring 338, 438, 538 may be configured with the same metal film (referred to as a "fourth metal film" in the explanations of the fourth to sixth embodiments) as the light-shielding portions 336, 436, 536. In this case, it is possible to reduce the number of metal films provided on the array substrate 321, 421, 521 by one.

[0056] (3) In the configurations described in the second to sixth embodiments, the touch panel pattern may be a mutual capacitance type in addition to a self-capacitance type.

[0057] (4) The configurations described in the third to sixth embodiments may be combined with the configuration described in the first embodiment. That is, the configurations described in the third to sixth embodiments may not have a touch panel function, the common electrode 535 may have a non-divided structure, and the touch wirings 338, 438, and 538 may not be provided.

[0058] (5) In the configuration described in the fifth embodiment, the pixel electrode 25 and the common electrode 35 may be arranged in the same layering order as in the sixth embodiment.

[0059] (6) In the configuration described in the sixth embodiment, the pixel electrode 525 and the common electrode 535 may be arranged in the same layering order as in the fifth embodiment.

[0060] (7) The pixel electrodes 25, 525 may be made of a first transparent electrode film, and the common electrodes 35, 135, 535 may be made of a second transparent electrode film. In this case, it is preferable to form slits in the common electrodes 35, 135, 535 for alignment control.

[0061] (8) The planar shape of the liquid crystal panels 11, 111 may be a vertically long rectangle, a square, a circle, a semicircle, an oval, an ellipse, a trapezoid, or the like.

[0062] (9) The display mode of the liquid crystal panel 11, 111 may be VA mode, IPS mode, or the like in addition to FFS mode.

[0063] (10) The liquid crystal panels 11 and 111 may be of a reflective or semi-transmissive type in addition to a transmissive type. If the liquid crystal panels 11 and 111 are of a reflective type, the backlight device can be omitted.

[0064] (11) Display panels other than the liquid crystal panels 11 and 111 (organic EL display panels, etc.) may also be used. [Explanation of symbols]

[0065] 11, 111... liquid crystal panel (display device), 20... opposing substrate, 21, 121, 321, 421, 521... array substrate, 24... TFT (transistor), 24A... gate electrode (first electrode), 24B... source electrode (second electrode), 24C... drain electrode (third electrode), 24D, 224D, 324D, 424D, 524D... semiconductor portion, 24D1, 224D1... channel forming portion, 31... gate insulating film (first insulating film), 32 , 132,332,432,532...first interlayer insulating film (second insulating film), 33,133,233,333,433,533...planarization film (third insulating film), 34,334,434,534...second interlayer insulating film (fourth insulating film), 36,136,236,336,436,536...light-shielding portion, 39...recess, 39A...bottom surface, 39B...inclined surface, 40,540...third interlayer insulating film (fifth insulating film), 236A...bottom portion, 236B...inclined portion

Claims

1. A first electrode; a semiconductor portion provided above the first electrode and overlapping the first electrode; a second electrode provided on an upper layer side of the semiconductor portion and connected to the semiconductor portion; a transistor having a third electrode provided on an upper layer side of the semiconductor portion, arranged at an interval from the second electrode, and connected to the semiconductor portion; a first insulating film provided above the first electrode and below the semiconductor portion; a second insulating film provided on an upper layer side of the second electrode and the third electrode; a third insulating film provided on an upper layer side of the second insulating film; a light-shielding portion provided above the third insulating film, the third insulating film has a thickness greater than that of the second insulating film, The light-shielding portion is electrically isolated and is arranged to overlap at least a channel-forming portion that is a portion of the semiconductor portion sandwiched between the second electrode and the third electrode.

2. a recess is provided in the third insulating film at least in a range overlapping with the channel constituent portion, and a peripheral portion of the recess is an inclined surface that slopes upward from a bottom surface of the recess, 2. The array substrate according to claim 1, wherein the light-shielding portion has a bottom portion disposed on the bottom surface of the recess, and an inclined portion disposed on the inclined surface of the recess.

3. 3. The array substrate according to claim 2, wherein the inclined portion is disposed so as to overlap the second electrode and the third electrode.

4. a fourth insulating film provided on an upper layer side of the third insulating film; 4. The array substrate according to claim 1, wherein the light-shielding portion is disposed on an upper layer side of the fourth insulating film.

5. a fourth insulating film provided on an upper layer side of the third insulating film; a fifth insulating film provided on an upper layer side of the fourth insulating film, The array substrate according to claim 1 , wherein the light-shielding portion is disposed on an upper layer side of the fifth insulating film.

6. An array substrate according to any one of claims 1 to 3; a counter substrate disposed opposite to the array substrate with a gap therebetween.

Images