Semiconductor element

Abstract

To provide a semiconductor element with suppressed increase in on-resistance in spite of being a normally-off type.SOLUTION: A semiconductor element 100 includes a first GaN layer 111, an AlxGa1-xN(0<x≤1) layer 112a, a second AlxGa1-xN(0<x≤1) layer 112b, a second GaN layer 113, and a p-type GaN layer 114. The first AlxGa1-xN layer 112a is formed in thickness where a two-dimensional electron gas 21 is not formed on a heterointerface between the first GaN layer 111 and the first AlxGa1-xN layer 112a in a non-gate bias state. The second AlxGa1-xN layer 122b is formed in thickness where a two-dimensional electron gas 21 is formed on a heterointerface between the first GaN layer 111 and the second AlxGa1-xN layer 112b in the non-gate bias state. The first AlxGa1-xN layer 112a is formed in a region where at least a gate electrode 115 is formed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As a semiconductor device with excellent high-frequency characteristics, the development of HEMT (High Electron Mobility Transistor) has been carried out. As one of the HEMTs, there is a GaN-based field-effect transistor having an AlGaN / GaN heterojunction formed by crystal growth of a thin film of Al x Ga 1-x N (0 < x ≦ 1) (hereinafter sometimes referred to as "AlGaN"). In the GaN-based field-effect transistor, a layer of two-dimensional electron gas (hereinafter sometimes referred to as "2DEG") formed by the accumulation of highly mobile two-dimensional electrons is formed on the AlGaN / GaN junction surface. The 2DEG can freely move on the heterointerface between the GaN layer and the Al x Ga 1-x N layer (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in a GaN-based field-effect transistor having an AlGaN / GaN structure, the threshold voltage often takes a negative value. When the threshold voltage is a negative value, it becomes a normally-on type. However, when the GaN-based field-effect transistor is used as a switching element, particularly when used in a field dealing with large power, it is preferable to use a normally-off type element that conducts when a positive voltage is applied to the gate.

[0005] In a GaN-based field effect transistor, in order to achieve normally-off operation, for example, methods such as reducing the thickness of the Al x Ga 1-x N layer, or reducing the Al composition ratio in the Al x Ga 1-x N layer can be mentioned.

[0006] FIG. 8 shows a GaN-based field effect transistor 900 that has been made normally-off by reducing the thickness of the Al x Ga 1-x N layer 912. FIG. 9 is a diagram showing the on-resistance Ron in the GaN-based field effect transistor 900 that has been made normally-off by reducing the thickness of the Al x Ga 1-x N layer 912. [[ID=​​​​​​​​​​​​​​​​​​​​​​​​​

[0009] Al x Ga 1-x The N layer 912 is in a state where no gate bias is applied and the first GaN layer 911 and Al x Ga 1-x The thickness is set to such a value that the 2DEG 21 is not formed in the portion of the first GaN layer 911 near the heterointerface with the N layer 912. This allows the GaN-based field effect transistor 900 to function as a normally-off type.

[0010] The drain-source on-resistance Ron is expressed by the following formula:

number

[0011] Al x Ga 1-x In the GaN-based field effect transistor 900 in which the thickness of the N layer 912 is thin, the first GaN layer 911 and the Al x Ga 1-x The concentration of the 2DEG 21 formed in the portion of the first GaN layer 911 near the heterointerface with the N layer 912 decreases, which causes a problem of increased drain-source on-resistance Ron.

[0012] In other words, in order to realize normally-off in semiconductor devices, x Ga 1-x When the thickness of the N layer 912 is reduced, there is a problem that the on-resistance Ron between the drain and source increases.

[0013] Therefore, an object of the present invention is to solve such problems, and to provide a semiconductor device that is of a normally-off type and in which an increase in on-resistance Ron is suppressed.

Means for Solving the Problems

[0014] The semiconductor device of the present invention includes a first GaN layer, a first Al x Ga 1-x N (0 < x ≦ 1) layer formed on the first GaN layer, and a second Al x Ga 1-x N layer formed adjacent to the first Al x Ga 1-x N (0 < x ≦ 1) layer on the first GaN layer, a second GaN layer formed on the first Al x Ga 1-x N layer and the second Al x Ga 1-x N layer, a p-type GaN layer formed on the second GaN layer, a source electrode formed on the second Al x Ga 1-x N layer, a drain electrode formed on the second Al x Ga 1-x N layer, and a gate electrode electrically connected to the p-type GaN layer. The p-type GaN layer is formed in an island shape in a region on the source electrode side above the second GaN layer. The first Al x Ga 1-x N layer is formed to have a thickness such that no two-dimensional electron gas is formed in a portion of the first GaN layer near the heterointerface between the first GaN layer and the first Al x Ga 1-x N layer in a gate-bias-free state, and the second Al x Ga 1-x N layer is formed to have a thickness such that a two-dimensional electron gas is formed in a portion of the first GaN layer near the heterointerface between the first GaN layer and the second Al x Ga[[ID=​​​​​ [Effect of the Invention]

[0015] The semiconductor device of the present invention has a first Al x Ga 1-x N (0 < x ≤ 1) layer formed on the first GaN layer, and a second Al<……>(省略内容较多,整体结构类似原文,保留原文标签和格式)N layer is formed in the region where the gate electrode is formed. Thereby, a normally-off type semiconductor device can be realized.

[0016] The second Al x Ga 1-x N layer is formed to have a thickness such that a two-dimensional electron gas is formed in a portion of the first GaN layer near the heterointerface between the first GaN layer and the second Al x Ga 1-x N layer in the non-gate-bias state. Thereby, an increase in the on-resistance between the drain and the source can be suppressed.

[0017] According to the present invention, it is possible to provide a semiconductor device that is normally-off and has an increase in on-resistance suppressed. [Brief Description of the Drawings]

[0018] [Figure 1] It is a cross-sectional view showing a GaN-based field-effect transistor 100 according to Embodiment 1. [Figure 2] It is a schematic diagram showing the energy band in the depth direction of each region in the thermal equilibrium state of the GaN-based field-effect transistor 100 according to Embodiment 1.​​​​​​​​​​​​​​​​​ [Figure 3] 2 is a diagram for explaining the on-resistance Ron in the GaN-based field-effect transistor 100 according to the first embodiment. FIG. [Figure 4] 2A to 2C are views for explaining a method for manufacturing the GaN-based field-effect transistor 100 according to the first embodiment. [Figure 5] FIG. 1 is a cross-sectional view showing a GaN-based field-effect transistor 200 according to a second embodiment. [Figure 6] 10 is a schematic diagram showing the energy band in the depth direction of each region in a thermal equilibrium state of a GaN-based field-effect transistor 200 according to a second embodiment. FIG. [Figure 7] 10 is a diagram for explaining the on-resistance Ron in the GaN-based field-effect transistor 200 according to the second embodiment. FIG. [Figure 8] FIG. 9 is a diagram showing a GaN-based field-effect transistor 900 that is normally turned off by reducing the thickness of an AlxGa1-xN layer 912. [Figure 9] 9 is a diagram illustrating the on-resistance Ron in a GaN-based field-effect transistor 900 that is normally turned off by reducing the thickness of the AlxGa1-xN layer 912. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0019] The semiconductor device of the present invention will be described below based on embodiments. Note that the embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0020] 1. Embodiment 1 In the following, in order to explain the semiconductor device of the present invention, a GaN-based field-effect transistor 100 according to embodiment 1 will be taken as an example. FIG.

[0021] 1.1. "GaN-based field-effect transistor 100" As shown in FIG. 1, a GaN-based field-effect transistor 100 includes a first GaN layer 111 formed on a substrate 110 via a buffer layer (not shown), and a first Al x Ga 1-x N (0 < x ≦ 1) layer (hereinafter, sometimes simply referred to as "first Al x Ga 1-x N layer"), 112a, and a second Al x Ga 1-x N (0 < x ≦ 1) layer (hereinafter, sometimes simply referred to as "second Al x Ga 1-x N layer"), 112b, and a second GaN layer 113 formed on the first Al x Ga 1-x N layer 112a and the second Al x Ga 1-x N layer 112b, and a p-type GaN layer 114 formed on the second GaN layer 113.

[0022] As the substrate 110, preferably, a substrate on which a GaN-based semiconductor grows on the C plane, for example, a C-plane sapphire substrate, a Si substrate, a SiC substrate, etc. can be exemplified. As the buffer layer, for example, a polycrystalline or amorphous GaN layer, an AlN layer, an AlGaN layer, or further an AlGaN / GaN superlattice layer, etc. can be exemplified.

[0023] The first Al x Ga 1-x N layer 112a and the second Al x [[ID=?]]Ga 1-x N layer 112b are formed on the first GaN layer 111. Also, the first Al x Ga 1-x N layer 112a and the second Al x Ga 1-x N layer 112b are formed adjacent to each other, and the first Al x Ga 1-x N layer 112a and the second Al x Ga 1-x N layer 112b are electrically connected. <​​​The N layer 112a is formed by the first GaN layer 111 and the first Al layer 112b in a no-gate bias state. x Ga 1-x The second Al layer 112a is formed to a thickness such that the 2DEG 21 is not formed in the portion of the first GaN layer 111 near the heterointerface with the N layer 112a. x Ga 1-x The N layer 112b is formed by the first GaN layer 111 and the second Al layer 112b in a no-gate bias state. x Ga 1-x The first GaN layer 111 is formed to a thickness that allows the 2DEG 21 to be formed in a portion of the first GaN layer 111 near the heterointerface with the N layer 112b. x Ga 1-x The N layer 112a is formed in a portion where a gate electrode 115, which will be described later, is formed.

[0025] 1st Al x Ga 1-x The thickness of the N layer 112a and the second Al x Ga 1-x The thickness of the N layer 112b can be calculated by simulation or obtained by actually fabricating a device as a prototype.

[0026] In the following description, the first GaN layer 111 and the first Al x Ga 1-x The portion of the first GaN layer 111 in the vicinity of the heterointerface between the first GaN layer 111 and the N layer 112a is referred to as the portion of the first GaN layer 111 in the vicinity of the heterointerface between the first GaN layer 111 and the N layer 112a. x Ga 1-x The term "heterointerface between the first GaN layer 111 and the second AlN layer 112a" is sometimes used. x Ga 1-x The portion of the first GaN layer 111 in the vicinity of the heterointerface between the first GaN layer 111 and the second AlN layer 112b is referred to as the portion of the first GaN layer 111 in the vicinity of the heterointerface between the first GaN layer 111 and the second AlN layer 112b. x Ga 1-x The heterointerface between the N layer 112b and the N layer 112a may be referred to as a "heterointerface between the N layer 112b and the N layer 112a."

[0027] It is known that the ease of forming 2DEG21 is affected by polarization due to differences in the lattice structure and lattice constant of GaN-based semiconductors. x Ga1-x N layer 112a and second Al x Ga 1-x When the Al composition ratio x of the N layer 112b is the same, the first Al x Ga 1-x N layer 112a or second Al x Ga 1-x The thicker the N layer 112b, the easier it is for the 2DEG 21 to be formed.

[0028] Therefore, in the no gate bias state, the first GaN layer 111 and the first Al x Ga 1-x The 2DEG 21 is not formed at the heterointerface between the first GaN layer 111 and the N layer 112a, and in a no-gate bias state, x Ga 1-x In order to satisfy the condition that the 2DEG 21 is formed at the heterointerface with the N layer 112b, the first Al x Ga 1-x The thickness of the N layer 112a is x Ga 1-x It is necessary that the thickness of the N layer 112b is thinner than that of the N layer 112b.

[0029] The second GaN layer 113 is x Ga 1-x N layer 112a and second Al x Ga 1-x The second Al layer 112b is formed in an island shape on the N layer 112b. x Ga 1-x A source electrode 116 and a drain electrode 117 are formed on the N layer 112b.

[0030] The p-type GaN layer 114 is shaped like an island on the second GaN layer 113 in a region close to the source electrode 116. A gate electrode 115 electrically connected to the p-type GaN layer 114 is formed on the p-type GaN layer 114. The region where the second GaN layer 113 is formed but where the p-type GaN layer 114 is not formed corresponds to a polarization super junction region (PSJ region).

[0031] In the GaN-based field-effect transistor 100, in the gate bias-free state, the relationship n1 < n2 ≤ n3 holds for the concentration n1 of the 2DEG 21 in the portion of the gate electrode 115, the concentration n2 of the 2DEG 21 in the PSJ region, and the concentration n3 of the 2DEG 21 in the portion between the PSJ region and the drain electrode 117. Note that the concentration of the 2DEG 21 in the portion between the source electrode 116 and the gate electrode 115 is also n3. In FIG. 1, the magnitude relationship of n1 < n2 ≤ n3 is schematically shown using the size of the black circles.

[0032] In addition, the first Al x Ga 1-x N layer 112a is formed to have a thickness such that no 2DEG 21 is formed at the heterointerface between the first GaN layer 111 and the first Al x Ga 1-x N layer 112a in the gate bias-free state. Therefore, the concentration n1 of the 2DEG 21 in the portion of the gate electrode 115 in the gate bias-free state is substantially zero.

[0033] For the concentration of the 2DHG 22, in the gate bias-free state, the relationship p1 < pz holds for the concentration p1 of the 2DHG 22 in the portion of the gate electrode 115 and the concentration p2 of the 2DHG 22 in the PSJ region. Note that in the gate bias-free state, the concentration p1 of the 2DHG 22 in the portion of the gate electrode 115 is substantially zero.

[0034] 1.2. Operating mechanism of the "GaN-based field-effect transistor 100" <00004​​

[0035] In Figures 2(a) to 2(c), the vertical direction represents the electron energy, Ec represents the energy at the bottom of the conduction band, Ev represents the energy at the top of the valence band, and Ef represents the Fermi energy.

[0036] In the portion between the source electrode 116 and the gate electrode 115 and the portion between the PSJ region and the drain electrode 117, as shown in FIG. 2(c), the first GaN layer 111 and the second Al x Ga 1-x A 2DEG 21 with a concentration of n3 is formed at the heterointerface with the N layer 112b.

[0037] In the PSJ region, as shown in FIG. 2(b), the conduction band is raised by the polarization effect of the second GaN layer 113. This raises the conduction band between the first GaN layer 111 and the second Al x Ga 1-x The concentration n2 of the 2DEG 21 formed at the heterointerface with the N layer 112b is smaller than the concentration n3 of the 2DEG 21 formed in the portion between the PSJ region and the drain electrode 117.

[0038] In the PSJ region, the valence band is raised by the polarization effect of the second GaN layer 113. This raises the valence band. x Ga 1-x A 2DHG 22 with a concentration p2 is formed at the heterointerface with the N layer 112b.

[0039] In the gate electrode 115 portion, the first Al x Ga 1-x The thickness of the N layer 112a is x Ga 1-x The thickness of the first Al layer 112b is thinner than that of the N layer 112b (see FIG. 1). x Ga 1-x The piezoelectric polarization of the N layer 112a is smaller than that in the PSJ region. As a result, as shown in FIG. 2(a), the first GaN layer 111 and the first Al x Ga 1-xThe concentration n1 of the 2DEG 21 formed at the heterointerface with the N layer 112a is lower than the concentration n2 of the 2DEG 21 in the PSJ region.

[0040] In the gate electrode 115 portion, the first Al x Ga 1-x The thickness of the N layer 112a is x Ga 1-x For the same reason as above, the thickness of the second GaN layer 113 and the first AlN layer 112b in the gate electrode 115 portion is x Ga 1-x The concentration p1 of the 2DHG 22 formed at the heterointerface with the N layer 112a is lower than the concentration p2 of the 2DHG 22 in the PSJ region.

[0041] In the GaN-based field effect transistor 100, the first Al x Ga 1-x The N layer 112a is formed in the region where the gate electrode 115 is formed. x Ga 1-x The N layer 112a is formed by the first GaN layer 111 and the first Al layer 112b in a no-gate bias state. x Ga 1-x The thickness is set to such a value that the 2DEG 21 is not formed at the heterointerface with the N layer 112a. This makes it possible to set the threshold voltage of the GaN-based field effect transistor 100 to a positive value, i.e., to realize a normally-off state.

[0042] Next, the on-resistance Ron of the GaN-based field-effect transistor 100 will be described with reference to Fig. 3. The on-resistance Ron between the drain and source of the GaN-based field-effect transistor 100 is expressed by the following formula.

number

[0043] Here, the on-resistance Ron of the GaN-based field-effect transistor 100 will be compared with that of the GaN-based field-effect transistor 900 (see FIGS. 8 and 9).

[0044] The GaN-based field effect transistor 900 is x Ga 1-x The N layer 912 is in a state where the first GaN layer 911 and the Al x Ga 1-x The thickness is set so that the 2DEG 21 is not formed at the heterointerface with the N layer 912 .

[0045] In the GaN-based field effect transistor 900, Al x Ga 1-x As the thickness of the N layer 912 is reduced, the Al x Ga 1-x The polarization of the N layer 912 is weakened. As a result, under gate bias conditions, the first GaN layer 911 and the Al x Ga 1-x The concentration of the 2DEG 21 formed at the heterointerface with the N layer 912 decreases.

[0046] As a result of the decrease in the concentration of the 2DEG 21, the access resistance (Rac1) between the source electrode 916 and the gate electrode 915, the resistance of the PSJ region (Rch-PSJ), and the access resistance (Rac2) between the PSJ region and the drain electrode 917 increase. As a result, the GaN-based field-effect transistor 900 has a problem in that the on-resistance Ron increases (see FIG. 9).

[0047] On the other hand, in the GaN-based field effect transistor 100 according to the first embodiment, the second Al x Ga 1-x The N layer 112b is formed by the first GaN layer 111 and the second Al layer 112b in a no-gate bias state. x Ga 1-x It is formed to a thickness that allows the 2DEG 21 to be formed at the heterointerface with the N layer 112b.

[0048] That is, the GaN-based field effect transistor 100 has a first GaN layer 111 and a second Al x Ga 1-x A 2DEG 21 equivalent to that of a normally-on GaN-based field effect transistor can be provided at the heterointerface with the N layer 112b, and an increase in the on-resistance Ron can be suppressed.

[0049] The GaN-based field-effect transistor 100 according to the first embodiment can provide a semiconductor device that is a normally-off type and in which an increase in the on-resistance Ron is suppressed.

[0050] 1.3. Manufacturing method of "GaN-based field-effect transistor 100" 4A to 4C are diagrams shown for explaining the method for manufacturing the GaN-based field-effect transistor 100 according to embodiment 1. Hereinafter, the method for manufacturing the GaN-based field-effect transistor 100 according to embodiment 1 will be explained with reference to FIG.

[0051] As shown in FIG. 4(a), a buffer layer (not shown), a first GaN layer 111, and an Al layer were grown on a substrate 110 by a conventionally known metalorganic chemical vapor deposition (MOCVD) method using TMG (trimethylgallium) as a Ga source, trimethylaluminum as an Al source, NH3 (ammonia) as a nitrogen source, and N2 gas and H2 gas as carrier gases. x Ga 1-x The N layer 112 is then epitaxially grown.

[0052] The growth temperature during epitaxial growth is, for example, 1100° C. A sapphire substrate (for example, a C-plane sapphire substrate), a Si substrate, a SiC substrate, or the like can be used as the substrate 110. A GaN layer, an AlN layer, an AlGaN layer, an AlGaN / GaN superlattice layer, or the like can be used as the buffer layer.

[0053] Next, as shown in FIG. 4(b), a mask such as a resist pattern (not shown) is formed in the region other than the region where the p-type GaN layer 114 is to be formed. x Ga 1-x The recess 112c is formed by etching the N layer 112 in the thickness direction. The etching can be performed by RIE (Reactive Ion Etching) or the like.

[0054] Al x Ga 1-x The portion of the N layer 112 where the recess 112c is formed is the first Al x Ga 1-x The N layer 112a and the other part are the second Al x Ga 1-x The etching depth is set to 1 / 100 of the first Al layer 112b. x Ga 1-x The portion that becomes the N layer 112a is in a state where the first GaN layer 111 and the first Al x Ga 1-x The second Al layer 112a is formed to a thickness such that the 2DEG 21 is not formed at the heterointerface with the N layer 112a. x Ga 1-x The portion that becomes the N layer 112b is the first GaN layer 111 and the second Al layer 112b in a no-gate bias state. x Ga 1-x The thickness is appropriately set so that the 2DEG 21 is formed at the heterointerface with the N layer 112b.

[0055] Next, a GaN layer is formed on the entire surface by, for example, MOCVD. Subsequently, a mask such as a resist pattern is formed on the region where the p-type GaN layer 114 is to be formed, and the GaN layer other than the GaN layer filling the recess 112c is removed by etching using this mask. The etching can be performed by RIE or the like.

[0056] Furthermore, a GaN layer is formed on the entire surface by MOCVD. Subsequently, a mask such as a resist pattern is formed on the island-shaped region where the second GaN layer 113 is to be formed. This mask is used for patterning to form the second GaN layer 113. The patterning can be performed by etching using the RIE method or the like (see FIG. 4(c)).

[0057] Next, p-type GaN is formed on the entire surface by MOCVD. Subsequently, a mask such as a resist pattern is formed on the island-shaped region where the p-type GaN layer 114 is to be formed. Patterning is performed using this mask to form the p-type GaN layer 114. Patterning can be performed by etching using the RIE method or the like.

[0058] Finally, a gate electrode 115 is formed on the p-type GaN layer 114, and Al x Ga 1-x A source electrode 116 and a drain electrode 117 are formed in predetermined regions on the N layer 112 (see FIG. 4(d)). In this manner, the GaN-based field effect transistor 100 can be manufactured.

[0059] In the GaN-based field effect transistor 100 according to the first embodiment, the first Al x Ga 1-x The N layer 112a is formed by the first GaN layer 111 and the first Al layer 112b in a no-gate bias state. x Ga 1-x The second Al layer 112a is formed to a thickness such that the 2DEG 21 is not formed at the heterointerface with the N layer 112a. x Ga 1-xThe N layer 112b is formed by the first GaN layer 111 and the second Al layer 112b in a no-gate bias state. x Ga 1-x The first Al layer 112b is formed to a thickness such that the 2DEG 21 is formed at the heterointerface with the N layer 112b. x Ga 1-x The N layer 112a is formed in the region where the gate electrode 115 is formed.

[0060] This allows the GaN-based field-effect transistor 100 to be normally off. Furthermore, the 2DEG 21 equivalent to that of a normally-on GaN-based field-effect transistor can be provided in the portion other than the gate electrode 115, thereby suppressing an increase in the on-resistance Ron.

[0061] That is, by adopting the above-described configuration, it is possible to suppress an increase in the drain-source on-resistance Ron while maintaining the normally-off characteristics.

[0062] According to a preferred embodiment of the GaN-based field-effect transistor 100 of the first embodiment, the GaN-based field-effect transistor 100 is a normally-off type GaN-based field-effect transistor, which makes the GaN-based field-effect transistor 100 suitable for use as a switching element, particularly in fields that handle large amounts of power.

[0063] 2. Embodiment 2 In the following, in order to explain the semiconductor device of the present invention, a GaN-based field-effect transistor 200 according to embodiment 2 will be taken as an example. Fig. 5 is a cross-sectional view showing the GaN-based field-effect transistor 200 according to embodiment 2.

[0064] The GaN-based field-effect transistor 200 will be described mainly with respect to the differences from the GaN-based field-effect transistor 100 according to the first embodiment, and a description of the commonalities will be omitted as appropriate.

[0065] The GaN-based field effect transistor 200 according to the second embodiment has a first Al xGa 1-x The region where the N layer 212a is formed is different from that of the GaN-based field-effect transistor 100 according to embodiment 1. That is, in the GaN-based field-effect transistor 100 according to embodiment 1, the first Al x Ga 1-x The region where the N layer 112a is formed is the region where the gate electrode 115 is formed. x Ga 1-x The region where the N layer 212 is formed is the region where the second GaN layer 213 is formed.

[0066] 2.1. "GaN-based field-effect transistor 200" As shown in FIG. 5, the GaN-based field-effect transistor 200 includes a first GaN layer 211 formed on a substrate 210 via a buffer layer (not shown), and a first Al layer 212 formed on the first GaN layer 211. x Ga 1-x N layer 212a and second Al x Ga 1-x N layer 212b and the first Al x Ga 1-x It has a second GaN layer 213 formed on the N layer 212a, and a p-type GaN layer 214 formed on the second GaN layer 213.

[0067] The second GaN layer 213 is x Ga 1-x The second Al layer 212a is formed in an island shape on the N layer 212a. x Ga 1-x A source electrode 216 and a drain electrode 217 are formed on the N layer 212b.

[0068] 1st Al x Ga 1-x The N layer 212a is formed by the first GaN layer 211 and the first Al layer 212b in a no-gate bias state. x Ga 1-x The thickness of the second Al layer 212a is such that the 2DEG 21 is not formed at the heterointerface with the N layer 212a. x Ga 1-xThe N layer 212b is formed by the first GaN layer 211 and the second Al layer 212b in a no-gate bias state. x Ga 1-x The first Al layer 212b is formed to a thickness such that the 2DEG 21 is formed at the heterointerface with the N layer 212b. x Ga 1-x The N layer 212a is formed in the region where the second GaN layer 213 is formed.

[0069] In the GaN-based field effect transistor 200, the first Al x Ga 1-x The N layer 212a is formed by the first GaN layer 211 and the first Al layer 212b in a no-gate bias state. x Ga 1-x The thickness of the first Al layer 212a is such that the 2DEG 21 is not formed at the heterointerface with the N layer 212a. x Ga 1-x N layer 212a is formed in the region where second GaN layer 213 is formed. Here, the region where second GaN layer 213 is formed includes the region where gate electrode 215 is formed. This makes it possible to realize GaN-based field-effect transistor 200 in a normally-off state.

[0070] 2.2. Operation mechanism of "GaN-based field-effect transistor 200" Fig. 6 is a schematic diagram showing energy bands in the depth direction for each region in a thermal equilibrium state of the GaN-based field-effect transistor 200 according to embodiment 2. Fig. 6(a) is a diagram showing the energy band of the gate electrode 215 in a thermal equilibrium state, Fig. 6(b) is a diagram showing the energy band of the PSJ region in a thermal equilibrium state, and Fig. 6(c) is a diagram showing the energy bands of the region between the source electrode 216 and the gate electrode 215 and the region between the PSJ region and the drain electrode 217 in a thermal equilibrium state.

[0071] The energy band of the GaN-based field-effect transistor 200 according to the second embodiment will be described below with reference to Figures 6(a) to 6(c). The energy band of the gate electrode 215 in Figure 6(a) is the same as the energy band of the gate electrode 115 of the first embodiment shown in Figure 2(a). The energy band of the portion between the source electrode 216 and the gate electrode 215 and the portion between the PSJ region and the drain electrode 217 in Figure 6(c) are the same as the energy band of the portion between the source electrode 116 and the gate electrode 115 and the portion between the PSJ region and the drain electrode 117 of the first embodiment shown in Figure 2(c). For this reason, Figures 6(a) and 6(c) are merely shown, and their description will be omitted.

[0072] In the PSJ region, as shown in FIG. 6(b), the conduction band is raised by the polarization effect of the second GaN layer 213. x Ga 1-x The concentration n2 of the 2DEG 21 formed at the heterointerface with the N layer 212a is lower than the concentration n3 of the 2DEG 21 in the portion between the PSJ region and the drain electrode 117.

[0073] In addition, in the PSJ region, the first Al x Ga 1-x The thickness of the N layer 212a is the second Al x Ga 1-x It is formed thinner than the N layer 212b (see FIG. 5). x Ga 1-x The piezoelectric polarization of the N layer 212a is generated by the second Al layer between the PSJ region and the drain electrode 117. x Ga 1-x The piezoelectric polarization of the first GaN layer 211 and the first Al layer 212b in the PSJ region is smaller than that of the N layer 212b. x Ga 1-x The concentration n2 of the 2DEG 21 formed at the heterointerface with the N layer 212a is smaller than the concentration n3 of the 2DEG 21 formed in the portion between the PSJ region and the drain electrode 217.

[0074] Furthermore, in the PSJ region, the valence band is raised by the polarization effect of the second GaN layer 213. This raises the valence band. x Ga 1-x A 2DHG 22 having a concentration p2 is formed at the heterointerface with the N layer 212a.

[0075] In the GaN-based field effect transistor 200, the first Al x Ga 1-x The N layer 212a is formed in the region where the gate electrode 215 is formed. x Ga 1-x The N layer 212a is formed by the first GaN layer 211 and the first Al layer 212b in a no-gate bias state. x Ga 1-x The thickness is set to such a value that the 2DEG 21 is not formed at the heterointerface with the N layer 212a.

[0076] This makes it possible to set the threshold voltage of the GaN-based field effect transistor 200 to a positive value, that is, to realize a normally-off state.

[0077] Next, the on-resistance Ron of the GaN-based field-effect transistor 200 will be described with reference to Fig. 7. The on-resistance Ron between the drain and source of the GaN-based field-effect transistor 200 is expressed by the following formula.

number

[0078] In the GaN-based field effect transistor 200 according to the second embodiment, the second Al x Ga 1-xThe N layer 212b is formed by the first GaN layer 211 and the second Al layer 212b in a no-gate bias state. x Ga 1-x The thickness is set to a value that allows the 2DEG 21 to be formed at the heterointerface with the N layer 212b, thereby making it possible to suppress an increase in the on-resistance Ron.

[0079] In the GaN-based field effect transistor 200, the first Al x Ga 1-x The N layer 212a is formed by the first GaN layer 211 and the first Al layer 212b in a no-gate bias state. x Ga 1-x The second Al layer 212a is formed to a thickness such that the 2DEG 21 is not formed at the heterointerface with the N layer 212a. x Ga 1-x The N layer 212b is formed by the first GaN layer 211 and the second Al layer 212b in a no-gate bias state. x Ga 1-x The thickness is such that the 2DEG 21 is formed at the heterointerface with the N layer 212b.

[0080] That is, the GaN-based field effect transistor 200 has a first GaN layer 211 and a second Al x Ga 1-x A 2DEG 21 equivalent to that of a normally-on GaN-based field effect transistor can be provided at the heterointerface with the N layer 212b, and an increase in the on-resistance Ron can be suppressed.

[0081] By adopting the above-described configuration, it is possible to suppress an increase in the drain-source on-resistance Ron while maintaining the normally-off characteristics.

[0082] According to a preferred embodiment of the GaN-based field-effect transistor 200 of the second embodiment, the GaN-based field-effect transistor 200 is a normally-off type GaN-based field-effect transistor, which makes it suitable for use as a switching element, particularly in fields that handle large amounts of power. [Explanation of symbols]

[0083] 100, 200... GaN-based field effect transistor, 110, 210... substrate, 111, 211... first GaN layer, 112a, 212a... first Al x Ga 1-x N layer, 112b, 212b...2nd Al x Ga 1-x N layer, 113, 213... second GaN layer, 114, 214... p-type GaN layer, 115, 215... gate electrode, 116, 216... source electrode, 117, 217... drain electrode

Claims

1. a first GaN layer; and A first Al layer formed on the first GaN layer. ｘ Ga １－ｘ N (0<x≦1) layers; The first Al layer is formed on the first GaN layer. ｘ Ga １－ｘ The second Al layer formed adjacent to the N layer ｘ Ga １－ｘ N (0<x≦1) layers; The first Al ｘ Ga １－ｘ N layer and the second Al ｘ Ga １－ｘ a second GaN layer formed on the N layer; a p-type GaN layer formed on the second GaN layer; Said second Al ｘ Ga １－ｘ a source electrode formed on the N layer; Said second Al ｘ Ga １－ｘ a drain electrode formed on the N layer; a gate electrode electrically connected to the p-type GaN layer, the p-type GaN layer is formed in an island shape in a region on the source electrode side on the second GaN layer, The first Al ｘ Ga １－ｘ The N layer is formed by the first GaN layer and the first Al layer in a no-gate bias state. ｘ Ga １－ｘ the first GaN layer is formed to a thickness such that two-dimensional electron gas is not generated in a portion of the first GaN layer in the vicinity of a heterointerface with an N layer; Said second Al ｘ Ga １－ｘ The N layer is formed by the first GaN layer and the second Al layer in a no-gate bias state. ｘ Ga １－ｘ the first GaN layer is formed to a thickness that allows two-dimensional electron gas to be formed in a portion of the first GaN layer in the vicinity of a heterointerface between the first GaN layer and an N layer; The first Al ｘ Ga １－ｘ A semiconductor device according to claim 1, wherein the N layer is formed at least in a region where the gate electrode is formed.

2. 10. The semiconductor device of claim 1, The first Al ｘ Ga １－ｘ a second GaN layer formed on the second GaN layer;

3. 3. The semiconductor device according to claim 1, A semiconductor device characterized by being a normally-off type GaN-based field effect transistor.

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