Semiconductor element

Abstract

To provide a semiconductor element with suppressed increase in on-resistance in spite of being a normally-off type.SOLUTION: A semiconductor element includes a first GaN layer 111, a first AlxGa1-xN(0<x≤1) layer 113, a second AlyGa1-yN(0<y≤1) layer 112, a second GaN layer 114, and a p-type GaN layer 115. The first AlxGa1-xN layer 113 is formed with an Al composition ratio x with which a two-dimensional electron gas 21 is not formed on a heterointerface between the first GaN layer 111 and the first AlxGa1-xN layer 114 in a non-gate bias state. The second AlyGa1-yN layer 112 is formed with an Al composition ratio y with which a two-dimensional electron gas is formed on a heterointerface between the first GaN layer 111 and the second AlyGa1-yN layer 112 in the non-gate bias state. The first AlxGa1-xN layer 113 is formed in a region where at least a gate electrode 116 is formed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As a semiconductor device having excellent high-frequency characteristics, the development of HEMT (High Electron Mobility Transistor) has been carried out. As one of the HEMTs, a GaN-based field-effect transistor having an AlGaN / GaN heterojunction formed by crystal growth of a thin film of Al ,

[0005] ,

[0003] , , , , , , , , , , , , ,

[0004] , Ga 1-x GaN (0 < x ≦ 1) (hereinafter sometimes referred to as "AlGaN") can be mentioned. In the GaN-based field-effect transistor, a layer of two-dimensional electron gas (hereinafter sometimes referred to as "2DEG") formed by gathering two-dimensional electrons having high mobility is formed on the AlGaN / GaN junction surface. The 2DEG can freely move on the heterointerface between the GaN layer and the Al x Ga 1-x GaN layer (see Patent Document 1).

Prior Art Documents

Patent Documents

[0006] FIG. 9 is a diagram showing a GaN-based field-effect transistor 900 that has been made normally-off by reducing the Al composition ratio x of the Al x Ga 1-x N layer 913. FIG. 10 is a diagram showing the on-resistance Ron in the GaN-based field-effect transistor 900 that has been made normally-off by reducing the Al composition ratio x of the Al x Ga 1-x N layer 913.

[0007] The GaN-based field-effect transistor 900 shown in FIG. 9 includes a substrate 910, a first GaN layer 911 formed on the substrate 910, and an Al x Ga 1-x N (0 < x ≤ 1) layer 913 (hereinafter sometimes simply referred to as "Al x Ga 1-x N layer 913"), a second GaN layer 914 formed on the Al x Ga 1-x N layer 913, and a p-type GaN layer 915 formed on the second GaN layer 914.

[0008] In FIG. 10, in the GaN-based field-effect transistor 900, in the gate bias state, the two-dimensional electron gas 21 (hereinafter sometimes referred to as "2DEG21") formed in a portion of the first GaN layer 911 near the heterointerface between the first GaN layer 911 and the Al x Ga 1-x N layer 913 is indicated by black circles. Also, in the gate bias state, between the second GaN layer 914 and the Al x Ga 1-xTwo-dimensional hole gas 22 (hereinafter, sometimes referred to as "2DHG 22") formed in a portion of second GaN layer 914 near the heterointerface with N layer 913 is indicated by a white circle.

[0009] Al x Ga 1-x The N layer 913 is in a state where no gate bias is applied and the first GaN layer 911 and Al x Ga 1-x It is formed with an Al composition ratio x such that the 2DEG 21 is not formed at the heterointerface with the N layer 913. This allows the GaN-based field effect transistor 900 to function as a normally-off type.

[0010] The drain-source on-resistance Ron is expressed by the following formula:

number

[0011] Al x Ga 1-x In the GaN-based field-effect transistor 900 in which the Al composition ratio x of the N layer 913 is small, the first GaN layer 911 and Al x Ga 1-x The concentration of the 2DEG 21 formed in the portion of the first GaN layer 911 near the heterointerface with the N layer 913 decreases, which causes a problem of increased drain-source on-resistance Ron.

[0012] In other words, in order to realize normally-off in semiconductor devices, x Ga 1-xWhen the Al composition ratio x of the N layer is decreased, there is a problem that the on-resistance Ron between the drain and the source increases.

[0013] Therefore, an object of the present invention is to solve such a problem, and an object is to provide a semiconductor device that is normally-off type and in which an increase in the on-resistance Ron is suppressed.

Means for Solving the Problem

[0014] The semiconductor device of the present invention includes a first GaN layer, a first Al x Ga 1-x N (0 < x ≤ 1) layer formed on the first GaN layer, and a second Al x Ga 1-x N layer formed adjacent to the first Al y Ga 1-y N (0 < y ≤ 1) layer, a second GaN layer formed on the first Al x Ga 1-x N layer and the second Al y Ga 1-y N layer, a p-type GaN layer formed on the second GaN layer, a source electrode formed on the second Al y Ga 1-y N layer, a drain electrode formed on the second Al y Ga 1-y N layer, and a gate electrode electrically connected to the p-type GaN layer. The p-type GaN layer is formed in an island shape in a region on the source electrode side above the second GaN layer. The first Al x Ga 1-x N layer is formed with an Al composition ratio such that a two-dimensional electron gas is not formed in a portion of the first GaN layer near the heterointerface between the first GaN layer and the first Al x Ga 1-x N layer in a gate-bias-free state. The second Al y Ga 1-y N layer is, in a gate-bias-free state, between the first GaN layer and the second Al y Ga 1-yThe first GaN layer is formed with an Al composition ratio in which a two-dimensional electron gas is formed in a portion of the first GaN layer near the heterointerface with the N layer, and the first Al x Ga 1-x N layer is formed at least in a region where the gate electrode is formed.

Advantages of the Invention

[0015] The semiconductor device of the present invention has a first Al x Ga 1-x N(0 < x ≤ 1) layer formed on the first GaN layer, and a second Al x Ga[[ID=]] 1-x N layer formed adjacent to the first Al y Ga 1-y N(0 < y ≤ 1) layer. The first Al x Ga 1-x N layer is formed with an Al composition ratio in which a two-dimensional electron gas is not formed in a portion of the first GaN layer near the heterointerface between the first GaN layer and the first Al x Ga 1-x N layer in a gate - bias - free state. Also, the first Al x Ga 1-x N layer is formed in a region where the gate electrode is formed, thereby realizing a normally - off - type semiconductor device.

[0016] The second Al y Ga 1-y N layer is formed with an Al composition ratio in which a two - dimensional electron gas is formed in a portion of the first GaN layer near the heterointerface between the first GaN layer and the second Al y Ga 1-y N layer in a gate - bias - free state, thereby suppressing an increase in the on - resistance between the drain and the source.

[0017] According to the present invention, it is possible to provide a semiconductor device that is normally - off - type and in which an increase in on - resistance is suppressed.

Brief Description of the Drawings

[0018] [Figure 1] 1 is a cross-sectional view showing a GaN-based field-effect transistor 100 according to a first embodiment. [Figure 2] 1 is a schematic diagram showing the energy band in the depth direction of each region in a thermal equilibrium state of the GaN-based field-effect transistor 100 according to the first embodiment. [Figure 3] 2 is a diagram for explaining the on-resistance Ron in the GaN-based field-effect transistor 100 according to the first embodiment. FIG. [Figure 4] 1 is a cross-sectional view showing a GaN-based field-effect transistor 100A according to a modified example of the first embodiment. [Figure 5] 2A to 2C are views for explaining a method for manufacturing the GaN-based field-effect transistor 100 according to the first embodiment. [Figure 6] FIG. 1 is a cross-sectional view showing a GaN-based field-effect transistor 200 according to a second embodiment. [Figure 7] 10 is a schematic diagram showing the energy band in the depth direction of each region in a thermal equilibrium state of a GaN-based field-effect transistor 200 according to a second embodiment. FIG. [Figure 8] 10 is a diagram for explaining the on-resistance Ron in the GaN-based field-effect transistor 200 according to the second embodiment. FIG. [Figure 9] 9 is a diagram illustrating a GaN-based field-effect transistor 900 that is normally turned off by reducing the Al composition ratio x of an AlxGa1-xN layer 913. FIG. [Figure 10] 1 is a diagram illustrating an on-resistance Ron in a GaN-based field-effect transistor 900 that is normally turned off by reducing the Al composition ratio x of the Al x Ga 1-x N layer 913. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0019] The semiconductor device of the present invention will be described below based on embodiments. Note that the embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0020] 1. Embodiment 1 Hereinafter, in order to describe the semiconductor device of the present invention, the GaN-based field-effect transistor 100 according to Embodiment 1 will be described as an example. FIG. 1 is a cross-sectional view showing the GaN-based field-effect transistor 100 according to Embodiment 1.

[0021] 1.1. Structure of "GaN-based field-effect transistor 100" As shown in FIG. 1, the GaN-based field-effect transistor 100 includes a first GaN layer 111 formed on a substrate 110 via a buffer layer (not shown), and a first Al x Ga 1-x N (0 < x ≦ 1) layer (hereinafter, may be simply referred to as "first Al x Ga 1-x N layer".), 113, and a second Al y Ga 1-y N (0 < y ≦ 1) layer (hereinafter, may be simply referred to as "second Al y Ga 1-y N layer".), 112, and a second GaN layer 114 formed on the first Al x Ga 1-x N layer 113 and the second Al y Ga 1-y N layer 112, and a p-type GaN layer 115 formed on the second GaN layer 114. [[ID=三十六]] [[ID=三十七]]

[0022] [[ID=三十八]] [[ID=三十九]]As the substrate 110, preferably, a substrate on which a GaN-based semiconductor grows on the C plane, for example, a C-plane sapphire substrate, a Si substrate, a SiC substrate, etc. can be exemplified. As the buffer layer, for example, a polycrystalline or amorphous GaN layer, an AlN layer, an AlGaN layer, or further an AlGaN / GaN superlattice layer, etc. can be exemplified. [[ID=四十]] [[ID=四十一]]

[0023] [[ID=四十二]] [[ID=四十三]]The first Al[[ID=四十四]] x [[ID=四十五]]Ga[[ID=四十六]] 1-x [[ID=四十七]]N layer 113 and the second Al[[ID=四十八]] y [[ID=四十九]]Ga[[ID=五十]] 1-y [[ID=五十一]]N layer 112 are formed on the first GaN layer 111. Also, the first Al[[ID=五十二]] x [[ID=五十三]]Ga[[ID=五十四]] 1-x [[ID=五十五]]N layer 113 and the second Aly Ga 1-y The first Al layer 112 is formed adjacent to the N layer 112. x Ga 1-x N layer 113 and second Al y Ga 1-y It is electrically connected to the N layer 112 .

[0024] 1st Al x Ga 1-x The N layer 113 is formed by the first GaN layer 111 and the first Al layer 112 in a no-gate bias state. x Ga 1-x The Al composition ratio x is such that the 2DEG 21 is not formed in the portion of the first GaN layer 111 near the heterointerface with the N layer 113. y Ga 1-y The N layer 112 is formed by the first GaN layer 111 and the second Al layer 112 in a no-gate bias state. y Ga 1-y The 2DEG 21 is formed in a portion of the first GaN layer 111 near the heterointerface with the N layer 112 with an Al composition ratio of y. x Ga 1-x The N layer 113 is formed in a portion where a gate electrode 116, which will be described later, is formed.

[0025] 1st Al x Ga 1-x The Al composition ratio x of the N layer 113 and the second Al y Ga 1-y The Al composition ratio y of the N layer 112 can be calculated by simulation or obtained by actually fabricating a device.

[0026] In the following description, the first GaN layer 111 and the first Al x Ga 1-x The portion of the first GaN layer 111 in the vicinity of the heterointerface between the first GaN layer 111 and the first AlN layer 113 is referred to as the “portion of the first GaN layer 111 in the vicinity of the heterointerface between the first GaN layer 111 and the first AlN layer 113.” x Ga 1-x The term "heterointerface between the first GaN layer 111 and the second AlN layer 113" is sometimes used. y Ga 1-yThe portion of the first GaN layer 111 in the vicinity of the heterointerface between the first GaN layer 111 and the second AlN layer 112 is referred to as the portion of the first GaN layer 111 in the vicinity of the heterointerface between the first GaN layer 111 and the second AlN layer 112. y Ga 1-y The heterointerface between the N layer 112 and the N layer 112 may be referred to as a "heterointerface between the N layer 112 and the N layer 112."

[0027] It is known that the ease of forming 2DEG21 is affected by polarization due to differences in the lattice structure and lattice constant of GaN-based semiconductors. x Ga 1-x The thickness of the N layer 113 and the second Al y Ga 1-y When the thickness of the N layer 112 is the same as that of the first Al x Ga 1-x The Al composition ratio x of the N layer 113 or the second Al y Ga 1-y The larger the Al composition ratio y of the N layer 112, the easier it is for the 2DEG 21 to be formed.

[0028] Therefore, in the no gate bias state, the first GaN layer 111 and the first Al x Ga 1-x The 2DEG 21 is not formed at the heterointerface between the first GaN layer 111 and the N layer 113, and in a no-gate bias state, y Ga 1-y In order to satisfy the condition that the 2DEG 21 is formed at the heterointerface between the first Al layer and the N layer 112, x Ga 1-x The Al composition ratio x of the N layer 113 is y Ga 1-y It is necessary that the Al composition ratio is smaller than the Al composition ratio y of the N layer 112 .

[0029] In the GaN-based field effect transistor 100 according to the first embodiment, the first Al x Ga 1-x N layer 113 and second Al y Ga 1-y The first Al layer 112 is formed to the same thickness as the N layer 112. x Ga 1-x N layer 113 and second Al y Ga 1-yIt is not essential that the N layer 112 be formed to the same thickness.

[0030] 1st Al x Ga 1-x The N layer 113 is formed by the first GaN layer 111 and the first Al layer 112 in a no-gate bias state. x Ga 1-x The second Al layer 113 may be formed to any thickness as long as the Al composition ratio x and thickness are such that the 2DEG 21 is not formed at the heterointerface with the N layer 113. y Ga 1-y The N layer 112 is formed by the first GaN layer 111 and the second Al layer 112 in a no-gate bias state. y Ga 1-y The Al composition ratio y and thickness may be any thickness as long as the 2DEG 21 is formed at the heterointerface with the N layer 112 .

[0031] As described above, the ease of forming the 2DEG 21 is affected by the polarization effect due to the difference in the lattice structure and lattice constant of the GaN-based semiconductor. x Ga 1-x N layer 113 and / or second Al y Ga 1-y By forming the N layer 112 to have a large thickness, the 2DEG 21 is easily formed.

[0032] For example, in a GaN-based field effect transistor 100A shown in FIG. x Ga 1-x The thickness of the N layer 113 is y Ga 1-y By forming the first Al layer 112 thinner than the N layer 112, x Ga 1-x In the N layer 113, in the no gate bias state, the first GaN layer 111 and the first Al x Ga 1-x The 2DEG 21 is less likely to be formed at the heterointerface with the N layer 113, and the second Al y Ga 1-y In the N layer 112, in the no gate bias state, the first GaN layer 111 and the second Al y Ga 1-yThis is preferable because the 2DEG 21 is easily formed at the heterointerface with the N layer 112.

[0033] Also, the 1st Al x Ga 1-x A part of the N layer 113 is formed as a second Al layer, as in the GaN-based field effect transistor 100A shown in FIG. y Ga 1-y The second Al layer 112 may be formed over the N layer 112. This allows the second Al layer 112 to be formed over the N layer 112 in the manufacturing process of the GaN-based field effect transistor 100, which will be described later. y Ga 1-y The first Al layer is placed inside the hole 112b (see FIG. 5(b)) formed in the N layer 112. x Ga 1-x The N layer 113 is formed, and the first Al layer formed in the region other than the predetermined region is x Ga 1-x When the N layer is removed by etching, the first Al x Ga 1-x The N layer can be removed by etching.

[0034] The second GaN layer 114 is x Ga 1-x N layer 113 and second Al y Ga 1-y The second Al layer 112 is formed in an island shape on the N layer 112. y Ga 1-y A source electrode 117 and a drain electrode 118 are formed on the N layer 112 .

[0035] The p-type GaN layer 115 is formed in an island shape in a region on the second GaN layer 114 and close to the source electrode 117. A gate electrode 116 electrically connected to the p-type GaN layer 115 is formed on the p-type GaN layer 115. The region where the second GaN layer 114 is formed but where the p-type GaN layer 115 is not formed corresponds to a polarization super junction region (PSJ region).

[0036] In the GaN-based field-effect transistor 100, in a gate-bias-free state, for the concentration n1 of the 2DEG 21 in the portion of the gate electrode 116, the concentration n2 of the 2DEG 21 in the PSJ region, and the concentration n3 of the 2DEG 21 in the portion between the PSJ region and the drain electrode 118, the relationship n1 < n2 ≤ n3 holds. Note that the concentration of the 2DEG 21 in the portion between the source electrode 117 and the gate electrode 116 is also n3. In FIG. 1, the magnitude relationship of n1 < n2 ≤ n3 is schematically shown using the size of the black circles.

[0037] Note that the first Al x Ga 1-x N layer 113 is formed with an Al composition ratio x at which no 2DEG 21 is formed at the heterointerface between the first GaN layer 111 and the first Al x Ga 1-x N layer 113 in a gate-bias-free state. Therefore, the concentration n1 of the 2DEG 21 in the portion of the gate electrode 116 in a gate-bias-free state is substantially zero.

[0038] For the concentration of the 2DHG 22, in a gate-bias-free state, for the concentration p1 of the 2DHG 22 in the portion of the gate electrode 116 and the concentration p2 of the 2DHG 22 in the PSJ region, the relationship p1 < p2 holds. Note that in a gate-bias-free state, the concentration p1 of the 2DHG 22 in the portion of the gate electrode 116 is substantially zero.

[0039] The energy band of the GaN-based field-effect transistor 100 will be described using FIG. 2. FIG. 2 is a schematic diagram showing the energy band in the depth direction of each region in the thermal equilibrium state of the GaN-based field-effect transistor 100 according to Embodiment 1. FIG. 2(a) is a diagram showing the energy band of the portion of the gate electrode 116 in the thermal equilibrium state, FIG. 2(b) is a diagram showing the energy band of the PSJ region in the thermal equilibrium state, and FIG. 2(c) is a diagram showing the energy band of the portion between the source electrode 117 and the gate electrode 116 and the portion between the PSJ region and the drain electrode 118 in the thermal equilibrium state.

[0040] In Figures 2(a) to 2(c), the vertical direction represents the electron energy, Ec represents the energy at the bottom of the conduction band, Ev represents the energy at the top of the valence band, and Ef represents the Fermi energy.

[0041] In the portion between the source electrode 117 and the gate electrode 116, and in the portion between the PSJ region and the drain electrode 118, as shown in FIG. 2(c), the first GaN layer 111 and the second Al y Ga 1-y At the heterointerface with the N layer 112, a 2DEG 21 with a concentration of n3 is formed.

[0042] In the PSJ region, as shown in FIG. 2(b), the conduction band is raised by the polarization effect of the second GaN layer 114. This raises the conduction band between the first GaN layer 111 and the second Al y Ga 1-y The concentration n2 of the 2DEG 21 formed at the heterointerface with the N layer 112 is smaller than the concentration n3 of the two-dimensional electron gas 2DEG 21 in the portion between the PSJ region and the drain electrode 118.

[0043] In the PSJ region, the valence band is raised by the polarization effect of the second GaN layer 114. This raises the valence band. y Ga 1-y At the heterointerface with the N layer 112, a 2DHG 22 having a concentration p2 is formed.

[0044] In the portion of the gate electrode 116, the first Al x Ga 1-x The Al composition ratio x of the N layer 113 is the second Al y Ga 1-y The Al composition ratio y is smaller than that of the N layer 112. Therefore, the first Al x Ga 1-x The piezoelectric polarization of the N layer 113 is y Ga 1-y The piezoelectric polarization of the first GaN layer 111 and the first Al layer 112 in the gate electrode 116 is smaller than that of the N layer 112. As a result, as shown in FIG. xGa 1-x The concentration n1 of the 2DEG 21 formed at the heterointerface with the N layer 113 is lower than the concentration n2 of the 2DEG 21 in the PSJ region.

[0045] In the portion of the gate electrode 116, the first Al x Ga 1-x The Al composition ratio x of the N layer 113 is the second Al y Ga 1-y The Al composition ratio y is smaller than that of the N layer 112. For the same reason as described above, the Al composition ratio y of the second GaN layer 114 and the first Al layer 116 in the gate electrode 116 is x Ga 1-x The concentration p1 of the 2DHG 22 formed at the heterointerface with the N layer 113 is lower than the concentration p2 of the 2DHG 22 in the PSJ region.

[0046] In the GaN-based field effect transistor 100, the first Al x Ga 1-x The N layer 113 is formed in the region where the gate electrode 116 is formed. x Ga 1-x The N layer 113 is formed by the first GaN layer 111 and the first Al layer 112 in a no-gate bias state. x Ga 1-x The Al composition ratio x is such that the 2DEG 21 is not formed at the heterointerface with the N layer 113. This allows the threshold voltage of the GaN-based field-effect transistor 100 to be a positive value, i.e., it is possible to realize a normally-off state.

[0047] Next, the on-resistance Ron of the GaN-based field-effect transistor 100 will be described with reference to Fig. 3. The on-resistance Ron between the drain and source of the GaN-based field-effect transistor 100 is expressed by the following formula.

number

[0048] Here, the on-resistance Ron of the GaN-based field-effect transistor 100 will be compared with that of a GaN-based field-effect transistor 900 (see FIGS. 9 and 10).

[0049] The GaN-based field effect transistor 900 is x Ga 1-x The N layer 913 is in a state where the first GaN layer 911 and the Al x Ga 1-x The thickness is set so that the 2DEG 21 is not formed at the heterointerface with the N layer 913 .

[0050] The GaN-based field effect transistor 900 is x Ga 1-x As the Al composition ratio x of the N layer 913 is reduced, x Ga 1-x The polarization of the N layer 913 is weakened. As a result, under gate bias conditions, the first GaN layer 911 and the Al x Ga 1-x The concentration of DEG21 at the heterointerface with the N layer 913 decreases.

[0051] As a result of the decrease in the concentration of 2DEG 21, the access resistance (Rac1) between the source electrode 917 and gate electrode 916, the resistance of the PSJ region (Rch-PSJ), and the access resistance (Rac2) between the PSJ region and drain electrode 918 increase. This results in a problem of an increase in on-resistance Ron (see FIG. 10).

[0052] On the other hand, in the GaN-based field effect transistor 100 according to the first embodiment, the second Aly Ga 1-y The N layer 112 is formed by the first GaN layer 111 and the second Al layer 112 in a no-gate bias state. y Ga 1-y The 2DEG 21 is formed at the heterointerface with the N layer 112 with an Al composition ratio of y.

[0053] That is, the GaN-based field effect transistor 100 has a first GaN layer 111 and a second Al y Ga 1-y At the heterointerface with the N layer 112, a 2DEG 21 equivalent to that of a normally-on GaN-based field effect transistor can be provided, and an increase in the on-resistance Ron can be suppressed.

[0054] The GaN-based field-effect transistor 100 according to the first embodiment can provide a semiconductor device that is a normally-off type and in which an increase in the on-resistance Ron is suppressed.

[0055] 1.3. Manufacturing method of "GaN-based field-effect transistor 100" 5A and 5B are diagrams shown for explaining a method for manufacturing the GaN-based field-effect transistor 100 according to embodiment 1. Hereinafter, the method for manufacturing the GaN-based field-effect transistor 100 according to embodiment 1 will be explained with reference to FIG.

[0056] As shown in FIG. 5(a), a buffer layer (not shown), a first GaN layer 111, and an Al layer were grown on a substrate 110 by a conventionally known metalorganic chemical vapor deposition (MOCVD) method using TMG (trimethylgallium) as a Ga source, TMA (trimethylaluminum) as an Al source, NH3 (ammonia) as a nitrogen source, and N2 gas and H2 gas as carrier gases. x Ga 1-x The N layer 112a is then epitaxially grown.

[0057] The growth temperature during epitaxial growth is, for example, 1100° C. The substrate 110 can be a sapphire substrate (for example, a C-plane sapphire substrate), a Si substrate, a SiC substrate, or the like. The buffer layer can be a GaN layer, an AlN layer, an AlGaN layer, an AlGaN / GaN superlattice layer, or the like.

[0058] Next, as shown in FIG. 5(b), a mask such as a resist pattern (not shown) is formed in the region other than the region where the p-type GaN layer 115 is to be formed, and Al x Ga 1-x The N layer 112a is etched in the thickness direction to form holes 112b. y Ga 1-y The etching is performed by using the RIE (Reactive Ion Etching) method or the like. The etching depth is x Ga 1-x The depth is set so that the portions of N layer 112a that will become holes 112b are removed and part of the surface of first GaN layer 111 is exposed.

[0059] Next, the 2nd Al y Ga 1-y The hole 112b formed in the N layer 112 is filled with the second Al y Ga 1-y The first Al layer has a smaller Al composition ratio than the N layer 112. x Ga 1-x The N layer 113 is buried. Specifically, for example, Al is deposited on the entire surface by MOCVD. x Ga 1-x The Al layer formed here is x Ga 1-x The N layer was later x Ga 1-x The layer that becomes the N layer 113, and the Al composition ratio x is the second Al y Ga 1-y The Al composition ratio y is smaller than that of the N layer 112. Next, a mask such as a resist pattern is formed in the region where the p-type GaN layer 115 is to be formed, and the first Al x Ga 1-xThe N layer is removed by etching, which can be performed by RIE or the like.

[0060] Furthermore, a second GaN layer is formed on the entire surface by MOCVD. Subsequently, a mask such as a resist pattern is formed on the island-shaped region where the second GaN layer 114 is to be formed. This mask is used to pattern the second GaN layer 114. Patterning can also be performed by etching using the RIE method or the like (see FIG. 5(c)).

[0061] Next, a p-type GaN layer is formed on the entire surface by MOCVD. Subsequently, a mask such as a resist pattern is formed on the island-shaped region where the p-type GaN layer 115 is to be formed. The p-type GaN layer 115 is patterned using this mask. The patterning can be performed by etching using the RIE method or the like.

[0062] Finally, a gate electrode 116 is formed on the p-type GaN layer 115, and a second Al y Ga 1-y A source electrode 117 and a drain electrode 118 are formed in predetermined regions on the N layer 112 (see FIG. 5(d)). In this manner, the GaN-based field effect transistor 100 can be manufactured.

[0063] In the GaN-based field effect transistor 100 according to the first embodiment, the first Al x Ga 1-x The N layer 113 is formed by the first GaN layer 111 and the first Al layer 112 in a no-gate bias state. x Ga 1-x The Al composition ratio x is such that the 2DEG 21 is not formed at the heterointerface between the N layer 113 and the second Al y Ga 1-y The N layer 112 is formed by the first GaN layer 111 and the second Al layer 112 in a no-gate bias state. y Ga 1-y The Al composition ratio y is set to form a 2DEG 21 at the heterointerface between the first Al layer 112 and the N layer 112. x Ga 1-xThe N layer 113 is formed in the region where the gate electrode 116 is formed.

[0064] As a result, the first GaN layer 111 and the second Al y Ga 1-y The heterointerface with the N layer 112, other than the gate electrode 116, can have a 2DEG 21 equivalent to that of a normally-on GaN-based field effect transistor, and an increase in the on-resistance Ron can be suppressed.

[0065] That is, by adopting the above-described configuration, it is possible to suppress an increase in the drain-source on-resistance Ron while maintaining the normally-off characteristics.

[0066] According to a preferred embodiment of the GaN-based field-effect transistor 100 of the first embodiment, the GaN-based field-effect transistor 100 is a normally-off type GaN-based field-effect transistor, which makes the GaN-based field-effect transistor 100 suitable for use as a switching element, particularly in fields that handle large amounts of power.

[0067] 2. Embodiment 2 In the following, in order to explain the semiconductor device of the present invention, a GaN-based field-effect transistor 200 according to embodiment 2 will be taken as an example. Fig. 6 is a cross-sectional view showing the GaN-based field-effect transistor 200 according to embodiment 2.

[0068] The GaN-based field-effect transistor 200 will be described mainly with respect to the differences from the GaN-based field-effect transistor 100 according to the first embodiment, and the description of the common points may be omitted as appropriate.

[0069] The GaN-based field effect transistor 200 according to the second embodiment has a first Al x Ga 1-x The region where the N layer 213 is formed is different from that of the GaN-based field-effect transistor 100 according to embodiment 1. That is, in the GaN-based field-effect transistor 100 according to embodiment 1, the first Al x Ga1-x The region where the N layer 113 is formed is the region where the gate electrode 116 is formed, whereas the first Al x Ga 1-x The region where the N layer 213 is formed is the region where the second GaN layer 214 is formed.

[0070] 2.1. Structure of "GaN-based field-effect transistor 200" As shown in FIG. 6, the GaN-based field-effect transistor 200 includes a first GaN layer 211 formed on a substrate 210 via a buffer layer (not shown), and a first Al layer 212 formed on the first GaN layer 211. x Ga 1-x N layer 213 and second Al y Ga 1-y N layer 212 and the first Al x Ga 1-x It has a second GaN layer 214 formed on the N layer 213 and a p-type GaN layer 215 formed on the second GaN layer 214 .

[0071] The second GaN layer 214 is x Ga 1-x The second Al layer 213 is formed in an island shape on the N layer 213. y Ga 1-y A source electrode 217 and a drain electrode 218 are formed on the N layer 212 .

[0072] 1st Al x Ga 1-x The N layer 213 is formed by the first GaN layer 211 and the first Al layer 212 in a no-gate bias state. x Ga 1-x The Al composition ratio x is such that the 2DEG 21 is not formed at the heterointerface between the N layer 213 and the second Al y Ga 1-y The N layer 212 is formed by the first GaN layer 211 and the second Al layer 212 in a no-gate bias state. y Ga 1-y The Al composition ratio y is set to form a 2DEG 21 at the heterointerface between the first Al layer 212 and the N layer 212. x Ga1-x The N layer 213 is formed in the region where the second GaN layer 214 is formed.

[0073] In the GaN-based field effect transistor 200, the first Al x Ga 1-x The N layer 213 is formed by the first GaN layer 211 and the first Al layer 212 in a no-gate bias state. x Ga 1-x The Al composition ratio x is such that the 2DEG 21 is not formed at the heterointerface between the first Al layer 213 and the N layer 213. x Ga 1-x N layer 213 is formed in the region where second GaN layer 214 is formed. Here, the region where second GaN layer 214 is formed includes the region where gate electrode 216 is formed. This makes it possible to realize GaN-based field-effect transistor 200 as a normally-off transistor.

[0074] 2.2. Operation mechanism of "GaN-based field-effect transistor 200" Fig. 7 is a schematic diagram showing the energy bands in the depth direction of each region in a thermal equilibrium state of the GaN-based field-effect transistor 200 according to embodiment 2. Fig. 7(a) is a diagram showing the energy band of the gate electrode 216 in a thermal equilibrium state, Fig. 7(b) is a diagram showing the energy band of the PSJ region in a thermal equilibrium state, and Fig. 7(c) is a diagram showing the energy bands of the region between the source electrode 217 and the gate electrode 216 and the region between the PSJ region and the drain electrode 218 in a thermal equilibrium state.

[0075] The energy band of the GaN-based field-effect transistor 200 according to the second embodiment will be described below with reference to Figures 7(a) to 7(c). The energy band of the gate electrode 216 in Figure 7(a) is the same as the energy band of the gate electrode 116 of the first embodiment shown in Figure 2(a). The energy band of the portion between the source electrode 217 and the gate electrode 216 and the portion between the PSJ region and the drain electrode 218 in Figure 7(c) are the same as the energy band of the portion between the source electrode 117 and the gate electrode 116 and the portion between the PSJ region and the drain electrode 118 of the first embodiment shown in Figure 2(c). For this reason, Figures 7(a) and 7(c) are merely shown, and their description will be omitted.

[0076] In the PSJ region, as shown in FIG. 7(b), the conduction band is raised by the polarization effect of the second GaN layer 214. x Ga 1-x The concentration n2 of the 2DEG 21 formed at the heterointerface with the N layer 213 is smaller than the concentration n3 of the 2DEG 21 in the portion between the PSJ region and the drain electrode 218.

[0077] In addition, in the PSJ region, the first Al x Ga 1-x The Al composition ratio x of the N layer 213 is the second Al y Ga 1-y The Al composition ratio y is smaller than that of the N layer 212. Therefore, the first Al x Ga 1-x The piezoelectric polarization of the N layer 213 is generated by the second Al layer between the PSJ region and the drain electrode 218. y Ga 1-y The piezoelectric polarization of the first GaN layer 211 and the first Al layer 212 in the PSJ region is smaller than that of the N layer 212. x Ga 1-x The concentration n2 of the 2DEG 21 formed at the heterointerface with the N layer 213 is smaller than the concentration n3 of the 2DEG 21 formed in the portion between the PSJ region and the drain electrode 218.

[0078] Furthermore, in the PSJ region, the valence band is raised by the polarization effect of the second GaN layer 214. This causes the second GaN layer 214 and the first Al x Ga 1-x At the heterointerface with the N layer 213, a 2DHG 22 having a concentration p2 is formed.

[0079] In the GaN-based field effect transistor 200, the first Al x Ga 1-x The N layer 213 is formed in the region where the gate electrode 216 is formed. x Ga 1-x The N layer 213 is formed by the first GaN layer 211 and the first Al layer 212 in a no-gate bias state. x Ga 1-x The Al composition ratio x is such that the 2DEG 21 is not formed at the heterointerface with the N layer 213 .

[0080] This makes it possible to set the threshold voltage of the GaN-based field effect transistor 200 to a positive value, that is, to realize a normally-off state.

[0081] Next, the on-resistance Ron of the GaN-based field-effect transistor 200 will be described with reference to Fig. 8. The on-resistance Ron between the drain and source of the GaN-based field-effect transistor 200 is expressed by the following formula.

number

[0082] In the GaN-based field effect transistor 200, the second Al y Ga 1-yThe N layer 212 is formed by the first GaN layer 211 and the second Al layer 212 in a no-gate bias state. y Ga 1-y The Al composition ratio is y, which allows the 2DEG 21 to be formed at the heterointerface with the N layer 212. This allows the 2DEG 21 to be equivalent to that of a normally-on GaN-based field effect transistor in the areas other than the gate electrode 116 and PSJ region. As a result, an increase in the on-resistance Ron can be suppressed.

[0083] In the GaN-based field effect transistor 200 according to the second embodiment, the first Al x Ga 1-x The N layer 213 is formed by the first GaN layer 211 and the first Al layer 212 in a no-gate bias state. x Ga 1-x The Al composition ratio x is such that the 2DEG 21 is not formed at the heterointerface with the N layer 213. y Ga 1-y The N layer 212 is formed by the first GaN layer 211 and the second Al layer 212 in a no-gate bias state. y Ga 1-y The 2DEG 21 is formed at the heterointerface with the N layer 212 with an Al composition ratio of y.

[0084] That is, the GaN-based field effect transistor 200 has a first GaN layer 211 and a second Al y Ga 1-y At the heterointerface with the N layer 212, a 2DEG 21 equivalent to that of a normally-on GaN-based field effect transistor can be provided, and an increase in the on-resistance Ron can be suppressed.

[0085] By employing the above-described configuration, it is possible to provide a GaN-based field effect transistor 200 that is a normally-off type and in which an increase in the on-resistance Ron is suppressed.

[0086] According to a preferred embodiment of the GaN-based field-effect transistor 200 of the second embodiment, the GaN-based field-effect transistor 200 is a normally-off type GaN-based field-effect transistor, which makes it suitable for use as a switching element, particularly in fields that handle large amounts of power. [Explanation of symbols]

[0087] 100, 200... GaN-based field effect transistor, 110, 210... substrate, 111, 211... first GaN layer, 112, 212... second Al y Ga 1-y N layer, 113,213...1st Al x Ga 1-x N layer, 114, 214... second GaN layer, 115, 215... p-type GaN layer, 116, 216... gate electrode, 117, 217... source electrode, 118, 218... drain electrode

Claims

1. a first GaN layer; and A first Al layer formed on the first GaN layer. ｘ Ga １－ｘ N (0<x≦1) layers; The first Al layer is formed on the first GaN layer. ｘ Ga １－ｘ The second Al layer formed adjacent to the N layer ｙ Ga １－ｙ N (0<y≦1) layers; The first Al ｘ Ga １－ｘ N layer and the second Al ｙ Ga １－ｙ a second GaN layer formed on the N layer; a p-type GaN layer formed on the second GaN layer; Said second Al ｙ Ga １－ｙ a source electrode formed on the N layer; Said second Al ｙ Ga １－ｙ a drain electrode formed on the N layer; a gate electrode electrically connected to the p-type GaN layer, the p-type GaN layer is formed in an island shape in a region on the source electrode side on the second GaN layer, The first Al ｘ Ga １－ｘ The N layer is formed by the first GaN layer and the first Al layer in a no-gate bias state. ｘ Ga １－ｘ a portion of the first GaN layer in the vicinity of a heterointerface with an N layer is formed to have an Al composition ratio such that two-dimensional electron gas is not formed; Said second Al ｙ Ga １－ｙ The N layer is formed by the first GaN layer and the second Al layer in a no-gate bias state. ｙ Ga １－ｙ a portion of the first GaN layer in the vicinity of a heterointerface with an N layer is formed to have an Al composition ratio such that a two-dimensional electron gas is formed; The first Al ｘ Ga １－ｘ A semiconductor device according to claim 1, wherein the N layer is formed at least in a region where the gate electrode is formed.

2. 10. The semiconductor device of claim 1, The first Al ｘ Ga １－ｘ a second GaN layer formed on the second GaN layer;

3. 3. The semiconductor device according to claim 1, A semiconductor device characterized by being a normally-off type GaN-based field effect transistor.

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