Semiconductor element

Abstract

To provide a semiconductor element with suppressed increase in on-resistance in spite of being a normally-off type.SOLUTION: A semiconductor element 100 includes a first GaN layer 111, an AlxGa1-xN(0<x≤1) layer 112, a second GaN layer 114, and a p-type GaN layer 115 formed on an AlxGa1-xN layer 112. The thickness and Al composition ratio of the AlxGa1-xN layer 112 is thickness and an AI composition ratio where a two-dimensional electron gas 21 is not formed on a heterointerface between the first GaN layer 111 and the AlxGa1-xN layer 112, in a part where the p-type GaN layer 115 is formed, in a non-gate bias state. The p-type GaN layer 115 and the second GaN layer 114 are formed adjacent to each other on the AlxGa1-xN layer 112.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As a semiconductor device with excellent high-frequency characteristics, the development of HEMT (High Electron Mobility Transistor) has been carried out. As one of the HEMTs, a GaN-based field-effect transistor having an AlGaN / GaN heterojunction formed by crystal growth of a thin film of Al , ,

[0005] , , , , , , , , ,

[0004] Ga 1-x GaN (0 < x ≤ 1) (hereinafter sometimes referred to as "AlGaN") can be mentioned. In a GaN-based field-effect transistor, a layer of two-dimensional electron gas (hereinafter sometimes referred to as "2DEG") formed by the accumulation of highly mobile two-dimensional electrons is formed on the AlGaN / GaN junction surface. The 2DEG can freely move on the heterointerface between the GaN layer and the Al x Ga 1-x GaN layer (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0006] FIG. 7 is a diagram showing a GaN-based field effect transistor 900 that has been made normally-off by reducing the Al composition ratio x of the Al x Ga 1-x N layer 913. FIG. 8 is a diagram showing the on-resistance Ron in the GaN-based field effect transistor 900 that has been made normally-off by reducing the Al composition ratio x of the Al x Ga 1-x N layer 913.

[0007] The GaN-based field effect transistor 900 shown in FIG. 7 has, on a substrate 910, a first GaN layer 911, an Al x Ga 1-x [[ID=二十九]]N (0 < x ≤ 1) layer 913 (hereinafter sometimes simply referred to as "Al x Ga 1-x N layer 913"), a second GaN layer 914 formed on the Al x Ga 1-x N layer 913, and a p-type GaN layer 915 formed on the second GaN layer 914.

[0008] In FIG. 7, in the GaN-based field effect transistor 900, a two-dimensional electron gas 21 (hereinafter sometimes referred to as "2DEG21") formed in a portion of the first GaN layer 911 near the heterointerface between the first GaN layer 911 and the Al x Ga 1-x N layer 913 is indicated by black circles in the gate bias state. Also, in the gate bias state, between the second GaN layer 914 and the Al x Ga 1-xTwo-dimensional hole gas 22 (hereinafter, sometimes referred to as "2DHG 22") formed in a portion of second GaN layer 914 near the heterointerface with N layer 913 is indicated by a white circle.

[0009] Al x Ga 1-x The N layer 913 is in a state where no gate bias is applied and the first GaN layer 911 and Al x Ga 1-x It is formed with an Al composition ratio x such that the 2DEG 21 is not formed at the heterointerface with the N layer 913. This allows the GaN-based field effect transistor 900 to function as a normally-off type.

[0010] The drain-source on-resistance Ron is expressed by the following formula:

number

[0011] Al x Ga 1-x In the GaN-based field-effect transistor 900 in which the Al composition ratio x of the N layer 913 is small, the first GaN layer 911 and Al x Ga 1-x Since the concentration of the 2DEG 21 formed at the heterointerface with the N layer 913 is low, there is a problem in that the on-resistance Ron between the drain and source becomes large.

[0012] In other words, in order to realize normally-off in semiconductor devices, x Ga 1-x When the Al composition ratio x of the N layer is reduced, the on-resistance Ron between the drain and source increases, which is a problem.

[0013] Therefore, an object of the present invention is to solve such problems, and to provide a semiconductor device which is normally-off type and in which an increase in on-resistance Ron is suppressed.

Means for Solving the Problems

[0014] The semiconductor device of the present invention includes a first GaN layer, an Al x Ga 1-x N (0 < x ≦ 1) layer formed on the first GaN layer, a second GaN layer formed on the Al x Ga 1-x N layer, a p-type GaN layer formed on the Al x Ga 1-x N layer, a source electrode formed on the Al x Ga 1-x N layer, a drain electrode formed on the Al x Ga 1-x N layer, and a gate electrode electrically connected to the p-type GaN layer. The thickness and Al composition ratio of the Al x Ga 1-x N layer are such that no two-dimensional electron gas is formed in the portion of the first GaN layer near the heterointerface between the first GaN layer and the Al x Ga 1-x N layer at the portion where the p-type GaN layer is formed in the gate bias-free state. The p-type GaN layer and the second GaN layer are formed adjacent to each other on the Al x Ga 1-x N layer.

Effects of the Invention

[0015] The semiconductor device of the present invention has a second GaN layer formed on the Al x Ga 1-x N layer and a p-type GaN layer formed on the Al x Ga 1-x N layer. In the portion where the p-type GaN layer is formed, in the gate bias-free state, the first GaN layer and the Al x Ga1-x The first GaN layer is formed to a thickness and Al composition ratio that prevents the formation of two-dimensional electron gas in the portion of the first GaN layer near the heterointerface with the N layer, thereby achieving a normally-off state.

[0016] In addition, in the portion of the AlxGa1-xN layer where the second GaN layer is formed, no p-type GaN layer is formed on the second GaN layer. Therefore, in the portion where the second GaN layer is formed, the first GaN layer and Al x Ga 1-x Two-dimensional electron gas is formed in the first GaN layer near the heterointerface with the N layer, which suppresses an increase in the drain-source on-resistance.

[0017] According to the present invention, it is possible to provide a semiconductor element that is of a normally-off type and in which an increase in on-resistance is suppressed. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a cross-sectional view showing a GaN-based field-effect transistor 100 according to a first embodiment. [Figure 2] 1 is a schematic diagram showing the energy band in the depth direction of each region in a thermal equilibrium state of the GaN-based field-effect transistor 100 according to the first embodiment. [Figure 3] 2 is a diagram for explaining the on-resistance Ron in the GaN-based field-effect transistor 100 according to the first embodiment. FIG. [Figure 4] 2A to 2C are views for explaining a method for manufacturing the GaN-based field-effect transistor 100 according to the first embodiment. [Figure 5] FIG. 1 is a cross-sectional view showing a GaN-based field-effect transistor 200 according to a second embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing a GaN-based field-effect transistor 300 according to a third embodiment. [Figure 7]This is a diagram showing a normally-off GaN-based field-effect transistor 900 by reducing the Al composition ratio x of the AlxGa1-xN layer 913. [Figure 8] This is a diagram showing the on-resistance Ron in a normally-off GaN-based field-effect transistor 900 by reducing the Al composition ratio x of the AlxGa1-xN layer 913.

Embodiments for Carrying Out the Invention

[0019] Hereinafter, the semiconductor device of the present invention will be described based on embodiments. Note that the embodiments described below do not limit the invention according to the claims. Also, not all of the elements and combinations thereof described in the embodiments are essential for the solution means of the present invention.

[0020] 1. Embodiment 1 Hereinafter, in order to describe the semiconductor device of the present invention, the GaN-based field-effect transistor 100 according to Embodiment 1 will be described as an example. FIG. 1 is a cross-sectional view showing the GaN-based field-effect transistor 100 according to Embodiment 1.

[0021] 1.1. Structure of "GaN-based field-effect transistor 100" As shown in FIG. 1, the GaN-based field-effect transistor 100 includes a first GaN layer 111 formed on a substrate 110 via a buffer layer (not shown), and an Al x Ga 1-x N (0 <x ≦ 1) layer 112 (hereinafter, may be simply referred to as "Al x Ga 1-x N layer 112".), and a second GaN layer 114 formed on the Al x Ga 1-x N layer 112, and a p-type GaN layer 115 formed on the Al x Ga 1-x N layer 112.

[0022] The substrate 110 is preferably a substrate on which a GaN-based semiconductor grows on the C-plane, such as a C-plane sapphire substrate, a Si substrate, or a SiC substrate. The buffer layer may be, for example, a polycrystalline or amorphous GaN layer, an AlN layer, an AlGaN layer, or an AlGaN / GaN superlattice layer.

[0023] The second GaN layer 114 is Al x Ga 1-x It is formed on the N layer 112. The region where the second GaN layer 114 is formed corresponds to the polarization super junction region (PSJ region).

[0024] The p-type GaN layer 115 is Al x Ga 1-x The p-type GaN layer 115 and the second GaN layer 114 are formed directly on the N layer 112. x Ga 1-x The second GaN layer 114 and the p-type GaN layer 115 are formed adjacent to each other on the N layer 112. Here, "adjacent" means adjacent to each other. The second GaN layer 114 and the p-type GaN layer 115 are formed adjacent to each other and are electrically connected. This allows the second GaN layer 114 and the p-type GaN layer 115, which form the PSJ structure, to be electrically connected to each other.

[0025] A gate electrode 116 electrically connected to the p-type GaN layer 115 is formed on the p-type GaN layer 115. x Ga 1-x A source electrode 117 and a drain electrode 118 are formed on the N layer 112 .

[0026] Al x Ga 1-x The thickness and Al composition ratio x of the N layer 112 are determined by the ratio of the first GaN layer 111 and Al in the portion where the p-type GaN layer 115 is formed in the no-gate bias state. x Ga 1-x The first GaN layer 111 is formed to a thickness and Al composition ratio x such that the 2DEG 21 is not formed in the portion of the first GaN layer 111 near the heterointerface with the N layer 112 .

[0027] Al x Ga 1-x The thickness and Al composition ratio x of the AlGaN layer 112 can be calculated by simulation or obtained by actually prototyping the device.

[0028] In the following description, the portion of the first GaN layer 111 near the heterointerface between the first GaN layer 111 and the Al x Ga 1-x GaN layer 112 may be referred to as the "heterointerface between the first GaN layer 111 and the Al x Ga 1-x GaN layer 112".

[0029] In the GaN-based field-effect transistor 100, in the ungated bias state, for the concentration n1 of the 2DEG in the portion of the gate electrode 116, the concentration n2 of the 2DEG in the PSJ region, and the concentration n3 of the 2DEG in the portion between the PSJ region and the drain electrode 118, the relationship n1 < n2 < n3 holds. Note that the concentration of the 2DEG in the portion between the source electrode 117 and the gate electrode 116 is also n3. In FIG. 1, the magnitude relationship n1 < n2 < n3 is schematically shown using the size of the black circles.

[0030] Note that the Al x Ga 1-x GaN layer 112 is formed at a thickness and Al composition ratio x such that no 2DEG is formed at the heterointerface between the first GaN layer 111 and the Al x Ga 1-x GaN layer 112 in the portion where the p-type GaN layer 115 is formed in the ungated bias state. Therefore, in the ungated bias state, the concentration n1 of the 2DEG in the portion of the gate electrode 116 is substantially zero.

[0031] For the concentration of the 2DHG22, in the ungated bias state, for the concentration p1 of the 2DHG22 in the portion of the gate electrode 116 and the concentration p2 of the 2DHG22 in the PSJ region, the magnitude relationship p1 < p2 holds. Note that in the ungated bias state, the concentration p1 of the 2DHG22 in the portion of the gate electrode 116 is substantially zero.

[0032] 1.2. Operation mechanism of "GaN-based field-effect transistor 100" The energy band of the GaN-based field-effect transistor 100 will be described with reference to Fig. 2. Fig. 2 is a schematic diagram showing the energy band in the depth direction of each region in the GaN-based field-effect transistor 100 according to the first embodiment in a thermal equilibrium state. Fig. 2(a) is a diagram showing the energy band of the gate electrode 116 in a thermal equilibrium state, Fig. 2(b) is a diagram showing the energy band of the PSJ region in a thermal equilibrium state, and Fig. 2(c) is a diagram showing the energy band of the region between the source electrode 117 and the gate electrode 116 and the region between the PSJ region and the drain electrode 118 in a thermal equilibrium state.

[0033] 2(a) to 2(c), the vertical direction represents the electron energy, Ec represents the energy at the bottom of the conduction band, Ev represents the energy at the top of the valence band, and Ef represents the Fermi energy.

[0034] In the portion between the source electrode 117 and the gate electrode 116, and in the portion between the PSJ region and the drain electrode 118, as shown in FIG. 2(c), the first GaN layer 111 and Al x Ga 1-x At the heterointerface with the N layer 112, a 2DEG 21 with a concentration of n3 is formed.

[0035] In the PSJ region, as shown in FIG. 2(b), the conduction band is raised by the polarization effect of the second GaN layer 114. This raises the conduction band between the first GaN layer 111 and Al x Ga 1-x The concentration n2 of the 2DEG 21 formed at the heterointerface with the N layer 112 is smaller than the concentration n3 of the 2DEG 21 formed in the portion between the PSJ region and the drain electrode 118.

[0036] In the PSJ region, the valence band is raised by the polarization effect of the second GaN layer 114. This raises the valence band. x Ga 1-xAt the heterointerface with the N layer 112, a 2DHG 22 having a concentration p2 is formed.

[0037] In the gate electrode 116 portion, Al x Ga 1-x The p-type GaN layer 115 is formed directly on the N layer 112. As a result, as shown in FIG. 2(a), the first GaN layer 111 and the Al x Ga 1-x The concentration n1 of the 2DEG 21 formed at the heterointerface with the N layer 112 is lower than the concentration n2 of the 2DEG 21 in the PSJ region.

[0038] In the gate electrode 116 portion, Al x Ga 1-x The p-type GaN layer 115 is formed directly on the N layer 112. For the same reason as above, the Al x Ga 1-x The concentration p1 of the 2DHG 22 formed at the interface between the N layer 112 and the p-type GaN layer 115 is smaller than the concentration p2 of the 2DHG 22 in the PSJ region.

[0039] In the GaN-based field effect transistor 100, Al x Ga 1-x The thickness and Al composition ratio x of the N layer 112 are determined by the ratio of the first GaN layer 111 and Al in the portion where the p-type GaN layer 115 is formed in the no-gate bias state. x Ga 1-x The p-type GaN layer 115 has a thickness and an Al composition ratio x such that the 2DEG 21 is not formed at the heterointerface with the N layer 112. A gate electrode 116 is formed on the p-type GaN layer 115.

[0040] This makes it possible to set the threshold voltage of the GaN-based field effect transistor 100 to a positive value, that is, to realize a normally-off state.

[0041] Next, the on-resistance Ron of the GaN-based field-effect transistor 100 will be described with reference to Fig. 3. Fig. 3 is a diagram shown for explaining the on-resistance Ron in the GaN-based field-effect transistor 100 according to the first embodiment.

[0042] In the GaN-based field effect transistor 100, the first GaN layer 111 and Al x Ga 1-x The 2DEG 21 is formed at the heterointerface with the N layer 112. The 2DEG 21 is formed by the first GaN layer 111 and the Al x Ga 1-x They can move freely along the heterointerface with the N layer 112. When a bias voltage is applied between the drain electrode 118 and the source electrode 117, the 2DEG 21 has high electron mobility and transports a large electron current from the source electrode 117 to the drain electrode 118.

[0043] The drain-source on-resistance R of the GaN-based field-effect transistor 100 on is expressed by the following formula:

number

[0044] The access resistances, that is, the resistance Rac1 of the portion between the source electrode 117 and the gate electrode 116, the resistance Rch-gate of the portion of the gate electrode 116, the resistance Rch-PSJ of the PSJ region, and the resistance Rac2 of the portion between the PSJ region and the drain electrode 118 are determined by the relationship between the first GaN layer 111 and the Al x Ga 1-x It is affected by the concentration of the 2DEG 21 formed at the heterointerface with the N layer 112.

[0045] In the GaN-based field effect transistor 100, the p-type GaN layer 115 is not formed on the second GaN layer 114. Therefore, in the PSJ region, even in a no-gate-bias state, the first GaN layer 111 and the Al x Ga 1-x A 2DEG 21 is formed at the heterointerface with the N layer 112 .

[0046] Here, the GaN-based field effect transistor 100 and the Al x Ga 1-x A comparison will be made with a GaN-based field effect transistor 900 (see FIGS. 7 and 8) in which the Al composition ratio x of the N layer 913 is reduced.

[0047] The GaN-based field effect transistor 900 is x Ga 1-x The N layer 913 is in a state where the first GaN layer 911 and the Al x Ga 1-x The Al composition ratio x is such that the 2DEG 21 is not formed at the heterointerface with the N layer 913 .

[0048] In the GaN-based field effect transistor 900, Al x Ga 1-x As the Al composition ratio x of the N layer 913 is reduced, x Ga 1-x The polarization of the N layer 913 is weakened. As a result, under gate bias conditions, the first GaN layer 911 and the Al x Ga 1-x The concentration of DEG21 formed at the heterointerface with the N layer 913 decreases.

[0049] As a result of the decrease in the concentration of the 2DEG 21, the access resistance (Rac1) between the source electrode 917 and the gate electrode 916, the resistance of the PSJ region (Rch-PSJ), and the access resistance (Rac2) between the PSJ region and the drain electrode 918 increase. As a result, the GaN-based field-effect transistor 900 has a problem in that the on-resistance Ron increases (see FIG. 8).

[0050] On the other hand, in the GaN-based field effect transistor 100 according to the first embodiment, the p-type GaN layer 115 is not formed on the second GaN layer 114. Therefore, in the no-gate-bias state, the p-type GaN layer 115 is not formed on the first GaN layer 111 and the Al x Ga 1-x A 2DEG 21 is formed at the heterointerface with the N layer 112 .

[0051] That is, in the GaN-based field-effect transistor 100, a 2DEG 21 equivalent to that of a normally-on GaN-based field-effect transistor is formed in the portion other than the portion of the gate electrode 116, and an increase in the on-resistance Ron can be suppressed.

[0052] The GaN-based field-effect transistor 100 according to the first embodiment is a normally-off type, but can suppress an increase in the on-resistance Ron.

[0053] 1.3. Manufacturing method of "GaN-based field-effect transistor 100" 4A to 4C are diagrams shown for explaining a method for manufacturing the GaN-based field-effect transistor 100 according to embodiment 1. Hereinafter, the method for manufacturing the GaN-based field-effect transistor 100 according to embodiment 1 will be explained with reference to FIG.

[0054] As shown in FIG. 4(a), a buffer layer (not shown), a first GaN layer 111, and an Al layer were grown on a substrate 110 by a conventionally known metalorganic chemical vapor deposition (MOCVD) method using TMG (trimethylgallium) as a Ga source, TMA (trimethylaluminum) as an Al source, NH3 (ammonia) as a nitrogen source, and N2 gas and H2 gas as carrier gases. x Ga 1-x The N layer 112 and the second GaN layer 114a are epitaxially grown in this order.

[0055] The growth temperature during epitaxial growth is, for example, 1100° C. The substrate 110 can be a sapphire substrate (for example, a C-plane sapphire substrate), a Si substrate, a SiC substrate, or the like. The buffer layer can be a GaN layer, an AlN layer, an AlGaN layer, an AlGaN / GaN superlattice layer, or the like.

[0056] Next, a mask such as a resist pattern is formed on the island-shaped region where the second GaN layer 114 is to be formed, and this mask is used to etch the second GaN layer 114a in the thickness direction to form the pattern of the second GaN layer 114 (see FIG. 4(b)). The etching can be performed by RIE (Reactive Ion Etching) or the like.

[0057] Next, a p-type GaN layer (reference numeral omitted) is formed on the entire surface by MOCVD. Subsequently, a mask such as a resist pattern is formed on the island-shaped region where the p-type GaN layer 115 is to be formed. The p-type GaN layer 115 is patterned using this mask. The patterning can be performed by etching using the RIE method or the like.

[0058] Finally, as shown in FIG. 4(d), a gate electrode 116 is formed on the p-type GaN layer 115, and an Al x Ga 1-x A source electrode 117 and a drain electrode 118 are formed in predetermined regions on the N layer 112 . In this manner, the GaN-based field effect transistor 100 can be manufactured.

[0059] In the GaN-based field effect transistor 100 according to the first embodiment, Al x Ga 1-x In the no-gate bias state, the N layer 112 is a portion where the p-type GaN layer 115 is formed, and is separated from the first GaN layer 111 and Al x Ga 1-x It is formed to a thickness and Al composition ratio x such that the 2DEG 21 is not formed at the heterointerface with the N layer 112. This allows the GaN-based field effect transistor 100 to be normally off.

[0060] Furthermore, in the GaN-based field effect transistor 100, the p-type GaN layer 115 is not formed on the second GaN layer 114. Therefore, in the no-gate-bias state, the first GaN layer 111 and Al x Ga 1-x 2DEG 21 is formed at the heterointerface with the N layer 112. This makes it possible to suppress an increase in the drain-source on-resistance Ron.

[0061] That is, the GaN-based field-effect transistor 100 according to the first embodiment can provide a semiconductor element that is normally-off type and in which an increase in the on-resistance Ron is suppressed.

[0062] According to a preferred embodiment of the GaN-based field-effect transistor 100 of the first embodiment, the GaN-based field-effect transistor 100 is a normally-off type GaN-based field-effect transistor, which makes the GaN-based field-effect transistor 100 suitable for use as a switching element, particularly in fields that handle large amounts of power.

[0063] 2. Embodiment 2 In the following, a GaN-based field effect transistor 200 according to the second embodiment will be taken as an example to explain the semiconductor device of the present invention.

[0064] FIG. 5 is a cross-sectional view showing a GaN-based field-effect transistor 200 according to the second embodiment. The description of the GaN-based field-effect transistor 200 according to the second embodiment will focus on the differences from the GaN-based field-effect transistor 100 according to the first embodiment, and the description of the common points may be omitted as appropriate.

[0065] As shown in FIG. 5, the GaN-based field-effect transistor 200 includes a first GaN layer 211 formed on a substrate 210 via a buffer layer (not shown), and an Al x Ga 1-x N layer 212 and Al xGa 1-x A second GaN layer 214 formed on the N layer 212 and an Al x Ga 1-x A p-type GaN layer 215 is formed on the N layer 212.

[0066] The second GaN layer 214 is Al x Ga 1-x The p-type GaN layer 215 is formed on the N-type layer 212. The region where the second GaN layer 214 is formed corresponds to the polarization super junction region (PSJ region). x Ga 1-x It is formed on the N layer 212 adjacent to the second GaN layer 214. It also has a protruding portion 215a that protrudes above the second GaN layer 214.

[0067] Al x Ga 1-x A source electrode 217 and a drain electrode 218 are formed on the N layer 212. Furthermore, a gate electrode 216 electrically connected to the p-type GaN layer 215 is provided on the p-type GaN layer 215.

[0068] In the GaN-based field effect transistor 200, similarly to the GaN-based field effect transistor 100 according to the first embodiment, Al x Ga 1-x In the no-gate bias state, the N layer 212 is a portion where the p-type GaN layer 215 is formed, and is separated from the first GaN layer 211 and Al x Ga 1-x The Al layer 212 is formed to a thickness and an Al composition ratio x such that the 2DEG 21 is not formed at the heterointerface with the N layer 212. x Ga 1-x A normally-off state can be realized without reducing the Al composition ratio x of the N layer 212.

[0069] Also, Al x Ga 1-xIn the N layer 212, except for the region where the protruding portion 215a is formed, the p-type GaN layer 215 is not formed on the second GaN layer 214. Therefore, in the no-gate bias state, the first GaN layer 211 and Al x Ga 1-x 2DEG 21 is formed at the heterointerface with the N layer 212. This makes it possible to suppress a decrease in 2DEG 21 in the PSJ region, and to suppress an increase in the drain-source on-resistance Ron.

[0070] Furthermore, in the GaN-based field-effect transistor 200 according to the second embodiment, the p-type GaN layer 215 is formed adjacent to the second GaN layer 214, and has a protruding portion 215a that protrudes above the second GaN layer 214. This makes it possible to ensure a more reliable electrical connection between the p-type GaN layer 215 and the second GaN layer 214.

[0071] The GaN-based field-effect transistor 200 according to the second embodiment can provide a semiconductor device that is normally-off type and in which an increase in the on-resistance Ron is further suppressed.

[0072] 3. Embodiment 3 In the following, a GaN-based field-effect transistor 300 according to a third embodiment will be taken as an example to explain the semiconductor device of the present invention.

[0073] FIG. 6 is a cross-sectional view showing a GaN-based field-effect transistor 300 according to the third embodiment. The description of the GaN-based field-effect transistor 300 according to the third embodiment will be centered on the differences from the GaN-based field-effect transistor 100 according to the first embodiment and the GaN-based field-effect transistor 200 according to the second embodiment, and the description of the common points may be omitted as appropriate.

[0074] As shown in FIG. 6, a GaN-based field-effect transistor 300 according to the third embodiment includes a first GaN layer 311 formed on a substrate 310 via a buffer layer (not shown), and an AlN layer 312 formed on the first GaN layer 311.x Ga 1-x N layer 312 and Al x Ga 1-x A second GaN layer 314 formed on the N layer 312 and an Al x Ga 1-x and a p-type GaN layer 215 formed on the N layer 312.

[0075] Al x Ga 1-x The N layer 312 has a first region (reference numeral omitted) formed to a first thickness and having a p-type GaN layer 315 formed thereon, and a second region (reference numeral omitted) formed to a second thickness thinner than the first thickness and having a second GaN layer 314 formed thereon. x Ga 1-x The N layer 312 is formed on the substrate 310 by metal organic chemical vapor deposition (MOCVD) or the like, by depositing a buffer layer (not shown), a first GaN layer 311, and an Al x Ga 1-x After the N layer 312 is epitaxially grown in sequence, a mask such as a resist pattern is formed on the portion that will become the first region. x Ga 1-x It can be formed by etching the N layer 312 in the thickness direction.

[0076] As shown in FIG. 6, the second GaN layer 314 is partially Al x Ga 1-x It may extend onto the first region of the N layer 312. The region where the second GaN layer 314 is formed corresponds to the polarization super junction region (PSJ region).

[0077] The p-type GaN layer 315 is Al x Ga 1-x The second region of the N layer 312, i.e., Al x Ga 1-x The p-type GaN layer 315 is formed on the second region of the N layer 312, which has a smaller thickness. x Ga 1-xIt is formed on the N layer 312 adjacent to the second GaN layer 314. It also has a protruding portion 315a that protrudes above the second GaN layer 314.

[0078] Al x Ga 1-x A source electrode 317 and a drain electrode 318 are formed on the N layer 312. A gate electrode 316 is provided on the p-type GaN layer 315 and is electrically connected to the p-type GaN layer 315.

[0079] The GaN-based field effect transistor 300 has a p-type GaN layer 315 made of Al x Ga 1-x It is formed directly on the N layer 312. x Ga 1-x The thickness of the first region of the N layer 312 on which the gate electrode 316 is formed is Al x Ga 1-x The thickness of the N layer 312 is thinner than the thickness of the second region where the gate electrode 316 is not formed. As a result, in a no-gate bias state, the first GaN layer 111 and the Al x Ga 1-x It is relatively easy to realize a configuration in which the 2DEG 21 is not formed at the heterointerface with the N layer 112. As a result, the GaN-based field effect transistor 300 can be made normally off.

[0080] Also, Al x Ga 1-x In the no-gate bias state, the N layer 312 is in contact with the first GaN layer 311 and Al in the area where the second GaN layer 314 is formed. x Ga 1-x Two-dimensional electron gas 21 is formed at the heterointerface with the N layer 312. This makes it possible to suppress a decrease in 2DEG 21 in the PSJ region, and to suppress an increase in the on-resistance Ron between the drain and source.

[0081] The GaN-based field-effect transistor 300 according to the third embodiment can provide a semiconductor device that is a normally-off type and in which an increase in the on-resistance Ron is further suppressed. [Explanation of symbols]

[0082] 100, 200, 300... GaN-based field effect transistor, 110, 210, 310... substrate, 111, 211, 311... first GaN layer, 112, 212, 312... Al x Ga 1-x N layer, 114, 214, 314... second GaN layer, 115, 215, 315... p-type GaN layer, 215a, 315a... extension portion, 116, 216, 316... gate electrode, 117, 217, 317... source electrode, 118, 218, 318... drain electrode

Claims

1. a first GaN layer; and Al formed on the first GaN layer ｘ Ga １－ｘ N (0<x≦1) layers; The Al ｘ Ga １－ｘ a second GaN layer formed on the N layer; The Al ｘ Ga １－ｘ a p-type GaN layer formed on the N layer; The Al ｘ Ga １－ｘ a source electrode formed on the N layer; The Al ｘ Ga １－ｘ a drain electrode formed on the N layer; a gate electrode electrically connected to the p-type GaN layer, The Al ｘ Ga １－ｘ The thickness and Al composition ratio of the N layer are determined such that, in a no-gate bias state, the thickness of the N layer is the same as that of the first GaN layer and the Al ｘ Ga １－ｘ a thickness and an Al composition ratio such that no two-dimensional electron gas is formed in a portion of the first GaN layer in the vicinity of a heterointerface between the first GaN layer and an N layer; The p-type GaN layer and the second GaN layer are ｘ Ga １－ｘ A semiconductor element characterized by being formed on and adjacent to an N layer.

2. 10. The semiconductor device of claim 1, The p-type GaN layer has a protruding portion that protrudes above the second GaN layer.

3. 10. The semiconductor device of claim 1, The Al ｘ Ga １－ｘ The thickness of the N layer in the region where the gate electrode is formed is ｘ Ga １－ｘ A semiconductor element comprising an N-layer, the N-layer being thinner than a region in an upper layer where the gate electrode is not formed.

4. The semiconductor device according to any one of claims 1 to 3, A semiconductor device characterized by being a normally-off type GaN-based field effect transistor.

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