Semiconductor device

Abstract

To provide a semiconductor device capable of improving reliability.SOLUTION: A semiconductor device according to an embodiment comprises: a semiconductor portion having a cell region and a termination region provided outside the cell region; a first electrode provided on a back surface of the semiconductor portion; a second electrode provided on a front surface of the semiconductor portion; a control electrode provided within the semiconductor portion via one of a plurality of first insulating films arranged in the direction from the cell region toward the termination region; and a third electrode provided within the semiconductor portion via a second insulating film between the control electrode. The control electrode comprises a first control section in contact with the first insulating film and a second control section in contact with the first insulating film and facing the first control section via the second insulating film. Among the plurality of first insulating films, a termination insulating film positioned closer to the termination region than the control electrode has a sloped surface inclined downward toward the underside of the first control section, and no second control section exists on this sloped surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In semiconductor devices such as MOSFETs having trench gates, a structure is known in which a field plate having the same potential as the source electrode is disposed inside the gate trench together with the gate electrode.

[0003] In the semiconductor device described above, the gate electrode and field plate are also formed in the termination region. A termination trench is further formed at the end of the termination region. If the voltage withstand capability of the gate electrode around this termination trench is insufficient, reliability will decrease. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-45628 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device that can improve reliability. [Means for solving the problem]

[0006] The semiconductor device according to one embodiment includes: a semiconductor portion having a cell region and a termination region provided outside the cell region; a first electrode provided on the back surface of the semiconductor portion; a second electrode provided on the front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulating films arranged in a direction from the cell region toward the termination region; a third electrode provided in the semiconductor portion with a second insulating film interposed between the third electrode and the control electrode; Equipped with the control electrode has a first control portion in contact with the first insulating film and a second control portion in contact with the first insulating film and facing the first control portion via the second insulating film; Among the multiple first insulating films, an adjacent insulating film adjacent to the termination insulating film provided closer to the termination region than the control electrode has a sloped portion that slopes downward toward the first control unit, and the second control unit is not present on the sloped portion. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 10A to 10C are cross-sectional views illustrating a step of forming an insulating film on the inner surface of each of the trench and the termination trench. [Figure 3] 10A to 10C are cross-sectional views illustrating a step of forming a third electrode and a fourth electrode. [Figure 4] FIG. 10 is a cross-sectional view illustrating a step of etching a part of the third electrode and the fourth electrode. [Figure 5] FIG. 10 is a cross-sectional view illustrating a step of covering the upper surfaces of the third electrode and the fourth electrode with an insulating film. [Figure 6] 10A to 10C are cross-sectional views illustrating a step of filling the inside of the trench with an insulating film. [Figure 7] 10A to 10C are cross-sectional views illustrating a step of removing the upper portion of the insulating film. [Figure 8] 10A to 10C are cross-sectional views illustrating a step of forming a gate insulating film. [Figure 9] 10A to 10C are cross-sectional views illustrating a step of forming a control electrode. [Figure 10] 5A to 5C are cross-sectional views illustrating steps of forming a second semiconductor layer and a third semiconductor layer. [Figure 11] 10A and 10B are cross-sectional views illustrating a process of dividing the control electrode into a first control section and a second control section. [Figure 12] 10A to 10C are cross-sectional views illustrating a step of forming an insulating film in a trench. [Figure 13]FIG. 10 is a cross-sectional view illustrating a step of forming a fourth semiconductor layer in the second semiconductor layer. [Figure 14] FIG. 10 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 15] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 16] 10A and 10B are cross-sectional views illustrating a step of placing a resist on the termination trench and on a trench adjacent to the termination trench. [Figure 17] 10A and 10B are cross-sectional views illustrating a step of leaving the control electrode. [Figure 18] 10A and 10B are cross-sectional views illustrating a step of dividing the control electrode into a first control section and a second control section. [Figure 19] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 20] 10A to 10C are cross-sectional views illustrating a step of forming a gate insulating film according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0009] (First embodiment) FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. In the following description, the arrangement and configuration of each part of the semiconductor device may be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward. In this embodiment, the X-direction and Y-direction correspond to the first and third directions and represent in-plane directions parallel to the front (or back) surface of the semiconductor device 1. The Z-direction corresponds to the second direction and represents the out-of-plane direction orthogonal to the front (or back) surface of the semiconductor device 1.

[0010] Also, p, p + The notation means that the p-type impurity concentration increases in this order. - , n, n +The notation indicates that the n-type impurity concentration increases in this order.

[0011] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the semiconductor region, can also be determined by, for example, SIMS.

[0012] 1 is, for example, a MOSFET. The semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, a second electrode 30, a control electrode 40, a third electrode 50, and a fourth electrode 60.

[0013] The semiconductor portion 10 is made of, for example, silicon. The semiconductor portion 10 has, for example, a back surface on which a first electrode 20 is provided and a front surface opposite thereto. The second electrode 30 is provided on the front surface side of the semiconductor portion 10. The first electrode 20 is a drain electrode.

[0014] The first electrode 20 is provided on the back surface of the semiconductor portion 10. The second electrode 30 is a source electrode and includes a metal layer 31 and a barrier metal layer 32. The metal layer 31 is made of, for example, aluminum (Al). On the other hand, the barrier metal layer 32 is made of, for example, a stack of titanium (Ti) and titanium nitride (TiN). The semiconductor portion 10 includes a cell region 100a and a termination region 100b.

[0015] The cell region 100a switches between an on state and an off state depending on the voltage applied to the control electrode 40. In the on state, a current path is created through which a current flows from the first electrode 20 to the second electrode 30. In the off state, the current path is not created, and therefore no current flows from the first electrode 20 to the second electrode 30.

[0016] The termination region 100b is provided outside the cell region 100a. In the termination region 100b, the above-mentioned current path is not generated regardless of whether a voltage is applied to the control electrode 40, and therefore, no current flows from the first electrode 20 to the second electrode 30.

[0017] The semiconductor section 10 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 12 of a second conductivity type, a third semiconductor layer 13 of the first conductivity type, a fourth semiconductor layer 14 of the second conductivity type, and a fifth semiconductor layer 15 of the first conductivity type. In this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type.

[0018] The first semiconductor layer 11 is n - The first semiconductor layer 11 is provided between the first electrode 20 and the second electrode 30.

[0019] The second semiconductor layer 12 is a p-type diffusion layer. The second semiconductor layer 12 is provided on the first semiconductor layer 11.

[0020] The third semiconductor layer 13 is n + The third semiconductor layer 13 is a first-conductivity-type source layer. The third semiconductor layer 13 is provided on the second semiconductor layer 12. The third semiconductor layer 13 contains a first-conductivity-type impurity at a concentration higher than the first-conductivity-type impurity concentration of the first semiconductor layer 11, and is electrically connected to the second electrode 30. The third semiconductor layer 13 is provided in the cell region 100a but not in the termination region 100b.

[0021] The fourth semiconductor layer 14 is p + The fourth semiconductor layer 14 is a contact layer having a second conductivity type. The fourth semiconductor layer 14 is connected to the second electrode 30 within the second semiconductor layer 12. The fourth semiconductor layer 14 contains a higher concentration of second conductivity type impurities than the second conductivity type impurities of the second semiconductor layer 12, and is electrically connected to the second electrode 30. In this embodiment, the fourth semiconductor layer 14 is provided in the second semiconductor layer 12. The second semiconductor layer 12 is electrically connected to the second electrode 30 via the fourth semiconductor layer 14.

[0022] The fifth semiconductor layer 15 is an n-type drain layer. The fifth semiconductor layer 15 is provided between the first semiconductor layer 11 and the first electrode 20. The fifth semiconductor layer 15 contains a first conductivity type impurity at a concentration higher than the first conductivity type impurity concentration of the first semiconductor layer 11, and is electrically connected to the first electrode 20.

[0023] The control electrode 40 provided in the cell region 100a is a gate electrode. The control electrode 40 is located between the first electrode 20 and the second electrode 30, and is provided inside a trench TR1 that opens in the surface of the semiconductor portion 10. On the other hand, as described above, the third semiconductor layer 13 is not provided in the termination region 100b. Therefore, the control electrode 40 provided in the termination region 100b is a dummy gate electrode.

[0024] The third electrode 50 is a field plate. The third electrode 50 is electrically connected to the second electrode 30 and is provided inside the trench TR1 at a distance from the control electrode 40. The third electrode 50 is provided, for example, to be located in the first semiconductor layer 11. Within the trench TR1, the distance from the third electrode 50 to the first electrode 20 is shorter than the distance from the control electrode 40 to the first electrode 20.

[0025] 1, control electrode 40 is provided at the same level as second semiconductor layer 12 in the direction from first electrode 20 to second electrode 30, i.e., the Z direction. Control electrode 40 includes a first control unit 40A and a second control unit 40B. First control unit 40A and second control unit 40B are aligned in the X direction inside trench TR1. However, the control electrode 40 arranged on the outermost side in termination region 100b is provided with first control unit 40A but not with second control unit 40B.

[0026] The trench TR1 extends in the X direction from the second electrode 30 toward the first electrode 20, and has a depth reaching into the first semiconductor layer 11 from the surface side of the semiconductor portion .

[0027] The termination trench TR2 is provided at the outermost end of the termination region 100b. The termination trench TR2 has a depth equal to that of the trench TR1. A fourth electrode 60 is provided in the termination trench TR2. The length of the fourth electrode 60 in the Z direction is longer than that of the third electrode 50. In other words, the thickness of the fourth electrode 60 is greater than that of the third electrode 50.

[0028] The fourth electrode 60 may be formed continuously so as to surround the entire periphery of the cell region 100 a, or may be formed intermittently so as to surround part of the periphery of the cell region 100 a. Although one fourth electrode 60 surrounds the cell region 100 a in a single layer in FIG. 1, multiple fourth electrodes 60 may surround the cell region 100 a in a multiple layer.

[0029] In this embodiment, a plurality of trenches TR1 are provided in each of the cell region 100a and the termination region 100b, aligned in the X direction. The second semiconductor layers 12 are provided between the plurality of trenches TR1, and face the first control unit 40A and the second control unit 40B of the control electrode 40 with the insulating film 51 interposed therebetween.

[0030] 1, the semiconductor device 1 further includes an insulating film 41 and an insulating film 51. In this embodiment, the insulating film 41 corresponds to the second insulating film, and the insulating film 51 corresponds to the first insulating film.

[0031] The insulating film 41 is provided in the trench TR1 so as to cover the first control unit 40A and the second control unit 40B. The insulating film 41 is also provided between the second electrode 30 and the control electrode 40, and functions as an interlayer insulating film that electrically insulates the control electrode 40 from the second electrode 30. The insulating film 41 is also provided between the semiconductor portion 10 and the third electrode 50, and electrically insulates the third electrode 50 from the semiconductor portion 10.

[0032] The insulating film 51 is provided between the semiconductor portion 10 and the control electrode 40 and functions as a gate insulating film that electrically insulates the control electrode 40 from the semiconductor portion 10. The second semiconductor layer 12 is provided to face the control electrode 40 via this gate insulating film. The third semiconductor layer 13 is in contact with this gate insulating film between the second semiconductor layer 12 and the second electrode 30. The insulating film 51 is also provided between the insulating film 41 and the third electrode 50. In the termination region 100b, the insulating film 51 provided in the trench TR1 adjacent to the termination trench TR2 has a sloped portion 51A. The sloped portion 51A is inclined toward the underside of the first control unit 40A. In the termination trench TR2, the insulating film 51 covers the fourth electrode 60. The insulating film 51 formed on the inner surface of the termination trench TR2 is also referred to as a termination insulating film. The insulating film 51 formed on the inner surface of the trench TR1 adjacent to the termination trench TR2 is also referred to as an adjacent insulating film.

[0033] A method for manufacturing the semiconductor device 1 according to this embodiment will be described below with reference to Figures 2 to 13. Here, the steps after forming the trench TR1 and the termination trench TR2 will be described.

[0034] First, as shown in Fig. 2, an insulating film 51 is formed on the inner surfaces of the trench TR1 and the termination trench TR2. The insulating film 51 is made of, for example, silicon oxide (SiO2).

[0035] 3, a third electrode 50 is formed in the trench TR1, and a fourth electrode 60 is formed in the termination trench TR2. The third electrode 50 and the fourth electrode 60 are formed, for example, as polysilicon films deposited simultaneously. In this embodiment, the third electrode 50 and the fourth electrode 60 are polysilicon films deposited simultaneously.

[0036] 4, the third electrode 50 is etched by, for example, CDE (Chemical Dry Etching). At this time, the fourth electrode 60 is protected with a resist so as not to be etched, and the third electrode 50 is etched.

[0037] 5, the upper surfaces (exposed surfaces) of the third electrode 50 and the fourth electrode 60 are covered with an insulating film 51. At this time, the upper end of the trench TR1 is open, while the upper end of the termination trench TR2 is closed by the insulating film 51.

[0038] 6, the upper surface of the insulating film 51 is covered with an insulating film 52, and the inside of the trench TR1 is filled with the insulating film 52. The insulating film 52 corresponds to a third insulating film and is formed using, for example, BPSG (Boron Phosphorus Silicon Glass). Note that the portion of the insulating film 52 that covers the upper surface of the insulating film 51 is removed by, for example, CMP (Chemical Mechanical Polisher). As a result, the insulating film 52 that filled the trench TR1 remains.

[0039] Next, as shown in FIG. 7, the portion of the insulating film 51 formed in the trench TR1 that is located above the third electrode 50 and the insulating film 52 that is surrounded by this portion are etched. In this process, a resist 70 is used to protect the insulating film 51 formed in the upper portion of the termination trench TR2. This resist 70 is formed so as to also cover the upper portion of the trench TR1 adjacent to the termination trench TR2. However, due to the side etching, the insulating films 51 and 52 are removed in a fan shape within the trench TR1. As a result, a sloped portion 51A is formed on the inner side surface of the trench TR1.

[0040] 8, insulating film 52 is removed, and then insulating film 51 functioning as a gate insulating film is formed in trench TR1. At this time, as shown in FIG. 8, in trench TR1 adjacent to termination trench TR2 in termination region 100b, insulating film 52 formed on slope portion 51A is also removed.

[0041] Next, as shown in FIG. 9, polysilicon 401 is filled into the trench TR1 and is also formed on the upper surface of the insulating film 51.

[0042] Next, as shown in FIG. 10 , the polysilicon 401 formed on the upper surface of the insulating film 51 is etched to leave the control electrode 40, which is the polysilicon 401 filled in the trench TR1. The polysilicon 401 is removed, for example, by CDE. Next, a second semiconductor layer 12 is formed on the first semiconductor layer 11. The second semiconductor layer 12 can be formed, for example, by implanting and diffusing p-type impurities. Next, a third semiconductor layer 13 is formed on the second semiconductor layer 12. The third semiconductor layer 13 can be formed, for example, by implanting and diffusing n-type impurities. However, the third semiconductor layer 13 is formed in the cell region 100a but not in the termination region 100b.

[0043] 11, the central portion of the control electrode 40 is removed. As a result, the control electrode 40 is divided into a first control unit 40A and a second control unit 40B. However, the portion of the control electrode 40 formed on the slope portion 51A of the insulating film 51 is also removed. Therefore, the first control unit 40A remains in the trench TR1 adjacent to the termination trench TR2. Note that the first control unit 40A and the second control unit 40B are connected at the end portion in the Y direction (depth direction), and therefore the electrical connection between the first control unit 40A and the second control unit 40B is maintained.

[0044] 12, an insulating film 41 is formed in the trench TR1. The insulating film 41 can be formed by CVD (Chemical Vapor Deposition) using, for example, non-doped BPSG.

[0045] 13, a fourth semiconductor layer 14 is formed in the second semiconductor layer 12. The fourth semiconductor layer 14 can be formed, for example, by forming a trench TR3 that penetrates the insulating film 41 and the third semiconductor layer 13 in the Z direction and terminates at the second semiconductor layer 12, and then injecting and diffusing p-type impurities from the trench TR3.

[0046] 1, the first electrode 20 and the second electrode 30 are formed, thereby completing the semiconductor device 1 shown in FIG.

[0047] Here, a comparative example to be compared with this embodiment will be described. Fig. 14 is a cross-sectional view of a semiconductor device according to the comparative example. In Fig. 14, the same components as those in the semiconductor device 1 described above are given the same reference numerals, and redundant explanations will be omitted.

[0048] In the semiconductor device 100 shown in FIG. 14, the second control unit 40B is also formed on the sloped surface 51A. The sloped surface 51A has a shape that slopes downward from the first control unit 40A. Therefore, the upper right end portion (see the circular area C in FIG. 14) of the second control unit 40B formed on the sloped surface 51A on the side of the termination trench TR2 has a pointed shape. Therefore, an electric field tends to concentrate on the oxide film (insulating films 41, 51) that contacts this pointed portion, which may shorten the life of this oxide film. As a result, the long-term reliability of the voltage withstand capability may be insufficient.

[0049] 11, the control electrode 40 formed on the sloped surface 51A is removed. Therefore, the second control unit 40B is not present on the sloped surface 51A. Therefore, according to this embodiment, it is possible to improve reliability.

[0050] (Second embodiment) Fig. 15 is a cross-sectional view of a semiconductor device according to a second embodiment. In Fig. 15, differences from the semiconductor device 1 according to the first embodiment will be mainly described. Components similar to those of the semiconductor device 1 according to the first embodiment are given the same reference numerals, and redundant description will be omitted.

[0051] In semiconductor device 2 according to this embodiment, control electrode 40 provided in trench TR1 adjacent to termination region 100b has second control unit 40B in addition to first control unit 40A. Second control unit 40B is located on sloped surface 51A.

[0052] The control electrode 40 provided in the trench TR1 is made of polysilicon containing impurities, similar to the control electrodes 40 provided in the other trenches TR1. On the other hand, the concentration of the impurities contained in the control electrode 40 provided in the trench TR1 is lower than the concentration of the impurities contained in the control electrodes 40 provided in the other trenches TR1. For example, the control electrode 40 provided in the trench TR1 may be made of undoped polysilicon containing no impurities.

[0053] 16 to 18, a method for manufacturing the semiconductor device 2 according to this embodiment will be described below, focusing on the differences from the first embodiment.

[0054] The steps up to the step of filling the trench TR1 with polysilicon 401 and depositing it on the upper surface of the insulating film 51 (see FIG. 9) are the same as those in the first embodiment, and therefore will not be described again. Note that the polysilicon 401 is undoped polysilicon that does not contain impurities.

[0055] 16, resist 71 is placed on termination trench TR2 and on trench TR1 adjacent to termination trench TR2. Subsequently, for example, phosphorus (P) is ion-implanted as an impurity from above (see arrows in FIG. 16). At this time, resist 71 functions as a mask, so that implantation of phosphorus into a portion of polysilicon 401 formed on termination trench TR2 and a portion formed in trench TR1 adjacent to termination trench TR2 is blocked.

[0056] Next, the resist 71 is stripped off. Subsequently, as shown in Fig. 17, the polysilicon 401 formed on the upper surface of the insulating film 51 is etched to leave the control electrode 40, which is the polysilicon 401 filled in the trench TR1. At this time, the control electrode 40 formed in the trench TR1 adjacent to the termination trench TR2 is made of undoped polysilicon, while the control electrode 40 formed in the other trenches TR1 is made of polysilicon containing phosphorus as an impurity.

[0057] Next, as shown in FIG. 18 , a second semiconductor layer 12 is formed on the first semiconductor layer 11, and a third semiconductor layer 13 is formed on the second semiconductor layer 12, as in the first embodiment. Subsequently, the central portion of the control electrode 40 is removed, as in the first embodiment. However, in this embodiment, as shown in FIG. 18 , the control electrode 40 formed on the sloped surface 51A remains. Therefore, the first control unit 40A and the second control unit 40B remain in the trench TR1 adjacent to the termination trench TR2. The first control unit 40A and the second control unit 40B formed in the trench TR1 adjacent to the termination trench TR2 are also connected at the terminal end in the Y direction (depth direction), so the electrical connection between the first control unit 40A and the second control unit 40B is maintained. The subsequent steps are the same as those in the first embodiment, and therefore will not be described.

[0058] In the semiconductor device 2 according to the present embodiment, the second control unit 40B is provided on the slope 51A of the trench TR1 adjacent to the termination trench TR2. If the second control unit 40B contains a high concentration of impurities (phosphorus), the accelerated oxidation of the second control unit 40B is promoted. In this case, the upper right end of the second control unit 40B becomes more pointed, which makes it easier for an electric field to concentrate on the oxide film in contact with the upper right end. As a result, the life of the oxide film is shortened, and the long-term reliability of the voltage withstand capability may become insufficient.

[0059] In contrast, in this embodiment, as described above, the impurity concentration of the second control unit 40B formed on the sloped surface 51A is lower than the impurity concentration of the other second control units 40B. This suppresses accelerated oxidation of the second control unit 40B, thereby suppressing the degree of protrusion at the upper right end. As a result, electric field concentration on the oxide film is alleviated, thereby improving reliability.

[0060] (Third embodiment) Fig. 19 is a cross-sectional view of a semiconductor device according to a third embodiment. In Fig. 19, differences from the semiconductor device 1 according to the first embodiment will be mainly described. Components similar to those of the semiconductor device 1 according to the first embodiment are given the same reference numerals, and redundant description will be omitted.

[0061] In the semiconductor device 3 according to this embodiment, in the trench TR1 adjacent to the termination region 100b, the position of the lower end of the slope portion 51A is different from that of the first embodiment. In the semiconductor device 1 according to the first embodiment described above, as shown in FIG. 1, the slope portion 51A faces the first control unit 40A in the X direction with the insulating film 41 interposed therebetween. In this case, the lower end of the insulating film 41 is located lower than the lower end of the slope portion 51A.

[0062] In contrast, in the semiconductor device 3 according to this embodiment, as shown in Fig. 19, an insulating film 52 is provided between the third electrode 50 and the sloped surface 51A. Therefore, the lower end of the sloped surface 51A extends closer to the lower end of the first control unit 40A than in the first embodiment. That is, in the cross-sectional view of Fig. 19, the lower end of the sloped surface 51A extends to the left.

[0063] A method for manufacturing the semiconductor device 3 according to this embodiment will be described below with reference to Fig. 20. Here, the differences from the first embodiment will be mainly described.

[0064] In this embodiment, the steps from the step of forming trench TR1 and termination trench TR2 (see FIG. 2) to the step of etching the upper part of insulating film 51 and the upper part of insulating film 52 formed in trench TR1 (see FIG. 7) are the same as those in the first embodiment, and therefore the description will be omitted.

[0065] Next, in this embodiment, as shown in FIG. 20, the insulating film 51 is left in the trench TR1 adjacent to the termination trench TR2, and the insulating film 52 is removed from the other trenches TR1.

[0066] Next, an insulating film 51 functioning as a gate insulating film is formed in the trench TR1. At this time, as shown in Fig. 20, in the trench TR1 adjacent to the termination trench TR2, a sloped surface 51A is formed on the insulating film 52. Therefore, the lower end of the sloped surface 51A extends further to the left in the X direction, i.e., to the first control unit 40A side, compared to the first embodiment.

[0067] The subsequent steps (FIGS. 9 to 13) are the same as those in the first embodiment, and therefore will not be described. Finally, returning to FIG. 19, the first electrode 20 and the second electrode 30 are formed. This completes the semiconductor device 3 shown in FIG. 19.

[0068] In the present embodiment described above, the second control section 40B is not present on the sloped surface section 51A, as in the first embodiment, so that the reliability can be improved according to the present embodiment.

[0069] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0070] 1, 2: Semiconductor device 10: Semiconductor Department 11: First semiconductor layer 12: Second semiconductor layer 13: Third semiconductor layer 14: Fourth semiconductor layer 15: Fifth semiconductor layer 20: 1st electrode 30:Second electrode 40: Control electrode 40A: First control section 40B: Second control section 41: insulating film 50: 3rd electrode 51: insulating film 51A: Slope section 52: insulating film 60: 4th electrode TR1: Trench TR2: Termination trench 100a: Cell area 100b: Termination area

Claims

1. a semiconductor portion having a cell region and a termination region provided outside the cell region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on the front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulating films arranged in a direction from the cell region toward the termination region; a third electrode provided in the semiconductor portion with a second insulating film interposed between the third electrode and the control electrode; Equipped with the control electrode has a first control portion in contact with the first insulating film, and a second control portion in contact with the first insulating film and facing the first control portion with the second insulating film interposed therebetween; a semiconductor device, wherein an adjacent insulating film, among the plurality of first insulating films, adjacent to a termination insulating film provided closer to the termination region than the control electrode has a sloped portion inclined toward a lower side of the first control portion, and the second control portion is not present on the sloped portion.

2. 2. The semiconductor device according to claim 1, wherein the slope portion of the adjacent insulating film faces the first control portion via the second insulating film, and a lower end of the second insulating film is located lower than a lower end of the slope portion.

3. the slope portion of the adjacent insulating film faces the first control portion via the second insulating film, The semiconductor device according to claim 1 , further comprising a third insulating film provided between said sloped surface portion and said third electrode.

4. The semiconductor portion is a first semiconductor layer provided with the termination insulating film and the adjacent insulating film; a second semiconductor layer provided on the first semiconductor layer; a third semiconductor layer provided on the second semiconductor layer; a fourth semiconductor layer connected to the second electrode within the second semiconductor layer; a fifth semiconductor layer provided between the first semiconductor layer and the first electrode; The semiconductor device according to claim 1 , comprising:

5. The semiconductor device according to claim 4 , wherein the third semiconductor layer is not present in the termination region.

6. a fourth electrode provided inside the termination insulating film; The semiconductor device according to claim 1 , wherein the fourth electrode has a thickness greater than a thickness of the third electrode.

7. The semiconductor device according to claim 1 , wherein said third electrode is electrically connected to said second electrode.

8. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a MOSFET.

9. a semiconductor portion having a cell region and a termination region provided outside the cell region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on the front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulating films arranged in a direction from the cell region toward the termination region; a third electrode provided in the semiconductor portion with a second insulating film interposed between the third electrode and the control electrode; Equipped with the control electrode has a first control portion in contact with the first insulating film, and a second control portion in contact with the first insulating film and facing the first control portion with the second insulating film interposed therebetween; a semiconductor device, wherein, among the plurality of first insulating films, an adjacent insulating film adjacent to a termination insulating film provided closer to the termination region than the control electrode has a sloped portion inclined toward a lower side of the first control unit, and a concentration of impurities contained in the second control unit provided in the sloped portion is lower than a concentration of the impurities contained in other second control units.

10. 10. The semiconductor device according to claim 9, wherein the second control portion provided on the slope portion is made of undoped polysilicon.

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