Semiconductor device

Abstract

To provide a semiconductor device capable of improving reliability.SOLUTION: A semiconductor device according to an embodiment comprises: a semiconductor portion having a cell region and a termination region provided outside the cell region; a first electrode provided on a back surface of the semiconductor portion; a second electrode provided on a front surface of the semiconductor portion; a control electrode provided within the semiconductor portion via one of a plurality of first insulating films arranged in the direction from the cell region toward the termination region; and a third electrode provided within the semiconductor portion via a second insulating film between the control electrode. Among the plurality of first insulating films, a hollow portion is provided inside a termination insulating film positioned closer to the termination region than the control electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In semiconductor devices such as MOSFETs having trench gates, a structure is known in which a field plate having the same potential as the source electrode is disposed inside the gate trench together with the gate electrode.

[0003] In the semiconductor device described above, the gate trench is also formed in the termination region. A termination trench is further formed at the end of the termination region. Because the internal structures of the gate trench and the termination trench are different, stress may occur. This stress may cause damage to the semiconductor device. In other words, there is a concern that the reliability of the semiconductor device may be reduced. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-45628 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device that can improve reliability. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a semiconductor portion having a cell region and a termination region provided outside the cell region, a first electrode provided on a back surface of the semiconductor portion, a second electrode provided on a front surface side of the semiconductor portion, a control electrode provided in the semiconductor portion via one of a plurality of first insulating films arranged in a direction from the cell region toward the termination region, and a third electrode provided in the semiconductor portion between the control electrode and the second insulating film. One of the plurality of first insulating films, which is provided closer to the termination region than the control electrode, has a hollow portion inside. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 10A to 10C are cross-sectional views illustrating a step of forming an insulating film on the inner surface of each of the trench and the termination trench. [Figure 3] 10A to 10C are cross-sectional views illustrating a step of forming a third electrode and a fourth electrode. [Figure 4] FIG. 10 is a cross-sectional view illustrating a step of etching a part of the third electrode and the fourth electrode. [Figure 5] FIG. 10 is a cross-sectional view illustrating a step of covering the upper surfaces of the third electrode and the fourth electrode with an insulating film. [Figure 6] 10A to 10C are cross-sectional views illustrating a step of filling the inside of the trench with an insulating film. [Figure 7] 10A to 10C are cross-sectional views illustrating a step of removing the upper portion of the insulating film. [Figure 8] 10A to 10C are cross-sectional views illustrating a step of forming a gate insulating film. [Figure 9] 10A to 10C are cross-sectional views illustrating a step of forming a control electrode. [Figure 10] 5A to 5C are cross-sectional views illustrating steps of forming a second semiconductor layer and a third semiconductor layer. [Figure 11] 10A and 10B are cross-sectional views illustrating a process of dividing the control electrode into a first control section and a second control section. [Figure 12] 10A to 10C are cross-sectional views illustrating a step of forming an insulating film in a trench. [Figure 13] FIG. 10 is a cross-sectional view illustrating a step of etching an insulating film formed directly above a fourth electrode. [Figure 14] FIG. 10 is a cross-sectional view illustrating a step of etching the fourth electrode. [Figure 15] 10A to 10C are cross-sectional views illustrating a step of forming a hollow portion 61 in the termination trench. [Figure 16] FIG. 10 is a cross-sectional view illustrating a step of forming a fourth semiconductor layer in the second semiconductor layer. [Figure 17] FIG. 10 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 18] FIG. 10 is a cross-sectional view of a semiconductor device according to a first modification. [Figure 19] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 20] FIG. 10 is a cross-sectional view illustrating a step of etching a part of the fourth electrode. [Figure 21] 10A to 10C are cross-sectional views illustrating a step of forming an insulating film in a termination trench. [Figure 22] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification. [Figure 23] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 24] FIG. 10 is a cross-sectional view illustrating a step of implanting ions into the third electrode with a resist placed on the fourth electrode. [Figure 25] FIG. 10 is a cross-sectional view of a semiconductor device according to a third modification. [Figure 26] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 27] 10A to 10C are cross-sectional views illustrating a step of forming an insulating film on the inner surface of each of the trench and the termination trench. [Figure 28] 10A to 10C are cross-sectional views illustrating a step of forming a third electrode and a fourth electrode. [Figure 29] FIG. 10 is a cross-sectional view illustrating a step of etching a part of the third electrode and the fourth electrode. [Figure 30] FIG. 10 is a cross-sectional view illustrating an oxidation step. [Figure 31]FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth modification. [Figure 32] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 33] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth modification. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0009] (First embodiment) FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. In the following description, the arrangement and configuration of each part of the semiconductor device may be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward. In this embodiment, the X-direction and Y-direction correspond to the first and third directions and represent in-plane directions parallel to the front (or back) surface of the semiconductor device 1. The Z-direction corresponds to the second direction and represents the out-of-plane direction orthogonal to the front (or back) surface of the semiconductor device 1.

[0010] Also, p, p + The notation means that the p-type impurity concentration increases in this order. - , n, n + The notation indicates that the n-type impurity concentration increases in this order.

[0011] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the semiconductor region, can also be determined by, for example, SIMS.

[0012] 1 is, for example, a MOSFET. The semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, a second electrode 30, a control electrode 40, and a third electrode 50.

[0013] The semiconductor portion 10 is made of, for example, silicon. The semiconductor portion 10 has, for example, a back surface on which a first electrode 20 is provided and a front surface opposite thereto. The second electrode 30 is provided on the front surface side of the semiconductor portion 10. The first electrode 20 is a drain electrode.

[0014] The first electrode 20 is provided on the back surface of the semiconductor portion 10. The second electrode 30 is a source electrode. The semiconductor portion 10 has a cell region 100a and a termination region 100b.

[0015] The cell region 100a switches between an on state and an off state depending on the voltage applied to the control electrode 40. In the on state, a current path is created through which a current flows from the first electrode 20 to the second electrode 30. In the off state, the current path is not created, and therefore no current flows from the first electrode 20 to the second electrode 30.

[0016] The termination region 100b is provided outside the cell region 100a. In the termination region 100b, the above-mentioned current path is not generated regardless of whether a voltage is applied to the control electrode 40, and therefore, no current flows from the first electrode 20 to the second electrode 30.

[0017] The semiconductor section 10 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 12 of a second conductivity type, a third semiconductor layer 13 of the first conductivity type, a fourth semiconductor layer 14 of the second conductivity type, and a fifth semiconductor layer 15 of the first conductivity type. In this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type.

[0018] The first semiconductor layer 11 is n - The first semiconductor layer 11 is provided between the first electrode 20 and the second electrode 30.

[0019] The second semiconductor layer 12 is a p-type diffusion layer. The second semiconductor layer 12 is provided on the first semiconductor layer 11.

[0020] The third semiconductor layer 13 is n + The third semiconductor layer 13 is a first-conductivity-type source layer. The third semiconductor layer 13 is provided on the second semiconductor layer 12. The third semiconductor layer 13 contains a first-conductivity-type impurity at a concentration higher than the first-conductivity-type impurity concentration of the first semiconductor layer 11, and is electrically connected to the second electrode 30. The third semiconductor layer 13 is provided in the cell region 100a but not in the termination region 100b.

[0021] The fourth semiconductor layer 14 is p + The fourth semiconductor layer 14 is a contact layer having a second conductivity type. The fourth semiconductor layer 14 is connected to the second electrode 30 within the second semiconductor layer 12. The fourth semiconductor layer 14 contains a higher concentration of second conductivity type impurities than the second conductivity type impurities of the second semiconductor layer 12, and is electrically connected to the second electrode 30. In this embodiment, the fourth semiconductor layer 14 is provided in the second semiconductor layer 12. The second semiconductor layer 12 is electrically connected to the second electrode 30 via the fourth semiconductor layer 14.

[0022] The fifth semiconductor layer 15 is an n-type drain layer. The fifth semiconductor layer 15 is provided between the first semiconductor layer 11 and the first electrode 20. The fifth semiconductor layer 15 contains a first conductivity type impurity at a concentration higher than the first conductivity type impurity concentration of the first semiconductor layer 11, and is electrically connected to the first electrode 20.

[0023] The control electrode 40 provided in the cell region 100a is a gate electrode. The control electrode 40 is located between the first electrode 20 and the second electrode 30, and is provided inside a trench TR1 that opens in the surface of the semiconductor portion 10. On the other hand, as described above, the third semiconductor layer 13 is not provided in the termination region 100b. Therefore, the control electrode 40 provided in the termination region 100b is a dummy gate electrode.

[0024] The third electrode 50 is a field plate. The third electrode 50 is electrically connected to the second electrode 30 and is provided inside the trench TR1 at a distance from the control electrode 40. The third electrode 50 is provided to be located in the first semiconductor layer 11. Within the trench TR1, the distance from the third electrode 50 to the first electrode 20 is shorter than the distance from the control electrode 40 to the first electrode 20.

[0025] 1, the control electrode 40 is provided at the same level as the second semiconductor layer 12 in the direction from the first electrode 20 to the second electrode 30, i.e., in the Z direction. The control electrode 40 includes a first control unit 40A and a second control unit 40B. The first control unit 40A and the second control unit 40B are aligned in the X direction inside the trench TR1.

[0026] The trench TR1 extends in the X direction from the second electrode 30 toward the first electrode 20, and has a depth reaching into the first semiconductor layer 11 from the surface side of the semiconductor portion .

[0027] Termination trench TR2 is provided at the outermost end of termination region 100b. Termination trench TR2 has the same depth as trench TR1. A hollow portion 61 surrounded by insulating films 41 and 51 is provided within termination trench TR2. In this embodiment, the lower end position of hollow portion 61 is the same as the lower end position of third electrode 50.

[0028] In this embodiment, it is desirable that the distance D1 between the trench TR1 adjacent to the termination trench TR2 and the termination trench TR2 is smaller than the distance D2 between the trenches TR1. This is because the breakdown voltage in the termination region 100b can be sufficiently ensured. The hollow portion 61 may be formed continuously so as to surround the entire outer periphery of the cell region 100a, or may be formed intermittently so as to surround part of the outer periphery of the cell region 100a.

[0029] In this embodiment, a plurality of trenches TR1 are provided in each of the cell region 100a and the termination region 100b, aligned in the X direction. The second semiconductor layers 12 are provided between the plurality of trenches TR1, and face the first control unit 40A and the second control unit 40B of the control electrode 40 with the insulating film 51 interposed therebetween.

[0030] 1, the semiconductor device 1 further includes an insulating film 41 and an insulating film 51. In this embodiment, the insulating film 41 corresponds to the second insulating film, and the insulating film 51 corresponds to the first insulating film.

[0031] The insulating film 41 is provided in the trench TR1 so as to cover the first control unit 40A and the second control unit 40B. The insulating film 41 is also provided between the second electrode 30 and the control electrode 40, and functions as an interlayer insulating film that electrically insulates the control electrode 40 from the second electrode 30. The insulating film 41 is also provided between the semiconductor portion 10 and the third electrode 50, and electrically insulates the third electrode 50 from the semiconductor portion 10.

[0032] The insulating film 51 is provided between the semiconductor portion 10 and the control electrode 40 and functions as a gate insulating film that electrically insulates the control electrode 40 from the semiconductor portion 10. The second semiconductor layer 12 is provided to face the control electrode 40 via this gate insulating film. The third semiconductor layer 13 is in contact with this gate insulating film between the second semiconductor layer 12 and the second electrode 30. The insulating film 51 is also provided between the insulating film 41 and the third electrode 50. The insulating film 51 is formed on the inner surface of the termination trench TR2 so as to surround the hollow portion 61. The insulating film 51 formed on the inner surface of the termination trench TR2 is also referred to as a termination insulating film. The insulating film 51 formed on the inner surface of the trench TR1 adjacent to the termination trench TR2 is also referred to as an adjacent insulating film.

[0033] 2 to 16, a method for manufacturing the semiconductor device 1 according to this embodiment will be described below. Here, the steps after forming the trench TR1 and the termination trench TR2 will be described.

[0034] First, as shown in Fig. 2, an insulating film 51 is formed on the inner surfaces of the trench TR1 and the termination trench TR2. The insulating film 51 is made of, for example, silicon oxide (SiO2).

[0035] 3, a third electrode 50 is formed in the trench TR1, and a fourth electrode 60 is formed in the termination trench TR2. The third electrode 50 and the fourth electrode 60 are formed using, for example, polysilicon. Note that the material of the third electrode 50 and the fourth electrode 60 is not limited to polysilicon, and may be the same material.

[0036] 4, the third electrode 50 and a portion of the fourth electrode 60 are etched by, for example, CDE (Chemical Dry Etching). At this time, the thickness of the mask and the like are adjusted so that the etching amount of the fourth electrode 60 is smaller than the etching amount of the third electrode 50.

[0037] 5, the upper surfaces (exposed surfaces) of the third electrode 50 and the fourth electrode 60 are covered with an insulating film 51. At this time, the upper end of the trench TR1 is open, while the upper end of the termination trench TR2 is closed by the insulating film 51.

[0038] 6, the inside of the trench TR1 is filled with an insulating film 52. The insulating film 52 corresponds to a third insulating film, and is formed using, for example, BPSG (Boron Phosphorus Silicon Glass).

[0039] Next, as shown in FIG. 7, the portion of the insulating film 51 formed in the trench TR1 that is located above the third electrode 50 and the insulating film 52 that is surrounded by this portion are etched.

[0040] Next, as shown in FIG. 8, the insulating film 52 is removed, and then an insulating film 51 that functions as a gate insulating film is formed in the trench TR1.

[0041] 9, the control electrode 40 is formed in the trench TR1. The control electrode 40 can be formed by filling the trench TR1 with, for example, polysilicon.

[0042] Next, as shown in FIG. 10, the upper portion of the control electrode 40 is etched. The control electrode 40 is removed, for example, by CDE. Next, a second semiconductor layer 12 is formed on the upper portion of the first semiconductor layer 11. The second semiconductor layer 12 can be formed, for example, by implanting and diffusing p-type impurities. Next, a third semiconductor layer 13 is formed on the upper portion of the second semiconductor layer 12. The third semiconductor layer 13 can be formed, for example, by implanting and diffusing n-type impurities. However, the third semiconductor layer 13 is formed in the cell region 100a but not in the termination region 100b.

[0043] 11, the central portion of the control electrode 40 is removed, resulting in the control electrode 40 being divided into a first control section 40A and a second control section 40B.

[0044] 12, an insulating film 41 is formed in the trench TR1. The insulating film 41 can be formed by CVD (Chemical Vapor Deposition) using, for example, non-doped BPSG.

[0045] 13, the insulating film 41 and the insulating film 51 formed directly above the fourth electrode 60 are etched. The insulating film 41 and the insulating film 51 can be removed by, for example, CDE or RIE (Reactive Ion Etching).

[0046] 14, the fourth electrode 60 is etched, thereby forming a cavity with an open upper end in the termination trench TR2.

[0047] 15, an insulating film 41 is deposited so as to close the upper opening of the termination trench TR2. This forms a hollow portion 61 in the termination trench TR2. The insulating film 41 can be deposited by, for example, CVD.

[0048] 16, the fourth semiconductor layer 14 is formed in the second semiconductor layer 12. The fourth semiconductor layer 14 can be formed, for example, by forming a trench TR3 that penetrates the insulating film 41 and the third semiconductor layer 13 in the Z direction and terminates at the second semiconductor layer 12, and then injecting and diffusing p-type impurities from the trench TR3.

[0049] 1, the first electrode 20 and the second electrode 30 are formed, thereby completing the semiconductor device 1 shown in FIG.

[0050] Here, a comparative example to be compared with this embodiment will be described. Fig. 17 is a cross-sectional view of a semiconductor device according to the comparative example. In Fig. 17, the same components as those in the semiconductor device 1 described above are given the same reference numerals, and redundant explanations will be omitted.

[0051] 17, the fourth electrode 60 remains in the termination trench TR2. The positions of the bottom ends of the fourth electrode 60 and the third electrode 50 are approximately the same. However, the fourth electrode 60 terminates at the top end of the termination trench TR2, whereas the top end of the third electrode 50 terminates in the middle of the trench TR1.

[0052] As described above, if the internal structure is different between the trench TR1 and the termination trench TR2, a crack CK (see FIG. 17) may occur in the mesa region between the termination trench TR2 and the trench TR1 due to the expansion stress of the fourth electrode 60. In this case, a leakage current occurs, which may result in insufficient long-term reliability.

[0053] 14, the fourth electrode 60 formed in the termination trench TR2 is removed. As a result, the inside of the termination trench TR2 becomes hollow, and no expansion stress is generated in the fourth electrode 60. Therefore, according to this embodiment, it is possible to improve reliability.

[0054] (First Modification) Fig. 18 is a cross-sectional view of a semiconductor device according to a first modification. In Fig. 18, differences from the semiconductor device 1 according to the first embodiment will be mainly described. Components similar to those of the semiconductor device 1 according to the first embodiment will be assigned the same reference numerals, and redundant description will be omitted.

[0055] In the semiconductor device 1a according to this modification, a plurality of termination trenches TR2 are aligned in the X direction. That is, the cell region 100a is surrounded by a plurality of termination trenches TR2.

[0056] Each termination trench TR2 has the hollow portion 61 described in the first embodiment. Therefore, even if a plurality of termination trenches TR2 are provided as in this modification, no expansion stress is generated in the fourth electrode 60. Therefore, in this modification as well, it is possible to improve reliability.

[0057] (Second embodiment) Fig. 19 is a cross-sectional view of a semiconductor device according to a second embodiment. In Fig. 19, differences from the semiconductor device 1 according to the first embodiment will be mainly described. Components similar to those in the semiconductor device 1 according to the first embodiment are given the same reference numerals, and redundant description will be omitted.

[0058] In the semiconductor device 2 according to this embodiment, the internal structure of the termination region 100b is different from that of the first embodiment. In the semiconductor device 1 according to the first embodiment described above, the inside of the termination region 100b is hollow, as shown in FIG.

[0059] 19, in the termination region 100b of the semiconductor device 2 according to this embodiment, a fourth electrode 60 is provided in the lower part of the internal space surrounded by the insulating film 51. Furthermore, an insulating film 41 is provided in the upper part of this internal space, i.e., on the fourth electrode 60.

[0060] To make the internal structure between the trench TR1 and the termination trench TR2 the same, it is desirable that the positions of the upper and lower ends of the fourth electrode 60 from the upper end of the termination trench TR2 are equal to the positions of the upper and lower ends of the third electrode 50 from the upper end of the trench TR1. In other words, it is desirable that the thickness (length in the Z direction) of the fourth electrode 60 is equal to the thickness (length in the Z direction) of the third electrode 50.

[0061] 20 to 22, a method for manufacturing the semiconductor device 2 according to this embodiment will be described below, focusing on the differences from the first embodiment.

[0062] In this embodiment, the steps from the step of forming the trench TR1 and the termination trench TR2 (see FIG. 2) to the step of forming the insulating film 41 in the trench TR1 (see FIG. 12) are the same as those in the first embodiment, and therefore the description will be omitted.

[0063] 20 , in this embodiment, the insulating film 41 and the insulating film 51 formed on the termination trench TR2 are etched, and part of the fourth electrode 60 is also etched. At this time, the thickness of the fourth electrode 60 remaining after etching is approximately equal to the thickness of the third electrode 50.

[0064] 21, an insulating film 41 is formed in the termination trench TR2. The insulating film 41 can be formed by CVD (Chemical Vapor Deposition) using, for example, non-doped BPSG.

[0065] 19, a fourth semiconductor layer 14 is formed in the second semiconductor layer 12 in the same manner as in the first embodiment, and then a first electrode 20 and a second electrode 30 are formed. This completes the semiconductor device 2 shown in FIG.

[0066] In the embodiment described above, the fourth electrode 60 is provided in the termination trench TR2, but the thickness of this fourth electrode 60 is approximately the same as the thickness of the third electrode 50 formed in the trench TR1. Furthermore, in the termination trench TR2, the insulating film 41 is provided on the fourth electrode 60, whereas in the trench TR1, the insulating film 41 is provided on the third electrode 50.

[0067] As described above, the internal structures of the termination trench TR2 and the trench TR1 are similar to each other, which reduces the expansion stress of the fourth electrode 60. Therefore, in this embodiment as well, it is possible to improve reliability.

[0068] (Second Modification) Fig. 22 is a cross-sectional view of a semiconductor device according to a second modification. In Fig. 22, differences from the semiconductor device 2 according to the second embodiment will be mainly described. Components similar to those of the semiconductor device 2 according to the second embodiment will be given the same reference numerals, and redundant description will be omitted.

[0069] In the semiconductor device 2a according to this modification, a plurality of termination trenches TR2 are aligned in the X direction. That is, the cell region 100a is surrounded by a plurality of termination trenches TR2.

[0070] Each termination trench TR2 has a fourth electrode 60 and an insulating film 41, similar to the second embodiment. The shape, dimensions, and arrangement of the fourth electrode 60 in the termination trench TR2 are substantially the same as the shape, dimensions, and arrangement of the third electrode 50 in the trench TR1. In addition, the insulating film 41 is formed on the fourth electrode 60 in the termination trench TR2, and the insulating film 41 is formed on the third electrode 50 in the trench TR1. Therefore, even when multiple termination trenches TR2 are provided as in this modification, the expansion stress of the fourth electrode 60 is alleviated. Therefore, this modification also makes it possible to improve reliability.

[0071] (Third embodiment) Fig. 23 is a cross-sectional view of a semiconductor device according to a third embodiment. In Fig. 23, differences from the semiconductor device 2 according to the second embodiment will be mainly described. Components similar to those of the semiconductor device 2 according to the second embodiment will be given the same reference numerals, and redundant description will be omitted.

[0072] In the semiconductor device 3 according to this embodiment, the internal structure of the termination trench TR2 is different from that of the second embodiment. In the semiconductor device 2 according to the second embodiment described above, as shown in Fig. 19 , a fourth electrode 60 and an insulating film 41 covering the fourth electrode 60 are formed in the internal space surrounded by the insulating film 51 in the termination trench TR2.

[0073] In contrast to this, in the termination trench TR2 of the semiconductor device 3 according to this embodiment, as shown in FIG. 23, the internal space surrounded by the insulating film 51 is filled with the fourth electrode 60, and the insulating film 41 is not formed.

[0074] In the second embodiment, the fourth electrode 60 and the third electrode 50 are made of polysilicon containing impurities, and the concentration of the impurities is the same between the fourth electrode 60 and the third electrode 50. On the other hand, in the present embodiment, the concentration of the impurities contained in the fourth electrode 60 is lower than the concentration of the impurities contained in the third electrode 50. For example, the fourth electrode 60 may be made of undoped polysilicon that does not contain impurities.

[0075] A method for manufacturing the semiconductor device 3 according to this embodiment will be described below with reference to Fig. 24. Here, the differences from the second embodiment will be mainly described.

[0076] In this embodiment, in the step of forming the third electrode 50 in the trench TR1 and the fourth electrode 60 in the termination trench TR2 (see FIG. 3), the third electrode 50 and the fourth electrode 60 are made of undoped polysilicon.

[0077] 24, a resist 70 is placed on the fourth electrode 60. Then, for example, phosphorus (P) as an impurity is ion-implanted from above the third electrode 50. At this time, the resist 70 functions as a mask, so that the implantation of phosphorus into the fourth electrode 60 is blocked. Then, an annealing process is performed. As a result, the impurity (phosphorus) is diffused within the third electrode 50.

[0078] The subsequent steps are the same as those in the second embodiment, and therefore will not be described again. However, in this embodiment, the step of etching a part of the fourth electrode 60 (see FIG. 20) is not performed.

[0079] In the semiconductor device 3 according to the present embodiment described above, the termination trench TR2 is provided with a fourth electrode 60. If the concentration of impurities (phosphorus) contained in the fourth electrode 60 is high, the accelerated oxidation of the fourth electrode 60 is promoted. As a result, the expansion stress of the fourth electrode 60 increases.

[0080] However, in this embodiment, the concentration of impurities contained in the fourth electrode 60 is set lower than the concentration of impurities contained in the third electrode 50. Therefore, accelerated oxidation of the fourth electrode 60 is suppressed compared to the third electrode 50, and the expansion stress of the fourth electrode 60 is alleviated. Therefore, in this embodiment as well, it is possible to improve reliability.

[0081] (Third Modification) Fig. 25 is a cross-sectional view of a semiconductor device according to a third modification. In Fig. 25, differences from the semiconductor device 3 according to the third embodiment will be mainly described. Components similar to those of the semiconductor device 3 according to the third embodiment will be assigned the same reference numerals, and redundant description will be omitted.

[0082] In the semiconductor device 3a according to this modification, a plurality of termination trenches TR2 are arranged side by side in the X direction. That is, the cell region 100a is surrounded by a plurality of termination trenches TR2 in a multi-layered manner.

[0083] Each termination trench TR2 has a fourth electrode 60, similar to the third embodiment. The impurity concentration of the fourth electrode 60 provided in each termination trench TR2 is lower than the impurity concentration of the third electrode 50 provided in the trench TR1. Therefore, even when multiple termination trenches TR2 are provided as in this modification, the expansion stress of the fourth electrode 60 is alleviated. Therefore, this modification also makes it possible to improve reliability.

[0084] (Fourth embodiment) Fig. 26 is a cross-sectional view of a semiconductor device according to a fourth embodiment. In Fig. 26, differences from the semiconductor device 1 according to the first embodiment will be mainly described. Components similar to those of the semiconductor device 1 according to the first embodiment are given the same reference numerals, and redundant description will be omitted.

[0085] In the semiconductor device 4 according to this embodiment, the internal structure of the termination trench TR2 is different from that of the first embodiment. In the semiconductor device 1 according to the first embodiment described above, the fourth electrode 60 is not provided in the internal space surrounded by the insulating film 51, but a hollow portion 61 is provided.

[0086] In contrast, in the termination trench TR2 of the semiconductor device 4 according to this embodiment, as shown in FIG. 26 , both a fourth electrode 60 and a hollow portion 61 are provided in the internal space surrounded by the insulating film 51. The fourth electrode 60 is provided along the inner surface of the insulating film 51. The fourth electrode 60 is also electrically connected to the third electrode 50 of the cell region 100a. The hollow portion 61 is surrounded by the fourth electrode 60.

[0087] Furthermore, in the semiconductor device 4 according to this embodiment, the width W2 corresponding to the length of the termination trench TR2 in the X direction is wider than the width W1 corresponding to the length of the trench TR1 in the X direction. In other words, the width of the termination insulating film is wider than the width of the adjacent insulating film.

[0088] 27 to 30, a method for manufacturing the semiconductor device 4 according to this embodiment will be described below. Here, the description will focus on steps that are different from the method for manufacturing the semiconductor device 1 according to the first embodiment described above.

[0089] 27, an insulating film 51 is formed on the inner surface of each of the trench TR1 and the termination trench TR2. At this time, the trench TR1 and the termination trench TR2 are each opened so that the width W2 is wider than the width W1. That is, the opening diameter of the termination trench TR2 is larger than the opening diameter of the trench TR1.

[0090] 28, a third electrode 50 is formed in the trench TR1, and a fourth electrode 60 is formed in the termination trench TR2. Subsequently, impurities such as phosphorus (P) are implanted into the surface layers S of the third electrode 50 and the fourth electrode 60. As a result, the surface layer S has a high impurity concentration.

[0091] The third electrode 50 and the fourth electrode 60 can be formed by depositing polysilicon in each trench using, for example, CVD. Since width W2 is greater than width W1, the internal capacitance of the termination trench TR2 is greater than the internal capacitance of trench TR1. As a result, when the same amount of polysilicon as trench TR1 is filled, multiple tiny voids 80 are generated in the termination trench TR2.

[0092] 29, the third electrode 50 and the fourth electrode 60 are partially etched by, for example, CDE. At this time, in the termination trench TR2, the voids 80 are connected to each other to form slits. As a result, the fourth electrode 60 remains along the inner surface of the insulating film 51.

[0093] 30 , the polysilicon contained in the third electrode 50 and the fourth electrode 60 is oxidized, and as a result, the upper surfaces of the third electrode 50 and the fourth electrode 60 are covered with an insulating film 51, which is an oxide film. At this time, the surface layer S of the fourth electrode 60 has a high impurity concentration as described above. Therefore, the upper opening of the termination trench TR2 is blocked by the insulating film 51 due to the accelerated oxidation. The subsequent steps are the same as those in the first embodiment, and therefore will not be described.

[0094] According to the present embodiment described above, the fourth electrode 60 is formed inside the termination trench TR2, and the hollow portion 61 also exists therein. This relieves the expansion stress of the fourth electrode 60, thereby improving reliability as in the first embodiment.

[0095] Additionally, in this embodiment, the fourth electrode 60 provided inside the termination trench TR2 is electrically connected to the third electrode 50 in the cell region 100a, which makes it possible to maintain the breakdown voltage in the termination region 100b.

[0096] (Fourth Modification) Fig. 31 is a cross-sectional view of a semiconductor device according to a fourth modification. In Fig. 31, differences from the semiconductor device 4 according to the fourth embodiment will be mainly described. Components similar to those of the semiconductor device 4 according to the fourth embodiment will be assigned the same reference numerals, and redundant description will be omitted.

[0097] In the semiconductor device 4a according to this modification, a plurality of termination trenches TR2 are aligned in the X direction. That is, the cell region 100a is surrounded by a plurality of termination trenches TR2 in a multi-layered manner.

[0098] Each termination trench TR2 has a fourth electrode 60 and a hollow portion 61, similar to the fourth embodiment. Therefore, even when multiple termination trenches TR2 are provided as in this modification, the expansion stress of the fourth electrode 60 is alleviated. Therefore, this modification also makes it possible to improve reliability. Furthermore, in this modification, the fourth electrode 60 is also electrically connected to the third electrode 50 in the cell region 100a. Therefore, it is possible to maintain the breakdown voltage in the termination region 100b.

[0099] (Fifth embodiment) Fig. 32 is a cross-sectional view of a semiconductor device according to the fifth embodiment. In Fig. 32, differences from the semiconductor device 4 according to the fourth embodiment will be mainly described. Components similar to those in the semiconductor device 4 according to the fourth embodiment are given the same reference numerals, and redundant description will be omitted.

[0100] In the semiconductor device 5 according to the first embodiment described above, the cross-sectional shape of the insulating film 51 in the XZ plane is rectangular. In contrast, in the semiconductor device 5 according to this embodiment, the cross-sectional shape of the insulating film 51 is inversely tapered, as shown in Fig. 32. That is, the width of the upper end of the insulating film 51 is narrower than the width of the lower end.

[0101] In the semiconductor device 5 configured as described above, similarly to the fourth embodiment, the termination trench TR2 is provided with a fourth electrode 60 and a hollow portion 61. This makes it possible to improve reliability by alleviating stress and ensure a breakdown voltage in the termination region 100b.

[0102] The semiconductor device 5 according to this embodiment can be manufactured using the same manufacturing process as the semiconductor device 4 according to the fourth embodiment. However, the termination trench TR2 is formed in an inversely tapered shape, with the width of the upper end being smaller than the width of the lower end. In this case, the upper opening width of the termination trench TR2 is narrower than in the fourth embodiment. Therefore, even if impurities are not implanted into the surface layer S to promote accelerated oxidation, the upper opening width of the termination trench TR2 can be easily blocked with the insulating film 51 in the step of oxidizing the fourth electrode 60.

[0103] Therefore, according to this embodiment, the step of implanting impurities into the surface layer S is not necessary, and the manufacturing time can be shortened.

[0104] (Fifth Modification) Fig. 33 is a cross-sectional view of a semiconductor device according to a fifth modification. In Fig. 33, differences from the semiconductor device 5 according to the fifth embodiment will be mainly described. Components similar to those in the semiconductor device 5 according to the fifth embodiment will be assigned the same reference numerals, and redundant description will be omitted.

[0105] In the semiconductor device 5a according to this modification, a plurality of termination trenches TR2 are arranged in the X direction. That is, the cell region 100a is surrounded by a plurality of termination trenches TR2 in a multi-layered manner.

[0106] Each termination trench TR2 has a fourth electrode 60 and a hollow portion 61, similar to the fifth embodiment. The fourth electrode 60 is electrically connected to the third electrode 50 in the cell region 100a. Therefore, in this modification as well, the expansion stress of the fourth electrode 60 is alleviated. Therefore, in this modification as well, it is possible to improve reliability by alleviating stress and ensure the breakdown voltage in the termination region 100b.

[0107] Also in this modification, the insulating film 51 is formed in an inverse tapered shape. This makes it easier to close the upper opening width of the termination trench TR2 with the insulating film 51, eliminating the need for a step of implanting impurities into the surface layer S. This makes it possible to shorten the manufacturing time.

[0108] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0109] 1, 1a: semiconductor device 2, 2a: Semiconductor device 3, 3a: Semiconductor device 10: Semiconductor Department 11: First semiconductor layer 12: Second semiconductor layer 13: Third semiconductor layer 14: Fourth semiconductor layer 15: Fifth semiconductor layer 20: 1st electrode 30: 2nd electrode 40: Control electrode 40A: First control section 40B: Second control section 41: insulating film 50: 3rd electrode 51: insulating film 52: insulating film 60: 4th electrode 61:Hollow part 70: Resist TR1: Trench TR2: Termination trench 100a: Cell area 100b: Termination area

Claims

1. a semiconductor portion having a cell region and a termination region provided outside the cell region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on the front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulating films arranged in a direction from the cell region toward the termination region; a third electrode provided in the semiconductor portion with a second insulating film interposed between the third electrode and the control electrode; Equipped with a hollow portion is provided inside a termination insulating film, of the plurality of first insulating films, that is provided closer to the termination region than the control electrode.

2. 2. The semiconductor device according to claim 1, wherein a distance between said termination insulating film and an adjacent insulating film adjacent to said termination insulating film among said plurality of first insulating films is smaller than a distance between said first insulating films.

3. The semiconductor device according to claim 1 , wherein a lower end position of said hollow portion is the same as a lower end position of said third electrode.

4. a semiconductor portion having a cell region and a termination region provided outside the cell region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on the front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulating films arranged in a direction from the cell region toward the termination region; a third electrode provided in the semiconductor portion with a second insulating film interposed between the third electrode and the control electrode; Equipped with a fourth electrode having the same thickness as the third electrode is provided in a termination insulating film provided on the termination region side of the control electrode among the plurality of first insulating films, and the second insulating film is provided on the fourth electrode.

5. The semiconductor device according to claim 4 , wherein the material of said fourth electrode is the same as the material of said third electrode.

6. 5. The semiconductor device according to claim 4, wherein the material of said second insulating film is BPSG (Boron Phosphorus Silicon Glass).

7. 5. The semiconductor device according to claim 1, wherein a plurality of said termination insulating films are provided.

8. The semiconductor portion is a first semiconductor layer provided with the trench and a termination insulating film; a second semiconductor layer provided on the first semiconductor layer; a third semiconductor layer provided on the second semiconductor layer; a fourth semiconductor layer connected to the second electrode within the second semiconductor layer; a fifth semiconductor layer provided between the first semiconductor layer and the first electrode; The semiconductor device according to claim 1 or 4, comprising:

9. The semiconductor device according to claim 8 , wherein the third semiconductor layer is not present in the termination region.

10. 5. The semiconductor device according to claim 1, wherein the third electrode is electrically connected to the second electrode.

11. a semiconductor portion having a cell region and a termination region provided outside the cell region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on the front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulating films arranged in a direction from the cell region toward the termination region; a third electrode provided in the semiconductor portion with a second insulating film interposed between the third electrode and the control electrode, a fourth electrode is provided in a termination insulating film provided closer to the termination region than the control electrode, among the plurality of first insulating films; a concentration of the impurity contained in the fourth electrode being lower than a concentration of the impurity contained in the third electrode;

12. The semiconductor device according to claim 11 , wherein the material of said fourth electrode is undoped polysilicon.

13. The semiconductor device according to claim 1 , further comprising a fourth electrode surrounding said hollow portion inside said termination insulating film.

14. 14. The semiconductor device according to claim 13, wherein the width of said termination insulating film is wider than the width of an adjacent insulating film, among said plurality of first insulating films, that is adjacent to said termination insulating film.

15. The semiconductor device according to claim 13 , wherein the fourth electrode is electrically connected to the third electrode in the cell region.

16. The semiconductor device according to claim 13 , wherein the termination insulating film has a reverse tapered cross section.

17. The semiconductor device according to claim 13 , wherein a plurality of said termination insulating films are provided.

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