Self-adaptive multi-conversion gain pixel

Abstract

To provide designs of multi-conversion gain pixels for capturing light on an image sensor.SOLUTION: Various structures for implementation of selective conversion gain circuitry in pixel circuits are disclosed. The conversion gain selection circuitry may include conversion gain selection gates that allow selection between full well capacity and partial well capacities in a floating diffusion region. Additional conversion gain selection circuit gates that are coupled to gate inputs of gates over the floating diffusion region may allow column-wise and row-wise control of the selection of the conversion gain. Implementing column-wise and row-wise control provides independent selection of the conversion gain for various pixel circuits across an image sensor. Additional circuitry and techniques are described for determining the selection of conversion gain for readouts of certain photodiodes based on readout signals from previous photodiodes.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 651,338, filed May 23, 2024, entitled "Self-Adaptive Multi-Conversion Gain Pixel," the disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002] The present disclosure relates generally to image sensors, and more particularly to multi-conversion gain pixel designs for capturing light onto an image sensor.

[0003] Image capture devices such as cameras are widely used in various electronic devices, such as mobile devices (e.g., smartphones, tablets, laptops, etc.), robotic equipment, or security surveillance devices, among others. An image capture device may include an image sensor having multiple light-gathering pixels. The pixels may include photodiodes. The image capture device can capture light from the environment and pass the light to the image sensor. When exposed to light, the photodiodes of the pixels can accumulate photoelectrons. Upon readout, the photoelectrons can be transferred out of the photodiodes to generate an analog image signal. Certain image sensors are CMOS image sensors with dual conversion gain (DCG) pixels that read out the photoelectron signal from the photodiode exposure twice using two different conversion gain signals, namely, high conversion gain (HCG) and low conversion gain (LCG), sequentially. These two signals can be processed by various image signal processor circuits that digitize the signals and generate an image. [Brief explanation of the drawings]

[0004] [Figure 1] 1 is a schematic diagram of an example DCG (dual conversion gain) pixel, according to some embodiments.

[0005] [Figure 2A] Shows full well capacity with DCG (dual conversion gain) gate turned on for low conversion gain (LCG).

[0006] [Figure 2B] Partial well capacity with DCG (dual conversion gain) gate turned off for high conversion gain (HCG).

[0007] [Figure 3] FIG. 2 is a schematic diagram of a pixel circuit including a conversion gain selection circuit according to some embodiments.

[0008] [Figure 4] FIG. 1 illustrates a top view of an image sensor implementing row and column logic control of conversion gain selection, according to some embodiments.

[0009] [Figure 5] 1 shows a plan view of a pixel circuit illustrating the readout and conversion gain selection process applied to the pixel circuit according to some embodiments.

[0010] [Figure 6] 1 is a flowchart illustrating an image generation process implementing a pixel circuit readout and conversion gain selection process according to some embodiments.

[0011] [Figure 7] 4A-4C illustrate timing diagrams of transistor operation for a photodiode in a pixel circuit according to some embodiments.

[0012] [Figure 8] FIG. 1 illustrates a schematic diagram of an analog domain implementation of feedback logic for readout and implementation of the conversion gain selection process, according to some embodiments.

[0013] [Figure 9]10 illustrates a timing diagram of a portion of a readout involving an analog feedback circuit, according to some embodiments.

[0014] [Figure 10] FIG. 1 shows a schematic diagram of a digital domain implementation of feedback logic for readout and implementation of the conversion gain selection process, according to some embodiments.

[0015] [Figure 11] 10 illustrates a timing diagram of a portion of a readout involving a digital feedback circuit, according to some embodiments.

[0016] [Figure 12] 10 illustrates various photodiode shutter and integration timing diagrams without dynamic refresh according to some embodiments.

[0017] [Figure 13] 10A-10C show timing diagrams for shuttering and integrating the same various photodiodes with the addition of dynamic refresh, according to some embodiments.

[0018] [Figure 14] 1 is a schematic diagram of a multi-conversion gain (MCG) pixel circuit including a conversion gain selection circuit according to some embodiments.

[0019] [Figure 15] 1 is a schematic diagram of an example image sensor, according to some embodiments.

[0020] [Figure 16] 1 is a flowchart illustrating an example method for processing image signals of an image sensor to generate a digital image, according to some embodiments.

[0021] [Figure 17] 1 illustrates a schematic representation of an example device that may include an image capture device (e.g., a camera) having an image sensor, according to some embodiments.

[0022] [Figure 18] 1 is a schematic block diagram of an example computing device that may include or host an embodiment of an image capture device (e.g., a camera) having an image sensor, according to some embodiments.

[0023] This specification includes references to "one embodiment" or "an embodiment." The phrases "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0024] "Comprising." This term is open-ended. As used in the following claims, this term does not exclude additional structures or steps. Consider a claim that recites "an apparatus comprising one or more processor units...." Such a claim does not exclude the apparatus from including additional components (e.g., a network interface unit, graphics circuitry, etc.).

[0025] "Configured to." Various units, circuits, or other components may be described or claimed as being "configured to" perform a task or tasks. In this context, "configured" is used to connote structure by indicating that the unit / circuit / component includes structure (e.g., a circuit) that performs that task or tasks during operation. In that way, a unit / circuit / component can be said to be configured to perform a task even when the specified unit / circuit / component is not currently operational (e.g., not turned on). A unit / circuit / component used with the phrase "configured to" includes hardware, e.g., a circuit, memory that stores executable program instructions to perform an operation, etc. A statement that a unit / circuit / component is "configured to" perform one or more tasks expressly intends that 35 U.S.C. § 112(f) will not be invoked with respect to that unit / circuit / component. Additionally, "configured to" can include general-purpose structure (e.g., general-purpose circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to operate in a manner capable of performing the task(s) in question. "Configured to" may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) adapted to perform or execute one or more tasks.

[0026] "first," "second," etc. As used herein, these terms are used as indicators of the nouns that follow and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, a buffer circuit may be described herein as performing write operations on "first" and "second" values. The terms "first" and "second" do not necessarily imply that the first value must be written before the second value.

[0027] "Based on." As used herein, this term is used to describe one or more factors that influence a decision. This term does not exclude additional factors that may influence the decision. That is, the decision may be based solely on those factors, or at least in part on those factors. Consider the phrase "determining A based on B." In this case, B is a factor that influences the decision on A, but such a phrase does not exclude that the decision on A is also based on C. In other examples, A may be determined solely on B.

[0028] In this specification, terms such as "first," "second," etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact, without departing from the intended scope. Although a first contact and a second contact are both contacts, they are not the same contact.

[0029] The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Also, as used herein, the term "and / or" should be understood to refer to and include any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] As used herein, the term "if" can be interpreted to mean "when," "upon," "in response to determining," or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (a stated condition or event) is detected" can be interpreted to mean "upon determining," "in response to determining," "upon detecting (the stated condition or event)," or "in response to detecting (the stated condition or event)," depending on the context. DETAILED DESCRIPTION OF THE INVENTION

[0031] Various embodiments described herein relate to CMOS (Complementary Metal Oxide Semiconductor) image sensors. In certain embodiments, the CMOS image sensor includes a dual conversion gain (DCG) pixel or a multiple conversion gain (MCG) pixel. DCG and MCG pixels are often used in low-noise, high dynamic range (HDR) CMOS image sensor devices. DCG pixels can read out photoelectron signals at two different gains: a high conversion gain (HCG) or a low conversion gain (LCG). MCG pixels can read out photoelectron signals at three or more different gains (e.g., an LCG and at least two HCGs).

[0032] 1 is a schematic diagram of an example DCG (dual conversion gain) pixel, according to some embodiments. In the illustrated embodiment, the DCG pixel 100 includes a photodiode (PD) 110. In certain embodiments, the DCG pixel 100 includes a transfer gate (TG) transistor 120, a floating diffusion (FD) region 130, a source follower (SF) transistor 140, a row select (RS) gate transistor 150, a reset voltage (VDD) 160, a dual conversion gain (DCG) transistor 170, a reset gate (RST) transistor 180, and an output (Vout) 190.

[0033] In various embodiments, the TG 120 may be disposed within the DCG pixel 100 to switch between a mode of maintaining photoelectrons in the PD 110 (e.g., accumulating photoelectrons in the photodiode) and a mode of discharging (e.g., transferring) photoelectrons from the PD 110 to the FD 130. For example, during readout, the TG 120 is turned on to couple the PD 110 to the FD 130, and photoelectrons may be transferred from the PD to the FD. The FD 130 may have a capacitance, and the transfer of photoelectrons to the FD 130 causes a current to flow through the capacitance, generating an analog voltage. The output 190 is coupled to the FD 130 through the SF 140 and the RA 150. The RS 150 may turn the output 190 on or off based on a row selection (e.g., under a control signal from a row logic circuit). The voltage of the FD 130 may be accessed and sampled through the output 190 when the RS 150 is turned on. RST 180 can be used to turn on / off the reset mode of DCG pixel 100. For example, turning on RST 180 while DCG 170 is turned on resets FD 130 to VDD 160. The various operations of the gates / transistors within DCG pixel 100 can be controlled by row logic or other external circuitry coupled to the DCG pixel.

[0034] In the illustrated embodiment, DCG 170 divides FD 130 into two portions: FD1 130A on a first side of DCG 170 and FD2 130B on a second side of DCG 170 (and between DCG 170 and RST 180). During operation of DCG pixel 100, turning DCG 170 on and off changes the well capacity of FD 130, switching it between LCG (full well capacity, including both FD1 130A and FD2 130B) and HCG (partial well capacity, FD1 130A only). For example, turning DCG 170 on enables LCG (full well capacity), and turning it off enables HCG (partial well capacity).

[0035] 2A and 2B illustrate the difference in well capacity between LCG and HCG. FIG. 2A shows full well capacity with DCG 170 turned on for LCG. In the illustrated embodiment, DCG 170 is turned on, lowering the barrier between FD1 130A and FD2 130B, allowing photoelectrons (e.g., "signal e") from PD 110 to transfer through TG 120 to the full well capacity of FD 130 (e.g., both FD1 130A and FD2 130B, along with the portion of FD 130 under DCG 170). FIG. 2B shows partial well capacity with DCG 170 turned off for HCG. In the illustrated embodiment, DCG 170 is turned off, which creates a barrier between FD1 130A and FD2 130B, and photoelectrons from PD 110 (e.g., "signal e-") transfer only to the partial well capacity of FD1 130A through TG 120. Thus, photoelectrons do not transfer to FD2 130B or to the portion of FD 130 below DCG 170. If photoelectrons transfer only to FD1 130A, the signal will be relatively high (as indicated by the vertical size of the shaded portion of FD1 130A corresponding to the potential).

[0036] A relatively high conversion gain (e.g., HCG) helps reduce the input-referred read noise of the image sensor due to a relatively high signal. However, a relatively high conversion gain utilizes a well capacity that is less than the full well capacity (FWC) of the floating diffusion (FD) region utilized at a lower conversion gain (as shown in FIGS. 2A and 2B). Reducing the well capacity can reduce the dynamic range of the pixel. Therefore, DCG / MCG pixels are implemented to overcome some of the trade-offs between using HCG and LCG by enabling both modes of operation. HCG mode can be useful in relatively dim lighting conditions to reduce read noise at low signal levels in the dark. LCG mode can be useful in relatively bright lighting conditions to improve FWC.

[0037] For DCG pixels, both the HCG signal and the LCG signal are typically read out because the lighting conditions are not known prior to reading out the DCG pixel signals. For example, the HCG signal and the LCG signal may be read out sequentially from the DCG pixel. For MCG pixels, each of the multiple signals may be read out sequentially. The multiple signals are then evaluated in post-capture processing to determine the appropriate gain to implement to generate the final image. However, reading out all pixels multiple times for all different conversion gains increases line time, reduces frame rate, and increases power consumption.

[0038] To address these current challenges with multiple readouts in DCG / MCG pixels, the present disclosure contemplates embodiments that implement a circuit architecture in DCG / MCG pixels that allows a signal readout of a pixel to be used to determine the conversion gain in a subsequent readout of nearby (e.g., local or adjacent) pixels. Embodiments of the present disclosure implement local control of the conversion gain within the pixel circuit through row and column logical addressing of a conversion gain circuit within the image sensor. For example, the conversion gain circuit may include gates controllable through row and column logical addressing that operate to turn on / off dual conversion gain gates disposed over a floating diffusion region of the pixel circuit, as described herein.

[0039] The row and column logic control implementation of the conversion gain circuit may be combined with a control logic feedback mechanism at the image sensor level to allow a pixel's conversion gain to be determined based on a signal readout from a local (e.g., neighboring) pixel. In various embodiments, the pixel's conversion gain is determined based on a signal value readout from a pixel of the same type (e.g., a pixel of the same color) that is local (e.g., nearby or adjacent) to the pixel. For example, for a DCG pixel, the signal value readout from the local pixel of the same type may determine whether LCG or HCG is implemented for the DCG pixel by evaluating the signal value readout from the local pixel against a predetermined threshold between LCG and HCG. The control logic feedback mechanism of the present disclosure includes embodiments implemented in either the analog domain or the digital domain associated with the image sensor. Determining a pixel's conversion gain based on a signal readout from a local pixel allows the pixel to be readout using only a single conversion gain, and each pixel in the image sensor requires only one frame of data to be readout. Therefore, the architecture and readout scheme of the present disclosure allows DCG / MCG pixels to be readout with only one frame of data per pixel. Thus, the architecture and readout scheme of the present disclosure allows for the benefits of DCG / MCG pixels (e.g., having different gains for different lighting conditions) to be realized without the reduced frame rate or increased power consumption that occurs with typical multi-frame readout schemes for DCG / MCG pixels.

[0040] FIG. 3 is a schematic diagram of a pixel circuit including a conversion gain selection circuit, according to some embodiments. In the illustrated embodiment, pixel circuit 300 includes four photodiodes 310A-D. Thus, pixel circuit 300 is an array of four pixels corresponding to the four photodiodes 310A-D. In various embodiments, pixel circuit 300 may be part of a larger pixel array. For example, pixel circuit 300 may be part of a Quadra color filter array (CFA) including three sets of different color pixels (e.g., four red (R) pixels, eight green (G) pixels, and four blue (B) pixels) for a total of 16 pixels. An example Quadra CFA is shown in FIG. 4 and described in more detail below.

[0041] In certain embodiments, the photodiodes 310A-D are photodiodes of the same color. Thus, the photodiodes 310A-D can accumulate photoelectrons when exposed to light of the same color spectrum. As an example, in a quadra-CFA such as that shown in FIG. 4, the photodiodes 310A-D may be green light spectrum photodiodes. Note that although the pixel circuit 300 is shown with four photodiodes 310A-D connected to a single floating diffusion region (FD 330), other embodiments may be contemplated in which the pixel circuit includes fewer or more photodiodes. For example, in some exemplary embodiments, the pixel circuit may include only one photodiode coupled to a floating diffusion region.

[0042] In various embodiments, photodiodes 310A-D may have corresponding target gates (TG) 320A-D. Having an individual target gate associated with each photodiode allows the accumulated photoelectrons in each photodiode to be read out independently by controlling the operation of the target gate. For example, the readout of photodiode 310A is controlled by the operation of TG 320A, which, when turned on, allows the transfer of accumulated photoelectrons from photodiode 310A to a floating diffusion region (e.g., FD node 330).

[0043] In the illustrated embodiment of pixel circuit 300, TGs 320A-D are coupled to a floating diffusion (FD) region at FD node 330. FD node 330 is further coupled to a source follower (SF) transistor 340, a row select (RS) gate transistor 350, a reset voltage (VDD) 380, and an output (Vout) 390. Similar to pixel 100 shown in FIG. 1, pixel circuit 300 has a floating diffusion region (represented by FD node 330) separated into a first portion FD1 330A and a second portion FD2 330B by a conversion gain select (CGS) gate (e.g., CGS1 360). The source of CGS1 360 is coupled to FD node 330, corresponding the source to first portion FD1 330A and the drain of CGS1 360 to second portion FD2 330B. The drain of CGS1 360 is in turn coupled to a reset gate (RST) 370 and a reset voltage (VDD) 380 .

[0044] In certain embodiments, the pixel circuit 300 includes a second conversion gain select (CGS) gate, CGS2 362. The source of CGS2 362 is coupled to the gate input of CGS1 360, allowing CGS2 362 to control the operation of CGS1 360 (e.g., turn it on / off). CGS1 360 and CGS2 362 may together form a conversion gain select circuit, which operates to control the gain of the pixel circuit 300 by controlling the well capacity of the floating diffusion region. For example, when CGS1 360 is turned on, the well capacity of the floating diffusion region is a full well capacity (FWC) that includes both the first portion FD1 330A and the second portion FD2 330B, and the pixel circuit 300 has a low conversion gain (LCG). When CGS1 360 is turned off, the well capacity is reduced to include only the first portion FD1 330A, and the pixel circuit 300 has a high conversion gain (HCG).

[0045] In various embodiments, a gate input of CGS2 362 is coupled to row logic control signal CGSr 364, and a drain of CGS2 362 is coupled to column logic control signal CGSc 366. Row logic control signal CGSr 364 and column logic control signal CGSc 366 may be coupled to various control logic circuits on the image sensor to provide control of CGS2 362, which in turn controls the operation (e.g., on / off) of CGS 360. For example, if a gate input of CGS2 362 is coupled to row logic control signal CGSr 364, a drain of CGS2 362 is coupled to column logic control signal CGSc 366, and a source of CGS2 362 is coupled to a gate input of CGS1 360, then CGS1 360 may be controlled by the row logic control signal and the column logic control signal according to the logical operations shown in Table I below. [Table 1]

[0046] As shown in Table 1, row logic control signal CGSr 364 and column logic control signal CGSc 366 operate through CGS2 362 with AND gate behavior, with CGS1 360 being turned on only when both control signals are high (e.g., 1). The implementation of CGS2 362 coupled to the gate input of CGS1 360, in combination with row logic control signal CGSr 364 and column logic control signal CGSc 366, provides a control logic scheme for CGS1 360 that is responsive to a combination of row and column logic. Thus, implementing conversion gain selection circuitry within pixel circuit 300 over various pixel circuits on an image sensor allows for individual control of gain across various pixels of the image sensor.

[0047] FIG. 4 is a top view of an image sensor implementing row and column logic control of conversion gain selection, according to some embodiments. In the illustrated embodiment, image sensor 400 includes four pixel circuits 300A-D. As shown in FIG. 4, pixel circuit 300A includes a set of four photodiodes 310A-D (corresponding to the same photodiodes in FIG. 3). Similarly, pixel circuits 300B, 300C, and 300D each include a set of four photodiodes (e.g., individual pixels). In various embodiments, as described above, the combination of pixel circuits 300A-D may be a quadra CFA, where pixel circuits 300A and 300D both include a set of four green pixels, for a total of eight green pixels (e.g., green light spectrum photodiodes). Pixel circuit 300B is a set of four blue pixels (e.g., blue light spectrum photodiodes), and pixel circuit 300C is a set of four red pixels (e.g., red light spectrum photodiodes). Note that the four pixel circuits 300A-D represent one unit of a quadra CFA that may be repeated on any number of units within the image sensor 400.

[0048] In the illustrated embodiment, the image sensor 400 includes various control logic, including, but not limited to, row control logic 410, column control logic 420, readout circuitry 430, and feedback logic 440. In various embodiments, the row control logic 410 outputs row logic control signals, i.e., CGSr 364A and CGSr 364B. As shown in FIG. 4, the CGSr 364A and CGSr 364B pass through a set of pixels along a row of the image sensor 400. In some embodiments, the CGSr 364A and CGSr 364B are row logic control signals corresponding to the row logic control signals for readout of the pixels. For example, the CGSr 364A may correspond to a row select control signal provided to the row select (RS) transistor 350 (shown in FIG. 3) in the pixel circuits 300A and 300B. Thus, the CGSr 364A may have a high value when the row select control signal requests readout of a row of the pixel circuits 300A and 300B. In other embodiments, CGSr 364A and CGSr 364B may be separate row logic control signals that operate independently of the row select control signals.

[0049] In certain embodiments, column control logic 420 outputs column logic control signals, i.e., CGSc 366A and CGSc 366B. As shown in FIG. 4, CGSc 366A and CGSc 366B pass through sets of pixels along columns in image sensor 400. Thus, CGSc 366A and CGSc 366B, in conjunction with CGSr 364A and CGSr 364B, provide independent control of conversion gain selection of sets of pixels (e.g., photodiodes) in the four illustrated pixel circuits 300A-D based on applied row and column control signals. For example, a combination of matrix logic in CGSr 364A and column logic in CGSc 366A may be applied to control conversion gain selection in pixel circuit 300A through operation of the pixel circuit's conversion gain selection circuitry (including CGS1 360) in accordance with the logical operations shown in Table 1 above.

[0050] In various embodiments, application of the column logic control signal CGSc 366 is performed to determine the conversion gain selection of an individual pixel circuit during readout of a row of pixel circuits. For example, as described above, CGSr 364 may correspond to the row logic control signal for readout of a row of pixel circuits. Thus, when CGSr 364 has a high value (e.g., a value of 1 as shown in Table 1 above) for a row of pixel circuits, the pixel circuits in the row are addressed for readout by the row logic control signal. In such a situation, the conversion gain of an individual pixel circuit may be switched (e.g., selected or determined) between LCG and HCG based on the corresponding CGSc 366 value applied to that pixel circuit and in accordance with the logical operation of Table 1. For example, providing a high value to the corresponding CGSc 366 sets the conversion gain for the pixel circuit in LCG, and providing a low value to the corresponding CGSc 366 sets the conversion gain for the pixel circuit in HCG. Thus, implementing column control logic in combination with row control logic allows for individualized control of conversion gain selection based on individually addressing selected columns or rows of pixel circuits within the image sensor.

[0051] 4 performs pixel signal readout of the various pixel circuits 300 in the image sensor 400. In certain embodiments, the readout circuit 430 is a column readout circuit that reads out pixel signal values ​​along a column of pixel circuits in the image sensor 400. Thus, row selection can be performed in combination with the column readout circuit to provide readout of a selected row along a column of pixel circuits in the image sensor 400.

[0052] In various embodiments, the pixel signal readout obtained by the readout circuit 430 is provided to feedback logic 440. In certain embodiments, the feedback logic 440 includes control logic that determines the conversion gain to be set for pixels in the image sensor 400 based on pixel signal readouts from other local (e.g., neighboring) pixels. For example, the feedback logic 440 may provide feedback 442 to the column control logic 420. The feedback 442 may include determining the conversion gain to be applied to the pixel based on the readout pixel signal (e.g., through control of the CGSc 366 for a particular column). Thus, the feedback 442 may be received by the column control logic 420 to determine the value of a particular column logic control signal CGSc 366 to control the conversion gain selection in the pixel circuits along a particular column during readout of the particular row (selected by the row control logic 410).

[0053] FIG. 5 shows a plan view of a pixel circuit illustrating a readout and conversion gain selection process applied to the pixel circuit, according to some embodiments. In the illustrated embodiment, pixel circuit 300A includes a set of four photodiodes (pixels) 310A-D. Pixel circuit 300A may be a 2×2 pixel circuit for a set of common-color photodiodes that are part of a quadra CFA, for example, as described herein. While the readout and conversion gain selection process is shown with respect to a set of four pixels as an example, it should be understood that the readout and conversion gain selection process described herein may be applied to any number of sets of multiple photodiodes (e.g., pixels) in a pixel circuit, or any other set of photodiodes. However, there may be limitations on the types of pixels that may be implemented in the readout and conversion gain selection process of the present disclosure. For example, a conversion selection process based on the readout of a previous pixel in a sequence may be limited to pixels (photodiodes) of the same color, because pixels of different colors may not have pixel readout signals suitable for comparison and conversion gain selection as described herein. However, embodiments may also be contemplated in which pixel read signals from pixels of one color may be implemented (e.g., by applying a normalization or another conversion process to the pixel read signals) in determining the conversion gain selection for pixels of a different color.

[0054] In various embodiments, the readout of the accumulated photoelectrons in each photodiode is performed sequentially. For example, as shown by the arrows in FIG. 5, photodiode 310A may be read out first, followed by photodiode 310B, then photodiode 310C, and then photodiode 310D. This sequential readout process within pixel circuits may be performed pixel circuit by pixel circuit across a row of the image sensor selected by row control logic 410 shown in FIG. 4. This process may then be repeated across additional rows to obtain a complete readout of all, or a selected number of, pixels on the image sensor. As described herein, an image may then be generated from the readout of pixels across the image sensor.

[0055] 6 is a flowchart illustrating an image generation process implementing a readout and conversion gain selection process for pixel circuit 300A, according to some embodiments. In readout and conversion gain selection at 610, photodiode 310A is read out with LCG 510 applied to the pixel circuit for readout of that photodiode (e.g., pixel) (also shown in FIG. 5). At 620, the pixel signal read out from photodiode 310A with LCG 510 is compared to a predetermined threshold to select a conversion gain (CG) for the next photodiode to be read out (e.g., photodiode 310B). For example, the pixel signal read out from photodiode 310A is compared to a predetermined threshold to determine (e.g., select) whether the conversion gain 520 of photodiode 310B is low (L) or high (H) (as shown in FIG. 5). For example, in some contemplated embodiments, the conversion gain may be selected as low (LCG) when the pixel signal readout exceeds (e.g., meets) a predetermined threshold, while the conversion gain is selected as high (HCG) when the pixel signal readout is below (e.g., does not meet) the predetermined threshold. LCG may be selected when the pixel signal readout exceeds the predetermined threshold because such a determination may indicate that the pixel signal readout has a large amount of signal (e.g., accumulated photoelectrons) corresponding to relatively bright lighting conditions suitable for LCG.

[0056] In certain embodiments, the comparison of the signal readout to the predetermined threshold is regulated by feedback logic 440, with the selection of the conversion gain 520 of the photodiode 310B being provided to the column control logic 420 as feedback 442 shown in FIG. 4. In some contemplated embodiments, the feedback logic 440 performs the comparison in the analog domain (as shown and described with respect to FIG. 8). In other contemplated embodiments, the feedback logic 440 performs the comparison in the digital domain (as shown and described with respect to FIG. 9).

[0057] At 630, the next photodiode after the previous photodiode (e.g., photodiode 310B after photodiode 310A) is read out with the conversion gain (e.g., LCG or HCG) selected at 620. If there are additional pixels (e.g., photodiodes) in the set that remain to be read out, at 640 it is determined to update the CG selection based on the readout of the current photodiode (e.g., photodiode 310B). The process then returns to 620 to compare the signal readout of photodiode 310B and determine the conversion gain selection for the next photodiode, i.e., photodiode 310C. These steps are repeated until all photodiodes in the set (e.g., pixel circuit 300A) (except for the first photodiode, which is read out with LCG) have been read out according to the conversion gain selected for that photodiode based on the previous signal readout. 5, photodiode 310B is read out with CG520 (selected as either L or H), photodiode 310C is read out with CG530 (selected as either L or H), and photodiode 310D is read out with CG540 (selected as either L or H). By updating the conversion gain selection of each photodiode in pixel circuit 300A based on the previously read pixel signal, consistency in the selected conversion gain is maintained across pixel circuits, reducing the likelihood of artifacts in the image caused by differences across the image.

[0058] Returning to FIG. 6 , as described herein, after the photodiodes in a set of photodiodes (e.g., pixel circuits) are read out, the readout may move on to another set of photodiodes in the image sensor. In some embodiments, the next set of photodiodes may be photodiodes of a different color or photodiodes spatially separated from the previous set of photodiodes, and the readout and conversion gain selection process for the next set may begin at 610 by again using the LCG for the first photodiode in the set, as shown in FIG. 6 . However, other embodiments may be contemplated in which the readout of the first photodiode in an adjacent set of photodiodes begins by selecting a conversion gain based on the readout from the last photodiode in the previous adjacent set. In any of these embodiments, the process for multiple sets of photodiodes (e.g., sets of pixel circuits) across the image sensor may be repeated until all, or a predetermined number of, sets / pixel circuits have been read out. After collection of all pixel signal readouts has been completed, an image with pixel-by-pixel conversion gain selection may be generated for the image sensor at 650.

[0059] The readout and conversion gain selection process described for the embodiments of Figures 5 and 6 will be further explained with reference to the timing diagram shown in Figure 7. Figure 7 shows a timing diagram of the operation of transistors for the photodiodes in pixel circuit 300A of Figure 5, according to some embodiments. Timing 700 is implemented for a set of four photodiodes 310A-D through the operation of their corresponding transfer gate (TG) transistors TG320A, TG320B, TG320C, and TG320D (shown in Figure 3). TG320A-D have corresponding curves in the timing diagram 700 of Figure 7. As also shown in Figure 3, these four transfer gate (TG) transistors are coupled to reset gate (RST) transistor 370 via CGS1 360 and CGS2 362, which also has a corresponding curve in the timing diagram 700 of Figure 7. As described herein, the operation of CGS1 360 and CGS2 362 is controlled by control signals, CGSr 364 and CGSc 366 (which have corresponding curves in timing 700 of FIG. 7). Note that in the illustrated embodiment, only the readout portion (e.g., readout 710) of timing 700 of pixel circuit 300A for these transistors is shown. Other portions of the pixel circuit's timing (e.g., shuttering, integration, and idle) and the operation of other transistors in the pixel circuit are not shown to simplify the drawing.

[0060] As shown in FIG. 7, pixel circuit 300A is read out by sequentially applying readout pulses to TG 320A, TG 320B, TG 320C, and TG 320D, with corresponding resets between readout pulses via RST 370. Row logic control signal CGSr 364 (e.g., a row select readout signal) is held high during each readout of each transfer gate (TG) 320A-D, as shown by the pulse curves, and then brought low between readouts (e.g., after the corresponding TG is turned off). Additionally, as described above, column logic control signal CGSc 366 is changed to select (e.g., switch) the LCG or HCG applied to the pixel circuit during each photodiode / transfer gate readout. For example, CGSc 366 is high during readout of TG 320A, applying LCG 510 (shown in FIG. 5) as the conversion gain for the pixel circuit during readout. Then, for the readout of TG 320B, CGSc 366 is either High (solid line) or Low (dashed line) to apply LCG or HCG, respectively, for L / H CG 520 based on feedback from the readout of TG 320A, as described herein. Similar logic applies to the CGSc 366 selection for the readouts of TG 320C and L / H CG 530, and TG 320D and L / H CG 540.

[0061] FIG. 8 shows a schematic diagram of an analog domain implementation of feedback logic for implementing the readout and conversion gain selection process, according to some embodiments. In the illustrated embodiment, an analog feedback circuit 800 is coupled to a column of pixel circuits in the image sensor 400 to receive Vout 390 (e.g., the pixel circuit readout signal shown in FIG. 3) and provide CGSc 366 (e.g., a column logic control signal). The analog feedback circuit 800 may be associated with the column control logic 420 and / or feedback logic 440 shown in FIG. 4 to provide a column-by-column analysis of Vout 390 to determine CGSc 366. In various embodiments, as shown in FIG. 8, the analog feedback circuit 800 is coupled between a reference voltage (Vref 802) and a ramp voltage (Vramp 804). The analog feedback circuit 800 is arranged to receive Vout 390 and provide conversion gain comparison / selection in the analog domain before the analog signal is read out by the ADC 810.

[0062] In the illustrated embodiment, the analog feedback circuit 800 includes a comparator 820 and sequential control logic 830. The comparator 820 may provide a comparison of Vout 390 against a predetermined threshold. The predetermined threshold may be, for example, an illumination threshold that distinguishes between when LCG is preferred (e.g., bright lighting conditions) and when HCG is preferred (e.g., dim lighting conditions). The sequential control logic 830 may then provide an appropriate control signal (e.g., either a high value of CGSc 366 for LCG or a low value of CGSc 366 for HCG) in response to the comparison to select the conversion gain as LCG or HCG for the next pixel readout. In some embodiments, the comparator 820 and sequential control logic 830 are part of the feedback logic 440 shown in FIG. 4, and feedback 442 is provided to the column control logic 420 to determine the value of CGSc 366 for the conversion gain selection. In other embodiments, the comparator 820 may be part of the feedback logic 440 and the sequential control logic 830 may be part of the column control logic 420, with feedback 442 provided from the comparator to the sequential control logic to determine the value of CGSc 366.

[0063] FIG. 9 shows a timing diagram of a portion of a readout involving the analog feedback circuit 800, according to some embodiments. In the illustrated embodiment, the timing 900 includes a portion of the timing for reading out a pulse of the transfer gate (TG) 320A corresponding to the photodiode 310A. As shown in FIG. 9, CGSr 364 and CGSc 366 are set high for LCG during the readout of the TG 320A. A comparison 910, as indicated by the vertical dotted line, is performed by the analog feedback circuit 800, which may be part of the feedback logic 440, after conversion of the reset voltage (Vrst) read by the ADC 810 but before conversion of the signal voltage (Vsig) read by the ADC 810. Following the readout and conversion of the signal voltage, feedback 442 may be provided to determine the value of CGSc 366 at the next photodiode / transfer gate readout.

[0064] 8, analog feedback circuit 800 requires a global voltage buffer (e.g., Vref 802) because the comparison and determination of control signals is completed in the analog domain. Implementing a global voltage buffer may increase power consumption for the operation of the image sensor. To reduce the power consumption increase of the readout and conversion gain selection process in the digital domain, various embodiments may be contemplated that implement feedback logic for such processes.

[0065] 10 shows a schematic diagram of a digital domain implementation of feedback logic for implementing the readout and conversion gain selection process, according to some embodiments. In the illustrated embodiment, a digital feedback circuit 1000 is coupled to a column of pixel circuits in the image sensor 400 to receive Vout 390 (e.g., the pixel circuit readout signal shown in FIG. 3) and provide CGSc 366 (e.g., a column logic control signal). The digital feedback circuit 1000 may be associated with the column control logic 420 and / or feedback logic 440 shown in FIG. 4 to provide a column-by-column analysis of Vout 390 to determine CGSc 366. In various embodiments, as shown in FIG. 10, the digital feedback circuit 1000 is coupled to a digital reference (Dref 1002) to provide a basis for comparing the signal output with a reference value.

[0066] In the illustrated embodiment, the digital feedback circuit 1000 includes a digital comparator 1010. The digital comparator 1010 is coupled to the output of the ADC 810 to receive ADC Out 812, which is a digital conversion of Vout 390. Thus, the digital comparator 1010 provides a comparison / selection of the conversion gain in the digital domain after the analog signal is read by the ADC 810. The digital comparator 1010 may provide a comparison of ADC Out 812 against a predetermined threshold. The predetermined threshold may be set, for example, by Dref 1002. In response to the comparison, the digital comparator 1010 may provide an appropriate control signal (e.g., either a High value of CGSc 366 for LCG or a Low value of CGSc 366 for HCG) to select the conversion gain as LCG or HCG for the next pixel readout. 4, and feedback 442 is provided to the column control logic 420 to determine the value of CGSc 366 for conversion gain selection. In other embodiments, the digital comparator 1010 may be part of the column control logic 420.

[0067] FIG. 11 shows a timing diagram of the portion of a readout involving digital feedback circuit 1000, according to some embodiments. In the illustrated embodiment, timing 1100 includes a portion of the timing for readout pulses of transfer gate (TG) 320A corresponding to photodiode 310A. As shown in FIG. 11, CGSr 364 and CGSc 366 are set high for LCG during readout of TG 320A. A comparison 1110 is performed by digital feedback circuit 1000 after conversion of the signal voltage (Vsig) by ADC 810, as indicated by the vertical dotted line. Feedback 442 is then provided to determine the value of CGSc 366 at the next photodiode / transfer gate readout.

[0068] In some contemplated embodiments, dynamic refresh of the pixel circuit may be implemented by utilizing various circuit elements described herein. For example, the LCG readout cycle of the set of photodiodes described above may be utilized to dynamically refresh several photodiodes by turning on the conversion gain select gates during integration and pulsing the transfer gates of those photodiodes simultaneously. Figure 12 shows a timing diagram for shuttering and integrating various photodiodes without dynamic refresh, according to some embodiments. Figure 13 shows a timing diagram for shuttering and integrating the same various photodiodes with the addition of dynamic refresh, according to some embodiments.

[0069] 12, timing 1200 includes shuttering 1210 and integration 1220. During shuttering 1210, RST 370 and CGSc 366 are turned on, while CGSr 364 is pulsed in accordance with each of transfer gates (TG) 320A-D to reset (e.g., drain) the photodiodes corresponding to each transfer gate. While the resetting of TGs 320A-D occurs during shuttering 1210, additional transfer gates (e.g., represented by TG320An and TG320Am) that are the first transfer gates in the set of photodiodes being read out remain off. Note that these transfer gates TG320An and TG320Am correspond to the photodiodes in the set that are first read out using LCG for conversion gain, as described herein, and that these transfer gates / photodiodes are not subject to conversion gain selection based on feedback from the other photodiode readouts.

[0070] Integration 1220 of TG320A-D follows shuttering 1210. During integration 1220, photoelectrons are accumulated in the photodiodes corresponding to TG320A-D. During this time, TG320An and TG320Am are turned on to prevent photoelectrons from accumulating in the corresponding photodiodes. Referring now to FIG. 13, in timing 1300, shuttering 1210 remains unchanged, while integration 1320 varies the timing of CGSr 364 to provide dynamic refreshing of the photodiodes and pixel circuits corresponding to TG320An and TG320Am. Dynamic refreshing is enabled by pulsing CGSr 364 along with CGSc 366, TG320An, and TG320Am. Thus, dynamic refreshing of these photodiodes and pixel circuits is achieved without additional circuitry beyond that shown in this disclosure.

[0071] While embodiments of the present disclosure describe various readout and conversion gain selection implementations for a dual conversion gain (DCG) pixel circuit that selects between low conversion gain (LCG) and high conversion gain (HCG), it should be understood that embodiments of a multi-conversion gain (MCG) pixel circuit are also contemplated by embodiments of the present disclosure. For example, additional floating diffusion portions can be created by adding another conversion gain selection (CGS) circuit gate between the floating diffusion region and the reset transistor, along with additional CGS circuit gates with additional column and row control logic applied to them. In such embodiments, additional column control logic can be added to implement the additional column control logic while utilizing the same or additional row control logic.

[0072] Figure 14 is a schematic diagram of a multi-conversion gain (MCG) pixel circuit including a conversion gain selection circuit according to some embodiments. In the illustrated embodiment, the MCG pixel circuit 1400 includes four photodiodes 310A-D, four transfer gates (TG) 320A-D, a floating diffusion (FD) node 330, a source follower (SF) transistor 340, a row select (RS) transistor 350, a reset (RST) transistor 370, V DD 380, and V OUT 390, as also shown in the illustration of Figure 3. The conversion gain selection (CGS) circuit of Figure 14 includes two first conversion gain selection (CGS) gates, CGS1 360A and CGS1 360B, that separate the floating diffusion region between the FD node 330 and RST 370 into three portions, FD1 330A, FD2 330B, and FD3 330C.

[0073] The CGS of the MCG pixel circuit 1400 further includes two second conversion gain select gates, CGS2 362A and CGS2 362B. The source of CGS2 362A is coupled to the gate input of CGS1 360A, and the source of CGS2 362B is coupled to the gate input of CGS1 360B. The gate inputs of CGS2 362A and CGS2 362B are coupled to CGSr 364 (e.g., a row control logic signal). It should be noted that some embodiments may also be contemplated in which separate row control logic signals are provided to CGS2 362A and CGS2 362B. The drain of CGS2 362A is coupled to a first column control logic signal CGSc 366A, and the drain of CGS2 362B is coupled to a second column control logic signal CGSc 366B. Thus, separate column control logic signals may be provided to CGS2 362A and CGS2 362B for independent operation of the conversion gain selection associated with turning on / off gates CGS1 360A and CGS1 360B.

[0074] FIG. 15 is a schematic diagram of an example image sensor, according to some embodiments. As shown in FIG. 15 , the image sensor 1500 may include a plurality of light-gathering pixels 1502 (e.g., a square PD pixel structure or a split PD pixel structure, as described herein) organized as a pixel array 1520. In some embodiments, the image sensor 1500 may include one or more amplifiers 1504, one or more ADC (analog-to-digital conversion) circuits and memories 1508, and one or more image signal processing circuits 1522. In various embodiments, the image signal processing circuits include data interface circuits. In some embodiments, the image signals of the pixels 1502 of the pixel array 1520 may be read out row by row or column by column (or even pixel by pixel). For illustrative purposes, in this example, the image sensor 1500 may also include a row logic circuit 1524 for providing control signals to perform a row-by-row readout of the pixels 1502. Using row-by-row readout, multiple pixels 1502 in the same row may be read out simultaneously or nearly simultaneously, while multiple pixels 1502 in the same column but in different rows may be read out sequentially, row-by-row.

[0075] In some embodiments, the readout of the image signals of the pixels 1502 may be performed using, for example, one or more readout circuits. For example, at least some of the pixels 1502 may include one or more photodiodes and pixel readout circuits. The photodiodes may generate and store photoelectrons when exposed to light. During readout, under control signals from the row logic circuit 1524, the row select transistor and the source follower transistor may be turned on and emit an analog signal output through the output 1526. The output 1526 may be coupled to a floating diffusion region, which may output an analog output signal having a reset value or a signal value depending on the states of the transfer gate and the reset gate.

[0076] FIG. 16 is a flowchart illustrating an example method for processing an image signal of an image sensor to generate a digital image, according to some embodiments. In FIG. 16 , in some embodiments, photoelectrons accumulate in a photodiode of at least one pixel on an image sensor in response to the at least one pixel being exposed to light, as indicated by block 1602. During readout, these photoelectrons may be transferred out of the photodiode and generate an analog signal output (e.g., an analog voltage output) in the FD region of the pixel, which may be further accessed at the pixel's output. In FIG. 16 , in some embodiments, in block 1604, the pixel provides an analog signal output having a reset value. In block 1606, the pixel provides an analog signal output having a signal value. Then, in block 1608, the reset value and the signal value are converted to a final digital signal value. In various embodiments, the final digital signal value is generated by a combination of an ADC, an SRAM, a digital processing circuit, and a data interface circuit. In block 1610, a digital image is generated from the final digital signal value. For example, the digital processing circuitry and / or the data interface circuitry may generate a digital image from the final digital signal values.

[0077] 17 shows a schematic representation of an example device 1700 that may include an image capture device (e.g., a camera) having an image sensor, according to some embodiments. In some embodiments, device 1700 may be a mobile device and / or a multifunction device. In various embodiments, device 1700 may be any of a variety of types of device, including, but not limited to, a personal computer system, a desktop computer, a laptop, a notebook, a tablet, a slate, a pad, or a netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game console, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device such as a switch, modem, or router, or generally any type of computing or electronic device.

[0078] In some embodiments, device 1700 may include a display system 1702 (e.g., including a display and / or a touch-sensitive surface) and / or one or more cameras 1704. In some non-limiting embodiments, display system 1702 and / or one or more front-facing cameras 1704a may be provided on the front side of device 1700, for example, as shown in FIG. 17 . Additionally or alternatively, one or more rear-facing cameras 1704b may be provided on the rear side of device 1700. In some embodiments comprising multiple cameras 1704, some or all of the cameras may be the same or similar to one another. Additionally or alternatively, some or all of the cameras may be different from one another. In various embodiments, the location(s) and / or configuration(s) of camera(s) 1704 may differ from those shown in FIG. 17 . In various embodiments, camera 1704 includes a lens 1705. An image sensor (eg, image sensor 1700) may receive light that passes through lens 1705 and reaches the image sensor.

[0079] Among other things, device 1700 may include memory 1706 (e.g., with an operating system 1708 and / or application(s) / program instructions 1710), one or more processors and / or controllers 1712 (e.g., with a CPU(s), memory controller(s), display controller(s), and / or camera controller(s), etc.), and / or one or more sensors 1716 (e.g., orientation sensor(s), proximity sensor(s), and / or position sensor(s), etc.). In some embodiments, device 1700 can communicate with one or more other devices and / or services, such as computing device(s) 1718, cloud services 1720, etc., via one or more network(s) 1722. For example, device 1700 may include a network interface that enables device 1700 to transmit data to and receive data from network(s) 1722. Additionally or alternatively, device 1700 may be capable of communicating with other devices via wireless communications using any of a variety of communication standards, protocols, and / or technologies.

[0080] 18 is a schematic block diagram of an example computing device, referred to as computer system 1800, that may include or host an embodiment of an image capture device (e.g., a camera) having an image sensor, according to some embodiments. Additionally, computer system 1800 may implement methods for controlling the operation of the camera and / or for performing image processing of images captured using the camera. In some embodiments, a device (described herein with reference to FIG. 18) may additionally or alternatively include some or all of the functional components of computer system 1800 described herein.

[0081] Computer system 1800 can be configured to perform any or all of the above-described embodiments. In different embodiments, computer system 1800 can be any of a variety of types of devices, including, but not limited to, a personal computer system, a desktop computer, a laptop, a notebook, a tablet, a slate, a pad, or a netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game console, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device such as a switch, modem, or router, or generally any type of computing or electronic device.

[0082] In the illustrated embodiment, computer system 1800 includes one or more processors 1802 coupled to system memory 1804 via an input / output (I / O) interface 1806. Computer system 1800 further includes one or more cameras 1808 coupled to I / O interface 1806. Computer system 1800 further includes a network interface 1810 coupled to I / O interface 1806, and one or more input / output devices 1812, such as a cursor control device 1814, a keyboard 1816, and a display(s) 1818. While in some cases, an embodiment may be implemented using a single instance of computer system 1800, it is contemplated that in other embodiments, multiple such systems, or multiple nodes comprising computer system 1800, may be configured to host different portions or instances of an embodiment. For example, in one embodiment, some elements may be implemented via one or more nodes of computer system 1800 that are different from the nodes implementing other elements.

[0083] In various embodiments, computer system 1800 may be a uniprocessor system including one processor 1802, or a multiprocessor system including multiple processors 1802 (e.g., two, four, eight, or another suitable number). Processor 1802 may be any suitable processor capable of executing instructions. For example, in various embodiments, processor 1802 may be a general-purpose or embedded processor implementing any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, or MIPS ISAs, or any other suitable ISA. Also, in some embodiments, one or more of processors 1802 may include additional types of processors, such as a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or the like. In a multiprocessor system, each of processors 1802 may generally, but not necessarily, implement the same ISA. In some embodiments, computer system 1800 may be implemented as a system-on-a-chip (SoC). For example, in some embodiments, the processor 1802, memory 1804, I / O interface 1806 (e.g., fabric), etc. may be implemented in a single SoC with multiple components integrated on a single chip. For example, the SoC may include multiple CPU cores, a multi-core GPU, a multi-core neural engine, a cache, one or more memories, etc. integrated on a single chip. In some embodiments, the SoC embodiment may implement a reduced instruction set computing (RISC) architecture, or any other suitable architecture.

[0084] The system memory 1804 may be configured to store program instructions 1820 accessible by the processor 1802. In various embodiments, the system memory 1804 may be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), non-volatile / flash-type memory, or any other type of memory. Additionally, existing camera control data 1822 in the memory 1804 may include any of the information or data structures for implementing the techniques described above. In some embodiments, the program instructions 1820 and / or data 1822 may be received, sent, or stored on different types of computer-accessible media, or on similar media separate from the system memory 1804 or the computer system 1800. In various embodiments, some or all of the functionality described herein may be performed via such a computer system 1800.

[0085] In one embodiment, I / O interface 1806 may be configured to coordinate I / O traffic between processor 1802, system memory 1804, and any peripheral devices within the device, including other peripheral interfaces such as network interface 1810 or input / output devices 1812. In some embodiments, I / O interface 1806 may perform any necessary protocol, timing, or other data conversions to convert data signals from one component (e.g., system memory 1804) into a format suitable for use by another component (e.g., processor 1802). In some embodiments, I / O interface 1806 may include support for devices attached via various types of peripheral buses, such as, for example, variants of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard. In some embodiments, the functionality of I / O interface 1806 may be split between two or more separate components, such as, for example, a northbridge and a southbridge. Additionally, in some embodiments, some or all of the functionality of I / O interface 1806 , such as an interface to system memory 1804 , may be incorporated directly into processor 1802 .

[0086] Network interface 1810 may be configured to allow data to be exchanged between computer system 1800 and other devices (e.g., carrier or agent devices) attached to network 1824, or between nodes of computer system 1800. Network 1824, in various embodiments, may include one or more networks, including, but not limited to, a local area network (LAN) (e.g., an Ethernet or enterprise network), a wide area network (WAN) (e.g., the Internet), a wireless data network, some other electronic data network, or some combination thereof. In various embodiments, network interface 1810 may support communication over a wired or wireless general-purpose data network, such as, for example, any suitable type of Ethernet network. It may also support communication over a telecommunications / telephone network, such as an analog voice network or a digital fiber communications network, a storage area network, such as a Fibre Channel SAN, or any other suitable type of network and / or protocol.

[0087] Input / output devices 1812, in some embodiments, may include one or more display terminals, keyboards, keypads, touchpads, scanning devices, voice or optical recognition devices, or any other devices suitable for inputting or accessing data by one or more computer systems 1800. Multiple input / output devices 1812 may be present within computer system 1800 or may be distributed on various nodes of computer system 1800. In some embodiments, similar input / output devices may be separate from computer system 1800 and may interact with one or more nodes of computer system 1800 through wired or wireless connections, such as via network interface 1810.

[0088] Those skilled in the art will appreciate that computer system 1800 is merely exemplary and is not intended to limit the scope of the embodiments. In particular, computer systems and devices may include any combination of hardware or software capable of performing the depicted functions, including computers, network devices, Internet appliances, PDAs, wireless telephones, pagers, etc. Computer system 1800 may also be connected to other devices not shown, or alternatively, may operate as a stand-alone system. Additionally, functionality provided by the illustrated components may, in some embodiments, be combined in fewer components or distributed among additional components. Similarly, in some embodiments, the functionality of some of the illustrated components may not be provided, and / or other additional functionality may be available.

[0089] Those skilled in the art will also understand that while various items are shown as being stored in memory or on storage during use, these items, or portions thereof, may be transferred between memory and other storage devices for purposes of memory management and data integrity. Alternatively, in other embodiments, some or all of the software components may execute in memory on another device and communicate with the illustrated computer system via computer-to-computer communications. Some or all of the system components or data structures may also be stored (e.g., as instructions or structured data) on a computer-accessible medium or portable item to be read by an appropriate drive, various examples of which are described above. In some embodiments, instructions stored on a computer-accessible medium separate from computer system 1800 may be transmitted to computer system 1800 via a transmission medium or signal, such as an electrical, electromagnetic, or digital signal, conveyed over a communications medium, such as a network and / or a wireless link. Various embodiments may further include receiving, sending, or storing instructions and / or data to be executed on a computer-accessible medium in accordance with the preceding description. Generally speaking, a computer-accessible medium may include a non-transitory computer-readable storage medium or memory medium, such as a magnetic medium or an optical medium, e.g., a disk or DVD / CD-ROM, a RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.), a volatile or non-volatile medium, such as a ROM, etc. In some embodiments, a computer-accessible medium may include a transmission medium or a signal, such as an electrical, electromagnetic, or digital signal, conveyed over a communication medium, such as a network and / or a wireless link.

[0090] The methods described herein may, in different embodiments, be implemented in the form of software, hardware, or a combination thereof. In addition, the order of method blocks may be changed, and various elements may be added, reordered, combined, omitted, modified, etc. Various modifications and variations may be made as would be apparent to one of ordinary skill in the art having the benefit of this disclosure. The various embodiments described herein are illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. Thus, for components described herein as singular, multiple versions may be provided. Boundaries between various components, operations, and data stores are somewhat arbitrary, and particular operations are illustrated in the context of specific exemplary configurations. Other allocations of functionality are contemplated and may be included within the scope of the following claims. Finally, structures and functions presented as separate components in exemplary configurations may be implemented as combined structures or components. These and other variations, modifications, additions, and improvements may be included within the scope of the embodiments, as defined by the following claims.

Claims

1. A pixel, A silicon substrate; at least two photodiodes formed on the substrate; a floating diffusion region coupled to the at least two photodiodes; a conversion gain selection circuit coupled to the floating diffusion region, the conversion gain selection circuit configured to determine a conversion gain of the pixel to be a first conversion gain or a second conversion gain, the conversion gain selection circuit comprising: a first gate having a source coupled to a portion of the floating diffusion region, wherein the conversion gain of the pixel is the first conversion gain when the first gate is on and the second conversion gain when the first gate is off; and a second gate having a source coupled to a gate input of the first gate, the second gate configured to control operation of the first gate in response to receiving a first control signal at the gate input of the second gate and a second control signal at the drain of the second gate; Pixel.

2. The pixel of claim 1 , wherein the first conversion gain is a low conversion gain and the second conversion gain is a high conversion gain.

3. The pixel of claim 1 , wherein the second gate is configured to turn on the first gate when the first control signal and the second control signal are both at a high level.

4. The pixel of claim 1 , wherein the second gate is configured to turn off the first gate when the first control signal or the second control signal is at a low level.

5. The pixel of claim 1 , wherein the first control signal is a row logic control signal and the second control signal is a column logic control signal.

6. The pixel of claim 1 , wherein the at least two photodiodes are photodiodes that accumulate photoelectrons when exposed to light of the same color spectrum.

7. 2. The pixel of claim 1, wherein the at least two photodiodes include a first photodiode and a second photodiode that accumulate photoelectrons when exposed to light, and the conversion gain selection circuit is configured to switch the conversion gain between transferring the accumulated photoelectrons from the first photodiode to the floating diffusion region and transferring the accumulated photoelectrons from the second photodiode to the floating diffusion region.

8. a first transfer gate coupled between the first photodiode and the floating diffusion region; a second transfer gate coupled between the second photodiode and the floating diffusion region; The pixel of claim 7 .

9. The pixel of claim 8 , further comprising a reset gate having a source coupled to a drain of the first gate of the conversion gain selection circuit.

10. 10. The pixel of claim 9, wherein the first gate is disposed over the floating diffusion region and divides the floating diffusion region into multiple portions, the portion of the floating diffusion region coupled to the source of the first gate being a first portion of the floating diffusion region, and a second portion of the floating diffusion region coupled to the drain of the first gate and the source of the reset gate.

11. The operation of the first gate comprises: when turned on, accumulated photoelectrons from the at least two photodiodes are transferred to a full well capacity of the floating diffusion region including both the first portion and the second portion; and when turned off, accumulated photoelectrons from the at least two photodiodes are transferred into a partial well capacity of the floating diffusion region including only the first portion. The pixel of claim 10.

12. 1. A system comprising: A pixel device, the pixel comprising: A silicon substrate; a first photodiode formed in the substrate and configured to accumulate photoelectrons upon exposure to light; a second photodiode formed in the substrate and configured to accumulate photoelectrons when exposed to light; a floating diffusion region coupled to the first photodiode and the second photodiode; a first transfer gate coupled between the first photodiode and the floating diffusion region; a second transfer gate coupled between the second photodiode and the floating diffusion region; a pixel device comprising: a conversion gain selection circuit coupled to the floating diffusion region, the conversion gain selection circuit configured to set a conversion gain of the pixel device as a first conversion gain or a second conversion gain in response to one or more control signals from a control logic; and the control logic coupled to the pixel device, the control logic comprising: receiving a readout of a first analog signal output from the pixel device at the first conversion gain, the first analog signal output corresponding to photoelectrons accumulated in the first photodiode; determining a selected conversion gain of the pixel device during readout of a second analog signal output from the pixel device, the second analog signal output corresponding to photoelectrons accumulated in the second photodiode, the selected conversion gain being one of the first conversion gain or the second conversion gain determined based on a value of the first analog signal output; configured to provide the one or more control signals to the conversion gain selection circuit to set the selected conversion gain for the second analog signal output. system.

13. The system of claim 12 , wherein the first conversion gain is a low conversion gain for the pixel device.

14. The conversion gain selection circuit a first gate having a source coupled to a portion of the floating diffusion region, the first gate having the first conversion gain when the first gate is on and the second conversion gain when the first gate is off; a second gate having a source coupled to a gate input of the first gate, the second gate configured to control operation of the first gate in response to receiving a first control signal of the one or more control signals at the gate input of the second gate and a second control signal of the one or more control signals at a drain of the second gate; The system of claim 12.

15. 15. The system of claim 14, wherein the first control signal is a row logic control signal, the second control signal is a column logic control signal, and the second photodiode is in one of a different row or a different column within the pixel device than the first photodiode.

16. 13. The system of claim 12, wherein the control logic is configured to determine the selected conversion gain based on a comparison of the value of the first analog signal output to a predetermined threshold.

17. 17. The system of claim 16, wherein the control logic is configured to perform the comparison of the value of the first analog signal output with the predetermined threshold in the analog domain.

18. 17. The system of claim 16, wherein the control logic is configured to perform the comparison of the value of the first analog signal output with the predetermined threshold in the digital domain.

19. 1. A method comprising: accumulating photoelectrons in a plurality of photodiodes formed in a silicon substrate, the photodiodes being part of a pixel device, by exposing the photodiodes to light; transferring the accumulated photoelectrons in a first photodiode to a floating diffusion region coupled to the plurality of photodiodes through a first transfer gate coupled between the first photodiode and the floating diffusion region; receiving, in control logic coupled to the pixel device, a readout of a first analog signal output from the floating diffusion region at a first conversion gain, the first analog signal output corresponding to the photoelectrons accumulated in the first photodiode; determining, in the control logic, during readout of a second analog signal output from the pixel device, a selected conversion gain of the pixel device, the selected conversion gain being one of the first conversion gain or a second conversion gain determined based on a value of the first analog signal output; providing, by the control logic, row logic control signals and column logic control signals to a conversion gain selection circuit, the conversion gain selection circuit including a first gate having a source coupled to a portion of the floating diffusion region and a second gate having a source coupled to a gate input of the first gate, the row logic control signal being received at a gate input of the second gate and the column logic control signal being received at a drain of the second gate, to set the selected conversion gain for the second analog signal output; transferring the accumulated photoelectrons in the second photodiode to the floating diffusion region through a second transfer gate, the second transfer gate being coupled between the second photodiode and the floating diffusion region; receiving, in the control logic, a readout of the second analog signal output from the floating diffusion region at the selected conversion gain, the second analog signal output corresponding to photoelectrons accumulated in the second photodiode; A method comprising:

20. determining, in the control logic, during readout of a third analog signal output from the pixel device, a second selected conversion gain for the pixel device, the second selected conversion gain being one of the first conversion gain or the second conversion gain determined based on a value of the second analog signal output; providing, by the control logic, the row logic control signal to the gate input of the second gate and the column logic control signal to the drain of the second gate to set the second selected conversion gain for the third analog signal output; transferring the accumulated photoelectrons in the third photodiode to the floating diffusion region through a third transfer gate, the third transfer gate being coupled between the third photodiode and the floating diffusion region; receiving, in the control logic, a readout of the third analog signal output from the floating diffusion region at the second selected conversion gain, the third analog signal output corresponding to photoelectrons accumulated in the third photodiode; 20. The method of claim 19 further comprising:

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