Transistor integration with stacked single-photon avalanche diode (SPAD) pixel arrays

Abstract

To provide a photodetector including a pixel array including a single-photon avalanche diode (SPAD).SOLUTION: A pixel array may have a configuration that includes one or more control transistors for each SPAD collocated on the same chip or wafer as the pixels and located on a surface of the wafer opposite to the light gathering surface of the pixel array. The control transistors may be positioned or configured for interconnection with a logic chip that is bonded to the wafer of the pixel array. The pixels may be formed in a substrate having doping gradient. The control transistors may be positioned on or within the SPADs, or adjacent to, but isolated from, the SPADs. Isolation between the individual SPADs and the respective control transistors may make use of shallow trench isolation regions or deep trench isolation regions.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure generally relates to image sensors that include pixel arrays having single photon avalanche diodes (SPADs) as photodetectors, light collecting elements, or photodetecting elements.

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application is non-provisional and claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application No. 63 / 083,262, filed September 25, 2020, the contents of which are incorporated herein by reference as if fully disclosed herein. [Background technology]

[0003] Electronic imaging or camera devices are now common on many types of electronic devices, such as cell phones, tablet or desktop computers, personal digital assistants, etc. These imaging devices may use only an array of individual light-gathering sensors, or pixels, which are often semiconductor-based and are processed to convert the light they receive into electrical signals that generate respective portions of the overall image.

[0004] Each individual pixel may be connected to associated circuitry (e.g., power lines, control electronics such as quenching or gating transistors, and other components or circuits) that controls the light-sensing or imaging operation of the pixel. The arrangement of the pixel's associated circuitry and light-collecting semiconductor portion may affect the pixel's light-collecting ability. How the pixel's associated circuitry and light-collecting semiconductor portion are arranged may better determine or determine the number of wafers included in an electronic imaging or camera device. In some embodiments, the pixel array may be implemented as part of a first wafer, with the associated circuitry implemented on a second wafer to which the first wafer is bonded. In other embodiments, the pixel array may be implemented as part of the first wafer and bonded or joined to a second wafer containing pixel control or other circuit components, which may be bonded or joined to a third wafer containing supply and logic components and circuits. Summary of the Invention

[0005] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description section. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0006] Disclosed herein are devices, systems, and structures for photodetectors, optical sensors, or image sensors, their internal components, and arrangements of their internal components. The image sensor may include a pixel array in which the photodetectors include single-photon avalanche diodes (SPADs). The image sensor may be formed by connecting or bonding one or more separately fabricated wafers or chips, such as a pixel wafer and a logic and / or control circuit wafer.

[0007] Various implementations and embodiments are directed to the internal structuring of the SPADs and the positioning of the various supply and / or control transistors of the SPADs. The particular supply and control transistors may be located on the pixel wafer in close proximity to the respective SPAD, or in some embodiments may be located separately on a dedicated wafer.

[0008] More specifically, a first set of embodiments discloses pixel array structures. One or more pixels may include a SPAD and one or more control transistors formed within the pixel and operatively connected to the SPAD. The control transistors may be formed within a semiconductor substrate of the pixel array, adjacent to a top surface of the pixel opposite the light-collecting surface of the pixel. The pixels may be disposed between insulating walls extending at least partially from the top surface of the pixel to the light-collecting surface of the pixel. An anode layer of the SPAD may be formed within the semiconductor substrate, and the substrate may be formed with a doping gradient. Particular embodiments within the first family describe embodiments having one, two, or three control transistors.

[0009] Another set of embodiments describes a pixel wafer formed in a semiconductor substrate having a plurality of pixel cells and a plurality of transistor regions arranged in a rectangular array. Each pixel in the pixel array includes a SPAD, and at least one control transistor is formed in each transistor region. Deep trench isolation walls may extend from a top surface of the pixel wafer into the semiconductor substrate or to near a back surface of the pixel wafer opposite the top surface. The deep trench isolation walls separate the transistor regions from the pixel cells. The SPAD in each pixel cell is formed by an n-type cathode adjacent the top surface and a p-type anode formed below the n-type cathode opposite the top surface. The semiconductor substrate may be a p-type semiconductor with a doping gradient.

[0010] Another set of embodiments describes a photodetector device including a pixel wafer including an array of pixel cells, a control transistor wafer having a first side bonded to the pixel wafer, and a logic wafer bonded to a second side of the control transistor wafer opposite the first side. Each pixel cell of the array of pixel cells in the pixel wafer includes a SPAD. The control transistor wafer includes, for each pixel cell, control transistors including at least a recharge transistor, a gating transistor, and a quenching transistor for each control transistor. The control transistor can control the photodetection operation of the SPAD for the corresponding pixel. The logic wafer can include circuitry that can receive an electrical signal via an interconnect pad from the control transistor wafer based on the photodetection operation. The present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings, in which like reference numerals indicate like structural elements, and in which: [Brief explanation of the drawings]

[0011] [Figure 1A] FIG. 1 shows a perspective view of an array of single photon avalanche diode (SPAD) pixels. [Figure 1B] FIG. 1 shows a perspective view of a SPAD pixel wafer attached to a logic or control circuit wafer. [Figure 1C] 1 shows two circuit diagrams of the supply or control circuitry associated with a single SPAD pixel. [Figure 1D] 1 shows a cross section of a SPAD pixel wafer connected to a supply, control, or logic wafer. [Figure 1E] 1 shows a cross-sectional view of a single SPAD pixel of a SPAD pixel array. [Figure 2] 1 shows a circuit diagram of supply and control circuitry associated with a SPAD pixel, according to one embodiment. [Figure 3A] 1 illustrates a plan view of components of a SPAD pixel, according to one embodiment. [Figure 3B] 3B illustrates a first cross-sectional view of the SPAD pixel of FIG. 3A according to one embodiment. [Figure 3C]3B illustrates a second cross-sectional view of the SPAD pixel of FIG. 3A according to one embodiment. [Figure 3D] 3B illustrates a third cross-sectional view of the SPAD pixel of FIG. 3A according to one embodiment. [Figure 3E] 3B illustrates a fourth cross-sectional view of the SPAD pixel of FIG. 3A according to one embodiment. [Figure 4A] 1 illustrates a plan view of components of a SPAD pixel, according to one embodiment. [Figure 4B] 4B illustrates a first cross-sectional view of the SPAD pixel of FIG. 4A according to one embodiment. [Figure 4C] 4B illustrates a second cross-sectional view of the SPAD pixel of FIG. 4A according to one embodiment. [Figure 5A] 1 shows a circuit diagram of supply and control circuitry associated with a SPAD pixel, according to one embodiment. [Figure 5B] 5B illustrates a cross-sectional view of a SPAD pixel implementing the circuit of FIG. 5A according to one embodiment. [Figure 6A] 1 shows a circuit diagram of supply and control circuitry associated with a SPAD pixel, according to one embodiment. [Figure 6B] 6B illustrates a plan view of the components of the SPAD pixel of FIG. 6A according to one embodiment. [Figure 6C] 6C illustrates a cross-sectional view of the SPAD pixel of FIG. 6B according to one embodiment. [Figure 7A] 1 illustrates a plan view of components of a SPAD pixel, according to one embodiment. [Figure 7B] 7B illustrates a cross-sectional view of the SPAD pixel of FIG. 7A according to one embodiment. [Figure 8A] 1 shows a circuit diagram of supply and control circuitry associated with a SPAD pixel, according to one embodiment. [Figure 8B] 8B illustrates a plan view of components of the SPAD pixel of FIG. 8A according to one embodiment. [Figure 8C] 8B illustrates a first cross-sectional view of the SPAD pixel of FIG. 8A according to one embodiment. [Figure 8D] 8B illustrates a second cross-sectional view of the SPAD pixel of FIG. 8A according to one embodiment. [Figure 9A]1 shows a plan view of a SPAD pixel having three control transistors according to one embodiment. [Figure 9B] 1 shows a circuit diagram of a SPAD pixel with four control transistors. [Figure 9C] 9C shows a circuit diagram of an inverter circuit such as may be included in the pixel of FIG. 9B. [Figure 9D] 9C shows a plan view of the pixel of FIG. 9B. [Figure 9E] 9D shows a cross-sectional view of the pixel of FIG. 9D. [Figure 10A] 1 shows a circuit diagram of supply and control circuitry associated with a SPAD pixel, according to one embodiment. [Figure 10B] 10B illustrates a plan view of the components of the SPAD pixel of FIG. 10A according to one embodiment. [Figure 10C] FIG. 10C illustrates a first cross-sectional view of the SPAD pixel of FIG. 10B according to one embodiment. [Figure 10D] FIG. 10C illustrates a second cross-sectional view of the SPAD pixel of FIG. 10B according to one embodiment. [Figure 10E] FIG. 10C illustrates a third cross-sectional view of the SPAD pixel of FIG. 10B according to one embodiment. [Figure 11] FIG. 2 is a plan view of a cross section of a SPAD pixel array according to one embodiment. [Figure 12A] FIG. 2 is a plan view of a cross section of a SPAD pixel array according to one embodiment. [Figure 12B] FIG. 12B is a detailed cross-sectional view of the SPAD pixel array of FIG. 12A according to one embodiment. [Figure 13A] FIG. 2 is a plan view of a cross section of a SPAD pixel array according to one embodiment. [Figure 13B] FIG. 13B is a detailed cross-sectional view of the SPAD pixel array of FIG. 13A according to one embodiment. [Figure 14A] FIG. 2 is a plan view of a cross section of a SPAD pixel array according to one embodiment. [Figure 14B] FIG. 14B is a detailed cross-sectional view of the SPAD pixel array of FIG. 14A according to one embodiment. [Figure 15A] 1 shows a circuit diagram of supply and control circuitry associated with a SPAD pixel, according to one embodiment. [Figure 15B] 15B illustrates a plan view of a SPAD pixel and various components of the supply and control circuitry of FIG. 15A, according to one embodiment. [Figure 15C] 15B illustrates a cross-sectional view of the SPAD pixel and circuitry of FIG. 15A according to one embodiment. [Figure 16] 1 shows a circuit diagram of supply and control circuitry associated with a SPAD pixel, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] The use of cross-hatching or shading in the accompanying figures is generally provided to clarify boundaries between adjacent elements and also to facilitate legibility of the figures. Thus, neither the presence nor absence of cross-hatching or shading is intended to convey or indicate any preference or requirement regarding particular materials, material properties, element proportions, element dimensions, commonalities of similarly illustrated elements, or any other characteristics, attributes, or properties with respect to any element shown in the accompanying figures.

[0013] Additionally, it will be understood that the proportions and dimensions (whether relative or absolute) of the various features and elements (and collections and groups thereof), as well as the boundaries, separations and relationships presented therebetween, are provided in the accompanying figures merely to facilitate understanding of the various embodiments described herein, and as such may not necessarily be presented or drawn to scale, and are not intended to imply any preference or requirement for the illustrated embodiment to the exclusion of the embodiment described with reference thereto.

[0014] Reference will now be made in detail to exemplary embodiments as illustrated in the accompanying drawings. It should be understood that the following description is not intended to limit these embodiments to a single preferred embodiment. On the contrary, the following description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the described embodiments as defined by the appended claims.

[0015] Embodiments described herein are generally directed to light detection sensors, photodetector (or "photoreceptor") structures, and devices and systems that use them. Examples of such devices include digital cameras, light detection and ranging (LIDAR) systems and devices, and the like. Such devices often use an array of photodetectors formed on a single semiconductor wafer. The individual photodetector and associated circuitry components are called pixels or pixel cells, and the semiconductor wafer is called a pixel wafer.

[0016] A pixel can include a single-photon avalanche diode (SPAD) as the light-detecting component, with the diode junction reverse-biased into the avalanche region. The cathode of the SPAD is often located near the surface of the pixel so that photons striking the cathode cause an extended cascade of charge carriers that are detected by circuitry connected to the SPAD. A pixel wafer can be formed with a plurality of SPAD pixels arranged in an array with a light-collecting surface on a first side, also referred to as the "backside," of the pixel wafer. The pixel wafer can be formed or fabricated with at least some of the detection circuitry on a second side, referred to as the "front side," opposite the light-collecting backside.

[0017] To increase the net light-collecting surface, in some embodiments, a pixel wafer can be fabricated or formed to primarily contain SPAD pixel cells with only limited additional circuitry on the pixel wafer, such as for biasing the SPADs. One or more additional wafers, called "logic" and / or "control" wafers, can then be formed to contain circuitry for detecting, conditioning, and / or processing signals generated by the SPAD pixels. The pixel wafer and other wafers can then be bonded or joined into a stack configuration with matching electrical interconnects.

[0018] In this implementation, certain circuit elements, such as the control transistors of the SPADs, may be formed on the logic wafer. Such control transistors may use higher voltage supplies or dual voltage supplies, such as quenching transistors, gating transistors, and recharging transistors. This may create challenges for circuit layout and space constraints within the logic wafer. For example, various other circuit components on the logic wafer (such as time sampling circuits, counters, image processors, graphics processors, or other components) may operate from lower voltage supplies.

[0019] One group of embodiments disclosed herein generally relates to a structure or configuration in which SPAD pixels and their associated control transistors can be formed or fabricated on a pixel wafer while still providing a large light-collection surface for the SPAD. Generally, each SPAD can be implemented with a cathode / anode junction forming a large avalanche region. The light-collection surface of the SPAD can be formed on one side of the pixel wafer, where a doping gradient is formed within the SPAD. The doping gradient allows photon-induced charge carriers to be guided to the avalanche region of the SPAD. The control transistor (and possibly other circuit components) can be formed on the side of the pixel wafer opposite the light-collection surface of the pixel wafer. The cathode / anode junction of the SPAD can be located, at least in part, within the pixel wafer below the control transistor to increase the junction area. The control transistor of each pixel may be electrically or otherwise isolated by using shallow trench isolation walls or structures, by deep trench isolation walls or structures, or by formation within a semiconductor well.

[0020] In a first family of embodiments, two control transistors for the SPAD may be formed on each pixel. In a second family of embodiments, three or more control or logic transistors for the SPAD may be formed on each pixel. In a third family of embodiments, a single control transistor for the SPAD may be formed on each pixel. In a fourth family of embodiments, the control transistor is formed on the pixel wafer but external to the corresponding pixel containing the SPAD. The control transistor is formed in a region separated from the SPAD pixel by a deep trench isolation wall. In a fifth family of embodiments, the control wafer is formed on a dedicated wafer separate from either the pixel wafer or the logic wafer. The dedicated wafer is positioned and bonded or joined between the pixel wafer and the logic wafer.

[0021] These and other embodiments are described below with reference to Figures 2-15C. Figures 1A-1E describe and outline general considerations and implementations for a dual-wafer image sensor including a pixel wafer and a logic and / or control circuit wafer. However, those skilled in the art will readily appreciate that the detailed description provided herein with respect to these Figures 2-15C is for illustrative purposes only and should not be construed as limiting.

[0022] Additionally, although particular electronic devices having image sensors are described or illustrated below, the embodiments described herein may be used with a variety of electronic devices, including, but not limited to, mobile phones, personal digital assistants, timing devices, health monitoring devices, wearable electronic devices, input devices (such as styluses), desktop computers, wearable electronic glasses, and the like.

[0023] Other embodiments and implementations are within the scope and spirit of this disclosure and the appended claims. For example, mechanisms implementing functionality may be physically located in various locations, including being distributed so that some of the functionality is implemented in different physical locations. Also, as used herein, including in the claims, "or" when used in a list of items preceded by "at least one" indicates a disjunctive list; for example, the list "at least one of A, B, or C" indicates A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, the term "exemplary" does not imply that the described example is preferred or better than other examples.

[0024] 1A-1E provide a general illustration of using multiple wafers, such as a pixel wafer containing an array of photodetectors together with a logic wafer, to fabricate a photodetector or image sensing device, an illustration that provides context and contrast for the description of the embodiments described in FIGS.

[0025] FIG. 1A shows a pixel array 100 formed on a single pixel wafer 108. The pixel array 100 is shown with a top surface 102 opposite a back surface 106. Individual pixels, such as pixels 104a and 104b, include photoreceptors, such as single-photon avalanche diodes (SPADs), and possibly associated circuitry. The pixel array can be formed in the pixel wafer 108 by any of a variety of semiconductor fabrication processes. For example, the pixel wafer 108 can be a p-type semiconductor with the photoreceptors and any associated circuitry formed by etching and deposition, ion implantation, and / or other fabrication methods. Associated circuitry or connection components to the anodes or cathodes of the photoreceptors can be formed on the top surface 102 by the fabrication process, such that the back surface 106 can be the side exposed to light for image capture. The pixel array 100 can be fabricated with various interconnect pads, such as interconnect pad 107.

[0026] The pixel array 100 can be fabricated to be coupled to a second wafer, herein referred to as a "logic wafer", which can include either a power supply voltage line or connection for a photoreceptor, various control transistors (as will be further described), a processing circuit (e.g., buffer, time-to-digital counter, image processor, filter, etc.), or other components.

[0027] FIG. 1B shows a perspective view 110 of pixel array 100 bonded or coupled to a logic (or control circuit) wafer 112. Pixel wafer 108 is inverted such that the back surface 106 is shown at the top, where the top surface 102 interfaces or bonds with logic wafer 112. Logic wafer 112 is also fabricated with interconnect pads that match and / or bond to interconnect pads 107 fabricated on pixel array 100 to make circuit or electrical connections.

[0028] FIG. 1C shows first and second circuit diagrams of circuits 120 and 140 that can be used in a dual-wafer process to form an image sensor as shown in FIGS. 1A - 1B. Second circuit 140 is based on the disclosure of U.S. Patent Application No. 15 / 879,350, the entire content of which is incorporated herein by reference. In circuits 120 and 140, the photoreceptors are SPADs 124 and 144 mounted on respective pixel wafers, 122 and 142, which are coupled or bonded to a logic wafer that includes the illustrated control transistors and voltage sources.

[0029] In the first circuit 120, various power supply voltages can exist, such as high voltage V DDH 134a, anode power supply voltage V SPAD 134b, and zero voltage source 134c. SPAD 124 is electrically coupled to anode power supply voltage V SPAD 134b via interconnect pads 123a and 123b between pixel wafer 122 and the logic wafer.

[0030] The logic and / or control circuitry, also referred to herein as a “logic circuit” or a “control circuitry”, comprises at least three transistors: a voltage V Q pMOS quenching transistor 126, which applies a voltage V FRCH a pMOS fast recharge transistor 128 applying a voltage V GATE and a pMOS gating transistor 126 for applying a voltage to the SPAD 124. A pMOS quenching transistor 126 allows the bias of the SPAD 124 to be reduced below breakdown after detection of a photon-induced avalanche current. A pMOS fast recharge transistor 128 can be gated to allow rapid restoration of charge carriers within the SPAD 124. A pMOS gating transistor 130 can control output signaling from the SPAD 124. The output signal is sent through a level-down shifter (which may have high-voltage transistor(s)) 132a and an inverter (possibly having low-voltage transistor(s)) 132b, either of which may also provide amplification to subsequent processing circuitry via an output connection link 134d. Those skilled in the art will recognize that alternatives or variations of the SPAD photoreceptor first circuit 120 are possible.

[0031] A second circuit 140 illustrates one such variation. In the second circuit 140, a SPAD 144 is included on a pixel wafer 142. The second circuit 140 has a first power supply voltage 152a and a second power supply voltage 152b. The pixel wafer 142 can be electrically connected to logic and control circuits in a separate logic wafer via interconnect pads 141a, 141b, and to the second power supply voltage 152b, which is connected to the anode of the SPAD 144. The second circuit 140 receives a voltage signal V RCH a pMOS recharge transistor 148 applying a voltage signal V QCH a pMOS quenching transistor 146 that applies a voltage signal V GATE and a combination of a pMOS select transistor 150a and an nMOS gating transistor 150b controlled by the select transistor 150a. The source of the nMOS gating transistor 150b is connected to circuit ground.

[0032] FIG. 1D shows a combined cross-sectional view and circuit diagram of one example of how pixel wafer 170 can be bonded or bonded to control circuit wafer 112. Pixel wafer 170 includes array 100 of SPAD pixels, such as SPAD pixel 162, separated by insulating walls, such as insulating wall 168. SPAD pixel 162 includes anode 166 and cathode 164. Pixel wafer 170 can also include bonding layer 172, which includes vias and interconnect links, such as via 174, to control circuit wafer 112. Pixel wafer 170 can be bonded or bonded to control circuit wafer 112 along interface 171. Electrical connections between pixel wafer 170 and control circuit wafer 112 can be provided by interconnect pads, such as interconnect pads 123a and 123b. As shown, the top surface of pixel wafer 170 can be backside 106, as described above in connection with FIGS. 1A-1B, which is the surface exposed to light for light sensing or image capture.

[0033] The control circuit wafer 112 may include a voltage source 180 that may provide one or more voltage levels to the pixel wafer 170 and possibly also to a quench / recharge circuit 182, such as circuits 120 and 140 described above.

[0034] 1E shows a cross-sectional view of various details of a SPAD 190, such as the SPAD of a SPAD pixel 162 in pixel wafer 170. SPAD 190 includes a p-type body 191 in which a p-type anode 192 and an n-type cathode 194 are fabricated. An avalanche region 193 may exist at the junction of p-type anode 192 and n-type cathode 194. SPAD pixel 162 may be electrically shielded from adjacent SPADs in pixel wafer 170 by insulating wall 168.

[0035] The SPAD pixel 162 may be doped such that the p-type body 191 has a doping gradient in which the concentration of dopant increases both vertically from the front surface 102 to the light-collecting back surface 106, as indicated by gradient indicator 196a, and laterally from the center of the p-type body to the insulating wall 168, as indicated by gradient indicator 196b. The doping gradient of the SPAD pixel 162 may be based on the doping gradient described in the disclosure of U.S. patent application Ser. No. 15 / 713,477, now U.S. Pat. No. 10,438,987, the contents of which are incorporated herein by reference in their entirety.

[0036] The doping gradient may allow photon-induced charge carriers to be guided toward the junction of the n-type cathode 194 and the p-type anode 192. For example, a centrally arriving photon 198a may generate charge carriers 199a (electrons in this case) that are then guided toward the junction by the vertical gradient. Alternatively, a photon 198b incident on a SPAD pixel 162 near a sidewall may generate charge carriers 199b that may be guided toward the center by the lateral doping gradient, and therefore may have a greater chance of inducing an avalanche current at the junction.

[0037] Overview and Background of the Family of Embodiments

[0038] Described below are at least four families of circuit, configuration, and layout embodiments of control circuits and pixel wafers, photoreceptor pixels and their included SPADs, and other components that may form part of an image sensor. It should be understood that this classification should not be construed as limiting or restrictive. Various features, components, and configurations of the embodiments may occur in more than one family. Furthermore, features, components, and configurations described in embodiments of these families may be combined in yet other embodiments.

[0039] Although descriptions of particular features, components, and subcomponents described with respect to a first embodiment may be referenced or described as applying to analogous features, components, and subcomponents of a second embodiment, it will be understood that those analogous features, components, and subcomponents of the second embodiment may be implemented with variations consistent with the scope of those descriptions.

[0040] In these embodiments, a dual level power supply voltage: a high level power supply voltage V DDH , and the low-level power supply voltage V DDL Additionally, embodiments may have a SPAD voltage supply and a ground supply. In some described embodiments, certain control transistors, such as gate transistors, may be located on the pixel array. In some embodiments, these may be control transistors that may need to operate from a high voltage supply.

[0041] The various components of the pixel may be formed by any of a variety of fabrication techniques, such as ion implantation, etching and deposition, or other fabrication techniques. The various components may be formed or fabricated in a semiconductor wafer, for example, a p-type substrate or an n-type substrate.

[0042] First family: Two transistors in a SPAD pixel cell

[0043] A first family of embodiments is directed to optical or image sensors and their internal components and features, including an array of pixels formed on a pixel wafer bonded or coupled to a logic or control circuit wafer. The pixels may include SPADs as photodetectors. In the first family of embodiments, two of the control circuit transistors are formed on the pixel wafer for each pixel. The pixels are also referred to herein as "pixel cells."

[0044] FIG. 2 shows a generalized diagram 200 of one embodiment of a pixel cell 210 and associated control and supply circuitry. The pixel cell 210 may be part of a pixel array on a pixel wafer. The pixel cell 210 typically includes high-voltage circuit elements such as a SPAD, a gate transistor, and a quenching transistor. The pixel cell 210 has interconnect pads 212a-212d that provide electrical connection to external circuit components, which may be located on a separate control wafer, as described above. The interconnect pads 212a-212d may be copper and may be bonded to matching copper interconnect pads on a logic wafer.

[0045] In contrast, the low voltage circuit segment 224 includes low voltage elements such as quenching transistors, buffers / inverters, etc. Generally, the low voltage circuit segment 224 includes circuitry external to the pixel cell 210 and V DDL A voltage may be derived from source 202. The output signal may be sent via connection 208 to further components, such as signal conditioning and image processing components.

[0046] FIG. 3A shows a plan view of a pixel cell 300, providing a first configuration of the components of pixel cell 210. The illustrated surface of pixel cell 300 may correspond to surface 102 in FIG. 1A, with the light-collecting surface of pixel cell 300 opposite the illustrated surface of pixel cell 300. Pixel cell 300 is comprised of a rectangular well surrounded by an insulating layer 302 that separates pixel cell 300 from other pixel cells in the pixel wafer. The insulating layer may be silicon dioxide. Pixel cell 300 has an anode layer 304 internally adjacent to insulating layer 302. Anode layer 304 may be p-type and may be electrically connected to interconnect pad 212d.

[0047] The pixel cell 300 is configured with a shallow trench isolation (STI) layer 306 within the anode layer 304 to form at least three regions within an isolated well: a first transistor region 315a, a central SPAD region 315b, and a second transistor region 315c. In the particular version of the embodiment shown, the first transistor region 315a is disposed on a first side of the central SPAD region 315b, and the second transistor region 315c is disposed on a second side of the central SPAD region 315b opposite the first side. In the particular version of the embodiment shown, the STI layer 306 forms a perimeter ring around the first transistor region 315a, the central SPAD region 315b, and the second transistor region 315c. Other variations of this embodiment may have alternative arrangements of the three regions.

[0048] The SPAD 214 in this configuration may be implemented as an n-type cathode layer 320 disposed on a p-type anode layer (relative to the orientation shown), as further shown and described below. The SPAD 214 may have a cathode electrode 322 connected to the n-type cathode layer 320. The cathode electrode may extend over some or all of the n-type cathode layer. The cathode electrode 322 may be electrically connected to an interconnect line 324, which may be a metal or other trace.

[0049] The pMOS HV quenching transistor 216 (which may be part of the pixel cell 210 of FIG. 2) may be located in the first transistor region 315a. The pMOS HV quenching transistor 216 may be located in an n-type semiconductor well (NW) 310a. The NW 310a may have an NW bias section 310b linked to an NW connection line 310c. A bias voltage may be applied to the NW connection line 310c. In some variations, the bias voltage may be 0.8V, although other bias voltages may also be used. The source of the pMOS HV quenching transistor 216 is connected to the interconnect pad 212a, as described above. The drain of the pMOS HV quenching transistor 216 is coupled to the interconnect line 324 to form the node 220 within the pixel cell 210. The gate 217 of the pMOS HV quenching transistor 216 is coupled to the interconnect pad 212b, as described above.

[0050] The nMOS gating transistor 218 may be located in the second transistor region 315c. The nMOS gating transistor 218 may be located in a p-type semiconductor well (PW) 344. The PW 344 may have a PW bias section 346a coupled with a PW connecting link 346b to which a PW bias voltage may be applied. In some variations, the PW bias applied voltage may be V DDL ~V DDH The PW 344 is then located within a deep n-type semiconductor well (DNW) 340. The DNW 340 may have a DNW bias section 342a coupled to a DNW connection line 342b. A bias voltage may be applied to the NW connection line 310c. In some variations, the bias voltage may be 0.8V, although other bias voltages may also be used. As noted above, the source of the nMOS gating transistor 218 is coupled to the power supply voltage V along the voltage supply link 222. DDL ~V DDH The drain of nMOS gating transistor 218 is coupled to interconnect line 324 to form node 220. The gate 219 of nMOS gating transistor 218 is coupled to interconnect pad 212c as described above.

[0051] The interconnect pads 212a-212d may be positioned above the surface of the pixel cell 300 (i.e., off-page), rather than in the plane of the top surface as shown. Such a configuration or positioning of the interconnect pads 212a-212d may be based on Figure 1D. Such a configuration, or a similar configuration, allows the wafer containing the pixel cell 300 to be bonded to a control wafer that includes the external circuit components (e.g., high-voltage circuit segment 224) shown in Figure 2.

[0052] FIG. 3B shows a horizontal ("X-axis") cross-section 350 taken along horizontal section line A-A' in FIG. 3A. The left and right edges of cross-section 350 indicate that insulating layer 302 and anode layer 304 may extend to the backside surface 106, which receives light for imaging, although this is not required. Cross-section 350 shows that pixel cell 300 includes a p-type substrate 354 (P-EPI) in which pMOS HV quenching transistor 216 is formed. STI layer 306 may be formed without extending to the backside surface 106, but may extend sufficiently to electrically insulate pMOS HV quenching transistor 216 and may extend deeper than NW 310a, although this is not required. NW 310a may extend to contact STI layer 306, or there may be a gap including an extension of p-type substrate 354 between NW 310a and STI layer 306. In the particular version of the embodiment shown in cross-section 350 , the NW bias distribution 310 b is positioned away from the drain 352 a and source 352 b of the pMOS HV quenching transistor 216 .

[0053] FIG. 3C shows a horizontal ("X-axis") cross-section 360 of pixel cell 300 taken along horizontal section line B-B' of FIG. 3A. The anode layer 304 and STI layer 306 of insulating layer 302 may be as described with respect to FIG. 3B. The pixel cell 300 of this embodiment has an n-type cathode layer 320 disposed above a p-type anode layer 362. The STI layer 306 may extend deeper than the p-type anode layer 362, but this is not required. The p-type substrate 354 is shown with doping gradient profile levels 364a and 364b, which may be based on the description made with respect to FIG. 1E. The n-type cathode layer 320 has a cathode electrode 322 that provides electrical connection to node 220, as described above.

[0054] 3D shows a horizontal ("X-axis") cross-section 370 of the pixel cell 300 along horizontal section line CC' of FIG. 3A. The insulating layer 302, anode layer 304, and STI layer 306 may be as described with respect to FIG. 3B. The PW 344 is shown included in the DNW 340. The PW bias section 346a is located within the PW 344 on the side of the nMOS gating transistor 218 opposite the location of the DNW bias section 342a, although this is not required. As noted above, conduction through the drain 343a and source 343b of the nMOS gating transistor 218 is controlled by a voltage signal applied to the gate 219.

[0055] 3E shows a vertical ("y-axis") cross-section 380 of the pixel cell 300 along vertical section line D-D' in FIG. 3A. The cross-section 380 shows that a doping gradient in the p-type substrate 354, indicated by graded level lines 386a and 386b, can extend beneath the pMOS HV quenching transistor 216 and the nMOS gating transistor 218. Due to this doping gradient, photon-induced charge carriers 388a induced by photons received at the center of the back surface of the pixel cell 300 can be guided without deflection toward the avalanche junction region at the interface between the p-type anode layer 362 and the n-type cathode layer 320. However, photons received toward the edge of the back surface of the pixel cell 300 can be deflected toward the avalanche junction region due to the doping gradient.

[0056] FIG. 4A shows a plan view of a second embodiment in which two control transistors may be included in each pixel cell of a pixel wafer. The pixel cell 400 can implement the circuitry described with respect to FIG. 2. The pixel cell 400 implements the layout or configuration of the pMOS HV quenching transistor 216 and nMOS gating transistor 218 described and shown with respect to FIG. 3. Unlike the embodiment described with respect to FIGS. 3A-3E, the pixel cell 400 does not use shallow trench isolation to form isolated regions for components. Instead, the pixel cell 400 implements a SPAD in which both the n-type cathode layer and the p-type anode layer, which form the avalanche junction, are formed at least partially below the surface of the pixel cell 400.

[0057] 4A shows a pixel cell 400 formed as a rectangular well with a surrounding insulating layer 302 and an anode layer 304, as described above in connection with FIGS. 3A-3E. The anode layer 304 is connected to a bias voltage source V through interconnect pad 212d, as previously described. SPAD The components of pixel cell 400 may be formed in or on a p-type substrate 402, as shown in more detail in Figures 4B-4C. Within p-type substrate 402, an n-type well (NW) 404 may be formed having a cathode electrode 420 in electrical connection to node 220.

[0058] 4A, the pMOS HV quenching transistor 216 may be disposed within the internal NW 408, which is itself disposed within the deep p-type well (DPW) 406. The DPW may be provided with a bias supply voltage in the DPW bias section 412, and the internal NW 408 may be coupled to an NW bias voltage 411a provided in the NW bias section 411b. As described for the embodiment of FIGS. 3A-3E, the pMOS HV quenching transistor 216 may have its source connected to the interconnect pad 212a, its gate 217 connected to the interconnect pad 212b, and its drain connected to the node 220.

[0059] The nMOS gated transistor 218 may be disposed within the PW 414, which may be supplied to the bias section 419a by a PW bias voltage 419b. The nMOS gated transistor 218 may have its drain and source connected as described for the embodiment of Figures 3A-3E, and its gate 219 connected to an interconnect pad 212c. The pMOS HV quenching transistor 216 is shown with its source / gate / drain axis perpendicular to the source / gate / drain axis of the nMOS gated transistor 218, although this is not required.

[0060] Figure 4B shows a horizontal cross-sectional ("X-axis") view 430 of pixel cell 400 along section line B-B' in Figure 4A, through nMOS-gated transistor 218. View 430 shows the placement of PW 414 within n-type cathode layer 404, which forms the cathode of the SPAD of pixel cell 400. A p-type anode layer 432 is disposed as a buried layer below n-type cathode layer 404 within p-type substrate 402. The nMOS-gated transistor has its drain 418a and source 418b disposed within PW 414, as shown for gate 219.

[0061] Figure 4C shows a shifted ("zigzag") vertical cross-section ("y-axis") 440 along the double and shifted section lines A-A' and C-C' shown in Figure 4A. Figure 4C shows that the n-type cathode layer 404 may extend as a buried layer beneath the pMOS HV quenching transistor 216 and the nMOS gating transistor 218, and may also extend to the surface of the pixel cell 400, away from the DPW 416 and PW 414 that provide isolation for the pMOS HV quenching transistor 216 and the nMOS gating transistor 218, respectively. As previously mentioned, the p-type substrate 402 may have a doping gradient, as indicated by doping gradient contours 444a and 444b, that may operate to direct photon-induced charge carriers toward the center of the pixel cell 400.

[0062] Figure 5A shows a circuit diagram 500 that is conceptually similar to the circuit diagram 200 of Figure 2, but with certain details. In circuit diagram 500, a pMOS gating transistor 518 is used instead of the nMOS gating transistor 218 of Figure 3. Other components shown in Figure 5A are as described in connection with Figures 2 and 3.

[0063] FIG. 5B shows a plan view of a third embodiment configuration in which two control transistors may be included in each pixel of a pixel wafer. Pixel 510 is similar to pixel cell 300 described in connection with FIGS. 3A-3E. Specifically, pixel 510 uses STI layer 306 to form isolation regions for the components shown in FIG. 5A. Region 512 may be as described for pixel cell 300. Pixel 510 differs from pixel cell 300 in that a pMOS gating transistor 518 is present instead of nMOS gating transistor 218 of pixel cell 300. The pMOS gating transistor 518 is formed in NW 516, having gate 519 connected to interconnect pad 212c, as shown. NW 516 may have bias section 514a to which NW bias voltage 514b is applied. Along horizontal section line C-C′ in FIG. 5B, the cross-sectional view is similar to the cross-sectional view shown in FIG. 3B and includes similar corresponding descriptions.

[0064] Figure 6A is a circuit diagram 600 showing a SPAD pixel cell including a SPAD 614 and two control transistors, as well as associated supply and control circuitry. This illustrates a fourth embodiment in which a pixel wafer with an array of SPAD photodetectors can include two control transistors, which may be located on a logic wafer to which the pixel wafer is otherwise bonded or coupled. The embodiment of Figure 6A includes two nMOS transistors in each pixel cell 602, so biasing may be implemented differently than in the previous embodiments.

[0065] Associated supplies and control circuitry external to the pixel cell 602 may include an nMOS quenching transistor 604 having its source connected to circuit ground 606 and its drain linked to the interconnect pad 612d of the pixel cell 602. The nMOS quenching transistor 604 is quenched by a voltage signal V applied to its gate 605. BN The output of the pixel cell 602 is received at the drain of the nMOS quenching transistor 604 and transmitted by a buffer 608, which may also provide amplification of the signal on an output line 609.

[0066] The pixel cell 602 includes at least a SPAD 614, an nMOS bias transistor 616, and an nMOS gating transistor 618. The nMOS bias transistor 616 is operable to place the SPAD 614 in a reverse bias state for photon detection. The drain of the nMOS gating transistor 618 is connected to V DDH The cathode of SPAD 614 is biased at power supply voltage V through interconnect pad 612a, and its gate is coupled to receive a gate signal through interconnect pad 612b. SPAD This supply voltage V SPAD In some implementations of this embodiment, V SPAD =V BD +V DDH V BD is the breakdown voltage of the SPAD614.

[0067] 6B shows a plan view 610 of the layout or configuration of the circuit components of the circuit diagram 600 within a pixel cell 602. As described for the previous embodiment, the pixel cell 602 may be housed within a rectangular insulating layer 302 with the anode layer 304 therein. The components within the pixel cell 602 may be implemented on a p-type substrate 622. An n-type cathode layer 624 may be present in a buried layer, extending beneath the nMOS bias transistor 616 and the nMOS gating transistor 618, as described below, to provide a large avalanche junction area. The n-type cathode layer may also extend to the top surface, as described below, with a cathode electrode 620 connected to an interconnect pad 612a.

[0068] An nMOS bias transistor 616 and an nMOS gating transistor 618 are formed in PWs 613 and 617, respectively. While not shown for simplicity, PWs 613 and 617 may have bias sections similar to bias section 419a, in which their respective bias voltages may be applied. While nMOS bias transistor 616 and nMOS gating transistor 618 are shown arranged with their drain / gate / source axes orthogonal, in other variations of this embodiment, nMOS bias transistor 616 and nMOS gating transistor 618 may be arranged differently within pixel cell 602. A gate 615 of nMOS bias transistor 616 is coupled to interconnect pad 612c, and a gate 619 of nMOS gating transistor 618 is coupled to interconnect pad 612b.

[0069] FIG. 6C shows a horizontal cross-sectional view 630 taken along section line B-B' shown in FIG. 6B. An nMOS gated transistor 618 is formed within a PW 617. The PW 617 is itself formed within an n-type cathode layer 624, which may extend below and beyond the PW 617. A p-anode layer 632 is formed below the n-type cathode layer 624 to enable a large avalanche region at the junction between the p-anode layer 632 and the n-type cathode layer 624. The p-type substrate 622 may be implemented with a doping gradient, as previously described. FIG. 6C also shows a vertical cross-sectional view taken along section line A-A' in FIG. 6B, and therefore the description will not be repeated.

[0070] 7A shows a plan view of a pixel cell 700 configuration of a fifth embodiment, in which each pixel cell on a pixel wafer includes two control transistors. This configuration is based on the circuit elements described in connection with pixel cell 602 of FIG. 6A. The difference is that here, pixel cell 700 is formed on an n-type substrate, and the control transistors are nMOS and are formed in respective deep n-wells (DNWs).

[0071] As described in the previous embodiment, the pixel cell 700 may be housed within a rectangular insulating layer 302. However, here there is an n-type cathode layer 705 internally adjacent to the insulating layer 302. In this embodiment, the n-type cathode layer 705 is connected to a cathode voltage V SPAD The cathode is connected to bias the V SPAD is V SPAD =V BD+ V DDH , V BD can be set as the breakdown voltage, but this is not required.

[0072] The pixel cell 700 can include a p-type anode layer 704 that extends beneath the nMOS bias transistor 616 and the nMOS gating transistor 618 and is disposed above an n-type cathode layer formed in an n-type substrate, as described further below. The p-type anode layer 704 is in contact with an anode electrode 720.

[0073] The nMOS gating transistor 618 is controlled by a signal applied to a gate 716 that is coupled to control circuitry external to the pixel cell 700 via interconnect pad 612b. The nMOS gating transistor 618 is disposed within the PW 714. The PW 714 may have a bias section 719 to which a bias voltage is applied. The PW 714 is formed within the DNW 712, which may have a bias section 717 to which a DNW bias voltage is applied. The gate 716 connects to the interconnect pad 612b and receives an external signal therefrom. The source of the nMOS gating transistor 618 is connected to V DDH V can be DDH Can be connected to a source.

[0074] The nMOS bias transistor 616 may be configured or formed similarly to the nMOS gating transistor 618. The nMOS bias transistor 616 may be formed within the PW 708, which may be formed within the DNW 706. The PW 708 and DNW 706 may be implemented with their respective bias sections as described above, but are not shown for simplicity. The gate 710 of the nMOS bias transistor 616 is coupled to an interconnect pad 612c and may receive an external signal via the interconnect pad 612c. The drain of the nMOS bias transistor 616, along with the drain of the nMOS gating transistor 618, is generally coupled to external circuit components via the interconnect pad 612d.

[0075] Figure 7B shows a horizontal cross-section 730 taken along section line A-A' in Figure 7A. The nMOS gated transistor 618 is shown in cross-section at the PW 714, which in turn is within the DNW 712. There is a portion of the p-anode layer 732 extending below the DNW 712, which may also have an extension 704 extending to the top surface of the pixel cell 700. An n-type cathode layer 734 may be formed below all or most of the p-anode layer 732 to increase the size of the avalanche region formed by the n-type cathode layer 734 and the p-anode layer 732. The region of the n-type substrate 702 below the n-type cathode layer 734 may be formed with a doping gradient, as indicated by doping gradient contour levels 738a and 738b.

[0076] 6A-6C is implemented similarly to the fifth embodiment described in connection with Figures 7A-7B, except that the semiconductor valence types (n-type and p-type) are reversed relative to the substrate, with respect to the anode and cathode of the SPAD. One skilled in the art would understand how to similarly implement the other aforementioned embodiments with reversed semiconductor types. Similarly, it will be understood that for each of the following embodiments, there is a similar corresponding embodiment having similarly reversed semiconductor types.

[0077] Second family: at least three transistors in a SPAD pixel cell

[0078] The following embodiments in this section describe circuits and configurations in which a pixel wafer containing an array of SPAD pixels can include three control transistors in each pixel cell. In other implementations, such control transistors can be located on a logic wafer to which the pixel wafer is bonded. Including three control transistors on the pixel wafer can provide more space for circuit components on the logic wafer. The circuits and configurations described in these embodiments can maintain a large avalanche area within each SPAD. Because many of the features, components, and subcomponents of the following embodiments are similar or may be similar to those of the previous embodiments, such features, components, and subcomponents will not be described in the same detail. Those skilled in the art will recognize possible modifications and adaptations that may be useful or necessary.

[0079] 8A is a circuit diagram 800 of a sixth embodiment in which there are three transistors in a pixel cell 802. The pixel cell 802 and SPAD 810 are connected at their anodes to a voltage source V SPAD The cathode of the SPAD 810 is connected to an interconnect pad 812e to the power supply voltage V. The cathode of the SPAD 810 is connected to the drain of a first internal pMOS transistor 814, which is a high-voltage quenching transistor, and its gate 815 is connected to an interconnect pad 812b through which a control signal can be received. The source of the first internal pMOS transistor 814 is connected to an interconnect pad 812a, and through which the power supply voltage V DDL 805 is received. External pMOS transistor 804 is a low voltage quenching transistor. The external control circuitry may include an inverting buffer 806 that applies the output signal of the SPAD on interconnect 808 to further components on the logic or control wafer.

[0080] The pixel cell 802 includes a pMOS recharge transistor 818, the gate 817 of which is connected to the interconnect pad 812c, through which further control signals can be applied. The pMOS recharge transistor 818 is connected to V DDHIn these embodiments, two high voltages are provided: V DDL and V DDH , and its offset and anode voltage V SPAD The drain of pMOS recharge transistor 818 is connected in series with the drain of nMOS gating transistor 820, which has its gate 821 connected to interconnect pad 812d. A gate signal (e.g., an "on / off" signal) can be received from external control circuitry via interconnect pad 812d. The node connecting the drains of pMOS recharge transistor 818 and nMOS gating transistor 820 is connected to the cathode of SPAD 810. The source of nMOS gating transistor 820 is connected to a reduced power supply voltage 822, which is V DDL ~V DDH or another value.

[0081] Figure 8B shows a plan view 830 of a configuration of certain elements of the pixel cell 802 of Figure 8A. The pixel cell 802 is surrounded by an insulating layer 302, which is an internal boundary anode layer 304, as previously described. The pixel cell 802 has an n-type cathode layer 834 formed in a semiconductor substrate 832, which may be p-type and n-type, respectively. A cathode electrode 824 may be formed on a surface of the n-type cathode layer 834. Although shown as a square, the cathode electrode 824 may extend over more or less of the cathode electrode 824.

[0082] Both the first internal pMOS transistor 814 and the pMOS recharge transistor 818 are formed in respective NWs 838a and 838b, which are in turn formed in respective deep p-wells (DPWs) 836a and 836b. The first internal pMOS transistor 814 and the pMOS recharge transistor 818 are arranged with their source / gate / drain axes in parallel, although other arrangements and configurations may be used. The nMOS gate transistor 820 is formed in a PW 823.

[0083] FIG. 8C shows a cross-sectional view 840 of a pixel cell 802 having the configuration described in connection with FIG. 8B along section line A-A'. An n-type layer 842 may be part of an n-type cathode layer and forms part of the cathode of the SPAD 810. As shown, a p-type anode layer 844 of the SPAD 810 is formed in the semiconductor substrate 832 below the n-type layer 842. The n-type layer 842 may extend below the DNWs 836a and 836b, as shown, to increase the avalanche junction area at the interface of the n-type layer 842 and the p-type anode layer 844. Away from the DNWs 836a and 836b, the n-type layer 842 interfaces with the n-type cathode layer 842, which may extend proximate to the top surface of the pixel cell 802.

[0084] Figure 8D shows a cross-sectional view 850 of a pixel cell 802 having the configuration described in connection with Figure 8B along section line B-B'. An nMOS gated transistor 820 is shown formed in a PW 823, which is in turn formed in an n-type cathode layer 834. A p-type anode layer 844 extends below the n-type cathode layer 834. The extension of the p-type anode layer 844 below the n-type cathode layer 834 and the n-type cathode layer 834 provides an increased avalanche junction area at their interface.

[0085] FIG. 9A shows a plan view 900 of a first variation of the embodiment described in connection with FIGS. 8A-8D. The embodiment shown in FIG. 9A modifies the circuit diagram 800 shown in FIG. 8A to replace the nMOS-gated transistor 820 with a pMOS-gated transistor 920 having a gate 921. The other components of the circuit diagram 800 are as described. The plan view 900 is as described for the plan view 830 above, except that the pMOS-gated transistor 920 is formed in an NW 912, which is in turn formed in a DPW 910. Using only pMOS for the control transistor may allow for simpler fabrication of this embodiment. The cross-sectional view along section line B-B' in FIG. 9A is similar to the cross-sectional view of FIG. 8C.

[0086] 9B-9E illustrate a second variation of the embodiment described in connection with FIGS. 8A-8D. In this second variation, the constituent transistors of the inverter 806, along with the gate and recharge transistors, are located on one side of the pixel cell containing the SPAD. Such an embodiment allows for improved speed because the inverter implemented on the pixel cell uses high-voltage transistors, while the inverter located on the logic wafer can be implemented with low-voltage transistors, thus eliminating the need for a voltage level shifter between the outputs of the pixel cell 802. In the embodiment of FIGS. 9B-9E, the pixel cell's SPAD is formed with a mostly buried anode and cathode for the SPAD junction, as described below, and the transistors are formed on the front side of the pixel wafer. The cathode of the SPAD can extend through the front side, for example, to make electrical connection to the transistors thereon.

[0087] 9B shows a configuration 930 in which a pixel cell 932 of a pixel wafer includes a SPAD 934, an inverter 938, a pMOS recharge transistor 936, and an nMOS gating transistor 940. The pixel cell 932 is connected to a voltage supply line V DDL 931 and the voltage V supplied via contact 933 SPAD The pixel wafer containing pixel cells 932 may be bonded or coupled to a logic wafer 945. The gate of recharge transistor 936 is controlled by a signal applied through contact 937, and the gate of gating transistor 940 is controlled by a signal applied through contact 941.

[0088] 9B also shows a section of a logic wafer 945, which may be connected to the pixel cells 932 via metal-metal connections 939. Alternatively, the logic wafer 945 may be bonded or connected to the pixel wafer including the pixel cells 932 by through-silicon vias (TSVs), as described below in connection with FIG. 15C. The logic wafer 945 may include one shot 942 that generates a standard pulse based on the output of the pixel cells 932. The output of the one shot may then be received by a histogram counter 944. The logic wafer 945 may include a microcontroller, microprocessor, signal processor, memory, or other component that may use the data of the histogram counter to generate image information or other information.

[0089] 9C shows a two-transistor configuration 950 that can be used to implement inverter 938. An upper pMOS transistor 952 is stacked so that its drain connects to the source of a lower nMOS transistor 954. The source of the upper pMOS transistor 952 is coupled to a voltage V DD and the drain of the lower nMOS transistor 954 is connected to ground. IN 951 is applied to the gates of both transistors shown, the output signal V OUT 953 is the input signal V IN 951. With this implementation of inverter 938 in pixel cell 932, there are two nMOS transistors: the gate transistor 940 and the lower nMOS transistor of inverter 938, and two pMOS transistors: the recharge transistor 936 and the upper pMOS transistor of inverter 938.

[0090] FIG. 9D shows a configuration 960 of a gate transistor 940, a recharge transistor 936, an upper pMOS transistor 952, and a lower nMOS transistor 954 implemented on the front side (opposite the light-collecting backside) of a pixel cell 932. This configuration is a variation of the configurations shown in FIGS. 8B and 9A. The features also shown in FIGS. 8B and 9A and shown in FIG. 9D may be as described above. The pMOS transistors 936 and 952 are formed in separate n-type wells (NWs) 838a and 838b, respectively. The two NWs 838a and 838b are then formed in deep p-type wells (DPWs) 836a and 836b. In this embodiment, the DPWs may be formed as a single DPW, although this is not required.

[0091] 9D, two nMOS transistors 940 and 954 are formed in a common p-type well (PW) 955. PW 955 may be biased to ground (0V) at one or more locations, such as at connection pad 956. The output of inverter 938 may be connected to logic wafer 945 via connection 939, which may be a metal-to-metal connection or another type of connection.

[0092] The cross-sectional view along the indicated section line AA' in FIG. 9D is as shown for the corresponding features in FIG. 8C and will not be described again.

[0093] FIG. 9E shows a cross-sectional view 970 along section line B-B' of FIG. 9D. FIG. 9E shows that the sections of the n-type cathode 962 and p-type anode 964 that form the junctions of the SPAD 934 are formed below the semiconductor structure that forms four transistors: the inverter 938, the pMOS recharge transistor 936, and the nMOS gate transistor 940. The n-type cathode 962 and p-type anode 964 may be formed in a p-type body 966, which may be implemented by a doping gradient, as described above with respect to FIG. 1E. The sections of the n-type cathode 962 may extend to the front side (shown at the top of FIG. 9E) of the cathode electrode 824 (or the like).

[0094] Third family: Single transistor in a SPAD pixel cell

[0095] In this family of embodiments, the pixel cell is formed with a SPAD and a single control transistor. These embodiments can facilitate fabrication of corresponding pixel arrays. For example, the embodiments can require fewer interconnect pads to bond with the associated control circuit wafer.

[0096] 10A is a circuit diagram 1000 of a pixel array section of a pixel cell 1002 and associated external control circuitry. The pixel cell 1002 includes a SPAD 1004 and a pMOS high-voltage (HV) quenching transistor 1006. As previously mentioned, the control circuitry may be located on a separate wafer bonded to the pixel wafer containing the pixel cell 1002. The control circuitry includes a low-voltage quenching transistor 1010 with its source connected to a voltage source 1014, which may be at a level V DDL The drain of the low voltage quenching transistor 1010 connects to the pixel cell 1002 at the interconnect pad 1008a, through which the signal from the pixel cell 1002 is obtained. The signal from the pixel cell 1002 is conditioned (e.g., amplified or buffered) by the inverting buffer 1012 and can be sent to further logic circuitry, V OUT can be generated.

[0097] The anode of the SPAD1004 is connected to a bias voltage V SPAD The cathode of SPAD 1004 is connected to the drain of a pMOS HV quenching transistor 1006, which receives a control signal at its gate 1007 via interconnect pad 1008b.

[0098] FIG. 10B shows a plan view 1020 of the top surface of a pixel cell 1002 in a configuration that implements the circuit diagram of FIG. 10A. The pMOS HV quenching transistor 1006 is located at a corner of the pixel cell 1002 to increase the avalanche region within the SPAD 1004. The pixel cell 1002 may be formed with a surrounding insulating layer 302 and its bordering anode layer 304, as described in previous embodiments. The pixel cell 1002 may include an n-type cathode layer 1030 formed in a p-type semiconductor substrate 1028. The n-type cathode layer 1030 may have a cathode electrode 1032 connected to the drain of the pMOS HV quenching transistor 1006. The pMOS HV quenching transistor 1006 may be isolated from the n-type cathode layer 1030 by a shallow trench isolation (STI) well 1024. Within the STI well 1024, the pMOS HV quenching transistor 1006 is formed within a NW 1026. The NW 1026 may have a bias section (not shown for simplicity) supplied by a voltage source as described in the previous embodiment.

[0099] 10C is a cross-sectional view 1040 of the pixel cell 1002 taken along section line B-B' of FIG. 10B. The pMOS HV quenching transistor 1006 is separated from the anode layer 304 and from a section of the n-type cathode layer 1030 formed over the p-anode region 1042 by STI walls 1024a and 1024b formed in the NW 1026. The anode layer 304 is separated from the V SPAD 1044 connected to the

[0100] Figure 10D is a cross-sectional view 1050 of the pixel cell 1002 along section line CC' in Figure 10B. The n-type cathode layer 1030 and P anode region 1042 of the SPAD 1004 can extend over a large area within the pixel cell 1002, allowing for improved light detection efficiency. The p-type semiconductor substrate 1028 can have a doping gradient, as shown in Figure 10E.

[0101] Figure 10E is a cross-sectional view 1060 of pixel cell 1002 taken along section line A-A' in Figure 10B. The p-type semiconductor substrate 1028 has a doping gradient, as indicated by doping level contours 1062a-1062c, that can guide photo-induced charge carriers into an avalanche region formed at the junction of the n-type cathode layer 1030 and the P anode region 1042.

[0102] Family 4: Transistors external to the pixel cell

[0103] In the family of embodiments described above, one or more control transistors are formed within the pixel cell, such as in an insulating layer 302 that may isolate individual pixel cells within the pixel array. In these embodiments, the control transistors are operatively or electrically isolated from the SPAD of the pixel cell by either being formed in a shallow trench isolation well or by being formed in a deep n-type or p-type well.

[0104] In a fourth family, embodiments are described for pixel wafers that include both pixel cells and their one or more respective control transistors. These embodiments can utilize deep trench isolation (DTI) to provide isolation between pixel cells and their associated control transistors. The DTI provides isolation of the pixel wafer into pixel regions and transistor regions separated by the DTI. Using DTI, an insulating material, such as oxide, is formed as a vertical wall from the top surface of the pixel wafer to or near the back (illuminated) side of the pixel wafer.

[0105] 11 shows a plan view of a portion of a pixel wafer 1100. The pixel wafer 1100 is formed as a rectangular array of pixel cells, such as pixel cell 1102, separated by DTI walls, such as DTI wall 1104a. Within pixel cell 1102, as previously described, is a boundary anode layer 304. The anode layer 304 is connected to interconnect pad 1008c via electrode 1108. A bias voltage V SPADmay be applied to the pixel cell 1102. The pixel cell 1102 includes a SPAD, and the combination of the SPAD in the pixel cell 1102 and the single associated pMOS quenching transistor 1006 implements the circuitry in the pixel cell 1002 of Figure 10A.

[0106] Within pixel cell 1102, the SPAD is formed as an n-type cathode layer 1105 disposed on a p-type anode layer. The n-type cathode layer 1105 is connected to the pMOS HV quenching transistor 1006 by connecting the cathode electrode 1106 to the drain of the pMOS HV quenching transistor 1006, as previously described. A vertical cross section through the center of pixel cell 1102 is similar to cross section 1050 in Figure 10D.

[0107] The pMOS HV quenching transistor 1006 is formed in a rectangular transistor that is separated from the array of pixel cells by a DTI wall 1104b. The configuration shown in pixel wafer 1100 can provide better noise and signal isolation between the pixel cells 1102 and the pMOS HV quenching transistor 1006.

[0108] 12A shows a plan view of a section of a pixel array 1200 implementing a variation of the embodiment of FIG. 11. The pixel wafer 1200 is formed as a rectangular array of pixel cells, such as pixel cell 1202, separated by DTI walls, such as DTI wall 1204a. Within pixel cell 1202 is a boundary anode layer 304, as previously described. The anode layer 304 is connected to interconnect pad 1008c via electrode 1208, which applies a bias voltage V SPAD can be applied. Pixel cell 1202 includes a SPAD. The SPAD has an n-type cathode layer 1205 located near the top surface of pixel cell 1202. Cathode electrode 1206 has a connection 1207 to a control transistor located in transistor region 1209, shown in more detail in FIG. 12B. The combination of the SPAD in pixel cell 1202 and the single control transistor in transistor region 1209 implements the circuitry in pixel cell 1002 of FIG. 10A.

[0109] The DTI walls 1204b surround the transistor region 1209. The DTI walls 1204b are oriented diagonally relative to the horizontal and vertical axes that define the rectangular array of pixels. Such a diagonal or diamond-shaped configuration of the transistor region 1209 can provide increased area within the pixel cell 1202.

[0110] 12B shows an expanded plan view of transistor region 1209 including pMOS HV quenching transistor 1006 associated with pixel cell 1202. pMOS HV quenching transistor 1006 is formed in NW 1212 and has its drain connected to connection 1207 as shown.

[0111] FIG. 13A shows a plan view of a portion of a pixel wafer 1300. The pixel wafer 1300 includes a rectangular array of pixel cells, such as pixel cell 1302. Horizontally oriented transistor regions 1306a-1306c alternate with the columns of the rectangular array of pixel cells. Horizontal DTI walls, such as horizontal DTI walls 1304a and 1304b, form separation between the transistor regions 1306a-1306c and the columns of the rectangular array of pixel cells. Vertical DTI walls, such as vertical DTI wall 1304c, form separation between pixel cells within each column of the rectangular array of pixel cells. For each pixel cell, transistor regions 1306a-1306c are for respective pMOS recharge and gate transistors configured to form circuitry within the pixel cell, as described in detail below.

[0112] Pixel cell 1302 includes a SPAD formed of an n-type cathode layer 1305 on a p-anode layer formed below the n-type cathode layer 1305. Pixel cell 1302 has an anode layer 304, as previously described, bounded by a DTI wall. The anode layer 304 is coupled from an anode electrode 1308 to interconnect pad 212d, as previously described. A vertical cross section through the center of pixel cell 1302 is similar to cross section 1050 in FIG. 10D. Cathode electrode 1310 has connections 1312a and 1312b to corresponding pMOS recharge and nMOS gate transistors in transistor region 1306a.

[0113] Figure 13B shows an expanded plan view 1320 of transistor section 1306a of pixel wafer 1300. Within transistor section 1306a is a pMOS HV quenching transistor 216 arranged in series with an nMOS gating transistor 218, connected to form a circuit that may be located within pixel cell 210 of Figure 2. The pMOS HV quenching transistor 216 is formed within NW 1324, which is formed within DNW 1322. The nMOS gating transistor 218 is formed within NW 1326.

[0114] Further, pMOS recharge transistors and nMOS gating transistors may be sequentially disposed within transistor region 1306a and associated with other pixel cells in the top row of pixel cells shown in FIG. 13A. Similarly, further pMOS recharge transistors and nMOS gating transistors may be sequentially disposed within transistor region 1306a and associated with other pixel cells in the second row of pixel cells shown in FIG.

[0115] FIG. 14A shows a plan view of a pixel array 1400. The pixel array 1400 is configured as a variation of the embodiment described in connection with FIGS. 13A-13B. The SPAD in each pixel cell is adapted to connect with three control transistors located within the transistor region to form the circuit shown in FIG. 8A within pixel cell 802. The pixel array 1400 includes a rectangular array of pixel cells, such as pixel cell 1402. Horizontally oriented transistor regions 1406a-1406b alternate with columns of the rectangular array of pixel cells. Horizontal DTI walls, such as horizontal DTI walls 1404a and 1404b, form separations between the transistor regions 1406a-1406b and the columns of the rectangular array of pixel cells. Vertical DTI walls, such as vertical DTI walls 1404c-1404d, form separations between pixel cells within each column of the rectangular array of pixel cells, forming transistor regions, such as transistor region 1406c, between pixel cells in the columns of the rectangular array of pixel cells.

[0116] The pixel cell 1402 may include an anode layer, as described above, adjacent to the DTI walls surrounding the pixel cell 1402. The pixel cell 1402 includes a SPAD having an n-type cathode layer 1408 connected via a cathode electrode 1410 to three control transistors located in transistor regions 1406a and 1406c, as shown in detail in FIG. 14B. In the illustrated embodiment, the nMOS gating transistor 820 and pMOS recharge transistor 818 associated with the pixel cell 1402 are located in the horizontally extending transistor region 1406a, and the internal pMOS transistor 814 associated with the pixel cell 1402 is located in the transistor region 1406c.

[0117] Figure 14B shows an enlarged plan view 1420 of pixel cell 1402 and transistor regions 1406a and 1406c of pixel array 1400. The configuration and connections shown in plan view 1420 implement the circuitry within pixel cell 802 of Figure 8A. The n-type cathode layer 1408 of the SPAD of pixel cell 1402 is connected by connection 1412a from the cathode electrode 1410 to the drain of nMOS gating transistor 820. The nMOS gating transistor 820 is formed within a PW 1424 formed within a DNW 1422. The n-type cathode layer 1408 of the SPAD of pixel cell 1402 is connected by connection 1412b from the cathode electrode 1410 to the drain of pMOS recharge transistor 818. The pMOS recharge transistor 818 is formed within a NW 1426. The internal pMOS transistor 814 is formed in transistor region 1406c in NW 1428 and is connected by connecting line 1412b to cathode electrode 1410. In other embodiments, the connections of the remaining components shown in Figure 14B are as described in the circuit diagram shown in Figure 8A.

[0118] Fifth Family: Control Transistors on Separate Wafers

[0119] Another set of embodiments is directed to a light-sensing and imaging device formed by bonding three different wafers: a pixel array wafer containing an array of pixel cells; a control circuit wafer that may contain bias and control circuit elements such as control transistors; and a logic wafer that may contain processing components. Such processing components may include, but are not limited to, filters, histogram counters, image or other digital processors, microprocessors, or further components. The control circuit wafer may include circuit elements such as gate or control transistors for SPADs in the pixel cells that may operate from a high-voltage source. Certain control transistors may be used to implement inverter circuits whose outputs are connected to the logic wafer.

[0120] 15A is a circuit diagram of an arrangement 1500 of certain components of a control circuit wafer 1504 disposed between a logic wafer 1502 corresponding to a SPAD 1508 and a pixel array wafer 1506. The wafers may be formed in separate semiconductor substrates, which may be either n-type or p-type. The logic wafer 1502 receives a voltage signal V BP The pMOS quenching transistor 1509 is coupled to a low-level power supply voltage V on a power supply line 1512a. DDL The drain of the pMOS quenching transistor connects to the control circuit wafer via interconnect pad 1510a. The logic circuit wafer 1502 may include additional circuit elements.

[0121] The pixel array wafer 1506 may include an array of pixel cells, at least some of which may include SPADs, such as SPAD 1508, for light detection. The pixel cells 1506 are connected to a bias voltage source V 1510e, which is supplied to the control circuit wafer 1504 through through silicon vias (TSVs) 1519a via interconnect pads 1510e. SPAD The anode of SPAD 1508 can be connected to the control circuit wafer 1504 by another TSV 1519b. The cathode of SPAD 1508 can be connected to a bias voltage source V SPAD can be connected to.

[0122] Control circuit wafer 1504 may include control transistors that control the light gathering or detecting operation of each SPAD on pixel array wafer 1506. In the illustrated embodiment, control circuit wafer 1504 includes three control transistors that implement the control circuit shown in FIG. 8A. There is a pMOS recharge transistor 1514 having a gate 1513 coupled to interconnect pad 1510c that receives input from an external control circuit, a pMOS high voltage quenching transistor 1518 having a gate 1517 connected to interconnect pad 1510b, and an nMOS gating transistor 1516 having a gate 1515 connected to interconnect pad 1510d. The description of these transistors and their interconnections is similar to that described with respect to FIG. 8A and will not be repeated here.

[0123] 15B is an expanded plan view 1520 showing the configuration of a pixel cell including SPAD 1508 and the configuration or layout of pMOS recharge transistor 1514, pMOS high-voltage quenching transistor 1518, and nMOS gating transistor 1516. nMOS gating transistor 1516 is formed within PW 1528, which is formed within DNW 1526. pMOS high-voltage quenching transistor 1518 is formed within NW 1530. pMOS recharge transistor 1514 is formed within NW 1532.

[0124] Figure 15C is a cross-sectional view 1540 of the control circuit wafer 1504 bonded or joined to the pixel array wafer 1506, taken along section line A-A' in Figure 15B. The SPADs 1508 may be formed as the junction of an n-type cathode layer 1508a and a p-anode layer 1508b. The pixel cells of the SPADs 1508 may be isolated from other pixel cells of the pixel array wafer 1506 by the insulating layer 302, as described above. Within the insulating layer 302 may be the anode layer 304, as described above. The semiconductor substrate within the pixel cells may be p-type and may have a doping gradient, as indicated by the doping contours 1507a-1507c.

[0125] Pixel array wafer 1506 can be bonded or bonded with intermediate layer 1541 to form a first combined layer 1542 that is bonded or bonded to control circuit wafer 1544. TSVs 1519 can provide electrical connections between SPADs 1508 and the control transistors of control circuit wafer 1544. Logic circuit wafer 1502 can be bonded or bonded to top surface 1546 of control circuit wafer 1544.

[0126] Within control circuit wafer 1544, pMOS high voltage quenching transistor 1518 may be disposed on insulating structure 1548a and nMOS gating transistor 1516 may be disposed on insulating structure 1548b. Node 1521 may be implemented as a conductor buried in the semiconductor substrate of control circuit wafer 1504.

[0127] Figure 16 shows a variation of the embodiment described in connection with Figures 15A-15C. The embodiment of Figure 16 uses three bonded or joined wafers: a pixel wafer containing an array of SPAD pixel cells without control transistors, an intermediate wafer containing control transistors that may be high voltage, and a logic wafer. The embodiment of Figure 16 differs from Figures 15A-15C in that the transistors for the inverter are located on the intermediate wafer. As described below, the SPAD pixel may be implemented as disclosed in connection with Figure 15B, and the configuration of the gate transistors, recharge transistors, and inverter transistors may be implemented as disclosed in connection with Figure 9D.

[0128] FIG. 16 shows a component configuration 1600 of logic wafer 1601, intermediate wafer 1605, and pixel wafer 1611. Intermediate wafer 1605 includes control transistors for one or more SPADs located on pixel wafer 1611. In this embodiment, pixel wafer 1611 includes an array of pixel cells, each including a SPAD, such as SPAD 1612. In this embodiment, intermediate wafer 1605 includes at least recharge transistor 1606, gating transistor 1610, and inverter 1608. Inverter 1608 may be formed as stacked pMOS and nMOS transistors, as shown in FIG. 9C, or may be implemented with another configuration of transistors. Pixel wafer 1611 may be bonded to intermediate wafer 1605 by through-silicon vias 1613a and 1613b, by metal-to-metal connections such as 1603 connecting logic wafer 1601 to intermediate wafer 1605, or by another structure. Logic wafer 1601 includes at least one shot 1602 and generates a standard pulse based on a signal received from inverter 1608. The standard pulse is received by histogram counter 1604. In addition to histogram counter 1604, logic wafer 1601 may include other associated logic circuits such as a microprocessor, microcontroller, signal processor, memory unit, etc. that may operate to generate image data.

[0129] In an embodiment of configuration 1600, at least some of the pixel cells of pixel array 1611 do not include an associated control transistor. In this embodiment, such pixel cells may have the structure shown in FIG. 15B and described above.

[0130] In intermediate wafer 1605 of configuration 1600, the two transistors of recharge transistor 1606, gate transistor 1610, and inverter 1608 may be arranged and implemented with the semiconductor structure shown in FIG. 9D and described above. In intermediate wafer 1605, such an implementation of four transistors may use the same or alternative structures to isolate each set of four transistors associated with SPAD 1612.

[0131] In the foregoing description, for purposes of explanation, specific terminology was used to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that specific details are not required to practice the described embodiments. Thus, the foregoing descriptions of the specific embodiments described herein have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. It will be apparent to those skilled in the art that many modifications and variations are possible in light of the above teachings.

Claims

1. A pixel of the pixel array, the pixels each having an insulating wall that forms a side surface of the pixel and extends at least partially through a semiconductor substrate of the pixel array between a top surface of the pixel array and a light collecting surface of the pixel array opposite the top surface; a single-photon avalanche diode (SPAD) including a cathode layer adjacent the top surface and an anode layer adjacent a side of the cathode layer within the semiconductor substrate opposite the top surface; a control transistor adjacent to the top surface and electrically connected to the SPAD.

2. the control transistor is a first control transistor; the pixel further comprises a second control transistor; the first control transistor is a gating transistor; The pixel of claim 1 , wherein the second control transistor is a quenching transistor electrically connected to the SPAD.

3. a shallow trench isolation material extending at least partially into the semiconductor substrate from the top surface; the shallow trench isolation material separates the first region of the pixel, the second region of the pixel, and the third region of the pixel; the quenching transistor is formed in the first region; the anode layer and the cathode layer of the SPAD are at least partially formed in the second region; The pixel of claim 2 , wherein the gating transistor is formed in the third region.

4. the gate transistor is an nMOS transistor, the first region includes an n-well region; 4. The pixel of claim 3, wherein the third region comprises a deep n-well region and a p-well region formed within the deep n-well region.

5. the gating transistor is a first pMOS transistor; the quenching transistor is a second pMOS transistor; the first region includes a first n-well region; the third region includes a second n-well region; the quenching transistor is formed in the first n-well region; The pixel of claim 3, wherein the gating transistor is formed in the second n-well region.

6. a p-well region; and a deep p-well region separated from the p-well region; the deep p-well region includes an interior n-well region; the quenching transistor is a pMOS transistor formed in the internal n-well region; The pixel of claim 2 , wherein the gate transistor is an nMOS transistor formed in the p-well region.

7. further comprising a first p-well region and a second p-well region; the quenching transistor is a first nMOS transistor formed in the first p-well region; The pixel of claim 2 , wherein the gating transistor is a second nMOS transistor formed in the second p-well region.

8. a first deep n-well region including a first p-well region, and a second deep n-well region including a second p-well region; the semiconductor substrate is n-type; the quenching transistor is a first nMOS transistor formed in the first p-well region; The pixel of claim 2 , wherein the gating transistor is a second nMOS transistor formed in the second p-well region.

9. the control transistor is a first control transistor, the pixel further includes a second control transistor; the pixel further includes a third control transistor; the first control transistor is a quenching transistor electrically connected between a first voltage source and a cathode of the SPAD; the second control transistor is a recharge transistor; the third control transistor is a gating transistor; the recharge transistor is connected in series with the gating transistor between a second voltage source and a third voltage source at a common node; The pixel of claim 1 , wherein the cathode of the SPAD is connected to the common node.

10. a deep p-well region including a first n-well region, a second n-well region separated from the first n-well region, and a p-well region; the gate transistor is an nMOS transistor formed in the p-well region, the recharge transistor is a first pMOS transistor formed in the first n-well region; The pixel of claim 9, wherein the quenching transistor is a second pMOS transistor formed in the second n-well region.

11. a first deep p-well region including the first n-well region, a second deep p-well region including the second n-well region, and a third deep p-well region including the third n-well region; the gate transistor is a first pMOS transistor formed in the first n-well region; the recharge transistor is a second pMOS transistor formed in the second n-well region; The pixel of claim 9, wherein the quenching transistor is a third pMOS transistor formed in the third n-well region.

12. a shallow trench isolation material extending at least partially into the semiconductor substrate from the top surface; the shallow trench isolation material separates the first region of the pixel, the second region of the pixel, and the third region of the pixel; the quenching transistor is formed in the first region; the anode layer and the cathode layer of the SPAD are formed at least partially within the second region; The pixel of claim 9 , wherein the gating transistor and the recharging transistor are formed in the third region.

13. a shallow trench isolation material extending at least partially into the semiconductor substrate from the top surface; the shallow trench isolation material separating the first region of the pixel from the second region of the pixel; the control transistor is formed in the first region; The pixel of claim 1 , wherein the anode layer and the cathode layer of the SPAD are at least partially formed in the second region.

14. a pixel wafer having a top surface and a back surface opposite the top surface, a semiconductor substrate; a rectangular array of pixel cells; a plurality of transistor regions; a deep trench isolation material extending into the semiconductor substrate from the top surface of the pixel wafer adjacent the back surface; each pixel cell of the rectangular array of pixel cells includes a single photon avalanche diode (SPAD); Each transistor region is associated with a corresponding pixel cell; each transistor region includes a control transistor electrically connected to the SPAD of the corresponding pixel cell with which the transistor region is associated; the deep trench isolation material forms a peripheral sidewall of each pixel cell of the rectangular array of pixel cells; each transistor region is separated from each pixel cell in the rectangular array of pixel cells by the deep trench isolation material; the SPAD of each pixel cell of the rectangular array of pixel cells is formed with an n-type cathode adjacent the top surface and a p-type anode formed below the n-type cathode on an opposite side of the top surface; the semiconductor substrate is p-type with a doping gradient; The control transistor of each transistor region controls the light-gathering operation of the SPAD of the corresponding pixel cell with which the transistor region is associated.

15. each transistor region is formed as a rectangular region oriented parallel to the rectangular array of pixel cells and located at a grid point of the rectangular array of pixel cells; 15. The pixel wafer of claim 14, wherein the control transistor is a pMOS transistor connected between the n-type cathode of the SPAD and a voltage source.

16. each transistor region is a rectangular region located at a grid point location of said rectangular array of pixel cells and oriented diagonally with respect to said rectangular array of pixel cells; 15. The pixel wafer of claim 14, wherein the control transistor is a pMOS transistor connected between the n-type cathode of the SPAD and a voltage source.

17. a first transistor region of the plurality of transistor regions arranged parallel to a first column of the rectangular array of pixel cells; the control transistor of the first transistor region is an nMOS gate transistor connected between the n-type cathode of the SPAD of the corresponding pixel cell and a first voltage source; 15. The pixel wafer of claim 14, wherein the first transistor region comprises a pMOS quenching transistor connected between the n-type cathode of the SPAD of the corresponding pixel cell and a second voltage source.

18. a second transistor region disposed in the first column of the rectangular array of pixel cells between the corresponding pixel cell and an adjacent pixel cell; 20. The pixel wafer of claim 17, wherein the second transistor region includes a pMOS fast recharge transistor connected between the n-type cathode of the SPAD of the corresponding pixel cell and a third voltage source.

19. a pixel wafer including an array of pixel cells, a pixel wafer in which at least one of the pixel cells includes a single photon avalanche diode (SPAD); a control transistor wafer including a first side bonded to the pixel wafer, a second side opposite the first side, and a group of control transistors including at least two of a recharge transistor, a gating transistor, or a quenching transistor; a logic wafer bonded to the second side of the control transistor wafer and including circuit components for receiving electrical signals from the control transistor wafer; the group of control transistors controls the light detection operation of the SPAD; A photodetector device, wherein the electrical signal is based on the photodetection operation.

20. the gate transistor is an nMOS transistor formed in a p-type well, the p-type well is formed within a deep n-type well; the recharge transistor is a first pMOS transistor formed in a first n-type well; the quenching transistor is a second pMOS transistor formed in a second n-type well; the drain of the gating transistor, the drain of the recharging transistor, and the drain of the quenching transistor are connected to a node in the control transistor wafer; 20. The photodetector device of claim 19, wherein the cathode of the SPAD is connected to the node.

21. the group of control transistors further includes a first transistor and a second transistor; the first transistor and the second transistor form an inverter circuit; 20. The photodetector device of claim 19, wherein the cathode of the SPAD is connected to the input of the inverter circuit.

22. a pixel wafer having a top surface and a back surface opposite the top surface, a semiconductor substrate and a rectangular array of pixel cells; At least one pixel cell includes a single photon avalanche diode (SPAD) including a cathode and an anode formed in the semiconductor substrate, and a group of control transistors formed adjacent the top surface; a pixel wafer, wherein the group of control transistors includes a recharge transistor of the SPAD, a gating transistor of the SPAD, and first and second transistors forming an inverter circuit having an input connected to the cathode of the SPAD.

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