Semiconductor device

Abstract

To increase the opening ratio of a semiconductor device.SOLUTION: A semiconductor device has a drive circuit part having a drive circuit, and a pixel part having a pixel on the same substrate. The pixel includes a light-transmissive gate electrode layer, a gate insulating layer, a light-transmissive source electrode layer and drain electrode layer disposed on the gate insulating layer, an oxide semiconductor layer disposed on the gate electrode layer with the gate insulating layer sandwiched between them to cover an upper surface and a side surface of the source electrode layer and an upper surface and a side surface of the drain electrode layer, a conductive layer which is disposed on a part of the oxide semiconductor layer and is lower in resistance than the source electrode layer and a second drain electrode layer, and an oxide insulating layer in contact with a part of the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. Thin film transistors (also called TFTs) Thin-film transistors are used in electronic devices such as ICs and electro-optical devices. It is widely used in various devices, and development is particularly urgent as a switching element for image display devices. Metal oxides exist in a wide variety of forms and are used in a variety of applications. Indium nitride is a well-known material that is used in transparent electrodes such as those required for liquid crystal displays. It is used as a polar material.

[0004] Some metal oxides exhibit semiconducting properties. Examples of oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin film transistors using metal oxides with such semiconducting properties as the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] When a driver circuit is formed on an insulating surface, the operating speed of a thin film transistor used in the driver circuit is , faster is preferable.

[0007] For example, the channel length (also called L) of a thin film transistor can be shortened, or the channel width (W However, if the channel length L is shortened, There is a problem that the switching characteristics, for example, the on-off ratio, becomes small. If the capacitance is increased, the capacitance load of the thin film transistor itself increases.

[0008] One embodiment of the present invention is a thin film transistor having stable electrical characteristics even when the channel length is short. It is another object of the present invention to provide a semiconductor device including the above.

[0009] In addition, when forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit may be formed on the same substrate. When formed on a substrate, the thin film transistor used in the pixel area must have excellent switching characteristics, For example, a large on-off ratio is required, and thin film transistors used in drive circuits are In particular, the higher the resolution of the display device, the faster the display image becomes. Since the writing time is shortened, the thin film transistors used in the driving circuit can be made to operate at a high speed. It is preferable that

[0010] In addition, one embodiment of the present invention is to prevent a complicated process and an increase in manufacturing cost. Multiple types of circuits are formed on the substrate, and multiple types of thin film transistors are used to match the characteristics of each of the multiple types of circuits. An object of the present invention is to provide a semiconductor device including a transistor. [Means for solving the problem]

[0011] One embodiment of the present invention is a display device having a driver circuit and a pixel portion (also referred to as a display portion) over the same substrate. The driving circuit and the pixel section each have a thin film transistor. The manufacturing cost can be reduced by fabricating the pixel portion.

[0012] In addition, a thin film transistor for a driving circuit and a thin film transistor for a pixel are formed on the same substrate. It is possible to manufacture display devices such as liquid crystal displays.

[0013] In one embodiment of the present invention, a thin film transistor (also referred to as a first thin film transistor) of a driving circuit The thin film transistor in the pixel portion (also called the second thin film transistor) is a semiconductor layer having a gate electrode, a source electrode, a drain electrode, and a channel forming region; The thin film transistor in the pixel portion is a bottom gate type thin film transistor including a Inverted coplanar type (bottom contact type) with a semiconductor layer overlapping the source and drain electrodes It is a thin film transistor (also called a GaN thin film transistor).

[0014] In one embodiment of the present invention, a gate electrode, a source electrode, and a drain electrode of a thin film transistor in a pixel portion are The drain electrode is made of a conductive layer having light-transmitting properties, and the semiconductor layer is made of a semiconductor layer having light-transmitting properties. That is, the gate electrode, source electrode, drain electrode of the thin film transistor are The gate electrode and the semiconductor layer are light-transmitting, which improves the aperture ratio of the pixel portion.

[0015] In one embodiment of the present invention, the gate electrode of the thin film transistor of the driver circuit is It is made of a material with a lower resistance than the material used for the gate electrode of a thin film transistor. The source and drain electrodes of the thin film transistors of the driver circuit are connected to the thin film transistors of the pixel section. The material is made of a material with a lower resistance than the source and drain electrodes of the transistor. The gate electrode, source electrode, and drain electrode of the thin film transistor in the driving circuit The resistance values ​​are the resistance values ​​of the gate electrode, source electrode, and drain electrode of the thin film transistor in the pixel portion. The resistance value of each of the gate electrodes is lower than that of the gate electrodes, thereby improving the operating speed of the drive circuit.

[0016] In one embodiment of the present invention, the thin film transistor of the driver circuit includes a semiconductor layer and a source electrode. A structure having a conductive layer between the semiconductor layer and the drain electrode and between the semiconductor layer and the drain electrode may also be used. The resistance of the layer is preferably lower than that of the semiconductor layer and higher than that of the source electrode and the drain electrode. It's nice.

[0017] In one embodiment of the present invention, the thin film transistor in the pixel portion has a drain electrode layer and a pixel electrode layer. The conductive layer is a layer between the drain electrode layer and the pixel electrode layer. This is intended to reduce contact resistance, and it is preferable that the resistance be lower than that of the drain electrode layer.

[0018] One embodiment of the present invention is a semiconductor device in which a driver circuit portion in which a driver circuit is provided and pixels are provided over the same substrate. a pixel portion, a first gate electrode layer provided in the drive circuit portion, and a second gate electrode layer provided in the pixel portion. a second gate electrode layer having a light-transmitting property and a second gate electrode layer having a light-transmitting property; A gate insulating layer is provided on the gate electrode layer, and the first gate insulating layer is provided between the gate insulating layer and the first gate electrode. a first oxide semiconductor layer provided on a gate electrode layer; and a first source electrode layer and a first drain electrode layer provided thereon; a second source electrode layer and a second drain electrode layer, which are provided on the gate insulating layer and have light-transmitting properties; a gate electrode layer and a second gate electrode layer, the second gate electrode layer being disposed on the gate insulating layer, the upper surface and side surface of the second source electrode layer and the upper surface and side surface of the second drain electrode layer. a second oxide semiconductor layer; and a second oxide semiconductor layer provided on a portion of the second oxide semiconductor layer. a conductive layer having a lower resistance than the source electrode layer and the second drain electrode layer; an oxide insulating layer in contact with a portion of the oxide semiconductor layer and a portion of the second oxide semiconductor layer; It is a semiconductor device.

[0019] In one embodiment of the present invention, the first source electrode layer and the first drain electrode layer are Boron, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and and scandium as the main component of a metal material or an alloy material. It may be a single layer or a multilayer.

[0020] In one embodiment of the present invention, the second source electrode layer and the second drain electrode layer are Indium oxide, indium oxide tin oxide alloy, indium oxide zinc oxide alloy, or zinc oxide It may also be a layer of lead.

[0021] In one aspect of the present invention, the conductive layer is made of molybdenum, titanium, chromium, tantalum, or tantalum. The main components are selected from the group consisting of tin, aluminum, copper, neodymium, and scandium. The insulating layer may be a single layer or a multilayer of layers made of a metal material or an alloy material.

[0022] In one aspect of the present invention, the pixel has a capacitance part, and the capacitance part includes a capacitance wiring and the capacitance The capacitor may have a capacitance electrode overlapping with a capacitance wiring, and the capacitance wiring and the capacitance electrode may be light-transmitting. stomach.

[0023] In one embodiment of the present invention, It may have a conductive layer.

[0024] In one embodiment of the present invention, the first oxide semiconductor layer and the first source electrode layer or An oxide conductive layer may be provided between the first drain electrode layer and the second drain electrode layer.

[0025] In one embodiment of the present invention, the oxide conductive layer is made of indium oxide, indium oxide sintered body, or the like. The layer may be a zinc alloy, an indium oxide zinc oxide alloy, or a zinc oxide layer.

[0026] One embodiment of the present invention is a method for manufacturing a semiconductor device in which a driver circuit portion and a pixel portion are formed over the same substrate. a first gate electrode layer is formed on the substrate in the driving circuit section; A second gate electrode layer is formed on the substrate in the elemental portion using a light-transmitting material. , the first gate electrode layer of the driving circuit section and the second gate electrode layer of the pixel section a gate insulating layer formed on the pixel portion; A second source electrode layer and a second drain electrode layer are formed using a material, and the gate insulating layer and forming an oxide semiconductor film on the substrate, and etching a portion of the oxide semiconductor film. and a gate insulating layer is sandwiched between the first gate electrode layer and the second gate electrode layer in the drive circuit section. a first oxide semiconductor layer formed on the first insulating film and sandwiching the gate insulating layer in the pixel portion; the second gate electrode layer in the pixel portion; and forming a second oxide semiconductor layer covering an upper surface and a side surface of the second drain electrode layer; The first oxide semiconductor layer and the second oxide semiconductor layer are dehydrated or dehydrated by heat treatment. and forming a gate insulating film between the first oxide semiconductor layer and the second oxide semiconductor layer. A conductive film is formed on the edge layer, and a part of the conductive film is etched to form the first forming a first source electrode layer and a first drain electrode layer on a part of the oxide semiconductor layer; and forming a conductive layer on a part of the second oxide semiconductor layer, and forming an oxide insulating layer on the second oxide semiconductor layer, and forming a front insulating layer on a portion of the oxide insulating layer. A contact hole is formed in the conductive layer, and a light-transmitting conductive film is formed on the oxide insulating layer. and forming a pixel electrode layer by etching a part of the light-transmitting conductive film. The present invention relates to a method for manufacturing a semiconductor device in which a

[0027] One embodiment of the present invention is a method for manufacturing a semiconductor device in which a driver circuit portion and a pixel portion are formed over the same substrate. a first gate electrode layer is formed on the substrate in the driving circuit section; A second gate electrode layer is formed on the substrate in the elemental portion using a light-transmitting material. , the first gate electrode layer of the driving circuit section and the second gate electrode layer of the pixel section a gate insulating layer formed on the pixel portion; A second source electrode layer and a second drain electrode layer are formed using a material, and the gate insulating layer and forming an oxide semiconductor film on the substrate, and etching a portion of the oxide semiconductor film. and a gate insulating layer is sandwiched between the first gate electrode layer and the second gate electrode layer in the drive circuit section. a first oxide semiconductor layer formed on the first insulating film and sandwiching the gate insulating layer in the pixel portion; the second gate electrode layer in the pixel portion; forming a second oxide semiconductor layer covering the upper and side surfaces of the first oxide semiconductor layer and the drain electrode layer; the oxide semiconductor layer and the second oxide semiconductor layer are dehydrated or dehydrogenated by heat treatment, An oxide semiconductor film is formed on the gate insulating layer with the first oxide semiconductor layer and the second oxide semiconductor layer sandwiched therebetween. forming a conductive film on the oxide conductive film; forming a conductive film on the oxide conductive film; By etching a part of the conductive film, a conductive film is formed on a part of the first oxide semiconductor layer. forming a first oxide conductive layer and a second oxide conductive layer, and a first source electrode layer on a portion of the oxide conductive layer; and a second source electrode layer on a portion of the second oxide conductive layer. a first drain electrode layer formed on the second oxide semiconductor layer; and a conductive layer formed on a portion of the second oxide semiconductor layer. and forming an oxide insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer. forming a contact hole in a part of the oxide insulating layer that leads to the conductive layer; A light-transmitting conductive film is formed over the oxide insulating layer, and a part of the light-transmitting conductive film is This is a method for manufacturing a semiconductor device in which a pixel electrode layer is formed by etching.

[0028] The oxide semiconductor used in this specification includes, for example, InMO3(ZnO)m(m> 0) and a thin film transistor using the thin film as an oxide semiconductor layer. Here, M is a metal element selected from Ga, Fe, Ni, Mn, and Co. It indicates multiple metal elements. For example, M can be Ga, or Ga and Ni, or In some cases, the oxide semiconductor may contain Ga and Fe, as well as other metal elements. In conductors, in addition to the metal elements contained as M, impurity elements such as Fe, Ni, and others are also present. In this specification, the transition metal element or the oxide of the transition metal is contained. is an oxide of the structure represented by InMO3(ZnO)m (m>0 and m is not an integer). Among the oxide semiconductor layers, the oxide semiconductor with a structure containing Ga as M is an In-Ga-Zn-O oxide. These thin films are also called In-Ga-Zn-O semiconductor films.

[0029] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn—O-based, and Zn—O-based oxide semiconductors can be used. The oxide semiconductor layer made of a silicon oxide may contain silicon oxide.

[0030] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), dehydration is performed. Hydrogenation or dehydrogenation is effective.

[0031] In addition, in the manufacturing process of the semiconductor device, nitrogen or a rare gas (argon, helium, etc.) When heat treatment is performed under an inert gas atmosphere, the oxide semiconductor layer It becomes oxygen deficient and has low resistance, that is, it becomes N-type (N - Then, the oxide semiconductor layer is The oxide insulating layer is formed in contact with the oxide semiconductor layer, and the oxide semiconductor layer is made to have an oxygen-excess state. This makes the semiconductor layer highly resistive, i.e., I-type. This results in good electrical properties. It becomes possible to manufacture and provide a semiconductor device having a highly reliable thin film transistor. .

[0032] In the manufacturing process of the semiconductor device, nitrogen or a rare gas (argon, helium, etc.) ) in an inert gas atmosphere at 350°C or higher, preferably 400°C or higher and 700°C or lower, Preferably, heat treatment is performed at a temperature higher than or equal to 420° C. and lower than or equal to 570° C. to reduce the moisture content of the oxide semiconductor layer. This reduces impurities such as those mentioned above. It also prevents subsequent re-impregnation with water (H2O).

[0033] Dehydration or dehydrogenation heat treatment must be carried out in a nitrogen atmosphere with an H2O concentration of 20 ppm or less. Alternatively, the process may be carried out in ultra-dry air with an H2O concentration of 20 ppm or less.

[0034] The dehydrated or dehydrogenated oxide semiconductor layer was analyzed by thermal desorption spectroscopy (also known as TDS). Even when measurements were taken up to 50°C, two peaks of water were observed, and at least one peak appeared near 300°C. Therefore, the thin film using the dehydrated or dehydrogenated oxide semiconductor layer was not detected. Even when measuring a film transistor up to 450°C using TDS, the temperature remains at least around 300°C. No apparent water peak is detected.

[0035] In the manufacturing process of the semiconductor device, the oxide semiconductor layer is prevented from being exposed to the air. It is important not to reconstitute the oxide semiconductor layer with water or hydrogen. The oxide semiconductor layer is then made low-resistance, i.e., N-type (N - After the oxidation, oxygen is supplied. When a thin film transistor is fabricated using an oxide semiconductor layer that has high resistance, The threshold voltage value of the thin film transistor can be made positive, and the so-called normally-off A switching element can be realized. The gate voltage of the thin film transistor is as close to 0V as possible. It is desirable that a channel is formed at a positive threshold voltage. If the threshold voltage is negative, even if the gate voltage is 0V, For example, in an active matrix type In display devices, the electrical characteristics of the thin film transistors that make up the circuits are important. The electrical characteristics of thin film transistors affect the performance of display devices. For example, even if the field effect mobility of a thin film transistor is high, If the threshold voltage value is high or negative, the circuit controls it. Furthermore, in the case of thin film transistors with high threshold voltages, it is difficult to When the voltage is low, the TFT cannot perform its switching function and may become a load. For example, in the case of an n-channel thin film transistor, when a positive voltage is applied to the gate electrode, It is desirable to have a transistor in which a channel is formed and drain current begins to flow only after the gate electrode is opened. There are transistors in which a channel does not form unless the driving voltage is high, and transistors in which a channel does not form even under negative voltage conditions. The transistor in which the channel is formed and the drain current flows is called a thin film transistor used in the circuit. It is not suitable as a

[0036] In addition, the gas atmosphere that is lowered from the heating temperature T is the same as the gas atmosphere that is heated up to the heating temperature T. It is also possible to switch to a different gas atmosphere. For example, large amounts of HCl may be added to the same furnace where dehydration or dehydrogenation was performed. The furnace is cooled by filling it with high-purity oxygen gas or N2O gas without exposing it to air. cormorant.

[0037] After reducing the moisture content in the film by heat treatment for dehydration or dehydrogenation, The mixture was slowly cooled (or cooled) in a dry atmosphere (dew point of -40°C or less, preferably -60°C or less). By using an oxide semiconductor film, the electrical characteristics of thin film transistors can be improved and mass productivity can be improved. This will realize a thin-film transistor that has both high performance and low noise.

[0038] In this specification, the term "heat treatment under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.)" refers to the treatment under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.). The heat treatment is referred to as heat treatment for dehydration or dehydrogenation. Therefore, dehydrogenation does not only mean the elimination of H2, but also the elimination of H, OH, etc. For convenience, the term "dehydration" or "dehydrogenation" will be used to include the elimination of these compounds.

[0039] In the manufacturing process of the semiconductor device, nitrogen or a rare gas (argon, helium, or the like) is not used. When heat treatment is performed in an active gas atmosphere, the oxide semiconductor layer is oxygen-deficient due to the heat treatment. It becomes depleted and has low resistance, that is, it becomes N-type (N - As a result, the source electrode layer and the High Resistance Source Region (HRS) The drain electrode layer is covered with an oxygen-deficient high-resistivity region (also called a source region). Anti-drain region (also called HRD (High Resistance Drain) region) ) is formed.

[0040] Specifically, the carrier concentration in the high-resistance drain region is 1×10 18 / cm 3 That's all, At least the carrier concentration of the channel formation region (1 × 10 18 / cm 3 higher than (less than). The carrier concentration in this specification is the carrier concentration determined by Hall effect measurement at room temperature. Points to a value.

[0041] In addition, an oxide conductive layer may be formed between the oxide semiconductor layer and the source electrode and the drain electrode. The oxide conductive layer preferably contains zinc oxide as a component, and more preferably contains indium oxide. For example, zinc oxide, zinc aluminum oxide, zinc oxynitride, Lead aluminum, zinc gallium oxide, or the like can be used. Drain region (LRN (Low Resistance N-type conduction ivity region, and LRD (Low Resistance Drain) region. ) or low resistance source region (LRN(Low Resistance N-type co nductivity) area, LRS (Low Resistance Source) Specifically, the carrier concentration in the low-resistance drain region is It is larger than the high resistance drain region (HRD region), for example, 1×10 20 / cm 3 1x or more 10 21 / cm 3 The thickness of the oxide conductive layer is preferably within the following range: By providing this between the source electrode and the drain electrode, the contact resistance can be reduced, and the transistor can be made faster. This allows for improved frequency characteristics of peripheral circuits (drive circuits). can be done.

[0042] The oxide conductive layer and the conductive layer for forming the source and drain electrodes can be formed successively. is.

[0043] Then, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is made into an oxygen-excess state. By this, the oxide semiconductor layer is made to have a higher resistance, that is, to be an i-type, and a channel formation region is formed. Note that the following method can be used to make the dehydrated or dehydrogenated oxide semiconductor layer into an oxygen-excess state: is deposited by, for example, a sputtering method so as to be in contact with the dehydrated or dehydrogenated oxide semiconductor layer. In addition, a method of forming an oxide insulating layer by the above method can be given. Heat treatment (e.g., heat treatment in an oxygen-containing atmosphere), heating in an inert gas atmosphere followed by oxidation Cooling in a dry atmosphere or ultra-dry air (dew point below -40°C, preferably below -60°C) A cooling process may be performed using a vacuum cleaner (below).

[0044] In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (which overlaps with the gate electrode layer) In order to make the oxide semiconductor into a channel formation region, the oxide semiconductor is selectively made into an oxygen-excess state. The conductive layer can be made highly resistive, i.e., I-type. For example, dehydrated or dehydrogenated oxide Form source and drain electrode layers made of metal electrodes such as Ti on the semiconductor layer. and selectively oxidizing an exposed region of the oxide semiconductor layer that does not overlap with the source electrode layer or the drain electrode layer. A channel formation region can be formed by selectively removing the oxide semiconductor layer. When the oxygen content is excessive, the high-resistance source region overlapping the source electrode layer and the drain electrode A high-resistance drain region is formed overlying the layer, and the high-resistance source region and the high-resistance drain region are formed. The region between the source electrode layer and the drain electrode layer is the channel forming region. The gate electrode is formed in a self-aligned manner between the drain electrode layers.

[0045] According to one embodiment of the present invention, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability is provided. It is possible to manufacture and provide the device.

[0046] Note that the oxide semiconductor layer overlapping with the drain electrode layer (and the source electrode layer) has a high resistance. By forming a drain region (and a high-resistance source region), the reliability of the drive circuit is improved. Specifically, by forming a high-resistance drain region, Conductivity is gradually increased from the drain electrode layer to the high-resistance drain region and channel formation region. Therefore, a high power supply potential V When connecting to a wiring that supplies DD, between the gate electrode layer and the drain electrode layer Even when a high electric field is applied, the high-resistance drain region acts as a buffer, preventing localized electric field concentration. The dielectric strength of the transistor can be improved.

[0047] In addition, by forming a high-resistance drain region (and a high-resistance source region), Specifically, the high-resistance source region and the high-resistance drain region can be formed. By forming a gate region, the flow of the transistor between the drain electrode layer and the source electrode layer The leakage current paths are the drain electrode layer, the high-resistance drain region on the drain electrode layer side, The order is the channel forming region, the high resistance source region on the source electrode layer side, and the source electrode layer. In the channel formation region, the high-resistance drain region on the drain electrode layer side is The leakage current flowing through the transistor is transmitted between the gate insulating layer, which has high resistance when the transistor is off, and the transistor. The back channel region (from the gate electrode layer) can be concentrated near the interface of the channel formation region. This can reduce leakage current in the surface of the channel formation region (a part of the surface of the channel formation region that is separated from the surface of the channel formation region).

[0048] In addition, a high-resistance source region overlapping the source electrode layer and a high-resistance drain region overlapping the drain electrode layer are formed. The gate electrode region overlaps with a part of the gate electrode layer via the gate insulating layer, although this depends on the width of the gate electrode layer. By adopting this structure, the electric field strength near the end of the drain electrode layer can be more effectively alleviated. It can be done.

[0049] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate

[0050] In addition to liquid crystal display devices, electrophoretic display devices are also used as display devices having a driving circuit. Examples of such display devices include those called electronic paper.

[0051] In addition, in a liquid crystal display device, when a pixel portion and a driver circuit are formed on the same substrate, In this case, logic gates such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. thin-film transistors that make up the circuit, as well as analog components such as sense amplifiers, constant voltage generators, and VCOs. The thin film transistors that make up the gate circuits have only positive polarity between the source and drain electrodes, or Therefore, the high resistance drain, which requires high dielectric strength, is The width of the source region may be designed to be wider than the width of the other high-resistance source region. The width of the source region and the high-resistance drain region overlapping with the gate electrode layer may be increased.

[0052] In addition, the thin-film transistors arranged in the drive circuit are single-gate thin-film transistors. However, if necessary, a multi-gate structure having a plurality of channel forming regions may be used. Thin film transistors can also be formed.

[0053] Furthermore, the liquid crystal display device is driven by an alternating current to prevent deterioration of the liquid crystal. As a result, the polarity of the signal potential applied to the pixel electrode layer is changed to positive or negative at regular intervals. The TFT connected to the pixel electrode layer has a pair of electrodes that alternately connects the source electrode layer and the drain electrode layer. In this specification, for convenience, one of the thin film transistors of the pixel is referred to as a source One electrode layer is called the drain electrode layer, and the other is called the drain electrode layer. The electrodes alternately function as source and drain electrode layers. Therefore, the width of the gate electrode layer of the thin film transistor arranged in the pixel is set to the width of the thin film transistor of the driver circuit. The width of the gate electrode layer of the pixel may be narrower than that of the pixel. The gate electrode layer of the thin film transistor arranged in the substrate overlaps with the source electrode layer or the drain electrode layer. It may be designed so that this does not occur.

[0054] In addition, thin film transistors are easily damaged by static electricity, so the thin film transistors in the pixel area It is preferable to provide a protection circuit for protecting the gate lines or source lines on the same substrate. The protection circuit is preferably formed using a nonlinear element using an oxide semiconductor layer. [Effects of the Invention]

[0055] According to one embodiment of the present invention, a thin film transistor having stable electrical characteristics is manufactured and provided. Therefore, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be obtained. An apparatus can be provided. [Brief explanation of the drawings]

[0056] [Figure 1] 1A to 1C illustrate a semiconductor device. [Figure 2] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 5] 1A to 1C illustrate a semiconductor device. [Figure 6] 1A to 1C illustrate a semiconductor device. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C illustrate a semiconductor device. [Figure 10] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 11] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 12] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 13] 3A and 3B are diagrams illustrating the configuration of a pulse output circuit and timing charts illustrating the operation of a shift register. [Figure 14] 1A to 1C illustrate a semiconductor device. [Figure 15] 1A to 1C illustrate a semiconductor device. [Figure 16] FIG. 1 is an external view showing an example of an electronic book. [Figure 17] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 18] FIG. 1 is an external view showing an example of a gaming machine. [Figure 19] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 20] 1A to 1C illustrate a semiconductor device. [Figure 21] 1A to 1C illustrate a semiconductor device. [Figure 22] 1A to 1C illustrate a semiconductor device. [Figure 23] 1A to 1C illustrate a semiconductor device. [Figure 24] 1A to 1C illustrate a semiconductor device. [Figure 25] 1A to 1C illustrate a semiconductor device. [Figure 26] 1A to 1C illustrate a semiconductor device. [Figure 27] 1A to 1C illustrate a semiconductor device. [Figure 28] 1A to 1C illustrate a semiconductor device. [Figure 29] 1A to 1C illustrate a semiconductor device. [Figure 30] 1A to 1C illustrate a semiconductor device. [Figure 31] 1A to 1C illustrate a semiconductor device. [Figure 32] 1A to 1C illustrate a semiconductor device. [Figure 33] 1A to 1C illustrate a semiconductor device. [Figure 34] 1A to 1C illustrate a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0057] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Those skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiments. In the configuration described below, parts that have the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for corresponding parts, and repeated explanations thereof will be omitted.

[0058] The contents shown in each embodiment can be appropriately combined or replaced with each other. Cut.

[0059] (Embodiment 1) The structure of the semiconductor device of this embodiment will be described with reference to FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device;

[0060] The semiconductor device shown in FIG. 1 has a driver circuit and a pixel portion on a substrate 400. The pixel includes a transistor 410 and a thin film transistor 420 .

[0061] The thin film transistor 410 includes a gate electrode layer 411 provided on a substrate 400 and a gate electrode layer 412. The gate insulating layer 402 is provided on the electrode layer 411, and the gate electrode 412 is provided between the gate insulating layer 402 and the gate electrode 411. At least a channel forming region 413 and a high resistance source region 414 are provided on the electrode layer 411. a and a high-resistance drain region 414b; and an oxide semiconductor layer 4 12, a source electrode layer 415a and a drain electrode layer 415b provided thereon. .

[0062] The gate electrode layer 411 preferably has low resistance. For example, the gate electrode layer is made of gold. It is preferable to use a metal material.

[0063] The gate insulating layer 402 may be, for example, a single layer of either an oxide insulating layer or a nitride insulating layer. The gate insulating layer 402 has a light-transmitting property. It is preferable that

[0064] The high-resistance source region 414a is formed in a self-aligned manner in contact with the lower surface of the source electrode layer 415a. The high-resistance drain region 414b is in contact with the lower surface of the drain electrode layer 415b. The channel forming region 413 is formed in a self-aligned manner. The high-resistance drain region 414b is a region (I-type region) having a higher resistance than the high-resistance drain region 414b.

[0065] The source electrode layer 415a and the drain electrode layer 415b preferably have low resistance. For example, a metal material is preferably used for the source electrode layer 415a and the drain electrode layer 415b. Desirable.

[0066] The driver circuit may include a gate electrode layer or a conductive film formed using the same conductive film as the gate electrode layer. a source electrode layer or a drain electrode layer; A conductive layer formed using the same conductive film is electrically connected to the gate insulating layer through an opening provided in the gate insulating layer. The semiconductor device shown in FIG. A conductive layer 457 formed using the same conductive film as the gate electrode 451 is provided on the conductive layer 457. A conductive layer 458 formed of the same conductive film as the electrode layer 421 is provided. A gate insulating layer 402 is provided, and a gate insulating layer 402 is provided on the gate insulating layer 402. The conductive layer 459 is electrically connected to the conductive layer 457 through an opening provided in the conductive layer 459 . The conductive layer 459 is formed from the same conductive film as the source electrode layer 415a and the drain electrode layer 415b. This allows for good contact and reduces contact resistance. Therefore, it is possible to reduce the number of openings, and by reducing the number of openings, it is possible to reduce the area occupied by the drive circuit. It is possible.

[0067] The thin film transistor 420 includes a gate electrode layer 421 provided on a substrate 400 and a gate electrode layer 422. The gate insulating layer 402 is provided on the electrode layer 421, and the gate insulating layer 402 is provided on the electrode layer 421. The source electrode layer 409a and the drain electrode layer 409b are connected to the source electrode layer 409a and the drain electrode layer 409b. The drain electrode layer 409b and the oxide semiconductor layer 42 provided on the gate insulating layer 402 2 and includes.

[0068] The gate electrode layer 421 is formed of a light-transmitting material in order to realize a display device with a high aperture ratio. The gate electrode layer 421 is formed using a light-transmitting film, for example.

[0069] In addition, the source electrode layer 409a and the drain electrode layer 409b are used to form a display having a high aperture ratio. In order to realize the device, a light-transmitting material is used, and the source electrode layer 409a and the drain electrode The pole layer 409b is formed using, for example, a light-transmitting film.

[0070] In this specification, a light-transmitting film is a film having a visible light transmittance of 75 to 100%. If the material is conductive, it is also called a transparent conductive film. In addition, the gate electrode layer, the source electrode layer, the drain electrode layer, the pixel electrode layer, and other electrode layers The wiring layer may be formed using a conductive film that is semi-transparent to visible light. Transparent means that the visible light transmittance is 50 to 75%.

[0071] Note that the thin film transistor 420 shown in FIG. 1 has a source electrode layer 409a and a drain electrode layer The top surface and side surfaces of the insulating film 409b are covered with the oxide semiconductor layer 422. The thin film transistor 420 includes a source electrode layer 409a and a drain electrode layer 409b. Alternatively, the oxide semiconductor layer 422 may be provided over part of b.

[0072] The pixel portion further includes a conductive layer 442 electrically connected to the drain electrode layer 409b. The conductive layer 442 shown in FIG. 1 is provided over part of the oxide semiconductor layer 422.

[0073] The conductive layer 442 preferably has low resistance. For example, the conductive layer 442 is made of a metal material. It is preferable that

[0074] The oxide semiconductor layer 422 also includes a region 428. The region 428 is formed under the conductive layer 442. The region 428 is formed in a self-aligned manner in contact with the surface. This means lower resistance, i.e., N-type (N - It is a region that is highly resistive (e.g., a high-resistivity source region or a high-resistivity The region 428 is an oxygen-deficient region, just like the anti-drain region. Therefore, the carrier concentration in the region 428 is As with the high-resistance source region or high-resistance drain region, the carrier concentration is higher than that of the channel formation region. The region 428 is also called a high resistance region.

[0075] The pixel section can also have a structure including a capacitor 454. The capacitor 454 is formed on the substrate 40. A conductive layer 438 is provided on the gate insulating layer 402, and a conductive layer 438 is provided on the conductive layer 438 with the gate insulating layer 402 interposed therebetween. The insulating film 430 includes a conductive layer 439 formed over the insulating film 430 and an oxide semiconductor layer 435 formed over the conductive layer 439 . The capacitor 454 functions as a storage capacitor of the pixel portion.

[0076] The aperture ratio of the pixel is improved by forming the capacitor 454 entirely from a light-transmitting material. Therefore, the conductive layer 438, the conductive layer 439, and the oxide semiconductor layer 435 can be transparent. It is preferable that the material has optical properties.

[0077] It is important for the capacitor 454 to have light-transmitting properties in order to improve the aperture ratio. In small LCD panels of 1000mW or less, the number of gate wirings is increased to improve the image quality. Even if the pixel size is made smaller to achieve higher definition, a high aperture ratio can be achieved. In addition, a light-transmitting film is used as a component of the thin film transistor 420 and the capacitor 454. In order to achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a group of high-density thin film transistors is arranged, the aperture ratio can be increased. For example, one pixel can be When there are 2 to 4 sub-pixels in a pixel, the thin film transistor must be transparent. In addition, each storage capacitor is also transparent, which can improve the aperture ratio.

[0078] The semiconductor device shown in FIG. 1 includes a driver circuit and a pixel portion, and at least an oxide semiconductor. The oxide insulating layer 416 is in contact with part of the layer 412 and part of the oxide semiconductor layer 422 .

[0079] In the semiconductor device illustrated in FIG. 1, a channel insulating layer is formed over the oxide insulating layer 416 in the driver circuit. The conductive layer 417 overlaps the gate electrode forming region 413. For example, the conductive layer 417 is 411 and the conductive layer 417. A gate voltage can be applied from above and below the oxide semiconductor layer 412 disposed in this manner. The gate electrode layer 411 and the conductive layer 417 are set to different potentials, for example, a fixed potential, GND, or 0V. In this case, the electrical properties of the TFT, such as the threshold voltage, can be controlled.

[0080] Furthermore, in the semiconductor device shown in FIG. 1, a thin film transistor (TFT) is provided over the oxide insulating layer 416 in the pixel portion. The pixel electrode layer 42 is in contact with the conductive layer 442 through an opening in the oxide insulating layer 416. It has 7.

[0081] The capacitor 454 is formed by a conductive layer provided on the gate insulating layer 402 without providing the conductive layer 438. the oxide semiconductor layer 439, the oxide semiconductor layer 435 provided over the conductive layer 439, and the oxide semiconductor layer 4 35 and the pixel electrode layer 427. Cut.

[0082] Note that a nitride insulating layer may be provided over the oxide insulating layer 416. The insulating layer 416 is in contact with the gate insulating layer 402 or a base insulating film provided below the insulating layer 416. It is preferable to do so in order to prevent moisture, hydrogen ions, and OH ions from the vicinity of the side surface of the substrate. - Impurities such as In particular, the gate insulating layer 40 in contact with the oxide insulating layer 416 It is effective to use a silicon nitride film as the insulating film for the oxide semiconductor layer 412. When a silicon nitride film is provided so as to surround the bottom surface, top surface, and side surfaces of the oxide semiconductor layer 422, The reliability of the display device is improved.

[0083] A planarization insulating layer may be provided between the oxide insulating layer 416 and the pixel electrode layer 427. When a nitride insulating layer is provided on the nitride insulating layer 416, a planarizing insulating layer is provided on the nitride insulating layer. The planarization insulating layer is preferably formed of a material such as polyimide, acrylic resin, or benzosilane. Use of heat-resistant organic materials such as clobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low-k materials and siloxane-based Resin, PSG (phosphor glass), BPSG (borophosphor glass), etc. are used as a planarizing insulating layer. Furthermore, by stacking multiple insulating films made of these materials, it is possible to achieve a flat surface. A smooth insulating layer may be formed.

[0084] The siloxane resin is a Si—O— compound formed using a siloxane material as a starting material. It corresponds to a resin containing Si bonds. In addition, siloxane resins do not contain organic groups (e.g. For example, an alkyl group or an aryl group may be used. The organic group may have a fluoro group. Good too.

[0085] The method for forming the planarizing insulating layer is not particularly limited, and may be a sputtering method depending on the material. , SOG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, Screen printing, offset printing, etc.), doctor knife, roll coater, car A tool such as a ten coater or a knife coater can be used.

[0086] Note that the oxide semiconductor layers 412 and 422 are treated with low moisture content as impurities. Heat treatment (heat treatment for dehydration or dehydrogenation) is carried out to reduce the amount of After heat treatment and slow cooling for oxidation, an oxide insulating layer was formed in contact with the oxide semiconductor layer. Reducing the carrier concentration in the oxide semiconductor layer by forming an oxide insulating film or the like is effective in thin film transistors. This leads to improved electrical characteristics and reliability of the transistor 410 and the thin film transistor 420. do.

[0087] In the semiconductor device shown in FIG. 1, the thin film transistors in the pixel portion are thin film transistors in the driver circuit portion. Since the thin film transistor 410 is required to operate at a higher speed, the channel length of the thin film transistor 410 is The channel length of the transistor 420 may be shorter than that of the thin film transistor. The channel length of the thin film transistor 410 is preferably about 1 μm to 5 μm. The channel length of 20 is preferably 5 μm to 20 μm.

[0088] As described above, an example of the semiconductor device of this embodiment has a first thin-film transistor and a second thin-film transistor on the same substrate. A driving circuit having a second thin film transistor (thin film transistor 410) and a The electrode of the second thin film transistor is The electrode of the first thin film transistor is made of a light-transmitting material. This improves the aperture ratio of the pixel area. This allows for the operation of the drive circuit to be improved. By providing a driver circuit and a pixel section in the display device, the number of wirings connecting the driver circuit and the pixel section can be reduced. In addition, the length of the wiring can be shortened, which allows for miniaturization and cost reduction of semiconductor devices. .

[0089] In addition, in an example of the semiconductor device of this embodiment, in a thin film transistor of a driver circuit, A conductive layer made of a light-transmitting material overlaps the channel forming region on the insulating layer. This allows the threshold voltage of the thin film transistor to be controlled. can be done.

[0090] In addition, in one example of the semiconductor device of this embodiment, the pixel electrode of the pixel portion is a conductive layer (conductive layer 442). The pixel portion is electrically connected to the drain electrode of the thin film transistor via the This makes it possible to reduce the contact resistance between the pixel electrode and the drain electrode of the thin film transistor. Cut.

[0091] In addition, in an example of the semiconductor device of this embodiment, a pixel electrode layer is connected to a conductive layer in a pixel portion. This structure electrically connects the pixel electrode layer and the oxide semiconductor layer. The contact resistance between the conductor layers can be reduced.

[0092] Next, an example of a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

[0093] First, a substrate 400 is prepared, a conductive film is formed on the substrate 400, and then a first photolithography is performed. A resist mask is formed on a part of the conductive film by a lithography process, and the resist mask is used The conductive film is etched to form a gate electrode layer 411 (see FIG. 2A). ).

[0094] The substrate 400 has an insulating surface and is at least heat-resistant enough to withstand subsequent heat treatment. The substrate 400 is, for example, a glass substrate. It is possible.

[0095] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. As the glass substrate, for example, aluminosilicate glass may be used. Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boric acid, it is more practical. Therefore, it is recommended to use a glass substrate containing more BaO than B2O3. It is preferable that:

[0096] Instead of the glass substrate, the substrate 400 may be a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. Alternatively, a substrate made of an insulating material such as a glass substrate may be used as the substrate 400. Since the semiconductor device shown in this embodiment mode is a transmission type, The substrate 400 is a light-transmitting substrate, but in the case of a reflective type, the substrate 400 is a non-transparent substrate. A substrate such as a light-transmitting metal substrate may also be used.

[0097] In addition, an insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 411. The film has a function of preventing the diffusion of impurity elements from the substrate 400, and is a silicon nitride film, a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, or a silicon oxynitride film; or a laminate of a plurality of films; It can be formed by a membrane.

[0098] Examples of materials for the conductive film for forming the gate electrode layer 411 include molybdenum and titanium. , chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. The gate electrode layer 411 and the conductive layer 412 can be made of a metal material or an alloy material containing the metal material as a main component. The conductive film for forming the conductive layer 457 is a film containing one or more of these materials. The film may be formed of a single layer or a laminated layer.

[0099] The conductive film for forming the gate electrode layer 411 may be, for example, a titanium film. an aluminum film formed on the titanium film; and a laminated film of a molybdenum film, an aluminum film provided on the molybdenum film, and It is preferable to use a three-layer laminate film of a molybdenum film provided on an aluminum film. The metal conductive film may be a single layer film, a two-layer laminated film, or a four or more layer laminated film. When a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used as the conductive film, Etching can be performed by dry etching using chlorine gas.

[0100] In addition, the driving circuit is formed of the same material as the gate electrode layer 411 and by the same photolithography process. A conductive layer 457 is formed. The conductive layer 457 functions as a terminal electrode or a terminal wiring.

[0101] Next, the resist mask is removed, and a conductive film is formed over the gate electrode layer 411 and the conductive layer 457. A resist mask is formed on a part of the conductive film by a second photolithography process. The conductive film is then etched using the resist mask, thereby forming a gate electrode layer 421. (See FIG. 2(B)).

[0102] As the conductive film for forming the gate electrode layer 421, a conductive film that transmits visible light is used. Electrical materials, such as In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn- O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Z nO series, Al-Zn-O series, In-Sn-O series, In-O series, Sn-O series, Zn-O series The conductive material can be applied, and the thickness of the conductive film is set to be in the range of 50 nm to 300 nm. The metal oxide film used for the gate electrode layer 421 can be formed by sputtering. methods such as arc discharge ion plating, vacuum deposition (electron beam deposition, etc.), and When using the sputtering method, SiO2 is added in an amount of 2% by weight or more. The film is formed using a target containing 10% by weight or less of the compound, and the crystallization is prevented from occurring in the light-transmitting conductive film. Harmful SiO x (x>0) may be included. This allows for the dehydration or decomposition in the subsequent step. This can prevent crystallization during the heat treatment for hydrogenation.

[0103] A conductive layer 458 is formed in the driver circuit portion using the same material and process as the gate electrode layer 421. A conductive layer 438 is formed in the pixel portion. The conductive layer 458 functions as a terminal electrode or a terminal wiring. The conductive layer 438 functions as a capacitor wiring. If a capacitance is required in the driving circuit, a capacitance wiring is also formed in the driving circuit.

[0104] Next, the resist mask is removed, and the gate electrode layer 411, the conductive layer 457, the conductive layer 458, and the gate electrode layer 411 are removed. The gate insulating layer 402 is formed over the gate electrode layer 421 and the conductive layer 438 .

[0105] The gate insulating layer 402 is formed by depositing a silicon oxide layer using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer formed as a single layer or a stacked layer; For example, when forming a silicon oxynitride layer, the deposition gas is SiH4, oxygen, and A silicon oxynitride layer may be formed by plasma CVD using silicon dioxide and nitrogen. The thickness of the insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminated layer, for example, a first gate insulating layer having a thickness of 50 nm or more and 200 nm or less; and a second gate insulating layer having a thickness of 5 The second gate insulating layer 402 is a stack of layers having a thickness of greater than or equal to 100 nm and less than or equal to 300 nm. As a result, a silicon oxide film was formed using a silicon target material doped with boron. By using - To prevent the intrusion of can be done.

[0106] In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed by plasma CVD. A protective insulating layer 402 is formed.

[0107] Next, a conductive film is formed over the gate insulating layer 402 and is then subjected to a third photolithography process. A resist mask is formed over a part of the conductive film, and the conductive film is etched using the resist mask. By this process, the source electrode layer 409a and the drain electrode layer 409b are formed.

[0108] Examples of the conductive film for forming the source electrode layer 409a and the drain electrode layer 409b include For example, conductive materials that are transparent to visible light, such as In—Sn—O-based materials, In—Sn- Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system In—O-based, Sn—O-based, and Zn—O-based oxide conductive films can be applied. The thickness of the conductive film is appropriately selected within the range of 50 nm to 300 nm. When sputtering is used as the method, the SiO2 content is 2% by weight or more and 10% by weight or less. The film is formed using a target containing SiO, which inhibits crystallization, on the transparent conductive film. x ( X>0), and the resulting hydroxyl group is subsequently formed during the heat treatment for dehydration or dehydrogenation in a subsequent step. It is preferable to suppress the crystallization of the oxide conductive layer that is to be formed.

[0109] In addition, the pixel portion is formed of the same material and process as the source electrode layer 409a and the drain electrode layer 409b. A conductive layer 439 is formed by this process. The conductive layer 439 functions as a capacitor electrode. In addition, when capacitance is required not only in the pixel section but also in the drive circuit, capacitance wiring is formed in the drive circuit. do.

[0110] Next, the resist mask is removed, and the gate insulating layer 402, the source electrode layer 409a, the drain electrode layer 409b, and the like are removed. An oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the electrode layer 409b and the conductive layer 439. After the oxide semiconductor film 430 is formed, heating is performed for dehydration or dehydrogenation. Even if the treatment is performed, the oxide semiconductor layer to be formed later is in an amorphous state. It is preferable to make the oxide semiconductor film 430 thin, ie, 50 nm or less. By reducing the thickness, when heat treatment is performed after the oxide semiconductor film 430 is formed, the oxide semiconductor film 430 formed later can be prevented from being damaged. Therefore, the oxide semiconductor layer can be prevented from being crystallized.

[0111] Before the oxide semiconductor film 430 was formed by a sputtering method, argon gas was introduced. The reverse sputtering is performed by introducing a gas into the gate insulating layer to generate plasma, and the dust adhering to the surface of the gate insulating layer is removed. It is preferable to remove the target. In a nitrogen atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is a method for modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. It's fine.

[0112] The oxide semiconductor film 430 may be an In—Ga—Zn—O system, an In—Sn—Zn—O system, or an I n-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al -Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-Sn- An O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor film is used. is formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. In addition, the film is formed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) atmosphere. Specifically, an oxide semiconductor film 4 was deposited by sputtering under an argon (argon) and oxygen atmosphere. When the sputtering method is used, SiO2 is added by 2 weight percent. % or more and 10 wt % or less of a target containing ZnO, and Harmful SiO x (x>0) may be included. This allows for the dehydration or decomposition in the subsequent step. During the heat treatment for hydrogenation, the oxide semiconductor layer to be formed later is crystallized. It can be suppressed.

[0113] Next, a resist mask is formed over the oxide semiconductor film 430 by a fourth photolithography process. and then removing unnecessary portions of the oxide semiconductor film 430 and the gate insulating layer 402 by etching. The gate insulating layer 402 is then removed to form a contact hole 426 that reaches the conductive layer 457. (See Figure 2(C)).

[0114] In this way, in a state where the oxide semiconductor film is laminated on the entire surface of the gate insulating layer, When the process of forming the contact holes is performed, the resist mask does not come into direct contact with the surface of the gate insulating layer. Therefore, contamination of the surface of the gate insulating layer (such as adhesion of impurities) can be prevented. The interface between the gate insulating layer and the oxide semiconductor film can be in a good condition, thereby improving reliability. leads to.

[0115] In addition, the present invention is not necessarily limited to this, and a resist pattern may be formed directly on the gate insulating layer. It is also possible to open tact holes. In that case, heat treatment is performed after removing the resist. It is preferable to carry out dehydration, dehydrogenation, and dehydroxylation treatments on the surface of the gate insulating film. For example, in an inert gas atmosphere (nitrogen, helium, neon, argon, etc.), or in an oxygen atmosphere The gate insulating layer is heated (for example, at a temperature between 400°C and 700°C) to It is sufficient to remove impurities such as hydrogen and water.

[0116] Next, a resist mask is formed by a fifth photolithography process. The oxide semiconductor film 430 is selectively etched using Process into a semiconductor layer.

[0117] Next, the resist mask is removed, and the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydrogenation is, for example, 400° C. or higher and 700° C. or lower, preferably The heat treatment time is 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. If the temperature is less than 425°C, the heat treatment time is longer than 1 hour. The substrate having the oxide semiconductor layer formed thereon is placed in an electric furnace, which is one type of heat treatment device, and an oxygen After the compound semiconductor layer was heat-treated in a nitrogen atmosphere, it was The oxide semiconductor layers 431 and 432 are obtained by preventing water and hydrogen from re-entering the oxide semiconductor layers. (See FIG. 3A.) In this embodiment, a process for dehydrating or dehydrogenating an oxide semiconductor layer is performed. From the heating temperature T, use the same furnace to a temperature that is high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below the temperature T. Dehydration or dehydrogenation is performed under a rare gas atmosphere such as helium, neon, or argon. cormorant.

[0118] The oxide semiconductor layer is heat-treated at a temperature of 400 to 700°C, and the oxide semiconductor layer is delaminated. This allows for hydration and dehydrogenation, preventing subsequent re-impregnation with water (H2O).

[0119] In the first heat treatment, nitrogen, helium, neon, argon, or the like is used. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of rare gases such as nitrogen, helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0120] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heat source such as a resistance heating element. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. Inert gases such as rare gases like argon or nitrogen that do not react with the material to be treated by heat treatment. When using a GRTA device, the heating temperature is set to, for example, 450°C or higher and 700°C or higher. It is preferable to do the following:

[0121] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized to form a microcrystalline film. In the case of a microcrystalline film, the percentage of crystalline components in the whole film may be is 80% or more (preferably 90% or more), and adjacent fine crystal grains are in contact with each other. It is preferable that the oxide semiconductor layer is filled with the oxide semiconductor layer. be.

[0122] The first heat treatment is performed on an oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is taken out of the heating device and A lithography process is performed to form a resist mask, and the resist mask is used to selectively The oxide semiconductor film is processed into an oxide semiconductor layer by etching.

[0123] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer is performed after the oxide semiconductor layer is formed. After a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer, The deposition may be performed either after forming the oxide semiconductor layer on the drain electrode layer or after forming the oxide semiconductor layer on the drain electrode layer.

[0124] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, or argon) is used. Heat treatment (for example, 400°C to 700°C) in an oxygen atmosphere under a rare gas such as argon ) to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0125] Note that the etching of the oxide semiconductor film here is not limited to wet etching, but may be dry etching. Etching may also be used.

[0126] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride ( CCl4) and the like) are preferred.

[0127] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0128] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0129] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0130] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the material. The indium contained in the oxide semiconductor layer may be extracted from the waste liquid after etching. By collecting and reusing materials such as these, resources can be used effectively and costs can be reduced. do.

[0131] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0132] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[atom The distance between the substrate and the target was set to 100 mm, the pressure was 0.2 Pa, and the DC DC) power supply 0.5 kW, argon and oxygen (argon: oxygen = 30 sccm: 20 sccm The oxide semiconductor film 430 is formed in an atmosphere of 1000 m m and 40% oxygen (oxygen flow rate ratio: 40%). Using a DC power supply is preferable because it reduces dust and ensures a uniform film thickness distribution. The thickness of the n-Ga-Zn-O based film is 5 nm to 200 nm. The get material may be, for example, In:Ga:ZnO=1:1:1 or In:Ga:ZnO= A target material such as 1:1:4 can also be used.

[0133] The sputtering method uses a high frequency power supply as the sputtering power source. There are two methods: DC sputtering and pulsed DC sputtering, which applies a bias voltage in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is also used. The sputtering method is mainly used when forming a metal film.

[0134] There are also multi-target sputtering systems that can accommodate multiple targets of different materials. The sputtering equipment can deposit layers of different materials in the same chamber, or It is also possible to form films by discharging multiple types of materials simultaneously using the bar.

[0135] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. E using a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the CR sputtering method.

[0136] In addition, as a film formation method using the sputtering method, the target material and the sputtering Reactive sputtering is a method of forming a compound thin film by chemically reacting the gas components with the There are also methods such as a sputtering method in which a voltage is applied to the substrate during film formation, and a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0137] Note that the oxide semiconductor layer 432 shown in FIG. 3A is a semiconductor layer including the source electrode layer 409a and the drain electrode layer 409b. The insulating film 409 is formed so as to cover the top and side surfaces of the electrode layer 409b. The etching selectivity of the source electrode layer 409a and the drain electrode layer 409b is not taken into consideration. The etching of the source electrode layer can be performed without being limited to this. If the source electrode layer 409a and the drain electrode layer 409b are not etched, The oxide semiconductor layer 432 is formed on the drain electrode layer 409a and part of the drain electrode layer 409b. The oxide semiconductor film can also be etched as shown above.

[0138] In addition, the pixel portion is formed using the same material and process as the oxide semiconductor layers 431 and 432. The oxide semiconductor layer 435 functions as a capacitor wiring. In addition, if capacitance is required not only for the pixel section but also for the driver circuit, the driver circuit also needs to have capacitance. A quantity of wiring is formed.

[0139] Next, the oxide semiconductor layer 431, the oxide semiconductor layer 432, the oxide semiconductor layer 435, and the gate electrode A conductive film is formed on the insulating layer 402, and a sixth photolithography process is performed on the conductive film. Then, a resist mask 433a and a resist mask 433b are formed, and selective etching is performed. Then, a source electrode layer 415a and a drain electrode layer 415b are formed (see FIG. 3B).

[0140] As a material of the conductive film for forming the source electrode layer 415a and the drain electrode layer 415b, is, for example, molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, Metallic materials such as neodymium and scandium or alloy materials containing these as the main components can be used. The conductive film for forming the source electrode layer 415a and the drain electrode layer 415b can be formed by It can be formed of a single layer or a laminated film containing one or more of these materials. Cut.

[0141] In addition, a conductive film for forming the source electrode layer 415a and the drain electrode layer 415b is The titanium film, the aluminum film provided on the titanium film, and the aluminum film provided on the aluminum film a three-layer laminated film of a titanium film coated with a molybdenum film, or a molybdenum film, and an aluminum film formed on the molybdenum film; A three-layer laminate film consisting of an aluminum film and a molybdenum film provided on the aluminum film is used. Of course, the metal conductive film may be a single layer film, a two-layer laminated film, or a four or more layer laminated film. Alternatively, a stack of a titanium film, an aluminum film, and a titanium film may be used as the conductive film. When a conductive film is used, it can be etched by dry etching using chlorine gas. Cut.

[0142] In addition, a resist mask is formed by the same process as the resist masks 433a and 433b. A mask 433c is formed, and the source electrode layer 415a and the drain electrode layer 415b are formed in the driver circuit area. The conductive layer 459 is formed using the same material and process as in b. It functions as a terminal wiring.

[0143] In addition, a resist mask is formed by the same process as the resist masks 433a and 433b. A mask 433d is formed, and a source electrode layer 415a and a drain electrode layer 415b are formed in the pixel portion. A conductive layer 442 is formed using the same material and process.

[0144] Next, the resist masks 433a to 433d are removed, and the oxide semiconductor layer 4 The oxide insulating layer 416 is formed in contact with the exposed surfaces of the oxide semiconductor layer 31 and the oxide semiconductor layer 432 .

[0145] The oxide insulating layer 416 has a thickness of at least 1 nm. For example, the oxide insulating layer 416 can be formed by using a method that prevents impurities such as water and hydrogen from being mixed therein. In this embodiment, the oxide insulating layer 416 can be formed to a thickness of 1000 nm. A silicon oxide film of 300 nm is formed by sputtering. The substrate temperature during film formation is The temperature is set to 100° C. in this embodiment. Film formation by the tarpaulin method can be performed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or The reaction can be carried out under an atmosphere of a rare gas (typically argon) and oxygen. A silicon oxide target or a silicon target can be used as the target. Silicon oxide film is formed by sputtering using a silicon target under oxygen and nitrogen atmosphere. The oxide semiconductor layer 431, the oxide semiconductor layer 432, and the oxide semiconductor layer 433 can be formed. The oxide insulating layer 416 formed in contact with the conductor layer 435 is resistant to moisture, hydrogen ions, and OH ions. - Na It uses an inorganic insulating film that does not contain any impurities and blocks them from entering from the outside. Typically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film is formed. The oxide insulating layer 416 is formed using an aluminum film or the like. The silicon oxide film is formed by using a silicon target material. Impurities (water, hydrogen ions, OH - It is possible to suppress the invasion of insects such as

[0146] The second heat treatment is carried out in an inert gas atmosphere or an oxygen gas atmosphere (preferably 200 ℃ or higher and 400 ℃ or lower, for example, 250 ℃ or higher and 350 ℃ or lower). The second heat treatment is carried out at 250°C for 1 hour in an atmosphere. The semiconductor layer 431, a part of the oxide semiconductor layer 432, and the oxide semiconductor layer 435 are oxide semiconductor layers. It is heated while in contact with insulating layer 416 .

[0147] Through the above steps, the oxide semiconductor layer 431, the oxide semiconductor layer 432, and the oxide semiconductor layer 433 are formed. The oxide semiconductor layer 431 and the oxide semiconductor layer 432 are formed by reducing the resistance of the oxide semiconductor layer 435. A part of the oxide insulating layer 416 is selectively made to have an excess oxygen state. The formation region 413 is an I-type region, and a portion of the oxide semiconductor layer 435 in contact with the oxide insulating layer 416 The portion is I-shaped, and the high-resistance source region 414a overlaps the source electrode layer 415a, and the drain The high-resistance drain region 414b overlaps the electrode layer 415b, and the region 422 overlaps the conductive layer 442. 8 are formed in a self-aligned manner (see FIG. 3(C)).

[0148] Depending on the thickness of the oxide semiconductor layer, the high-resistance source region 414a and the high-resistance drain region 4 The formation ranges of the oxide semiconductor layer 14b and the region 428 are different. In this case, the source electrode layer, the drain electrode layer, and the portions overlapping with the conductive layer are all N-type ( N -) region, and when the film thickness of the oxide semiconductor layer is, for example, 30 nm to 50 nm, The portions overlapping with the source electrode layer, the drain electrode layer, and the conductive layer are the source electrode layer, the drain electrode layer, and the conductive layer. An N-type region is formed in the vicinity of the polar layer and the conductive layer, and an I-type region is formed below the N-type region. is formed.

[0149] Furthermore, by forming the high-resistance drain region 414b (or the high-resistance source region 414a), As a result, the reliability of the driving circuit can be improved. By forming 14b, the transistor is connected from the drain electrode layer to the high resistance drain region 414 b) It is possible to make the structure capable of gradually changing the conductivity toward the channel formation region. Therefore, the drain electrode layer 415b is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated by the gate electrode layer 411 and the drain electrode layer 415b, Even if a high electric field is applied to the high-resistance drain region 414b (or the high-resistance source region 414a), This acts as a buffer to prevent localized electric field concentration, improving the dielectric strength of the transistor. can be done.

[0150] Furthermore, by forming the high-resistance drain region 414b (or the high-resistance source region 414a), This makes it possible to reduce the leakage current of the drive circuit.

[0151] Next, a seventh photolithography step is performed to form a resist mask, and the oxide insulating layer 4 By etching 16, a contact hole 441 reaching the conductive layer 442 is formed (FIG. 4 (See (A)). In addition, the etching here reduces the contacts that reach the gate electrode layers 411 and 421. Contact holes are also formed.

[0152] Next, after removing the resist mask, a light-transmitting conductive film is formed. Indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, ITO and the like) are formed into a film by sputtering or vacuum deposition. In addition, a conductive film containing nitrogen is formed as a light-transmitting conductive film. -Zn-O based film, i.e. Al-Zn-ON based film, Zn-O based film containing nitrogen, nitrogen It is also possible to use a Sn-Zn-O based film containing zinc. The composition ratio (atomic %) is set to 47 atomic % or less, and the aluminum content in the Al-Zn-ON film is The composition ratio (atomic %) of aluminum in the Al-Zn-ON film is larger than that of %) is larger than the composition ratio (atomic %) of nitrogen in the Al-Zn-ON film. The etching process for materials is carried out using a hydrochloric acid-based solution. However, the etching of ITO in particular requires the use of a solution containing a large amount of residual Residue is easily generated, so indium oxide zinc oxide alloy is used to improve etching processability. (In2O3-ZnO) may also be used.

[0153] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0154] Next, an eighth photolithography step is performed to form a resist mask and then etch the Then, unnecessary portions are removed to form a pixel electrode layer 427 and a conductive layer 417 (see FIG. 4(B)). .).

[0155] 5(A1) and 5(A2) are a cross-sectional view and a top view of the gate wiring terminal portion at this stage. 5A and 5B are cross-sectional views taken along the line C1-C2 in FIG. 5A. In FIG. 5A1, the conductive layer 155 is formed over the oxide insulating layer 416. is a terminal electrode for connection that functions as an input terminal. In the terminal portion, a gate electrode layer 411 and a terminal electrode 151 formed of the same material as the gate wiring are formed. The source electrode layer 415a and the connection electrode 153 made of the same material as the source wiring are gated. The connection electrode 153 and the conductive layer 155 overlap and contact each other via the insulating layer 402. The contact is made via a contact hole provided in the oxide insulating layer 416 .

[0156] 5B1 and 5B2 are a cross-sectional view and a top view of the source wiring terminal portion, respectively. FIG. 5(B1) is a cross-sectional view taken along the line D1-D2 in FIG. 5(B2). In FIG. 5B1, the conductive layer 155 formed over the oxide insulating layer 416 corresponds to , are terminal electrodes for connection that function as input terminals. In this portion, the terminal electrode 156 formed of the same material as the gate electrode layer 411 and the gate wiring is A gate electrode is formed below the source electrode layer 415a and the terminal electrode 150 electrically connected to the source wiring. The terminal electrode 156 is electrically connected to the terminal electrode 150 via the insulating layer 402. The terminal electrode 156 is set to a potential different from that of the terminal electrode 150, for example, floating, GN If you set it to D, 0V, etc., a capacitance for noise countermeasures or static electricity countermeasures will be formed. The terminal electrode 150 can be connected to the conductive layer 155 via the oxide insulating layer 416. is electrically connected to.

[0157] Through the above steps, the thin film transistor 410 and the thin film transistor 411 are formed on the same substrate using eight masks. The film transistor 420 can be fabricated separately for the driver circuit or pixel portion. Therefore, the manufacturing cost can be reduced compared to when the pixel portion and the driver circuit are manufactured in separate processes. The thin film transistor 410, which is a transistor for the driving circuit, is a high resistance source. The oxide layer 414a has a high-resistance drain region 414b, and a channel-forming region 413. The thin film transistor is a pixel transistor including a compound semiconductor layer 412. The transistor 420 is a bottom-contact thin film transistor including an oxide semiconductor layer 422. The thin film transistor 410 has a high resistance drain region that acts as a buffer even when a high electric field is applied. This prevents localized electric field concentration and improves the dielectric strength of the transistor. do.

[0158] In the manufacturing method of the semiconductor device shown in FIGS. 2 to 4, the gate insulating layer is used as a dielectric. The storage capacitor formed by the line and the capacitance electrode can also be formed on the same substrate. The pixel section is configured by arranging the resistor 420 and the storage capacitor in a matrix corresponding to each pixel. By disposing a driver circuit having a thin film transistor 410 around the pixel portion, The present invention can be used as one of the substrates for manufacturing a display device of a passive matrix type. For convenience, such a substrate is also called an active matrix substrate.

[0159] In addition, the conductive layer 417 is provided so as to overlap with the channel formation region 413 of the oxide semiconductor layer. By this, a bias-thermal stress test (hereinafter referred to as In the BT test, the threshold voltage of the thin film transistor 410 before and after the BT test was The amount of change in voltage can be reduced. 1 or different, and can also function as a gate electrode layer. The conductive layer 417 may be in a GND state, a state in which a potential of 0V is applied, or a floating state. It may be in a locking state.

[0160] In the method for manufacturing a semiconductor device described with reference to FIGS. 2 to 4, a resist mask is used. If the resist mask is formed by the inkjet method, the photoresist mask can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0161] (Embodiment 2) In this embodiment, in the thin film transistor of the driver circuit of Embodiment 1, an oxide semiconductor A low-resistance source region and a low-resistance drain region are provided between the layer and the source electrode layer or the drain electrode layer. An example in which an oxide conductive layer is provided as a region will be described. The present invention can be carried out by repeating the same parts as those in the first embodiment or parts having similar functions and steps. The explanation of the return is omitted.

[0162] The structure of the semiconductor device of this embodiment will be described with reference to FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device.

[0163] The semiconductor device shown in FIG. 6 includes a substrate 400 and a semiconductor device on the substrate 400, similar to the semiconductor device shown in FIG. The driver circuit includes a thin film transistor 410, and the pixel portion includes It has a thin film transistor 420 .

[0164] The thin film transistor 410 includes a gate electrode layer 411 provided on a substrate 400 and a gate electrode layer 412. The gate insulating layer 402 is provided on the electrode layer 411, and the gate electrode 412 is provided between the gate insulating layer 402 and the gate electrode 411. At least a channel forming region 413 and a high resistance source region 414 are provided on the electrode layer 411. a high-resistance drain region 414b; and an oxide semiconductor layer The oxide conductive layer 408a and the oxide conductive layer 408b are provided on the oxide conductive layer 412. The source electrode layer 415a is provided over the oxide conductive layer 408a, and the source electrode layer 415b is provided over the oxide conductive layer 408b. and a drain electrode layer 415b.

[0165] The oxide conductive layer 408a and the oxide conductive layer 408b are formed of a material selected from the group consisting of a silicon dioxide film, ... A material having a low resistance and a resistance higher than that of the source electrode layer 415a and the drain electrode layer 415b. Materials such as In-Sn-Zn-O, In-Al-Zn-O, and Sn -Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn- O series, Sn-Zn-O series, Al-Zn-O series, In-Sn-O series, In-O series, Sn-O Conductive metal oxides such as Zn—O and Zn—O can be used. The thickness of the oxide conductive layer 408a and the oxide conductive layer 408b is appropriately selected within the range of 50 nm to 300 nm. In addition, when using the sputtering method, the SiO2 content is 2% by weight or more and 10% by weight or less. The target is used to form a film, and the resulting transparent conductive film contains S, which inhibits crystallization. iO x (x>0) may be included. This allows for the dehydration or dehydrogenation to be carried out in the subsequent step. Therefore, crystallization of the oxide conductive layer 408 can be suppressed during heat treatment for forming the oxide conductive layer 408. The oxide conductive layer 408a functions as a low-resistance source region, and the oxide conductive layer 408b functions as a low-resistance drain region. It functions as a region.

[0166] In addition, the driver circuit may be formed using a gate electrode layer or a conductive film formed using the same conductive film as the gate electrode layer. The drain electrode layer, the source electrode layer, or the gate insulating layer is exposed to the semiconductor layer through an opening provided in the gate insulating layer. The conductive layer is electrically connected to the conductive layer formed using the same conductive film as the source electrode layer or the drain electrode layer. The semiconductor device shown in FIG. A conductive layer 457 formed using the same conductive film and a gate electrode 458 formed on the conductive layer 457 The electrode layer 421 has a conductive layer 458 formed of the same conductive film, and a gate electrode layer 458 is formed on the conductive layer 458. A gate insulating layer 402 is provided on the gate insulating layer 402. The oxide conductive layer 446 is electrically connected to the conductive layer 457 through the opening. The conductive layer 459 is disposed on the oxide conductive layer 446. The conductive layer 459 is formed using the same conductive film and process as the oxide conductive layer 408a and the oxide conductive layer 408b. The source electrode layer 415a and the drain electrode layer 415b are formed by the same conductive film and the same process. This allows for good contact and reduces contact resistance. Therefore, the number of openings can be reduced, and the occupied area can be reduced by reducing the number of openings. .

[0167] The thin film transistor 420 is a gate electrode provided on the substrate 400 in the same manner as the semiconductor device shown in FIG. a gate electrode layer 421, a gate insulating layer 402 provided on the gate electrode layer 421, and a gate insulating layer 402 provided on the gate electrode layer 421. A source electrode layer 409a and a drain electrode layer 409b are provided over the insulating layer 402. and on the source electrode layer 409a, the drain electrode layer 409b and the gate insulating layer 402. and an oxide semiconductor layer 422 provided thereon.

[0168] The pixel portion has an oxide conductive layer 447 electrically connected to the drain electrode layer 409b. The conductive layer 442 is provided over the oxide conductive layer 447. The oxide semiconductor layer 447 is provided on part of the oxide semiconductor layer 422 .

[0169] The oxide semiconductor layer 422 also includes a region 428. The region 428 is formed under the conductive layer 442. It is formed in a self-aligned manner in contact with the surface.

[0170] In addition, the semiconductor device shown in FIG. 6 includes a driver circuit and a pixel portion, and at least an oxide semiconductor The oxide insulating layer 416 is in contact with part of the layer 412 and part of the oxide semiconductor layer 422 .

[0171] Note that a nitride insulating layer may be provided over the oxide insulating layer 416. The insulating layer 416 is in contact with the gate insulating layer 402 or a base insulating film provided below the insulating layer 416. It is preferable to do so in order to prevent moisture, hydrogen ions, and OH ions from the vicinity of the side surface of the substrate. - Impurities such as In particular, the gate insulating layer 40 in contact with the oxide insulating layer 416 Alternatively, it is effective to use a silicon nitride film as the insulating film serving as the base. When a silicon nitride film is provided so as to surround the upper and side surfaces, the reliability of the display device is improved.

[0172] In addition, in the semiconductor device illustrated in FIG. 6, a channel insulating film is formed on the oxide insulating layer 416 in the driver circuit. The conductive layer 417 overlaps the formation region 413. For example, the conductive layer 417 is formed by 11 and set to the same potential, a gate electrode layer 411 and a conductive layer 417 are electrically connected to each other. A gate voltage can be applied to the disposed oxide semiconductor layer 412 from above and below. The gate electrode layer 411 and the conductive layer 417 are set to different potentials, for example, a fixed potential, a GND potential, or 0V. In this case, the electrical properties of the TFT, such as the threshold voltage, can be controlled. That is, one of the gate electrode layer 411 and the conductive layer 417 functions as a first gate electrode layer. The other of the gate electrode layer 411 and the conductive layer 417 functions as a second gate electrode layer. This allows the thin film transistor 410 to be used as a four-terminal thin film transistor. .

[0173] Furthermore, in the semiconductor device shown in FIG. 6, a thin film transistor (TFT) is provided over the oxide insulating layer 416 in the pixel portion. The pixel electrode layer 42 is in contact with the conductive layer 442 through an opening in the oxide insulating layer 416. It has 7.

[0174] Note that a planarization insulating layer may be provided between the oxide insulating layer 416 and the pixel electrode layer 427. When a nitride insulating layer is provided on the nitride insulating layer 416, a planarizing insulating layer is provided on the nitride insulating layer. It is preferable to provide

[0175] Note that the oxide semiconductor layers 412 and 422 are formed by reducing impurities such as moisture. Heat treatment for dehydration or dehydrogenation is carried out. After heat treatment for the oxide insulating layer and slow cooling, the oxide insulating layer was formed in contact with the oxide semiconductor layer. Reducing the carrier concentration in the oxide semiconductor layer by forming an insulating film or the like is effective in thin film transistors. This leads to improved electrical characteristics and reliability of the thin film transistor 410 and the thin film transistor 420. .

[0176] In the semiconductor device shown in FIG. 6, the thin film transistors in the driver circuit section are arranged in a different manner from the thin film transistors in the pixel section. Since the thin film transistor 410 is required to operate at a higher speed, the channel length of the thin film transistor 410 is The channel length of the transistor 420 may be shorter than that of the thin film transistor. The channel length of the thin film transistor 410 is preferably about 1 μm to 5 μm. The channel length of 20 is preferably 5 μm to 20 μm.

[0177] As described above, an example of the semiconductor device of this embodiment has the structure shown in FIG. 1 and further includes a source electrode a low-resistance source region formed of an oxide conductive layer between the drain electrode layer and the oxide semiconductor layer; Alternatively, it has a structure with a low-resistance drain region. This allows the frequency of the peripheral circuit (drive circuit) to be controlled. For example, compared to the contact between a metal electrode layer and an oxide semiconductor layer, The contact between the metal electrode layer and the low-resistance source region and the low-resistance drain region reduces the contact resistance. In addition, the electrode layer using molybdenum (for example, a molybdenum layer, an aluminum layer) The contact resistance with the oxide semiconductor layer is high, which is Molybdenum is less likely to be oxidized than titanium, so it has the effect of extracting oxygen from the oxide semiconductor layer. This is because the contact interface between the molybdenum layer and the oxide semiconductor layer is weak and does not become n-type. A low-resistance source region and a low-resistance drain region are provided between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. By interposing a rain region, contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (drive circuit) Furthermore, by providing a low-resistance source region and a low-resistance drain region, As a result, the channel length of the thin film transistor is increased by the distance between the low resistance source region and the low resistance drain region. Since the thickness is determined when etching the layer that will become the channel, the channel length can be made shorter.

[0178] Next, an example of a method for manufacturing the semiconductor device shown in FIG. 6 will be described with reference to FIGS.

[0179] First, a substrate 400 is prepared in the same manner as in the process shown in FIG. 2(A), and a conductive film is formed on the substrate 400. After forming the conductive film, a resist mask is formed on a part of the conductive film by a first photolithography process. The conductive film is etched using the resist mask to form a gate electrode layer 4 11 and a conductive layer 457 are formed.

[0180] Next, a conductive film is formed on the gate electrode layer 411 and the conductive layer 457 in the same manner as in the step shown in FIG. and forming a resist mask on a part of the conductive film by a second photolithography process. The conductive film is etched using the resist mask to form a gate electrode layer 4 21, the conductive layer 458, and the conductive layer 438 are formed.

[0181] Next, in the same manner as in the step shown in FIG. 2C, the gate electrode layer 411, the conductive layer 457, and the conductive layer 45 8. A gate insulating layer 402 is formed on the gate electrode layer 421 and the conductive layer 438, and the gate insulating layer 402 is formed on the gate electrode layer 421 and the conductive layer 438. A conductive film is formed on the edge layer 402, and a part of the conductive film is removed by a third photolithography process. forming a resist mask over the conductive film, and etching the conductive film using the resist mask; The source electrode layer 409a, the drain electrode layer 409b, and the conductive layer 439 were formed by , the gate insulating layer 402, the source electrode layer 409a, the drain electrode layer 409b, and the conductive layer 4 An oxide semiconductor film 430 having a thickness of 2 nm to 200 nm is formed on the oxide semiconductor film 39. A resist mask is formed on the body film 430 by a fourth photolithography process, and an etching By this etching, unnecessary portions of the oxide semiconductor film 430 and the gate insulating layer 402 are removed, and the gate insulating layer 402 is A contact hole 426 reaching the conductive layer 457 is formed in the insulating layer 402 .

[0182] Next, similarly to the step shown in FIG. 3A, a fifth photolithography step is performed to form an oxide semiconductor film. A resist mask is formed over part of the film 430, and the oxide semiconductor The oxide semiconductor film 430 is etched to form an island-shaped oxide semiconductor layer. The oxide semiconductor layer is processed and then dehydrated or dehydrogenated.

[0183] The temperature of the first heat treatment for dehydration or dehydrogenation is, for example, 400° C. or higher and 700° C. or lower. Preferably, the temperature is 425°C or higher. If the temperature is 425°C or higher, the heat treatment time is 1 hour or longer. However, if it is below 425°C, the heat treatment time should be longer than 1 hour. Here, a substrate having an oxide semiconductor layer formed thereon is placed in an electric furnace, which is one type of heat treatment apparatus. After the oxide semiconductor layer was subjected to heat treatment under a nitrogen atmosphere, the oxide semiconductor layer was exposed to the air. The oxide semiconductor layer 431 is prevented from being recontaminated with water or hydrogen without being touched. In this embodiment, the heating temperature at which the oxide semiconductor layer is dehydrated or dehydrogenated is From T to a temperature that is high enough to prevent water from entering again, specifically 100°C higher than the heating temperature T The same furnace is used to slowly cool the temperature in a nitrogen atmosphere until the temperature drops to 100°C or more. Dehydration or dehydrogenation is carried out in an atmosphere of a rare gas such as helium, neon, or argon.

[0184] The oxide semiconductor layer is heat-treated at a temperature of 400 to 700°C, and the oxide semiconductor layer is delaminated. This allows for hydration and dehydrogenation, preventing subsequent re-impregnation with water (H2O).

[0185] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain nitrogen, water, hydrogen, etc. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e., impurity concentration is 20 ppm or less, preferably is preferably 1 ppm or less, and more preferably 0.1 ppm or less.

[0186] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be annealed. In some cases, the film crystallizes to form a microcrystalline or polycrystalline layer. The proportion of the total is 80% or more (preferably 90% or more), and adjacent fine crystal grains are the same. It is preferable that the oxide semiconductor layer is filled so as to be in contact with the surface of the oxide semiconductor layer. It may be a state.

[0187] The first heat treatment is performed on an oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is taken out of the heating device and A resist mask is formed by a lithography process, and the resist mask is used to selectively The oxide semiconductor film is processed by etching.

[0188] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer is performed after the oxide semiconductor layer is formed. After a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer, This may be performed either after forming an insulating film on the drain electrode layer or after forming an insulating film on the drain electrode layer.

[0189] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, or argon) is used. Heat treatment (for example, 400°C to 700°C) in an oxygen atmosphere under argon or other Impurities such as hydrogen and water contained in the gate insulating layer may be removed.

[0190] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and the resistance is increased. In this embodiment, the oxide semiconductor film is formed into an i-type film (see FIG. 7A). In the above example, the first heat treatment is performed to dehydrate or dehydrogenate the material. However, the present invention is not limited to this. It is sufficient if it is a process after the deposition of the compound semiconductor film.

[0191] Next, the oxide semiconductor layer 431, the oxide semiconductor layer 432, the oxide semiconductor layer 435, and the gate electrode An oxide conductive film 405 is formed on the insulating layer 402, and a conductive film is formed on the oxide conductive film 405. A sixth photolithography process is performed on the conductive film on the oxide conductive film 405. A resist mask 433a and a resist mask 433b are formed, and selective etching is performed. A source electrode layer 415a and a drain electrode layer 415b are formed (see FIG. 7B).

[0192] The oxide conductive film 405 is formed by a method such as sputtering or vacuum evaporation (electron beam evaporation). The oxide conductive film 40 is formed by arc discharge ion plating or spraying. The material of 5 preferably contains zinc oxide as a component, and does not contain indium oxide. Such an oxide conductive film 405 is preferably made of zinc oxide, zinc oxide, or the like. Lead aluminum, zinc aluminum oxynitride, zinc gallium oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm to 300 nm. When using this method, film formation is performed using a target containing 2% to 10% by weight of SiO2. The oxide conductive film contains SiOx (X>0), which inhibits crystallization, and the decrystallization process is performed later. It is preferable to prevent crystallization during the heat treatment for hydration or dehydrogenation. .

[0193] When the conductive film on the oxide conductive film 405 is etched, the oxide conductive film 405 and the oxide conductive film 405 are etched. The oxide semiconductor layer 431, the oxide semiconductor layer 432, and the oxide semiconductor layer 435 are also removed. The materials and etching conditions are adjusted accordingly.

[0194] In addition, a resist mask is formed by the same process as the resist masks 433a and 433b. A mask 433c is formed, and the source electrode layer 415a and the drain electrode layer 415b are formed in the driver circuit area. The conductive layer 459 is formed using the same material and process as in b. It functions as a terminal wiring.

[0195] In addition, a resist mask is formed by the same process as the resist masks 433a and 433b. A mask 433d is formed, and a source electrode layer 415a and a drain electrode layer 415b are formed in the pixel portion. A conductive layer 442 is formed using the same material and process.

[0196] Next, a resist mask 433a, a resist mask 433b, a resist mask 433c, and The resist mask 433d is removed, and the source electrode layer 415a, the drain electrode layer 415b, The oxide conductive film 405 is etched using the conductive layer 459 and the conductive layer 442 as masks. The oxide conductive layer 408a, the oxide conductive layer 408b, the oxide conductive layer 446, and the oxide conductive layer 447 For example, the oxide conductive film 405 containing zinc oxide is formed by, for example, removing a resist. It can be easily etched using alkaline solutions such as syneresis.

[0197] In addition, the channel region can be formed by utilizing the difference in etching rate between the oxide semiconductor layer and the oxide conductive layer. The oxide conductive layer is then subjected to an etching process to divide the oxide conductive layer. The etching rate of the oxide semiconductor layer is faster than that of the oxide semiconductor layer. The oxide conductive layer on the semiconductor layer is selectively etched.

[0198] The resist masks 433a, 433b, 433c, and 433d are removed by an ashing process. In the case of etching using a stripping solution, the oxide conductive film is preferably removed by a process. 405, the oxide semiconductor layer 431, the oxide semiconductor layer 432, and the oxide semiconductor layer 435 are formed. To avoid excessive etching, the etching conditions (type of etchant, concentration, etching Adjust the time (time) accordingly.

[0199] After etching the oxide semiconductor layer into an island shape, an oxide conductive film is formed on the oxide conductive film. Conductive films are stacked to form a wiring pattern including a source electrode layer and a drain electrode layer using the same mask. By etching the oxide conductive film, an oxide conductive film is formed under the wiring pattern of the conductive film on the oxide conductive film. The conductive film can be left behind.

[0200] Also, in the contact between the conductive layer 457 and the conductive layer 459, an oxide is formed in the lower layer of the source wiring. By forming the conductive layer 446, the oxide conductive layer 446 serves as a buffer. The oxide conductive layer 446 does not form an insulating oxide with metal, so the resistance component is Only series resistance is used.

[0201] In addition, the source electrode layer 415a, the drain electrode layer 415b, the conductive layer 459, and the conductive layer 44 When the first heat treatment is performed after selectively etching the conductive film for forming the second insulating film, an acid The oxide conductive layer 408a, the oxide conductive layer 408b, the oxide conductive layer 446, and the oxide conductive layer 447 Unless the oxide conductive layer 408 contains a crystallization inhibitor such as silicon oxide, The oxide conductive layer 408b, the oxide conductive layer 446, and the oxide conductive layer 447 are crystallized. The oxide semiconductor layer is not crystallized by the heat treatment and remains amorphous. The crystals of the layer grow in a columnar shape relative to the underlying surface. When the conductive film on the upper layer of the oxide conductive film is etched to form the oxide conductive film, the lower layer Undercuts can be prevented from forming in the membrane.

[0202] Next, the oxide semiconductor layers 431 and 432 are formed in the same manner as in the step shown in FIG. An oxide insulating layer 416 is formed on the exposed surface, and then the insulating layer 416 is heated under an inert gas atmosphere or an oxygen gas atmosphere. By performing the second heat treatment, the oxide semiconductor layer 431, The oxide semiconductor layer 432 and the oxide semiconductor layer 435 are partly in contact with the oxide insulating layer 416. It is heated in this state.

[0203] By going through the above steps, a part of the region that has been made low resistance by dehydration or dehydrogenation is selected. As a result, the channel formation region in contact with the oxide insulating layer 416 The oxide semiconductor layer 435 in contact with the oxide insulating layer 416 is an I-type. The portion of the oxide semiconductor layer 431 overlapping the low-resistance source region (the oxide conductive layer 408a) A high-resistance source region 414a is formed in a self-aligned manner in the SiO 2 layer, and a low-resistance drain region (oxide conductive layer) is formed in the SiO 2 layer. A high-resistance drain region 414b is formed in a portion of the oxide semiconductor layer 431 that overlaps the drain layer 408b. The region 4 is formed in a self-aligned manner in a portion of the oxide semiconductor layer 432 that overlaps the oxide conductive layer 447. 28 is formed in a self-aligned manner (see FIG. 7(C)).

[0204] Through the above steps, the thin film transistor 410 and the thin film transistor 420 are formed on the same substrate. It can be made.

[0205] Next, a seventh photolithography step is performed in the same manner as in the step shown in FIG. A mask is formed and the oxide insulating layer 416 is etched to form a contact hole that reaches the conductive layer 442. A gate hole 441 is formed (see FIG. 8(A)). Contact holes reaching the electrode layers 411 and 421 are also formed.

[0206] Next, similarly to the process shown in FIG. 4(B), the resist mask is removed, and then a light-transmitting conductive film is formed. A conductive film is formed, an eighth photolithography process is performed, a resist mask is formed, and etching is performed. Unnecessary portions are removed by etching to form the pixel electrode layer 427 and the conductive layer 417.

[0207] Through the above steps, the thin film transistor 410 and the thin film transistor 411 are formed on the same substrate using eight masks. The film transistor 420 can be fabricated separately for the driver circuit or pixel portion. Therefore, the manufacturing cost can be reduced compared to when the pixel portion and the driver circuit are manufactured in separate processes. The thin film transistor 410, which is a transistor for the driving circuit, is a high resistance source. The oxide layer 414a has a high-resistance drain region 414b, and a channel-forming region 413. The thin film transistor is a pixel transistor including a compound semiconductor layer 412. The transistor 420 is a bottom-contact thin film transistor including an oxide semiconductor layer 432. The thin film transistor 410 has a high resistance drain region that acts as a buffer even when a high electric field is applied. This prevents localized electric field concentration, thereby improving the dielectric strength of the transistor.

[0208] In the method for manufacturing a semiconductor device shown in FIGS. 7 and 8, the gate insulating layer is used as a dielectric and the capacitance The storage capacitor formed by the line and the capacitance electrode can also be formed on the same substrate. The pixel section is configured by arranging the resistor 420 and the storage capacitor in a matrix corresponding to each pixel. By disposing a driver circuit having a thin film transistor 410 around the pixel portion, The substrate may be a passive matrix substrate.

[0209] (Embodiment 3) In this embodiment, a liquid crystal display device which is an example of a semiconductor device according to one embodiment of the present invention will be described. This will be explained using FIG.

[0210] The liquid crystal display device shown in FIG. 9 includes a driving circuit including a thin film transistor 170, a thin film transistor 180 and a pixel portion including a capacitor 147, a pixel electrode layer 110, and an insulating layer functioning as an alignment film. A substrate 100 provided with an edge layer 191, an insulating layer 193 functioning as an alignment film, and a counter electrode layer 194, and a counter substrate 190 on which a colored layer 195 functioning as a color filter is provided. are opposed to each other with the liquid crystal layer 192 sandwiched therebetween. A polarizing plate (a layer having a polarizer, a single layer) is provided on one surface of the substrate 100 and the counter substrate 190. The gate wiring terminals are provided with connecting electrodes 196a and 196b. 117, a terminal electrode 121, a connection electrode 120, and a terminal electrode 128 for connection are provided. The terminal portion of the base wiring is provided with a terminal electrode 122, a connection electrode 118, and a connection terminal electrode 129. is provided.

[0211] The thin film transistor 170 may be, for example, the thin film transistor of the driver circuit shown in the first embodiment. As the thin film transistor 180, for example, the thin film transistor shown in Embodiment 1 can be applied. A thin film transistor can be applied to the pixel portion. As a result, the thin film transistor 410 shown in FIG. 1 is applied as the thin film transistor 170. When the thin film transistor 420 shown in FIG. 1 is used as the thin film transistor 180, explain.

[0212] Furthermore, the capacitor 147 may be the capacitor shown in the first embodiment. In the liquid crystal display device shown in FIG. 9, the capacitor 454 shown in FIG. 1 is used as the capacitor 147, for example. This section explains the case where

[0213] In this way, the gate insulating layer 102 is used as a dielectric, and the dielectric, the capacitor wiring layer, and the capacitor electrode form a dielectric film. The capacitor 147, which is a storage capacitor, can also be formed on the same substrate. Without providing wiring, the pixel electrodes are connected to adjacent pixels via the protective insulating film and the gate insulating layer 102. A storage capacitor may be formed by overlapping with the gate wiring.

[0214] The terminal electrodes 128 and 129 formed on the terminal portion are FPC (Flexible Printed Circuit). d Circuit). The terminal electrode 128 formed on either side of the connection electrode 120 and the connection electrode 117 is connected to the input of the gate wiring. The connection electrode 118 is sandwiched between the terminal electrode 122 and the terminal electrode 122. The terminal electrode 129 formed by this is a terminal electrode for connection that functions as an input terminal of the source wiring. It is the extreme.

[0215] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. The electrode is provided on the active matrix substrate, and the terminal electrically connecting to the common electrode is provided on the terminal section. This terminal is used to set the common electrode to a fixed potential, such as GND or 0V. is.

[0216] Further, a thin film that functions as an alignment film is formed over the oxide insulating layer 107, the conductive layer 111, and the pixel electrode layer 110. An insulating layer 191 is formed.

[0217] The counter substrate 190 is provided with a colored layer 195, a counter electrode layer 194, and an insulating layer that functions as an alignment film. The substrate 100 and the counter substrate 190 are connected to each other so as to form a layer 193. The liquid crystal layer 192 is sandwiched between the spacers and bonded together with a sealing material (not shown). The lamination step may be carried out under reduced pressure.

[0218] The sealing material typically uses visible light curing, ultraviolet curing, or thermosetting resin. It is preferable to use an acrylic resin, an epoxy resin, an amine resin, or the like. In addition, the sealing material contains a photopolymerization initiator (typically ultraviolet light), a heat curing agent, and a filler. A coupling agent may be included.

[0219] The liquid crystal layer 192 is formed by sealing a liquid crystal material in the gap. Before bonding the substrate 190 to the substrate 192, a liquid crystal layer 192 is applied by a dispenser method (dropping method). Alternatively, the substrate 100 and the counter substrate 190 may be bonded together and then capillary action may be used. The liquid crystal layer 192 can also be formed by an injection method in which liquid crystal is injected into the liquid crystal material. There is no particular limitation on the liquid crystal material, and various materials can be used. If a material exhibiting the above formula is used, the alignment film can be made unnecessary.

[0220] In addition, a polarizing plate 196a is provided on the outer side of the substrate 100, and a polarizing plate 196b is provided on the outer side of the counter substrate 190. By providing the insulating film, the transmissive liquid crystal display device of this embodiment mode can be manufactured. .

[0221] Although not shown in the present embodiment, a black matrix (light-shielding layer), a polarizing member, a phase Optical members (optical substrates) such as a reflecting member and an anti-reflection member may also be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Lights, sidelights, etc. may also be used.

[0222] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0223] Furthermore, when displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention. In order to improve the moving image characteristics of the liquid crystal display device, There is a driving technology called black insertion, which displays a full black screen every other frame.

[0224] In addition, the vertical synchronization frequency is set to 1.5 times the normal frequency, preferably 2 times or more, to improve the video characteristics. There is also a driving technology called double speed driving that improves the image quality.

[0225] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode light source or multiple EL light sources. There is also a driving technology that drives each light source to light intermittently within one frame period independently. As the light source, three or more types of LEDs may be used, or white light emitting LEDs may be used. , independently control multiple LEDs, and control the switching timing of the optical modulation of the liquid crystal layer and the LED This driving technology can also synchronize the timing of light emission with the timing of LEDs being turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. can reduce power consumption.

[0226] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0227] A semiconductor device is formed by using a thin film transistor using an oxide semiconductor. In particular, the above method can reduce costs. By forming a thin-film insulating film, a thin-film transistor with stable electrical characteristics can be fabricated. Therefore, it is possible to provide a thin film transistor having good electrical characteristics and high reliability. It is possible to provide a semiconductor device that

[0228] Since the semiconductor layer in the channel formation region is a high resistance region, the electrical characteristics of the thin film transistor are This stabilizes the device and prevents an increase in off-state current. This results in good electrical characteristics and reliability. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with good performance.

[0229] In addition, thin film transistors are easily damaged by static electricity, etc., so they are A protection circuit is preferably provided over the same substrate. It is preferable to configure the protection circuit using linear elements. For example, the protection circuit is In this embodiment, a plurality of protection circuits can be provided between the terminal and the signal line input terminal. A surge voltage is applied to the scanning lines, signal lines, and capacitance lines due to static electricity or the like, and the transistor Therefore, when a surge voltage is applied to the protection circuit, The protection circuit is arranged in parallel with the scanning line. The nonlinear element is a two-terminal element such as a diode. It is composed of a three-terminal element such as a thin-film transistor in the pixel area. It is also possible to form a nonlinear element in the same process as the capacitor 180. For example, By connecting the IN terminal, it can have the same characteristics as a diode.

[0230] (Fourth embodiment) In this embodiment, at least a part of the driver circuit and a semiconductor device on which a pixel portion is disposed are disposed on the same substrate. An example of the device is described below.

[0231] The thin film transistor disposed in the pixel portion is formed according to the first or second embodiment. The thin film transistor described in Embodiment 1 or 2 is an n-channel TFT. Therefore, some of the driver circuits can be configured with n-channel TFTs. The thin film transistors in the pixel portion are formed on the same substrate.

[0232] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 has a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control It is electrically connected to the IC.

[0233] In FIG. 10A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of externally provided components such as drive circuits, thereby reducing costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability or yield can be improved.

[0234] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driver circuit start signal (GSP1) (also called a start pulse) It supplies a clock signal (GCK1) for the scanning line driver circuit 1. It also supplies a timing control circuit 5305 is a second scanning line driver circuit, for example, start signal (GSP2) (also called start pulse), clock for the second scanning line driver circuit The timing control circuit 5305 also supplies a signal line drive circuit (GCK2). For example, the signal line driver circuit start signal (SSP) and the signal line driver circuit Circuit clock signal (SCK), video signal data (DATA) (also known as simply video signal) Each clock signal is a multiple of clock signals with different periods. The clock signal may be the same as the clock signal itself, or may be an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 may be It is possible to omit either 303 or 304.

[0235] In FIG. 10B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, thin-film transistors have lower field-effect mobility than transistors using single-crystal semiconductors. The driving circuit formed on the substrate 5300 can be configured by the film transistor. Therefore, it is possible to increase the size of the display device, reduce the number of processes, reduce costs, or improve yields. This can be achieved.

[0236] The thin film transistor described in Embodiment 1 or 2 is an n-channel TFT. In Fig. 11(A) and Fig. 11(B), a signal line driver circuit configured with an n-channel TFT is shown. An example of the configuration and operation will be described below.

[0237] The signal line driver circuit shown in FIG. 11A includes a shift register 5601 and a switching circuit The switching circuit 5602 has a plurality of switching circuits. The switching circuits 5602_1 to 5602_N (N is a natural number of 2 or more) are each a thin-film transistor. Multiple transistors named 5603_1 to 5603_k (k is a natural number greater than or equal to 2) The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be described.

[0238] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0239] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0240] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_k functions as a switch.

[0241] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0242] Next, the operation of the signal line driver circuit of FIG. 11(A) will be explained with reference to the timing chart of FIG. 11(B). 11B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0243] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0244] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0245] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0246] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. A circuit including the thin film transistor described in Embodiment 2 can be used. In this case, the polarity of all the transistors in the shift register 5601 is changed to N-channel type or can be constructed with only one polarity of P-channel type.

[0247] Furthermore, a part of the scanning line driving circuit and the signal line driving circuit, or the scanning line driving circuit or the signal line driving circuit An example of a shift register used as part of a driver circuit will be described.

[0248] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is supplied to the shift register. The selection signal is generated by inputting the (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, a buffer is required. The capacitor used is one that can pass a large current.

[0249] Furthermore, a part of the scanning line driving circuit and the signal line driving circuit, or the scanning line driving circuit or the signal line driving circuit One form of shift register used in a part of the driving circuit will be explained with reference to FIGS. 12 and 13. do.

[0250] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 12(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number in the range of 2≦n≦N), the pulse output circuit The signal from 10_(n-1) (called the previous signal OUT(n-1)) (n is 2 or more and N or less) In the first pulse output circuit 10_1, a third pulse (a natural number) is input. A signal from the pulse output circuit 10_3 is input to the n-th pulse output circuit 10_n in the second stage or later. Then, the signal from the (n+2)th pulse output circuit 10_n+2, which is two stages later (later stage signal OU Therefore, the pulse output circuit of each stage outputs the pulse to the next stage and / or The first output signal (OUT(1)(SR)~) is input to the pulse output circuit of the previous stage. OUT(N)(SR)), a second output signal (OUT(1) to OUT(N)(SR)) that is input to another circuit, etc. T(N)) is output. As shown in FIG. 12(A), Since the next stage signal OUT(n+2) is not input to the two stages, for example, If the configuration is such that the first start pulse SP2 and the third start pulse SP3 are input, good.

[0251] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0252] In addition, each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N is Input terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth It is assumed that the device has an input terminal 25, a first output terminal 26, and a second output terminal 27 (FIG. 12( The first input terminal 21, the second input terminal 22, and the third input terminal 23 are It is electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. In A), the first pulse output circuit 10_1 has a first input terminal 21 connected to a first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third The input terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. are actively connected.

[0253] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 12B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0254] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin film In addition to the transistor, the four-terminal thin film transistor described in the above embodiment may be used. In this specification, a thin film transistor is a thin film transistor having two gate electrodes interposed between a semiconductor layer and a gate electrode. When an electrode is provided, the gate electrode below the semiconductor layer is referred to as the lower gate electrode, and the semiconductor layer is referred to as the The upper gate electrode is also called the upper gate electrode.

[0255] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, A configuration that allows for control of the threshold voltage is preferable. The threshold voltage is determined by the gate insulating film above and below the channel forming region of the thin film transistor. By providing a gate electrode and controlling the potential of the upper and / or lower gate electrodes, a desired The value can be controlled.

[0256] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0257] The first pulse output circuit 10_1 includes a first transistor 31 to a thirteenth transistor 43. In addition, the first input terminal 21 to the fifth input terminal 25 and the first output In addition to the first output terminal 26 and the second output terminal 27, a power supply line 5 to which a first high power supply potential VDD is supplied is also provided. 1, a power supply line 52 to which a second high power supply potential Vcc is supplied, a power supply line 53 to which a low power supply potential VSS is supplied, A signal or a power supply voltage is supplied from the power supply line 53 to the first transistor 31 to the thirteenth transistor 43. The magnitude relationship of the power supply potentials of the power supply lines in FIG. 12(C) is as follows: The power supply potential VDD is set to a potential equal to or higher than the second power supply potential Vcc, and the second power supply potential Vcc is set to a potential equal to or higher than the third power supply potential Vcc. The potential is higher than the power supply potential VSS. The lock signal (CK4) is a signal that alternates between H and L levels at regular intervals. The potential when the power is high is VDD, and the potential when the power is low is VSS. By making the potential Vcc of the line 52 lower than the potential VDD of the power supply line 51, the operation is not affected. The potential applied to the gate electrode of the transistor can be kept low without applying a This reduces the shift in the threshold voltage of the transistor, thereby suppressing degradation. Among the transistors 31 to 43, the first transistor 31, the sixth transistor The transistors 36 to 9th transistors 39 are four-terminal transistors. The first transistor 31 and the sixth to ninth transistors 36 to 39 are preferably 39 controls the potential of the gate electrode of the transistor 33 and the gate electrode of the transistor 40. A transistor that needs to be switched by a control signal, and the gate electrode is The response to the control signal is fast (the rise of the ON current is steep), which allows for a more accurate pulse output. This is a transistor that can reduce the malfunction of the circuit. By using this pulse, the threshold voltage can be controlled, and malfunctions can be further reduced. It can be an output circuit.

[0258] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. A thin film transistor is an element having a terminal. A thin film transistor has a channel in a region overlapping with a gate. It has a semiconductor region (also called a channel formation region) where a region is formed, and controls the potential of the gate By doing so, it is possible to control the current flowing between the drain and source through the channel region. Here, the source and drain can be determined depending on the structure and operating conditions of the thin film transistor. Since the voltage changes depending on the source and drain, it is difficult to determine which is the source and which is the drain. Here, the regions that function as a source and a drain are not called a source or a drain. In such cases, for example, they may be referred to as the first terminal and the second terminal. do.

[0259] In FIG. 12C, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the first gate electrode and the second gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal the gate electrode of the ninth transistor 39 is electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. and the gate electrode of the fourth transistor 34, the gate electrode of which is electrically connected to the fourth The sixth transistor 36 has a first terminal electrically connected to the input terminal 24. 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the fourth transistor The gate electrode (first gate electrode and The gate electrode of the seventh transistor (2) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (a first gate electrode and a second gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the first gate electrode and the second gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to each other. The gate electrodes (first gate electrode and second gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor 33 are electrically connected to each other. The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the twelfth transistor 42. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the first gate electrode and the second gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5. 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 are electrically connected to the are electrically connected.

[0260] In FIG. 12C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point between the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is called a node Let's call it B.

[0261] In addition, in FIG. 12(C) and FIG. 13(A), node A is set to a floating state, and the boost A capacitor may be provided separately to perform a test strap operation. In order to maintain the capacitance, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0262] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. The shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 13(B) is a vertical blanking period, and the period 62 corresponds to a gate selection period. Correct.

[0263] As shown in FIG. 13A, the ninth power supply voltage Vcc is applied to the gate electrode. By providing the transistor 39, the following occurs before and after the bootstrap operation: The advantages are as follows:

[0264] If the ninth transistor 39, to whose gate electrode the second power supply potential Vcc is applied, is not present, the block When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and source, the gate and drain In both cases, a large bias voltage is applied, which causes a large stress on the transistor. Therefore, the ninth power supply potential Vcc is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 rises, but the potential of the second terminal of the first transistor 31 does not rise. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0265] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, thereby reducing the number of transistors.

[0266] The semiconductor layers of the first to thirteenth transistors 31 to 43 are made of an oxide. By using a semiconductor, the off-current of the thin film transistor is reduced, and the on-current and The field effect mobility can be increased and the degree of degradation can be reduced. Therefore, malfunctions in the circuit can be reduced. , a higher potential is applied to the gate electrode than in a transistor using amorphous silicon. Therefore, the degree of deterioration of the transistor due to the second power supply potential Vcc is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line. Since the number of power supply lines to be routed can be reduced, the circuit can be made smaller.

[0267] The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 the clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38 The voltage supplied to the gate electrodes (first gate electrode and second gate electrode) by the second input terminal 22 is The clock signal is applied to the gate electrode of the seventh transistor 37 (the gate electrode of the first and second transistors). a clock signal provided by the second input terminal 22 to the gate electrode of the eighth transistor; The third input terminal 23 is connected to the gate electrodes (first gate electrode and second gate electrode) of the gate electrode 38. The same effect can be achieved by switching the wiring so that the clock signal is supplied by In the shift register shown in FIG. 13A, the seventh transistor 37 and The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the inverter 38, the second input terminal 22 and the third input terminal 23 The voltage drop at node B is caused by the voltage drop at the gate of the seventh transistor 37. The potential of the gate electrode of the eighth transistor 38 decreases. On the other hand, in the shift register shown in FIG. 13(A), the seventh The seventh transistor 37 and the eighth transistor 38 are both in an on state. is on, the eighth transistor 38 is off, then the seventh transistor 37 is off, By turning off the eighth transistor 38, the second input terminal 22 and the third input terminal The voltage drop at the node B caused by the voltage drop at the input terminal 23 is absorbed by the eighth transistor. Therefore, the number of times the potential of the gate electrode of the transistor 38 is decreased can be reduced to one. The gate electrodes (first gate electrode and second gate electrode) of the transistor 37 are connected to the third input terminal. The clock signal provided by the input terminal 23 is applied to the gate electrode of the eighth transistor 38 (the A clock signal supplied by a second input terminal 22 is input to the first gate electrode and the second gate electrode. By using a clock signal, the number of fluctuations in the potential of node B is reduced, and noise can be reduced. This can be done.

[0268] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0269] (Embodiment 5) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. A part or the whole of a driver circuit having a transistor is formed integrally on the same substrate as the pixel portion, A system panel can be formed.

[0270] The display device includes a display element. The display element is a liquid crystal element (also called a liquid crystal display element). It is possible.

[0271] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a plurality of pixels, each of which has a means for supplying a current to the display element. Alternatively, only the pixel electrode (also referred to as a pixel electrode layer) of the display element may be formed. After the conductive film that will become the pixel electrode is formed, but before etching is performed to form the pixel electrode. It can be in any form, and any form is applicable.

[0272] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or display element is IC (Integrated Circuit) by COG (Chip On Glass) method ) is also included in the display device.

[0273] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 14(A1) and 14(A2) show thin film transistors 4010 and 4011. and a liquid crystal element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealing material. 14(A1)(B) is a plan view of the panel sealed with 4005. A2) corresponds to the cross section at MN.

[0274] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0275] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 14(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0276] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 14B, the thin film transistor included in the pixel portion 4002 is a thin film transistor 4010 and a thin film transistor 401 included in a scanning line driver circuit 4004 1. An oxide insulating layer 404 is formed on the thin film transistors 4010 and 4011. 1 and an insulating layer 4021 are provided in this order.

[0277] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in Embodiment 1 or 2. Highly reliable thin film transistors including the thin film transistors for the driver circuits can be applied. As the transistor 4011, for example, the thin film transistor 410 shown in the first or second embodiment is used. The pixel thin film transistor 4010 can be, for example, 2 can be used. The transistors 4010 and 4011 are n-channel thin film transistors.

[0278] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as a second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0279] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 4. 006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 The overlapping portion corresponds to the liquid crystal element 4013. The counter electrode layer 4031 is provided with oxide insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between oxide insulating layers 4032 and 4033. .

[0280] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film A room can be used.

[0281] The spacers 4035 are columnar spacers obtained by selectively etching the insulating film. The distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is It should be noted that a spherical spacer may be used as the spacer 4035. In addition, the counter electrode layer 4031 is provided over the same substrate as the thin film transistor 4010. The common connection portion is used to electrically connect the conductive layer disposed between the pair of substrates to the common potential line. The counter electrode layer 4031 and the common potential line can be electrically connected via the conductive particles. The conductive particles are contained in the sealing material 4005 .

[0282] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small.

[0283] The liquid crystal display device of this embodiment may be a transmissive liquid crystal display device or a semi-transmissive liquid crystal display device. It can also be applied.

[0284] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. In this example, a colored layer (also called a color filter) and an electrode layer used in a display element are provided in this order. However, the polarizing plate may be provided on the inner side of the substrate. Also, the laminated structure of the polarizing plate and the colored layer is not included in this embodiment. The shape is not limited to a specific shape, and may be appropriately determined depending on the materials of the polarizing plate and the colored layer and the manufacturing process conditions.

[0285] The thin film transistor 4011 is in contact with the semiconductor layer including the channel formation region as a protective insulating film. The oxide insulating layer 4041 is formed on the oxide insulating layer 4042. The oxide insulating layer 416 may be formed using a material and a method similar to those of the oxide insulating layer 416 described in Section 1. As the insulating layer 4041, a silicon oxide film is formed by sputtering in the same manner as in the first embodiment. Complete.

[0286] Further, a protective insulating layer may be formed over the oxide insulating layer 4041.

[0287] In addition, in order to reduce the surface irregularities caused by the thin film transistor, An insulating layer 4021 is formed to function as a planarization insulating film. Heat-resistant resins such as imide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin In addition to the above organic materials, low dielectric constant materials (L low-k materials), siloxane resin, PSG (phosphor glass), BPSG (phosphor boron glass) In addition, a plurality of insulating films made of these materials can be stacked. In this way, the insulating layer 4021 may be formed.

[0288] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, lean printing, offset printing, etc.), doctor knife, roll coater, curtain coater The insulating layer 4021 is baked and the semiconductor is baked. By combining this with annealing of the layer, it becomes possible to efficiently manufacture a semiconductor device.

[0289] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0290] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0291] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples of the polymer include ethylenediamine or its derivatives, and copolymers of two or more of these.

[0292] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion 40 Various signals and potentials applied to O2 are supplied from FPC4018.

[0293] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. It is formed of the same conductive film as the gate electrode layer.

[0294] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0295] In FIG. 14, a signal line driver circuit 4003 is formed separately and is mounted on the first substrate 4001. Although an example of mounting is shown, the present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. May be implemented.

[0296] FIG. 15 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed in this specification. 1 shows an example of a semiconductor device configured as a liquid crystal display module.

[0297] FIG. 15 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. 05 is required for color display, and in the case of the RGB method, it is necessary to set the values ​​for red, green, and blue. A corresponding colored layer is provided for each pixel. On the outside of the polarizer 2601, a polarizer 2606, a polarizer 2607, and a diffusion plate 2613 are arranged. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and the circuit board 2612 is a flexible The cable wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, External circuits such as a control circuit and a power supply circuit are built in. They may be laminated with a retardation plate interposed therebetween.

[0298] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated) Birefringence mode, FLC (Ferroelectric Liquid Crystal uid Crystal) mode, AFLC(AntiFerroelectric L You can use modes such as IQID Crystal.

[0299] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0300] (Sixth embodiment) The semiconductor device disclosed in the present specification is flexible and can be used for electronic books (electronic books). child books), posters, advertisements on trains and other vehicles, various cards such as credit cards The present invention can be applied to the display unit in an electronic device, etc. An example of the electronic device is shown in FIG.

[0301] FIG. 16 shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and The housing 2701 and the housing 2703 are made up of two housings. The shaft 2711 serves as an axis for opening and closing. This configuration allows the device to operate like a paper book.

[0302] The housing 2701 incorporates a display unit 2705, and the housing 2703 incorporates a display unit 2707. The display unit 2705 and the display unit 2707 are configured to display a series of images. Alternatively, a different image may be displayed. By doing so, for example, a text image is displayed on the right display unit (display unit 2705 in FIG. 16) and A different image can be displayed on the display unit on the side (display unit 2707 in FIG. 16).

[0303] 16 shows an example in which the housing 2701 is provided with an operation unit. 701, a power switch 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The surface may be provided with a keyboard, a pointing device, etc. On the back or side, there are external connection terminals (earphone terminal, USB terminal, AC adapter and US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. You may do so.

[0304] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0305] (Embodiment 7) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receiver) (also called signal processors), computer monitors, digital cameras, digital video cameras , digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable games Examples include gaming machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. .

[0306] FIG. 17A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0307] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0308] The television device 9600 is configured to include a receiver, a modem, and the like. It is possible to receive more general television broadcasts, and also to receive them by wire or wirelessly via a modem. By connecting to a communication network, it can be transmitted in one direction (sender to receiver) or two directions (transmit to receiver). It is also possible to communicate information between followers and recipients, or between recipients themselves.

[0309] FIG. 17B shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0310] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US It is equipped with a terminal that can be connected to various cables such as B cable, a recording medium insertion section, etc. These may be incorporated on the same surface as the display, but providing them on the side or back enhances the design. For example, the recording medium insertion portion of the digital photo frame 9700 is Insert a memory that stores image data taken with a digital camera into the The captured image data can be displayed on the display portion 9703 .

[0311] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0312] FIG. 18(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9882 is incorporated in the housing 9891, and a display unit 9883 is incorporated in the housing 9891. 18(A) also includes a speaker unit 9884, a recording medium insertion unit 9 886, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor Sa9888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature Degree, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient , vibration, odor or infrared measuring functions), microphone 9889) etc. Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the configuration includes the semiconductor device disclosed in the specification, and other auxiliary equipment is provided as appropriate. The portable gaming machine shown in FIG. 18(A) can be configured as follows. It has the function of reading out the programs or data stored in the device and displaying them on the display, and wirelessly connecting to other portable gaming machines. It has a function to communicate and share information. The functions are not limited to these, and various other functions may be provided.

[0313] FIG. 18(B) shows an example of a slot machine 9900, which is a large gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. Machine 9900 also has other operating means such as a start lever and stop switch, coin It is equipped with an insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is The present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in this specification. , and other auxiliary equipment may be provided as appropriate.

[0314] FIG. 19A is a perspective view showing an example of a portable computer.

[0315] The portable computer of FIG. 19(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0316] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching a part of the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. If necessary, the external connection port 9305 can be used to connect a communication cable that complies with the USB communication standard. is doing.

[0317] The upper housing 9301 further includes a display unit 9 that can be slid into the upper housing 9301 and stored therein. 307, which allows for a wide display screen. The orientation of the screen of the 307 can be adjusted by the user. If it is used as a power panel, input operations can be performed by touching part of the retractable display. .

[0318] The display portion 9303 or the storable display portion 9307 is a display device such as a liquid crystal display panel. Use.

[0319] The portable computer shown in FIG. 19(A) is configured with a receiver and the like, and is also A broadcast can be received and an image can be displayed on the display portion 9303 or the display portion 9307. , while the hinge unit connecting the upper housing 9301 and the lower housing 9302 is in the closed state. The display portion 9307 is slid to expose the entire screen, and the user can adjust the screen angle. In this case, the hinge unit is opened and the display unit 93 is opened. 03 is not displayed, and only the circuit for displaying the TV broadcast is activated. This allows for minimal power consumption, making it ideal for portable computers with limited battery capacity. It is useful in

[0320] FIG. 19(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0321] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band part 9204 for attaching the body to the arm, and a fastening state of the band part 9204 to the arm are adjusted. The device is composed of an adjustment unit 9205, a display unit 9201, a speaker 9207, and a microphone 9208. It has been completed.

[0322] The main body also has an operation switch 9203, which is a power input button. When you press the button for switching the display or the button for starting the image capture, the Internet program starts. Each function can be associated with another function, such as starting a new program.

[0323] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 9(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0324] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0325] The mobile phone shown in FIG. 19(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. The system is configured with a storage device and the like, so that television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 1 may have a function for collecting location information such as GPS.

[0326] The display portion 9201 is an image display device such as a liquid crystal display panel. Since mobile phones are small and lightweight, their battery capacity is limited. The display device used in 1 preferably uses a panel that can be driven with low power consumption.

[0327] Although FIG. 19B illustrates an electronic device that is worn on the arm, it is not limited to this. Anything that has a portable shape is acceptable.

[0328] (Embodiment 8) In this embodiment mode, the thin film transistor shown in Embodiment Modes 1 and 2 is used as one mode of a semiconductor device. An example of a display device having a film transistor will be described with reference to FIGS. 20 to 33. This embodiment will be described with reference to FIGS. 20 to 33 as an example of a liquid crystal display device using a liquid crystal element as a display element. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. The thin film transistors shown in Embodiments 1 and 2 can be applied. and a thin-film transistor having high electrical characteristics and high reliability that can be fabricated in the same manner as in the process shown in the second embodiment. The TFT 628 and the TFT 629 are transistors each having an oxide semiconductor layer as a channel formation region. 20 to 33 show an example of a thin film transistor, which is a thin film transistor. Although the present invention is not limited to this, a case where a thin film transistor 420 shown in FIG. There is no.

[0329] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type LCD devices are a type of LCD panel that controls the alignment of liquid crystal molecules. In a VA type LCD device, when no voltage is applied, the liquid crystal molecules are in contact with the panel surface. In this embodiment, the pixels are arranged in a vertical direction. Divide into regions (for example, 2 to 4 sub-pixels) and tilt the molecules in different directions in each region. This is called multi-domain or multi-domain design. This paper describes a liquid crystal display device that takes multi-domain design into consideration.

[0330] 21 and 22 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to the cutting line GH shown in the figure. 20. Also, FIG. 22 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these figures.

[0331] FIG. 20 shows a TFT 628, a pixel electrode layer 624 electrically connected thereto, and a storage capacitor 6 A substrate 600 on which a counter electrode layer 640 and the like are formed is overlapped with a counter substrate 601. The figure shows the state after the two panels are stacked and liquid crystal is injected.

[0332] On the opposing substrate 601, a first colored film, a second colored film, and a third colored film (not shown) are formed. A protrusion 644 is formed on the counter electrode layer 640. This structure controls the alignment of the liquid crystal. The height of the protrusion 644 for controlling the pixel electrode layer 624 is different from the height of the spacer. An alignment film 648 is formed, and an alignment film 646 is also formed on the counter electrode layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601. There are.

[0333] Although columnar spacers are used here, bead spacers may also be scattered. Furthermore, the spacers may be formed on the pixel electrode layer 624 formed on the substrate 600 .

[0334] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 is connected to the TFT 628 and covers the storage capacitor 630. an insulating film 620 covering the insulating film 620; an insulating film 621 covering the insulating film 620; and an insulating film 622 covering the insulating film 621. The conductive layer 632 and the oxide semiconductor of the TFT 628 are formed by the contact holes 623 that penetrate the conductive layer 632 and the TFT 628, respectively. The TFT 628 is electrically connected to the body layer and the wiring 618. A thin film transistor can be used as appropriate. The capacitance wiring 604, which is the first capacitance wiring formed at the same time as the gate wiring 602, and the gate insulating The insulating film 606 and the capacitance wiring 61, which is the second capacitance wiring, are formed at the same time as the wirings 616 and 618. It consists of 7.

[0335] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0336] For example, the pixel electrode layer 624 is formed using the materials described in Embodiments 1 and 2. The pixel electrode layer 624 is provided with a slit 625. The slit 625 controls the alignment of the liquid crystal. It has the function of

[0337] The TFT 629 and the pixel electrode layer 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode layer 624, and the storage capacitor 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the panel is composed of a pixel electrode layer 624 and a pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels. The device is configured with two sub-pixels, but is not limited to this. The display device may also be constructed with multiple sub-pixels, three or more.

[0338] 22 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is the same as the pixel electrode layer 624. On the counter electrode layer 640, a protrusion for controlling the alignment of the liquid crystal is formed. 22, the pixel electrode layer 624 and the pixel electrode layer 626 are formed. The area where the counter electrode layer 640 overlaps with the pixel electrode layer 624 and the pixel electrode layer 626 is indicated by a broken line. The figure shows how the elements are arranged in a mutually overlapping manner.

[0339] The equivalent circuit of this pixel structure is shown in Figure 23. Both TFT628 and TFT629 have gate electrodes. The TFT 628 is electrically connected to the line 602 and the wiring 616. 30 and the liquid crystal element 651 are electrically connected. In this case, the capacitor wiring 604 and the capacitor By making the potential of the capacitance wiring 605 different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 can be controlled individually. This allows for precise control of the liquid crystal orientation, widening the viewing angle.

[0340] When a voltage is applied to the pixel electrode layer 624 in which the slit 625 is provided, A distortion of the electric field (a diagonal electric field) occurs in the vicinity of the slit 625. By arranging the protrusions 644 so that they interdigitate with each other, an oblique electric field is effectively generated. By controlling the orientation of the liquid crystal, the direction in which the liquid crystal is oriented varies depending on the location. In other words, the multi-domain structure widens the viewing angle of the LCD panel.

[0341] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 24 to 27. do.

[0342] 24 and 25 show the pixel structure of a VA type liquid crystal display panel. 24 is a plan view of the semiconductor device shown in FIG. 20, and a cross-sectional structure corresponding to the cutting line YZ shown in the figure is shown in FIG. The following description will be made with reference to both figures.

[0343] This pixel structure has multiple pixel electrodes in one pixel, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independently The system has a configuration for controlling the temperature.

[0344] The pixel electrode layer 624 is formed by passing through the insulating film 620, the insulating film 621, and the insulating film 622. The conductive layer 611 is connected to the conductive layer 611 through a contact hole 623 formed therein. The high-resistance drain region 613 of the conductor layer is connected to the TFT 628 via the wiring 618. The pixel electrode layer 626 includes the insulating films 620, 621, and 622. The conductive layer 612 is connected to the conductive layer 612 through a contact hole 627 that penetrates the conductive layer 612. A high-resistance drain region 614 of the oxide semiconductor layer is connected to a TFT 629 via a wiring 619 The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are They are separated so that different gate signals can be applied. On the other hand, they function as data lines. The wiring 616 is shared by the TFT 628 and the TFT 629. The thin film transistors shown in Embodiments 1 and 2 are used for the TFT 629 and the TFT 630. In addition, a capacitance wiring 690 is provided. 2, a first gate insulating film 606a is formed on the gate wiring 603 and the capacitance wiring 690, and a second A gate insulating film 606b is formed.

[0345] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes and are separated by a slit 625. The pixel electrode layer 626 surrounds the outside of the pixel electrode layer 624 that spreads in a V shape. The voltage applied to the pixel electrode layer 624 and the pixel electrode layer 626 is applied to the TFT 628. The orientation of the liquid crystal is controlled by varying the polarity of the TFT 629. The equivalent circuit is shown in Figure 27. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is The gate wiring 602 and the gate wiring 603 are connected to different gates. By giving a signal, the operation timing of TFT628 and TFT629 can be made different. In addition, both the TFT 628 and the TFT 629 are connected to the wiring 616. The TFT 628 is connected to a storage capacitor 630 and a liquid crystal element 651. , a storage capacitor 631 and a liquid crystal element 652 are connected.

[0346] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 26 shows the structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode is connected to the pixel electrode, but a slit 641 is formed. The electrode layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, widening the viewing angle.

[0347] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a first liquid crystal pixel. In addition, the pixel electrode layer 626, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped. The first liquid crystal element and the second liquid crystal element are overlapped with each other to form a second liquid crystal element. The liquid crystal display device has a multi-domain structure in which the liquid crystal elements are arranged.

[0348] Next, we will explain about the in-plane switching type liquid crystal display device. In the in-plane switching type, the liquid crystal molecules in the cell This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be widened to approximately 180 degrees. The liquid crystal display device used will be described below.

[0349] FIG. 28 shows a TFT 628 and a pixel electrically connected to the TFT 628 via a conductive layer 611. The substrate 600 on which the electrode layer 624 is formed is superimposed on the counter substrate 601, and liquid crystal is injected. A colored film 636, a flattening film 637, etc. are formed on the counter substrate 601. In addition, no counter electrode layer is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the substrate 600 and the opposing substrate 601 via an alignment film 646 and an alignment film 648. It is being done.

[0350] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a The TFT 628, which is the thin film transistor shown in the first and second embodiments, is formed. The electrode layer 607 can be formed simultaneously with the gate wiring 602 of the TFT 628. The same material as that of the pixel electrode layer 427 described in Embodiments 1 and 2 can be used. The electrode layer 607 is formed in a shape that is divided into approximately pixel shapes. A gate insulating film 606 is formed on the layer 607 and the capacitor wiring 604 .

[0351] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 16 is a data line that carries a video signal in the liquid crystal display panel, and is a wiring that extends in one direction. At the same time, the wiring 618 serves as one of the source and drain electrodes of the TFT 628. The other electrode of the source and drain of the TFT 628 is formed by the high-resistance drain of the oxide semiconductor layer. The pixel electrode layer 624 is connected to the second pixel electrode through the conductive layer 611 and the in-region 613. The conductive layer 611 is formed using a material similar to that of the conductive layer 442 described in Embodiment 1. It is possible.

[0352] An insulating film 620 is formed on the wiring 616 and the wiring 618, and an insulating film 620 is formed on the insulating film 620. On the insulating film 621, an insulating film 620 and an insulating film 621 are formed. through the contact hole 623, the conductive layer 611, and the high-resistance drain region 613. A pixel electrode layer 624 connected to the wiring 618 is formed. The pixel electrode layer 624 is formed as described in Embodiment 1. The pixel electrode layer 427 is formed using the same material as that of the pixel electrode layer 427 shown in .

[0353] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0354] 29 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 28. The pixel electrode layer 624 is provided with slits 625. The slit 625 is for controlling the alignment of the liquid crystal. In this case, the electric field is applied to the electrode layer 6 The gate electrode layer 607 and the pixel electrode layer 624 are connected to each other. The gate insulating film 606 is formed, and the thickness of the gate insulating film 606 is 50 to 200 nm. is sufficiently thin compared to the thickness of the liquid crystal layer, which is 2 to 10 μm, and therefore, the thickness of the substrate 600 is substantially An electric field is generated in the direction parallel to the liquid crystal (horizontal direction). This electric field controls the orientation of the liquid crystal. The liquid crystal molecules are rotated horizontally by using an electric field in a direction approximately parallel to the substrate. Since the molecules are horizontal in all states, the influence of contrast due to the viewing angle is minimal. The viewing angle is widened. In addition, the electrode layer 607 and the pixel electrode layer 624 are both light-transmitting electrodes. Since it is a polar, the aperture ratio can be improved.

[0355] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0356] Figures 30 and 31 show the pixel structure of an IPS type liquid crystal display device. Figure 31 is a plan view. The cross-sectional structure corresponding to the cutting line VW shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0357] FIG. 30 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is placed on top of the other substrate and liquid crystal is injected. A color film 636, a flattening film 637, etc. are formed on the counter substrate 601 side. Furthermore, an alignment film 646 and an alignment layer are not provided between the substrate 600 and the counter substrate 601. A liquid crystal layer 650 is formed via a film 648 .

[0358] On the substrate 600, a common potential line 609 and the TFTs shown in the first and second embodiments are provided. The common potential line 609 is formed at the same time as the gate wiring 602 of the TFT 628. The electrode layer 607 is formed in a shape that is partitioned into approximately the shape of a pixel. As the TFT 628, the thin film transistor shown in the first and second embodiments is applied. It is possible.

[0359] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 16 is a data line that carries a video signal in the liquid crystal display panel and extends in one direction. At the same time, the wiring 618 serves as one of the source and drain electrodes of the TFT 628. , which serves as the other electrode of the source and drain, and the conductive layer 611 and the high-resistance drain region 613 The wiring is connected to the pixel electrode layer 624 via the wiring.

[0360] An insulating film 620 is formed on the wiring 616 and the wiring 618, and an insulating film 6 21 is formed on the insulating film 621. In addition, the insulating film 620 and the insulating film 621 are formed on the insulating film 621. The conductive layer 611 is formed through a contact hole 623, a conductive layer 611, and a high-resistance drain region 613. A pixel electrode layer 624 is formed to connect to the line 618. The pixel electrode layer 624 is formed by the same method as in the first embodiment. The pixel electrode layer 427 is formed using the same material as that of the pixel electrode layer 427 shown in FIG. The pixel electrode layer 624 generates a horizontal electric field together with the comb-shaped electrode formed at the same time as the common potential line 609. The comb-teeth portion of the pixel electrode layer 624 is formed at the same time as the common potential line 609. The electrodes are formed so as to interdigitate with the comb-shaped electrodes.

[0361] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. The molecules are rotated horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast and results in a wider viewing angle.

[0362] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by providing a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitor electrode 615 and the pixel electrode layer 624 are formed by the contact hole. It is connected via 633.

[0363] Next, the configuration of a TN type liquid crystal display device will be described.

[0364] Figures 32 and 33 show the pixel structure of a TN type liquid crystal display device. Figure 33 is a plan view. The cross-sectional structure corresponding to the cutting line KL shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0365] The pixel electrode layer 624 is formed by a contact hole 623 penetrating the insulating film 620 and the insulating film 621. The data is connected to a wiring 618 via the conductive layer 611 and the high-resistance drain region 613. The wiring 616, which functions as a line, is connected to the TFT 628. Either the TFT shown in Mode 1 or Mode 2 can be applied.

[0366] The pixel electrode layer 624 is formed using a material similar to that of the pixel electrode layer 427 described in Embodiment 1. The capacitance wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. Gate insulating films 606a and 606b are formed on the gate wiring 602 and the capacitance wiring 604. The storage capacitor is formed by a capacitor wiring 604, a capacitor electrode 615, and a capacitor wiring 604 and a capacitor electrode 615. The capacitor electrode 6 is formed by the gate insulating films 606a and 606b between the electrodes 615. 15 and the pixel electrode layer 624 are connected via a contact hole 633 .

[0367] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is formed by interposing an alignment film 648 and a counter electrode layer 640 between the pixel electrode layer 624 and the counter electrode layer 640. The alignment film 646 is formed therebetween.

[0368] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0369] A colored film 636 may be formed on the substrate 600 side. A polarizing plate is attached to the surface opposite to the surface on which the transistor is formed, and A polarizing plate is attached to the surface opposite to the surface on which the counter electrode layer 640 is formed.

[0370] The wiring 618 is connected to the pixel electrode layer 6 via the conductive layer 611 and the high-resistance drain region 613. 24.

[0371] A liquid crystal display device can be configured as described above.

[0372] (Embodiment 9) An example of electronic paper will be shown as one mode of the semiconductor device.

[0373] The thin film transistors of the first and second embodiments are electrically connected to the switching elements. The present invention may also be used in electronic paper that drives electronic ink using an element that displays the image. is also called an electrophoretic display (electrophoretic display) and has the same readability as paper. It has the advantage of being able to consume less power and be made thinner and lighter than other display devices. There are.

[0374] Electrophoretic displays can be of various forms, but the first particle has a positive charge. The microcapsules containing the negatively charged second particles are mixed with a solvent or solute. By applying an electric field to the microcapsules, By moving the particles in the capsule in opposite directions, only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and are not mobile in the absence of an electric field. The first particles and the second particles are different in color (including colorless).

[0375] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. The polarizing plate and counter substrate required for a display device are not required, reducing the thickness and weight.

[0376] The microcapsules dispersed in a solvent are called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Furthermore, color display is possible by using color filters or particles containing pigments.

[0377] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. An active matrix substrate obtained by using transistors can be used.

[0378] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, a semiconductor, or the like. Conductive materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A material selected from magnetochromic materials, magnetophoretic materials, or a composite material of these materials is used. That's fine.

[0379] Figure 34 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device may be the thin film transistor shown in Embodiments 1 and 2. It can be fabricated in the same way as a thin-film transistor containing an oxide semiconductor layer, and is a highly reliable thin-film transistor. The thin film transistors shown in the first and second embodiments are also thin film transistors. It can also be applied as register 581.

[0380] The electronic paper in Figure 34 is an example that uses the twisting ball display method. The display method is a method in which the first electrode layer, which is an electrode layer that uses spherical particles painted in black and white, is used as a display element. and a second electrode layer, and a potential difference is generated between the first electrode layer and the second electrode layer. This method displays images by controlling the orientation of all spherical particles.

[0381] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The photodiode is provided on a substrate 580 and is covered with an insulating film 583 that is in contact with the semiconductor layer. The source electrode layer or the drain electrode layer of the thin film transistor 581 is connected to the first electrode 581 through a conductive layer 582. The conductive layer 582 is electrically connected to the first electrode layer 587 and the insulating layer 5 The first electrode layer 587 and the second electrode layer 596 are in contact with each other through an opening formed in the substrate 596. Between the electrode layer 588 and the black area 590a and the white area 590b, there is a liquid A spherical particle 589 is provided that includes a cavity 594 filled with The periphery of the pixel electrode 89 is filled with a filler 595 such as resin. The second electrode layer 588 corresponds to a thin film transistor. The common connection portion is electrically connected to a common potential line provided on the same substrate as the transistor 581. 588 and the second electrode layer 589 through the conductive particles disposed between the pair of substrates. The wires can be electrically connected.

[0382] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, it is possible to retain an image that has been displayed once. Therefore, a semiconductor device with a display function (simply a display device, or a device equipped with a display device) is required to transmit signals from a radio wave source. The displayed image can be preserved even if the device (also called a semiconductor device) is moved away. It becomes possible.

[0383] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. . [Explanation of symbols]

[0384] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 28 transistors 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 42 transistors 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 boards 102 Gate insulating layer 107 Oxide insulating layer 110 Pixel electrode layer 111 Conductive layer 117 Connecting electrode 118 Connection electrode 120 connecting electrode 121 Terminal electrode 122 Terminal electrode 128 Terminal electrode 129 Terminal electrode 147 capacity 150 terminal electrode 151 Terminal electrode 153 Connecting electrode 155 Conductive Layer 156 Terminal electrode 170 Thin-Film Transistor 180 Thin Film Transistor 190 Opposing substrate 191 Insulating layer 192 Liquid Crystal Layer 193 Insulating Layer 194 Counter electrode layer 195 Colored layer 196a Polarizing plate 196b Polarizing plate 400 boards 402 Gate insulating layer 405 Oxide Conductive Film 408a Oxide conductive layer 408b Oxide conductive layer 409a Source electrode layer 409b Drain electrode layer 410 Thin Film Transistor 411 Gate electrode layer 412 Oxide semiconductor layer 413 Channel formation region 414a High-resistance source region 414b High-resistivity drain region 415a Source electrode layer 415b Drain electrode layer 416 Oxide insulating layer 417 Conductive Layer 420 Thin Film Transistor 421 Gate electrode layer 422 Oxide semiconductor layer 426 Contact Hole 427 Pixel electrode layer 428 areas 430 Oxide semiconductor film 431 Oxide semiconductor layer 432 Oxide semiconductor layer 433a Resist mask 433b Resist mask 433c Resist mask 433d resist mask 435 Oxide semiconductor layer 438 Conductive Layer 439 Conductive Layer 441 Contact Hole 442 Conductive layer 446 Oxide conductive layer 447 Oxide Conductive Layer 454 capacity 457 Conductive Layer 458 Conductive Layer 459 Conductive Layer 580 board 581 Thin-film transistor 582 Conductive layer 583 Insulating Film 584 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 PCB 600 boards 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate insulating film 606a Gate insulating film 606b Gate insulating film 607 Electrode layer 609 Common potential line 611 Conductive layer 612 Conductive layer 613 High-resistivity drain region 614 High-resistivity drain region 615 Capacitive electrode 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 insulating film 621 Insulating film 622 insulating film 623 Contact Hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 632 Conductive layer 633 Contact Hole 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Alignment Film 648 Alignment Film 650 LCD layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 696 Insulating Film 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 Thin Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Oxide insulating layer 4035 Spacer 4040 Conductive layer 4041 oxide insulating layer 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin-film transistor 5604 Wiring 5605 Wiring 9201 Display section 9202 Display button 9203 Operation switch 9204 Band Club 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Controlled Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

1. a first transistor and a capacitor provided in a pixel portion; a second transistor provided in the drive circuit portion; the first transistor includes a first oxide semiconductor layer, a first source electrode layer and a first drain electrode layer in contact with a bottom surface of the first oxide semiconductor layer, and a first gate electrode layer overlapping with the first oxide semiconductor layer in a cross-sectional view; the capacitor has a first conductive layer and a second conductive layer as a pair of electrodes; the second conductive layer is the same layer as the first source electrode layer and the first drain electrode layer and has the same material as the first source electrode layer and the first drain electrode layer; the second transistor includes: a second oxide semiconductor layer; a second gate electrode layer below the second oxide semiconductor layer and overlapping with the second oxide semiconductor layer; a third gate electrode layer above the second oxide semiconductor layer and overlapping with the second oxide semiconductor layer; a second source electrode layer in contact with the second oxide semiconductor layer; and a second drain electrode layer in contact with the second oxide semiconductor layer; the second gate electrode layer is electrically connected to the third gate electrode layer; the first transistor does not have a gate electrode of the first transistor on an opposite side to a side of the first oxide semiconductor layer on which the first gate electrode layer is provided, a lower surface of the first oxide semiconductor layer has a region in contact with an insulating layer in contact with lower surfaces of the first source electrode layer and the first drain electrode layer, in a region that does not overlap with the first gate electrode layer in a cross-sectional view; the second source electrode layer and the second drain electrode layer are single layers containing an element selected from the group consisting of molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium.

2. a first transistor and a capacitor provided in a pixel portion; a second transistor provided in the drive circuit portion; the first transistor includes a first oxide semiconductor layer, a first source electrode layer and a first drain electrode layer in contact with a lower surface of the first oxide semiconductor layer, and a first gate electrode layer overlapping with the first oxide semiconductor layer in a cross-sectional view; the capacitor has a first conductive layer and a second conductive layer as a pair of electrodes; the second conductive layer is the same layer as the first source electrode layer and the first drain electrode layer and has the same material as the first source electrode layer and the first drain electrode layer; the second transistor includes: a second oxide semiconductor layer; a second gate electrode layer below the second oxide semiconductor layer and overlapping with the second oxide semiconductor layer; a third gate electrode layer above the second oxide semiconductor layer and overlapping with the second oxide semiconductor layer; a second source electrode layer in contact with the second oxide semiconductor layer; and a second drain electrode layer in contact with the second oxide semiconductor layer; the second gate electrode layer is electrically connected to the third gate electrode layer; the first transistor does not have a gate electrode of the first transistor on an opposite side to a side of the first oxide semiconductor layer on which the first gate electrode layer is provided, a lower surface of the first oxide semiconductor layer has a region in contact with an insulating layer in contact with lower surfaces of the first source electrode layer and the first drain electrode layer, in a region that does not overlap with the first gate electrode layer in a cross-sectional view; the second source electrode layer and the second drain electrode layer are single layers containing an element selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium; The semiconductor device, wherein the first oxide semiconductor layer and the second oxide semiconductor layer each contain In, Ga, and Zn.

Images