Imaging element and imaging device

Abstract

To read a plurality of desired partial areas in an imaging area at high speed.SOLUTION: A solid-state image sensor includes a plurality of photoelectric conversion units PD, a signal line 27 that outputs a signal based on charges photoelectrically converted by the photoelectric conversion unit PD, a first selection unit SEL that is provided between the photoelectric conversion unit PD and the signal line 27 and outputs the signal of the selected photoelectric conversion unit PD, and a second selection unit ASEL that is provided between the first selection unit SEL and the signal line 27 and outputs the signal of the photoelectric conversion unit PD output from the first selection unit SEL to the signal line 27.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a solid-state imaging device and an imaging apparatus using the same. [Background technology]

[0002] Although a region selection technique for selecting an arbitrary region in an imaging device is known, it is not possible to read out multiple regions from the imaging region using the region selection technique. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-46600 Summary of the Invention [Means for solving the problem]

[0004] A solid-state imaging element according to a first aspect has a plurality of photoelectric conversion units, signal lines to which signals based on charges photoelectrically converted by the photoelectric conversion units are output, a first selection unit provided between the photoelectric conversion units and the signal lines to output the signals of the selected photoelectric conversion units, and a second selection unit provided between the first selection unit and the signal lines to output the signals of the photoelectric conversion units output from the first selection unit to the signal lines.

[0005] The solid-state imaging element according to the second aspect is the first aspect, and is provided with an area setting unit that selects the first selection unit or the second selection unit of a partial area of ​​the imaging area in which the multiple photoelectric conversion units are arranged.

[0006] In a third aspect of the solid-state imaging element, in the second aspect, the imaging area is divided into a plurality of predetermined areas, the area setting unit supplies a selection control signal for each of the predetermined plurality of areas to collectively select or deselect the first selection unit or the second selection unit of that area, and the partial area consists of one or more of the predetermined plurality of areas.

[0007] A solid-state imaging element according to a fourth aspect is the second aspect, wherein the area setting unit has a holding unit that holds a selection control signal for selecting or deselecting the first selection unit or the second selection unit, a writing unit that writes the selection control signal into the holding unit in response to a write control signal, and a writing control unit that supplies the write control signal to the writing unit.

[0008] A solid-state imaging element according to a fifth aspect is one in which, in any one of the second to fourth aspects, there are a plurality of partial regions, and the solid-state imaging element is provided with a control unit that selects the second selection unit or the first selection unit of each row of the plurality of partial regions, and performs read control for the row selected by the second selection unit or the first selection unit.

[0009] A solid-state imaging element according to a sixth aspect comprises a plurality of photoelectric conversion units, signal lines through which signals based on charges photoelectrically converted by the photoelectric conversion units are output, a selection unit provided between the photoelectric conversion units and the signal lines and outputting the signal of the selected photoelectric conversion unit, an amplification unit provided in series with the selection unit between the photoelectric conversion units and the signal lines and outputting the signal of the photoelectric conversion unit, and a power supply control means for selectively supplying an effective voltage level that is effective for the operation of the amplification unit or an ineffective voltage level that is not effective for the operation as a power supply voltage for the amplification unit.

[0010] A solid-state imaging element according to the seventh aspect has a plurality of photoelectric conversion units, a signal line through which a signal based on the charge photoelectrically converted by the photoelectric conversion units is output, a first selection unit provided in common to two or more of the plurality of photoelectric conversion units and outputting the signal of the selected two or more photoelectric conversion units, and a second selection unit provided between the first selection unit and the signal line and outputting the signal of the photoelectric conversion unit output from the first selection unit to the signal line.

[0011] The solid-state imaging element according to the eighth aspect is the seventh aspect, and further comprises an area setting unit that selects the first selection unit or the second selection unit of a partial area of ​​the imaging area in which the plurality of photoelectric conversion units are arranged.

[0012] A solid-state imaging element according to a ninth aspect is the same as that of the eighth aspect, in which the imaging area is divided into a plurality of predetermined areas, the area setting unit supplies a selection control signal for each of the predetermined plurality of areas to collectively select or deselect the first selection unit or the second selection unit of that area, and the partial area consists of one or more of the predetermined plurality of areas.

[0013] A solid-state imaging element according to a tenth aspect is the same as that of the eighth aspect, wherein the area setting unit has a holding unit that holds a selection control signal for selecting or deselecting the first selection unit or the second selection unit, a writing unit that writes the selection control signal into the holding unit in response to a write control signal, and a writing control unit that supplies the write control signal to the writing unit.

[0014] A solid-state imaging element according to an eleventh aspect is an element of any one of the eighth to tenth aspects, which has a plurality of partial regions, and is provided with a control unit that selects the second selection unit or the first selection unit of each row of the plurality of partial regions, and performs read control for the row selected by the second selection unit or the first selection unit.

[0015] A solid-state imaging element according to a twelfth aspect comprises a plurality of photoelectric conversion units, a signal line through which a signal based on the charges photoelectrically converted by the photoelectric conversion units is output, a selection unit provided in common to two or more of the plurality of photoelectric conversion units and outputting the signal of the selected two or more photoelectric conversion units, an amplification unit provided in series with the selection unit between the two or more photoelectric conversion units and the signal line and outputting the signal of the two or more photoelectric conversion units, and a power supply control means for selectively supplying an effective voltage level that is effective for the operation of the amplification unit or an ineffective voltage level that is not effective for the operation as a power supply voltage for the amplification unit.

[0016] An imaging device according to the 13th aspect comprises a solid-state imaging element according to any one of the second to fifth and eighth to eleventh aspects, and a user interface for a user to specify the partial area, and the partial area is set in accordance with instructions given by the user interface.

[0017] An imaging device according to the 14th aspect comprises a solid-state imaging element according to any one of the second to fifth and eighth to eleventh aspects, and a detection unit that detects the positions of multiple imaging targets in the imaging area based on image signals from the solid-state imaging element, and the partial area is set according to the positions detected by the detection unit. As means for solving the above problems, the following aspects are also presented: An imaging element according to a first aspect includes a plurality of pixels each having a photoelectric conversion unit that converts light into an electric charge, a transfer unit that transfers the electric charge converted by the photoelectric conversion unit to a floating diffusion, a first transistor including a gate electrically connected to the floating diffusion and outputting a signal, and a second transistor electrically connected to the first transistor and outputting the signal, a control line that outputs a control signal for controlling the transfer unit, the first transfer control line being electrically connected to the transfer unit of a first pixel among the plurality of pixels, the transfer unit of a second pixel among the plurality of pixels that is arranged together with the first pixel in a first direction, and the transfer unit of a third pixel among the plurality of pixels that is arranged alongside the first pixel in the first direction, The pixel circuit includes a second transfer control line electrically connected to the transfer unit of a fourth pixel arranged together with the first pixel in a second direction intersecting the first direction, the transfer unit of a fifth pixel among the plurality of pixels arranged together with the fourth pixel in the first direction, and the transfer unit of a sixth pixel among the plurality of pixels arranged alongside the fourth pixel in the first direction; a first control line that outputs a control signal for controlling the second transistor, the first control line being electrically connected to the second transistor of the first pixel, the second transistor of the second pixel, and the second transistor of the fourth pixel; and a second control line that outputs a control signal for controlling the second transistor, the second control line being electrically connected to the second transistor of the third pixel and the second transistor of the sixth pixel. In the second surface imaging device, the pixel in the first surface imaging device has a reset section that resets the potential of the floating diffusion. The imaging element with a third surface is an imaging element with the second surface, and includes a first reset control line that outputs a control signal for controlling the reset unit, the first reset control line being electrically connected to the reset unit of the first pixel, the reset unit of the second pixel, and the reset unit of the third pixel, and a second reset control line that outputs a control signal for controlling the reset unit, the second reset control line being electrically connected to the reset unit of the fourth pixel, the reset unit of the fifth pixel, and the reset unit of the sixth pixel. The imaging element according to the fourth aspect includes a photoelectric conversion unit that converts light into electric charges, a floating diffusion to which the electric charges converted by the photoelectric conversion unit are transferred, a reset unit that resets the potential of the floating diffusion, a plurality of pixels each having a first transistor including a gate electrically connected to the floating diffusion and outputting a signal, and a second transistor electrically connected to the first transistor and outputting the signal, a control line from which a control signal for controlling the reset unit is output, the first reset control line being electrically connected to the reset unit of a first pixel among the plurality of pixels, the reset unit of a second pixel among the plurality of pixels that is arranged together with the first pixel in a first direction, and the reset unit of a third pixel among the plurality of pixels that is arranged alongside the first pixel in the first direction, a control line electrically connected to the reset portion of a fourth pixel of the plurality of pixels that is arranged together with the first pixel in a second direction intersecting the first direction, the reset portion of a fifth pixel of the plurality of pixels that is arranged together with the fourth pixel in the first direction, and the reset portion of a sixth pixel of the plurality of pixels that is arranged alongside the fourth pixel in the first direction; a first control line from which a control signal for controlling the second transistor is output, the first control line being electrically connected to the second transistor of the first pixel, the second transistor of the second pixel, and the second transistor of the fourth pixel; and a second control line from which a control signal for controlling the second transistor is output, the second control line being electrically connected to the second transistor of the third pixel and the second transistor of the sixth pixel. The imaging element having the fifth surface is an imaging element having any one of the first to fourth surfaces, in which the second pixel is disposed adjacent to the first pixel in the first direction. The sixth surface imaging element is an imaging element having any one of the first to fifth surfaces, in which the fourth pixel is disposed adjacent to the first pixel in the second direction. The imaging element according to the seventh aspect is the imaging element according to any one of the first to sixth aspects, wherein the second transistor of the fifth pixel is electrically connected to the first control line. An imaging element according to an eighth aspect is an imaging element according to any one of the first to seventh aspects, wherein the pixel has a third transistor electrically connected to the first transistor and outputs the signal; a control line from which a control signal for controlling the third transistor is output, the third control line being electrically connected to the third transistor of the first pixel, the third transistor of the second pixel, and the third transistor of the third pixel; and a fourth control line from which a control signal for controlling the third transistor is output, the fourth control line being electrically connected to the third transistor of the fourth pixel, the third transistor of the fifth pixel, and the third transistor of the sixth pixel. An image sensor according to a ninth aspect is the image sensor according to the eighth aspect, wherein the third transistor electrically connects the first transistor and the second transistor. The imaging element according to the tenth aspect is an imaging element according to any one of the first to ninth aspects, which includes a first signal line through which the signal is output and which is electrically connected to the second transistor of the first pixel. The imaging device according to an eleventh aspect is the imaging device according to the tenth aspect, further comprising a first conversion section for converting the signal output to the first signal line into a digital signal. The imaging element according to the twelfth surface is the imaging element according to the tenth or eleventh surface, wherein the second transistor of the fourth pixel is electrically connected to the first signal line. The imaging element according to the thirteenth surface is an imaging element according to any one of the tenth to twelfth surfaces, which includes a second signal line through which the signal is output and which is electrically connected to the second transistor of the second pixel. The fourteenth surface imaging element is the thirteenth surface imaging element, further comprising a second conversion section for converting the signal output to the second signal line into a digital signal. An image sensor according to a fifteenth surface is the image sensor according to the thirteenth or fourteenth surface, in which the second transistor of the fifth pixel is electrically connected to the second signal line. The imaging element according to the sixteenth surface includes a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges, a first transfer unit that transfers the electric charges converted by the first photoelectric conversion unit to a floating diffusion, a second transfer unit that transfers the electric charges converted by the second photoelectric conversion unit to the floating diffusion, a plurality of pixel blocks each including a first transistor that includes a gate electrically connected to the floating diffusion and outputs a signal, and a second transistor that is electrically connected to the first transistor and outputs the signal, a control line that outputs a control signal for controlling the first transfer unit, the first transfer control line being electrically connected to the first transfer unit of a first pixel block among the plurality of pixel blocks, the first transfer unit of a second pixel block among the plurality of pixel blocks that is arranged together with the first pixel block in a first direction, and the first transfer unit of a third pixel block among the plurality of pixel blocks that is arranged alongside the first pixel block in the first direction, a second transfer control line electrically connected to the second transfer unit of the pixel block, the second transfer unit of the second pixel block, and the second transfer unit of the third pixel block; a control line through which a control signal for controlling the first transfer unit is output, the control line being electrically connected to the first transfer unit of a fourth pixel block arranged together with the first pixel block in a second direction intersecting the first direction among the plurality of pixel blocks, the first transfer unit of a fifth pixel block arranged together with the fourth pixel block in the first direction among the plurality of pixel blocks, and the first transfer unit of a sixth pixel block arranged alongside the fourth pixel block in the first direction among the plurality of pixel blocks; a fourth transfer control line through which a control signal for controlling the second transfer unit is output, the fourth transfer control line being electrically connected to the second transfer unit of the fourth pixel block, the second transfer unit of the fifth pixel block, and the second transfer unit of the sixth pixel block;The pixel block includes a first control line electrically connected to the second transistor of the second pixel block and the second transistor of the fourth pixel block, and a second control line that outputs a control signal for controlling the second transistor and is electrically connected to the second transistor of the third pixel block and the second transistor of the sixth pixel block. The seventeenth surface image sensor is the same as the sixteenth surface image sensor, in which the pixel block has a reset unit that resets the potential of the floating diffusion. The imaging element according to the 18th surface is an imaging element according to the 17th surface, which includes a control line through which a control signal for controlling the reset unit is output, a first reset control line electrically connected to the reset unit of the first pixel block, the reset unit of the second pixel block, and the reset unit of the third pixel block, and a second reset control line through which a control signal for controlling the reset unit is output, electrically connected to the reset unit of the fourth pixel block, the reset unit of the fifth pixel block, and the reset unit of the sixth pixel block. The imaging element according to the 19th aspect includes a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges, a floating diffusion to which the electric charges converted by the first photoelectric conversion unit and the electric charges converted by the second photoelectric conversion unit are transferred, a reset unit that resets the potential of the floating diffusion, a plurality of pixel blocks having a first transistor that includes a gate electrically connected to the floating diffusion and outputs a signal, and a second transistor that is electrically connected to the first transistor and outputs the signal, a control line that outputs a control signal for controlling the reset unit, the first reset control line being electrically connected to the reset unit of a first pixel block among the plurality of pixel blocks, the reset unit of a second pixel block among the plurality of pixel blocks that is arranged together with the first pixel block in a first direction, and the reset unit of a third pixel block among the plurality of pixel blocks that is arranged alongside the first pixel block in the first direction, a control line for outputting a control signal to control the second transistor, the control line being electrically connected to the reset unit of a fourth pixel block among the plurality of pixel blocks that is arranged together with the first pixel block in a second direction intersecting the first direction, the reset unit of a fifth pixel block among the plurality of pixel blocks that is arranged together with the fourth pixel block in the first direction, and the reset unit of a sixth pixel block among the plurality of pixel blocks that is arranged alongside the fourth pixel block in the first direction; a control line for outputting a control signal to control the second transistor, the control line being electrically connected to the second transistor of the first pixel block, the second transistor of the second pixel block, and the second transistor of the fourth pixel block; and a control line for outputting a control signal to control the second transistor, the control line being electrically connected to the second transistor of the third pixel block and the second transistor of the sixth pixel block. The twentieth surface imaging element is an imaging element having any one of the sixteenth to nineteenth surfaces, in which the second pixel block is disposed adjacent to the first pixel block in the first direction. The imaging element having the 21st surface is an imaging element having any one of the 16th to 20th surfaces, in which the fourth pixel block is disposed adjacent to the first pixel block in the second direction. An image sensor according to a 22nd surface is an image sensor according to any one of the 16th to 21st surfaces, wherein the second transistor of the fifth pixel block is electrically connected to the first control line. An imaging element according to a 23rd aspect is an imaging element according to any one of the 16th to 22nd aspects, wherein the pixel block has a third transistor electrically connected to the first transistor and outputs the signal; a control line from which a control signal for controlling the third transistor is output, the third control line being electrically connected to the third transistor of the first pixel block, the third transistor of the second pixel block, and the third transistor of the third pixel block; and a fourth control line from which a control signal for controlling the third transistor is output, the fourth control line being electrically connected to the third transistor of the fourth pixel block, the third transistor of the fifth pixel block, and the third transistor of the sixth pixel block. An image pickup device according to a 24th surface is the image pickup device according to the 23rd surface, wherein the third transistor electrically connects the first transistor and the second transistor. The imaging element according to the 25th surface is an imaging element according to any one of the 16th to 24th surfaces, which includes a first signal line through which the signal is output and which is electrically connected to the second transistor of the first pixel block. The 26th surface imaging element is the 25th surface imaging element, further comprising a first conversion section for converting the signal output to the first signal line into a digital signal. An image sensor according to a 27th surface is the image sensor according to the 25th or 26th surface, wherein the second transistor of the fourth pixel block is electrically connected to the first signal line. The imaging element according to the 28th surface is an imaging element according to any one of the 25th to 27th surfaces, which includes a second signal line through which the signal is output and which is electrically connected to the second transistor of the second pixel block. The 29th surface imaging element is the 28th surface imaging element, further comprising a second conversion section for converting the signal output to the second signal line into a digital signal. An image sensor according to a thirtieth surface is the image sensor according to the twenty-eighth or twenty-ninth surface, wherein the second transistor of the fifth pixel block is electrically connected to the second signal line. The imaging element according to the 31st surface is the imaging element according to any one of the 16th to 30th surfaces, in which the second photoelectric conversion unit is disposed next to the first photoelectric conversion unit. The imaging element based on the 32nd surface is the imaging element based on the 31st surface, in which the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the second direction. An imaging element having a 33rd surface is an imaging element having any one of the 16th to 30th surfaces, in which the second photoelectric conversion unit is arranged alongside the first photoelectric conversion unit in the second direction. An imaging device according to a thirty-fourth aspect includes an imaging element according to any one of the first to thirty-third aspects. [Effects of the Invention]

[0018] According to the present invention, it is possible to provide a solid-state imaging element capable of reading out desired partial regions of an imaging region at high speed, and an imaging apparatus using the same. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a schematic block diagram showing an electronic camera according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device in FIG. [Figure 3] FIG. 2 is a schematic plan view showing the solid-state imaging device in FIG. [Figure 4] 2 is a circuit diagram showing a predetermined partial area that forms a part of the imaging area of ​​the solid-state imaging element in FIG. 1. FIG. [Figure 5] FIG. 5 is a circuit diagram illustrating an abstraction of the circuit shown in FIG. [Figure 6] 2 is a diagram schematically showing an example of setting a partial region to be read out from the imaging region of the solid-state imaging element in FIG. 1; FIG. [Figure 7] 7 is a diagram showing a selection control signal for realizing the setting example shown in FIG. 6 in the solid-state imaging device in FIG. [Figure 8] 2 is a timing chart showing an example of readout control in a partial area imaging mode of the solid-state imaging element in FIG. 1; [Figure 9] 1. FIG. 4 is a diagram schematically illustrating another example of setting a partial region to be read out of the imaging region of the solid-state imaging element in FIG. [Figure 10] 10 is a diagram showing a selection control signal for realizing the setting example shown in FIG. 9 in the solid-state imaging device in FIG. [Figure 11] 1. FIG. 4 is a diagram schematically illustrating yet another setting example of a partial region to be read out of the imaging region of the solid-state imaging element in FIG. [Figure 12] 12 is a diagram showing a selection control signal for realizing the setting example shown in FIG. 11. FIG. [Figure 13] 10 is a timing chart showing another example of readout control in the partial area imaging mode of the solid-state imaging element in FIG. [Figure 14] 2 is a timing chart showing an example of readout control in a full-area imaging mode of the solid-state imaging element in FIG. 1; [Figure 15] 4 is a schematic flowchart showing an example of the operation of the electronic camera shown in FIG. 1 in a first partial area photographing mode. [Figure 16] 10 is a schematic flowchart showing an example of the operation of the electronic camera shown in FIG. 1 in a second partial area photographing mode. [Figure 17]FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a second embodiment of the present invention. [Figure 18] 18 is a circuit diagram showing a predetermined partial area that forms a part of the imaging area of ​​the solid-state imaging element shown in FIG. 17. FIG. [Figure 19] FIG. 19 is a circuit diagram illustrating an abstraction of the circuit shown in FIG. 18. [Figure 20] 18 is a diagram showing power supply voltage signals that realize the same settings as the setting example shown in FIG. 6 in the solid-state imaging device shown in FIG. 17. FIG. [Figure 21] FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a third embodiment of the present invention. [Figure 22] 22 is a circuit diagram showing a predetermined partial area that forms a part of the imaging area of ​​the solid-state imaging element shown in FIG. 21. FIG. [Figure 23] 22 is a timing chart showing an example of readout control in a partial area imaging mode of the solid-state imaging element shown in FIG. 21. [Figure 24] FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a fourth embodiment of the present invention. [Figure 25] 25 is a circuit diagram showing a predetermined partial area that forms a part of the imaging area of ​​the solid-state imaging element shown in FIG. 24. FIG. [Figure 26] FIG. 26 is a circuit diagram illustrating an abstraction of the circuit shown in FIG. 25. [Figure 27] 25 is a timing chart showing an example of readout control in a partial area imaging mode of the solid-state imaging element shown in FIG. 24. [Figure 28] FIG. 11 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a fifth embodiment of the present invention. [Figure 29] 29 is a circuit diagram showing a part of an imaging region of the solid-state imaging element shown in FIG. 28. [Figure 30] 29 is a timing chart showing write control signals when an H signal and an L signal are written to a capacitor in the solid-state imaging device shown in FIG. 28. [Figure 31]29 is a timing chart showing write control signals for realizing the same settings as the setting example shown in FIG. 6 in the solid-state imaging device shown in FIG. 28. [Figure 32] FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a sixth embodiment of the present invention. [Figure 33] 33 is a circuit diagram showing a part of an imaging region of the solid-state imaging element shown in FIG. 32. [Figure 34] FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a seventh embodiment of the present invention. [Figure 35] 35 is a circuit diagram showing a part of an imaging region of the solid-state imaging element shown in FIG. 34. [Figure 36] FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to an eighth embodiment of the present invention. [Figure 37] FIG. 37 is a circuit diagram showing one pixel of the solid-state imaging device shown in FIG. [Figure 38] 37 is a timing chart showing write control signals for realizing the same settings as the setting example shown in FIG. 6 in the solid-state imaging device shown in FIG. 36. DETAILED DESCRIPTION OF THE INVENTION

[0020] A solid-state imaging device and an imaging apparatus according to the present invention will be described below with reference to the drawings.

[0021] [First embodiment]

[0022] FIG. 1 is a schematic block diagram showing an electronic camera 1 as an imaging device according to a first embodiment of the present invention.

[0023] The electronic camera 1 according to this embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this and can be applied to various imaging devices such as other electronic cameras such as compact cameras, electronic cameras mounted on mobile phones, electronic cameras such as video cameras that capture moving images, surveillance cameras that capture monitoring moving images, imaging devices that are incorporated into microscopes to capture microscopic images, and imaging devices that are incorporated into telescopes to capture telescopic images.

[0024] A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of this photographing lens 2 are driven by a lens control unit 3. In the image space of this photographing lens 2, the imaging surface of a solid-state imaging device 4 is arranged.

[0025] The solid-state imaging element 4 is driven by commands from the imaging control unit 5 and outputs a digital image signal. When capturing a still image, the imaging control unit 5 controls the solid-state imaging element 4 to perform a predetermined readout operation after a so-called global reset, which resets all pixels simultaneously, followed by exposure using a mechanical shutter (not shown). In electronic viewfinder mode or video capture (such as in first and second partial area capture modes or full area capture mode, which will be described later), the imaging control unit 5 controls the solid-state imaging element 4 to perform a predetermined readout operation while using a so-called rolling electronic shutter. The digital signal processing unit 6 performs image processing, such as digital amplification, color interpolation, and white balance processing, on the digital image signal output from the solid-state imaging element 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in a memory 7. The memory 7 is connected to a bus 8. The bus 8 is also connected to the lens control unit 3, the imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. An operation unit 14 such as a release button is connected to the CPU 9. A recording medium 11a is detachably attached to the recording unit 11.

[0026] When an instruction to select electronic viewfinder mode, video recording, or still image recording is issued via the operation unit 14, the CPU 9 in the electronic camera 1 drives the imaging control unit 5 accordingly. At this time, the lens control unit 3 adjusts the focus and aperture as appropriate. The solid-state imaging element 4 is driven by commands from the imaging control unit 5 to output a digital image signal. The digital image signal from the solid-state imaging element 4 is processed by the digital signal processing unit 6 and then stored in memory 7. The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal on the recording medium 11a during video recording. When capturing still images, the CPU 9 processes the digital image signal from the solid-state imaging element 4 in the digital signal processing unit 6 and stores it in memory 7. In still image recording, the CPU 9 then performs desired processing as necessary via the image processing unit 13 or image compression unit 12 based on commands from the operation unit 14, and then causes the recording unit 11 to output the processed signal, which is then recorded on the recording medium 11a.

[0027] Fig. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging element 4 in Fig. 1. In this embodiment, the solid-state imaging element 4 is configured as a CMOS type solid-state imaging element, but may also be configured as, for example, another XY address type solid-state imaging element.

[0028] The solid-state imaging element 4 includes pixels PX arranged in a two-dimensional matrix of N rows and M columns in an imaging region 21, a vertical scanning circuit 22, an area setting circuit 23, control lines 24 to 26 provided for each row of the pixels PX, a plurality (M) of vertical signal lines 27 provided for each column of the pixels PX and receiving signals from the pixels PX in the corresponding column, a constant current source 28 provided for each vertical signal line 27, a column amplifier 29, a CDS circuit (correlated double sampling circuit) 30, and an A / D converter 31 provided corresponding to each vertical signal line 27, a horizontal readout circuit 32, and a control line 33 provided for each predetermined partial area AR (see FIG. 3 described later) of the imaging region 21. The predetermined partial area AR is a predetermined part (partial area) of the imaging region 21.

[0029] An analog amplifier or a so-called switched capacitor amplifier may be used as the column amplifier 29. Also, the column amplifier 29 does not necessarily have to be provided.

[0030] FIG. 3 is a schematic plan view showing the solid-state imaging device 4 (particularly its imaging region 21) in FIG. 1. In this embodiment, as shown in FIG. 3, the imaging region 21 of the solid-state imaging device 4 is divided into J×K predetermined partial regions AR arranged in a matrix of J rows and K columns. When distinguishing between the predetermined partial regions AR, the predetermined partial region AR in the jth row and kth column is denoted by the symbol AR(j, k). As shown in FIGS. 4 and 5, each predetermined partial region AR is made up of A×B pixels PX in A rows and B columns (A is an integer equal to or greater than 2, and B is an integer equal to or greater than 1). In this embodiment, the sizes of the predetermined partial regions AR (the number of rows A and the number of columns B of pixels PX) are the same, but this is not limited to this in the present invention. However, it is preferable that the number of rows A of pixels PX in each predetermined partial region AR is the same.

[0031] 4 is a circuit diagram showing a predetermined partial area AR constituting a part of the imaging area 21 of the solid-state imaging device 4 in FIG. 4 shows a predetermined partial area AR(j,k) in the jth row and the kth column, and a part of an adjacent predetermined partial area AR(j-1,k) in the j-1th row and the kth column. The predetermined partial area AR(j,k) is made up of A×B pixels PX arranged in A rows and B columns from the nth row to the (n+A-1)th row. For convenience of illustration, FIG. 4 does not show the connections of the control lines 24-26 and 33 and the power supply line 34 described later. However, the control lines 24-26 are connected in common to each row of the pixels PX, the control line 33 is connected in common to each predetermined partial area AR, and the power supply line 34 is connected in common to all the pixels PX.

[0032] In this embodiment, all pixels PX have the same circuit configuration. Unlike a general CMOS image sensor, each pixel PX has two selection transistors (SEL, ASEL) for selecting the pixel PX in this embodiment, but the other configurations of each pixel PX are the same as those of a general CMOS image sensor.

[0033] That is, as shown in Fig. 4, each pixel PX includes a photodiode PD as a photoelectric conversion unit that generates and accumulates charge in response to incident light, a floating capacitance unit FD as a charge-voltage conversion unit that receives the charge and converts the charge into a voltage, an amplifier transistor AMP as an amplifier that outputs a signal corresponding to the potential of the floating capacitance unit FD as an output signal of the pixel PX, a transfer transistor TX that transfers charge from the photodiode PD to the floating capacitance unit FD, a reset transistor RST that resets the potential of the floating capacitance unit FD, a selection transistor SEL that serves as a selection switch serving as a first selection unit for selecting the pixel PX, and a selection transistor ASEL that serves as a selection switch serving as a second selection unit for selecting the pixel PX, all of which are connected as shown in Fig. 4. In this embodiment, the drains of the amplifier transistors AMP of all pixels PX (point b in Fig. 4) are commonly connected by a power supply line 34, to which a fixed effective voltage level VDD that is effective for the operation of the amplifier transistor AMP is supplied as a power supply voltage for the amplifier transistor AMP. This effective voltage level VDD is also supplied to the drains of the reset transistors RST of each pixel PX via the power supply line 34. In FIG. 2, the power supply line 34 is omitted.

[0034] In this embodiment, the output signal of each pixel PX is output to a vertical signal line 27 that receives the output signal of the pixel PX and the output signals of the pixels PX aligned in the column direction relative to the pixel PX only when both the first and second selection units of the pixel PX are in a selected state. Specifically, in this embodiment, this is achieved by connecting selection transistors SEL and ASEL in series in each pixel PX between the source of the amplification transistor AMP and the vertical signal line 27 corresponding to the pixel PX. Only when both selection transistors SEL and ASEL are on (in a selected state), is the output signal of the pixel PX output to the vertical signal line 27. Note that the connection order of the selection transistors SEL and ASEL between the amplification transistor AMP and the vertical signal line 27 may be reversed from the order shown in FIG. 4.

[0035] Although not shown in the drawings, in this embodiment, a plurality of types of color filters, each of which transmits light of a different color component, are arranged in a predetermined color array (e.g., a Bayer array) on the light incident side of the photodiode PD of each pixel PX. The pixel PX outputs an electrical signal corresponding to each color through color separation by the color filters.

[0036] In this embodiment, the transistors TX, AMP, RST, SEL, and ASEL are all nMOS transistors.

[0037] The gates of the transfer transistors TX for each row of pixels PX are commonly connected to a control line 25, to which a control signal φTX is supplied from the vertical scanning circuit 22. The gates of the reset transistors RST for each row of pixels PX are commonly connected to a control line 24, to which a control signal φRST is supplied from the vertical scanning circuit 22. The gates of the selection transistors SEL for each row are commonly connected to a control line 26, to which a control signal φSEL is supplied from the vertical scanning circuit 22. When distinguishing between the control signals φTX for each row, the control signal φTX supplied to the gates of the transfer transistors TX of the pixels PX in the nth row is denoted by the symbol φTX(n). This also applies to the other control signals φRST and φSEL.

[0038] The gates of the select transistors ASEL (point a in FIG. 4) are commonly connected to a control line 33 for each predetermined partial area AR, and a control signal φASEL is supplied thereto from the area setting circuit 23. FIG. 5 is an abstract illustration of the circuit shown in FIG. 4, focusing on the connection relationship of the gates (point a) of the select transistors ASEL in each predetermined partial area AR via the control line 33. When each control signal φASEL is distinguished for each predetermined partial area AR, the control signal φASEL supplied to the gate of the select transistor ASEL of the pixel PX in the jth row and kth column of the predetermined partial area AR(j,k) is indicated by the symbol φASEL(j,k). Note that the layout of the area setting circuit 23 and the actual layout (routing path, etc.) of the control lines 33 are not limited in any way.

[0039] 1, the region setting circuit 23 supplies a control signal φASEL as a selection control signal for collectively selecting or deselecting the selection transistors ASEL serving as the second selection units of the pixels PX in each of the predetermined partial regions AR in the imaging region 21. As a result, the region setting circuit 23 sets the predetermined partial region AR, in which the selection transistors ASEL are set to the selected state, as a region from which output signals of the pixels PX in the imaging region 21 are read out.

[0040] 1, the vertical scanning circuit 22 outputs control signals φTX, φRST, and φSEL for each row of pixels PX, and, in conjunction with the area setting operation by the area setting circuit 23, realizes still image readout operations and moving image readout operations such as first and second partial area shooting modes, which will be described later. By this control, signals (analog signals) of the pixels PX in the area set by the area setting circuit 23 are supplied to the corresponding vertical signal lines 27.

[0041] The signals read out to the vertical signal lines 27 are amplified by a column amplifier 29 for each column, and then processed by a CDS circuit 30 to obtain the difference between the optical signal (a signal containing optical information photoelectrically converted by the pixel PX) and the dark signal (a differential signal containing a noise component to be subtracted from the optical signal), and then converted into a digital signal by an A / D converter 31, which then stores the digital signal. The digital image signals stored in each A / D converter 31 are horizontally scanned by a horizontal readout circuit 32, converted into a predetermined signal format as necessary, and output to the outside (digital signal processing unit 6 in FIG. 1).

[0042] The CDS circuit 30 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in Fig. 1, and samples the output signal of the column amplifier 29 as a dark signal when φDARKC switches from high level (H) to low level (L). It also receives a light signal sampling signal φSIGC from the timing generation circuit under the control of the imaging control unit 5 in Fig. 1, and samples the output signal of the column amplifier 29 as a light signal when φSIGC switches from high level to low level. The CDS circuit 30 then outputs a signal corresponding to the difference between the sampled dark signal and the light signal, based on the clock and pulses from the timing generation circuit. A known configuration can be used for the CDS circuit 30.

[0043] 6 is a diagram schematically illustrating an example of setting partial areas to be read out of the imaging area 21 of the solid-state imaging element 4 in the partial area shooting mode. The partial area shooting mode is an operating mode in which output signals of pixels PX of one desired partial area or desired partial areas of the imaging area 21 of the solid-state imaging element 4 are selectively read out. For ease of understanding, in FIG. 6, it is assumed that N=9, M=12, A=3, and B=3, the imaging area 21 is made up of 9×12 pixels PX in 9 rows and 12 columns, and each predetermined partial area AR is made up of pixels PX in 3 rows and 3 columns. The following description is equally applicable even if the values ​​of N, M, A, and B are other values.

[0044] 6, the predetermined partial areas AR(3,1), AR(1,2), AR(2,3), and AR(1,4) set as the four partial areas to be read are hatched. In this example, each partial area to be read consists of one predetermined partial area AR.

[0045] Figure 7 shows the selection control signal φASEL that realizes the setting example shown in Figure 6 in the solid-state imaging device 4 in Figure 1. The selection control signals φASEL(3,1), φASEL(1,2), φASEL(2,3), and φASEL(1,4) supplied to the gates of the selection transistors ASEL in the predetermined partial areas AR(3,1), AR(1,2), AR(2,3), and AR(1,4) are maintained at a high level (H), and the other selection control signals φASEL are maintained at a low level (L). As a result, the selection transistors ASEL in the predetermined partial areas AR(3,1), AR(1,2), AR(2,3), and AR(1,4) are maintained on, while the selection transistors ASEL in the other predetermined partial areas AR are maintained off.

[0046] In this embodiment, in the partial area shooting mode, when the partial area to be read out is set as shown in Fig. 6, for example, read control is performed as shown in Fig. 8. Fig. 8 is a timing chart showing an example of read control in the partial area shooting mode of the solid-state imaging element 4 in Fig. 1.

[0047] In the example shown in FIG. 8 , during a period T1, the vertical scanning circuit 22 simultaneously reads out the first, fourth, and seventh rows of pixels PX in the imaging region 21, which correspond to the first row of pixels PX in each predefined partial region AR. During the following period T2, the vertical scanning circuit 22 simultaneously reads out the second, fifth, and eighth rows of pixels PX in the imaging region 21, which correspond to the second row of pixels PX in each predefined partial region AR. During the following period T3, the vertical scanning circuit 22 simultaneously reads out the third, sixth, and ninth rows of pixels PX in the imaging region 21, which correspond to the third row of pixels PX in each predefined partial region AR. This completes the readout of one frame. By sequentially repeating the periods T1 to T3, multiple frames are read out using the rolling electronic shutter. For example, the exposure period for the first row of pixels PX is the period from when the control signal φTX(1) for the first row changed from high to low last time to when the control signal φTX(1) changes from high to low this time. The read control for each of the periods T1 to T3 will be described in detail below.

[0048] Immediately before the start of each of the periods T1 to T3, the transistors SEL, RST, and TX of the pixels PX in all rows are turned off.

[0049] In period T1, φSEL(1) in the first row, φSEL(4) in the fourth row, and φSEL(7) in the seventh row are set to a high level, turning on the selection transistors SEL(1), SEL(4), and SEL(7) of the pixels PX in the first, fourth, and seventh rows, and selecting the pixels PX in the first, fourth, and seventh rows. However, since the selection control signal φASEL is now as shown in Fig. 7 so as to realize the setting example shown in Fig. 6, the selection transistors ASEL of the pixels PX in the hatched columns (the fourth to sixth columns and the tenth to twelfth columns) of the pixels PX in the first row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (the first to third columns and the seventh to ninth columns) of the pixels PX in the first row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (7th to 9th columns) of the pixels PX in the 4th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (1st to 6th columns, 10th to 12th columns) of the pixels PX in the 4th row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (1st to 3rd columns) of the pixels PX in the 7th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (4th to 12th columns) of the pixels PX in the 7th row are turned off.

[0050] Therefore, during period T1, the output signals of only the pixels PX in which both the selection transistors SEL and ASEL are on (pixels PX in the 4th to 6th columns and the 10th to 12th columns in the 1st row, pixels PX in the 7th to 9th columns in the 4th row, and pixels PX in the 1st to 3rd columns in the 7th row) can be output to the corresponding vertical signal line 27.

[0051] Immediately after the start of period T1, for a fixed period of time, the control signals φRST(1), φRST(4), φRST(7) of the first, fourth, and seventh rows are set to high level, the reset transistors RST of the pixels PX of the first, fourth, and seventh rows are temporarily turned on, and the potential of the floating capacitance unit FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

[0052] By setting the dark signal sampling signal φDARKC to a high level for a certain period of time from a subsequent point t1 during the period T1, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the fourth to sixth and tenth to twelfth columns in the first row, the pixels PX in the seventh to ninth columns in the fourth row, and the pixels PX in the first to third columns in the seventh row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal.

[0053] After that, from time t2 during period T1, the control signals φTX(1), φTX(4), and φTX(7) for the first, fourth, and seventh rows are set to high level for a fixed period of time, turning on the transfer transistors TX of the pixels PX in the first, fourth, and seventh rows. As a result, the signal charges accumulated in the photodiodes PD of the pixels PX in the first, fourth, and seventh rows are transferred to the floating capacitance units FD of the pixels PX in the first, fourth, and seventh rows, respectively. The potentials of the floating capacitance units FD of the pixels PX in the first, fourth, and seventh rows (the potentials of the gates of the amplification transistors AMP), excluding noise components, are proportional to the amount of each signal charge and the reciprocal of the capacitance values ​​of the floating capacitance units FD of the pixels PX in the first, fourth, and seventh rows.

[0054] By setting the optical signal sampling signal φSIGC to a high level for a certain period of time from a subsequent point t3 during the period T1, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the fourth to sixth and tenth to twelfth columns in the first row, the pixels PX in the seventh to ninth columns in the fourth row, and the pixels PX in the first to third columns in the seventh row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal.

[0055] After that, after φSIGC goes low, the CDS circuit 30 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 31 converts the signal corresponding to this difference into a digital signal and stores it. The digital image signal stored in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output as a digital image signal to the outside (digital signal processing unit 6 in FIG. 1).

[0056] In period T2 after period T1, φSEL(2) in the second row, φSEL(5) in the fifth row, and φSEL(8) in the eighth row are set to a high level, turning on the selection transistors SEL(2), SEL(5), and SEL(8) of the pixels PX in the second, fifth, and eighth rows, and selecting the pixels PX in the second, fifth, and eighth rows. However, since the selection control signal φASEL is now as shown in Fig. 7 so as to realize the setting example shown in Fig. 6, the selection transistors ASEL of the pixels PX in the hatched columns (the fourth to sixth columns and the tenth to twelfth columns) of the pixels PX in the second row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (the first to third columns and the seventh to ninth columns) of the pixels PX in the second row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (7th to 9th columns) of the pixels PX in the 5th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (1st to 6th columns, 10th to 12th columns) of the pixels PX in the 5th row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (1st to 3rd columns) of the pixels PX in the 8th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (4th to 12th columns) of the pixels PX in the 8th row are turned off.

[0057] Therefore, during period T2, the output signals of only the pixels PX in which both the selection transistors SEL and ASEL are turned on (pixels PX in the 4th to 6th columns and the 10th to 12th columns in the 2nd row, pixels PX in the 7th to 9th columns in the 5th row, and pixels PX in the 1st to 3rd columns in the 8th row) can be output to the corresponding vertical signal line 27.

[0058] Immediately after the start of period T2, for a fixed period of time, the control signals φRST(2), φRST(5), φRST(8) on the second, fifth, and eighth rows are set to high level, the reset transistors RST of the pixels PX on the second, fifth, and eighth rows are temporarily turned on, and the potential of the floating capacitance unit FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

[0059] By setting the dark signal sampling signal φDARKC to a high level for a certain period of time from a later point in time during the period T2, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the fourth to sixth and tenth to twelfth columns in the second row, the pixels PX in the seventh to ninth columns in the fifth row, and the pixels PX in the first to third columns in the eighth row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal.

[0060] From a later point during period T2, the control signals φTX(2), φTX(5), and φTX(8) for the second, fifth, and eighth rows are set to high level for a fixed period of time, turning on the transfer transistors TX of the pixels PX in the second, fifth, and eighth rows. As a result, the signal charges accumulated in the photodiodes PD of the pixels PX in the second, fifth, and eighth rows are transferred to the floating capacitance units FD of the pixels PX in the second, fifth, and eighth rows, respectively. The potentials of the floating capacitance units FD of the pixels PX in the second, fifth, and eighth rows (the potentials of the gates of the amplification transistors AMP), excluding noise components, are proportional to the amounts of the signal charges and the reciprocals of the capacitance values ​​of the floating capacitance units FD of the pixels PX in the second, fifth, and eighth rows.

[0061] By setting the optical signal sampling signal φSIGC to a high level for a certain period of time from a later point in time during the period T2, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the fourth to sixth and tenth to twelfth columns in the second row, the pixels PX in the seventh to ninth columns in the fifth row, and the pixels PX in the first to third columns in the eighth row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal.

[0062] After that, after φSIGC goes low, the CDS circuit 30 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 31 converts the signal corresponding to this difference into a digital signal and stores it. The digital image signal stored in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output as a digital image signal to the outside (digital signal processing unit 6 in FIG. 1).

[0063] In period T3 after period T2, φSEL(3) in the third row, φSEL(6) in the sixth row, and φSEL(9) in the ninth row are set to a high level, turning on the selection transistors SEL(3), SEL(6), and SEL(9) of the pixels PX in the third, sixth, and ninth rows, and selecting the pixels PX in the third, sixth, and ninth rows. However, since the selection control signal φASEL is now as shown in FIG. 7 so as to realize the setting example shown in FIG. 6, the selection transistors ASEL of the pixels PX in the hatched columns (the fourth to sixth, tenth to twelfth columns) of the pixels PX in the third row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (the first to third, seventh to ninth columns) of the pixels PX in the third row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (7th to 9th columns) of the pixels PX in the 6th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (1st to 6th columns, 10th to 12th columns) of the pixels PX in the 6th row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (1st to 3rd columns) of the pixels PX in the 8th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (4th to 12th columns) of the pixels PX in the 9th row are turned off.

[0064] Therefore, during period T3, the output signals of only the pixels PX in which both the selection transistors SEL and ASEL are on (pixels PX in the 4th to 6th columns and the 10th to 12th columns in the 3rd row, pixels PX in the 7th to 9th columns in the 6th row, and pixels PX in the 1st to 3rd columns in the 9th row) can be output to the corresponding vertical signal line 27.

[0065] Immediately after the start of period T3, for a fixed period of time, the control signals φRST(3), φRST(6), φRST(9) on the third, sixth, and ninth rows are set to high level, the reset transistors RST of the pixels PX on the third, sixth, and ninth rows are temporarily turned on, and the potential of the floating capacitance unit FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

[0066] By setting the dark signal sampling signal φDARKC to a high level for a certain period of time from a later point in time during period T3, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the fourth to sixth and tenth to twelfth columns in the third row, the pixels PX in the seventh to ninth columns in the sixth row, and the pixels PX in the first to third columns in the ninth row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal.

[0067] From a later point during period T3, the control signals φTX(3), φTX(6), and φTX(9) for the third, sixth, and ninth rows are set to high level for a fixed period of time, turning on the transfer transistors TX of the pixels PX in the third, sixth, and ninth rows. As a result, the signal charges accumulated in the photodiodes PD of the pixels PX in the third, sixth, and ninth rows are transferred to the floating capacitance units FD of the pixels PX in the third, sixth, and ninth rows, respectively. The potentials of the floating capacitance units FD of the pixels PX in the third, sixth, and ninth rows (the potentials of the gates of the amplification transistors AMP), excluding noise components, are proportional to the amounts of the signal charges and the reciprocals of the capacitance values ​​of the floating capacitance units FD of the pixels PX in the third, sixth, and ninth rows.

[0068] By setting the optical signal sampling signal φSIGC to a high level for a certain period of time from a later point in time during period T3, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the fourth to sixth and tenth to twelfth columns in the third row, the pixels PX in the seventh to ninth columns in the sixth row, and the pixels PX in the first to third columns in the ninth row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal.

[0069] After that, after φSIGC goes low, the CDS circuit 30 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 31 converts the signal corresponding to this difference into a digital signal and stores it. The digital image signal stored in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output as a digital image signal to the outside (digital signal processing unit 6 in FIG. 1).

[0070] In this way, output signals from the pixels PX in the plurality of partial regions set as shown in FIG. 6 are read out.

[0071] Fig. 9 is a diagram schematically showing another setting example of a partial area to be read out of the imaging area 21 of the solid-state imaging element 4 in the partial area shooting mode, and corresponds to Fig. 6. Fig. 10 shows the selection control signal φASEL that realizes the setting example shown in Fig. 9 in the solid-state imaging element 4 in Fig. 1, and corresponds to Fig. 7.

[0072] 9, the predetermined partial areas AR(1,1), AR(1,2), AR(2,3), and AR(2,4) set as the two partial areas to be read are hatched. In this example, one partial area to be read consists of two predetermined partial areas AR(1,1) and AR(1,2), and the other partial area to be read consists of two predetermined partial areas AR(2,3) and AR(2,4).

[0073] Thus, in this embodiment, each of the one or more partial areas to be read may consist of one predetermined partial area AR or may consist of multiple predetermined partial areas AR. Also, in this embodiment, when multiple partial areas are read, each partial area does not necessarily have to consist of the same number of predetermined partial areas AR, and the number of predetermined partial areas AR that make up one partial area to be read may be different from the number of predetermined partial areas AR that make up another partial area to be read.

[0074] In this embodiment, even when the partial area to be read is set as shown in FIG. 9 in the partial area shooting mode, read control is performed as shown in FIG. 8, in the same way as when the partial area to be read is set as shown in FIG. 6, for example.

[0075] Fig. 11 is a diagram schematically showing yet another setting example of a partial area to be read out of the imaging area 21 of the solid-state imaging element 4 in the partial area shooting mode, and corresponds to Fig. 6. Fig. 12 shows the selection control signal φASEL that realizes the setting example shown in Fig. 11 in the solid-state imaging element 4 in Fig. 1, and corresponds to Fig. 7.

[0076] In Fig. 11, the preset partial areas AR(3,1), AR(1,1), AR(2,3), and AR(1,4) that are set as the four partial areas to be read are hatched. In the setting example shown in Fig. 6 and the setting example shown in Fig. 9, two or more preset partial areas AR are not set as areas to be read in any column of the preset partial areas AR, whereas in the setting example shown in Fig. 11, two preset partial areas AR(3,1) and AR(1,1) are set as partial areas to be read in the first column of the preset partial areas AR.

[0077] Therefore, in this embodiment, even if the partial area to be read out is set as shown in Figure 11 in the partial area shooting mode, if readout control is performed as shown in Figure 8, the output signals of two or more pixels PX will be read out simultaneously to the same vertical signal line 27, causing interference between the two signals, and the output signals of the pixels PX will not be able to be read out properly. Specifically, during period T1 in FIG. 8, the output signals of the pixels PX in the first to third columns in the first row and the output signals of the pixels PX in the first to third columns in the seventh row are simultaneously read out onto the same vertical signal line 27, causing interference between the two signals; during period T2 in FIG. 8, the output signals of the pixels PX in the first to third columns in the second row and the output signals of the pixels PX in the first to third columns in the eighth row are simultaneously read out onto the same vertical signal line 27, causing interference between the two signals; and during period T3 in FIG. 8, the output signals of the pixels PX in the first to third columns in the third row and the output signals of the pixels PX in the first to third columns in the ninth row are simultaneously read out onto the same vertical signal line 27, causing interference between the two signals.

[0078] Therefore, in this embodiment, if it is permitted that the partial area to be read out in the partial area shooting mode is set as shown in Fig. 11, the vertical scanning circuit 22 may perform, for example, the read control shown in Fig. 13 instead of the read control shown in Fig. 8. Fig. 13 is a timing chart showing another example of the read control in the partial area shooting mode of the solid-state imaging element 4 in Fig. 1, and corresponds to Fig. 8.

[0079] In the example shown in Figure 13, the vertical scanning circuit 22 performs read control in accordance with the setting of the partial area shown in Figure 11 to be read out, so that read control is performed simultaneously for as many pixel rows as possible, with the necessary condition that output signals of two or more pixels PX are not read out simultaneously to the same vertical signal line 27.

[0080] 13, the vertical scanning circuit 22 simultaneously controls readout of the first and fourth rows of pixels PX in the imaging region 21 during a period T1, simultaneously controls readout of the second and fifth rows of pixels PX in the imaging region 21 during the following period T2, simultaneously controls readout of the third and sixth rows of pixels PX in the imaging region 21 during the following period T3, simultaneously controls readout of the seventh row of pixels PX in the imaging region 21 during the following period T4, simultaneously controls readout of the eighth row of pixels PX in the imaging region 21 during the following period T5, and simultaneously controls readout of the ninth row of pixels PX in the imaging region 21 during the following period T6, thereby completing readout of one frame. By sequentially repeating the periods T1 to T6, multiple frames are read out by the rolling electronic shutter.

[0081] In this embodiment, the region setting circuit 23 may be configured to arbitrarily set the region to be read out in partial region shooting mode under the constraint that two or more predetermined partial regions AR are not simultaneously set as readout regions in any column of the predetermined partial regions AR, and the vertical scanning circuit 22 may be configured to always perform the readout control shown in FIG. 8 in partial region shooting mode. In the following description, this configuration will be referred to as a "restricted partial region setting configuration." In this case, region settings such as those shown in FIG. 6 and FIG. 9 are permitted, but region settings such as those shown in FIG. 11 are not permitted. Such a vertical scanning circuit 22 may be configured using, for example, vertical shift registers, switches, etc., or a decoder circuit using a memory, etc.

[0082] Alternatively, in this embodiment, the region setting circuit 23 may be configured to arbitrarily set the region to be read out without any restrictions when setting the partial region to be read out in the partial region imaging mode, and the vertical scanning circuit 22 may be configured to simultaneously read out as many pixel rows as possible in the partial region imaging mode, depending on the partial region setting, with the necessary condition that output signals from two or more pixels PX are not simultaneously read out to the same vertical signal line 27. In the following description, this configuration will be referred to as a "partial region setting configuration without restrictions." In this case, not only the region setting shown in FIG. 6 or FIG. 9 but also the region setting shown in FIG. 11 is permitted. In the region setting shown in FIG. 6 or FIG. 9, the vertical scanning circuit 22 performs, for example, the read control shown in FIG. 8, and in the region setting shown in FIG. 11, the read control, for example, shown in FIG. 13. Such a vertical scanning circuit 22 may be configured using, for example, a decoder circuit using a memory or the like to select the required row each time.

[0083] As can be seen from the above description, in this embodiment, the region setting circuit 23 constitutes a region setting unit that selects the selection transistors ASEL of the pixels PX in a plurality of desired partial regions of the imaging region 21. Also, in this embodiment, the vertical scanning circuit 22 constitutes a control unit that selects the selection transistors SEL of the pixels PX in each row of the plurality of partial regions, and performs read control on the pixels PX in the row whose selection transistors SEL are selected.

[0084] When performing the readout control shown in Fig. 8 in the case of the region setting shown in Fig. 6 or the region setting shown in Fig. 9, or when performing the readout control shown in Fig. 11 in the case of the region setting shown in Fig. 11, the vertical scanning circuit 22 simultaneously selects the selection transistors SEL of the pixels PX in one row of at least one of the plurality of partial regions (plurality of partial regions set as readout regions) and the selection transistors SEL of the pixels PX in one row different from the one row in at least one other partial region among the plurality of partial regions, and performs readout control on the pixels PX in these rows. Here, any vertical signal line 27 that receives the output signals of the pixels PX in the at least one partial region is different from any vertical signal line 27 that receives the output signals of the pixels PX in the at least one other partial region.

[0085] Furthermore, when performing the readout control shown in FIG. 8 in the case of the region setting shown in FIG. 6 or the region setting shown in FIG. 9, the vertical scanning circuit 22 simultaneously selects the select transistors SEL of the pixels PX in one row of each of the plurality of partial regions (the plurality of partial regions set as readout regions) and performs readout control on the pixels PX in this row, and then sequentially repeats this control for the pixels in the remaining rows of each of the plurality of partial regions. Here, the plurality of partial regions have the same number of rows of pixels PX. Furthermore, any row of pixels PX in at least one of the plurality of partial regions is different from any row of pixels PX in at least one other of the plurality of partial regions. Furthermore, any vertical signal line 27 receiving output signals from pixels PX in each of the plurality of partial regions is different from any vertical signal line 27 receiving output signals from pixels PX in partial regions other than the partial region.

[0086] Fig. 14 is a timing chart showing an example of readout control in the full-area shooting mode of the solid-state imaging element 4 in Fig. 1, and corresponds to Fig. 8 and Fig. 13. The full-area shooting mode is an operation mode in which output signals from pixels PX in the entire imaging area 21 of the solid-state imaging element 4 are read out.

[0087] In the full-area imaging mode, all of the selection control signals φASEL supplied to the gates of the selection transistors ASEL in all of the predetermined partial areas AR are maintained at a high level (H), thereby maintaining the selection transistors ASEL in the entire area of ​​the imaging area 21 (all of the predetermined partial areas AR) in an on state.

[0088] In this embodiment, in the full area shooting mode, readout control is performed, for example, as shown in Fig. 14. In the example shown in Fig. 14, the vertical scanning circuit 22 performs sequential readout control for each row from the first row of pixels PX to the ninth row of pixels PX in the imaging area 21 during each of periods T1 to T9, thereby completing the readout of one frame. In the full area shooting mode during still image shooting, exposure is performed by a mechanical shutter (not shown) after a so-called global reset in which all pixels PX are simultaneously reset, and then the periods T1 to T9 are performed once. In the full area shooting mode during moving image shooting, the periods T1 to T9 are repeated sequentially, and multiple frames are read out by a rolling electronic shutter.

[0089] In this embodiment, each pixel PX of the solid-state imaging device 4 has a selection transistor ASEL in addition to the selection transistor SEL. Therefore, in the partial area imaging mode, when multiple partial areas are set as readout areas, for example, as shown in FIGS. 6, 9, and 11, readout control can be performed as shown in FIGS. 8 and 13, and pixels PX in multiple different rows can be read out simultaneously. Therefore, according to this embodiment, the time required to read out one frame's worth of image signals can be shortened, and multiple desired partial areas can be read out at high speed. Specifically, to read out one frame's worth of image signals, periods T1 to T9 are required in the full area imaging mode as shown in FIG. 14, whereas in the partial area imaging mode, only periods T1 to T3 are required in the case shown in FIG. 8 and only periods T1 to T6 are required in the case shown in FIG. 13.

[0090] In the imaging device disclosed in Patent Document 1, pixels PX of multiple different rows cannot be read out simultaneously, so when multiple partial areas are set as readout areas in partial area shooting mode, it takes a longer time to read out image signals for one frame than in the present embodiment. For example, in the imaging device disclosed in Patent Document 1, when multiple partial areas are set as readout areas in partial area shooting mode, for example, as shown in Figures 6 and 11, it ends up having to perform readout control similar to the readout control shown in Figure 14 in full area shooting mode, and it takes a longer time to read out image signals for one frame.

[0091] When the user commands the first partial area shooting mode via the operation unit 14, the electronic camera 1 according to this embodiment performs the operation shown in Fig. 15. Fig. 15 is a schematic flowchart showing an example of the operation of the electronic camera 1 shown in Fig. 1 in the first partial area shooting mode.

[0092] When the first partial area shooting mode is commanded by the operation unit 14, the CPU 9 first performs automatic exposure control (AE) and automatic focus control (AF) (step S1). The AE in step S1 is performed, for example, by the CPU 9 calculating an optimal exposure amount based on a photometric signal from an automatic exposure photometric sensor (not shown) provided separately from the solid-state image sensor 4, and controlling the lens control unit 3 so that the aperture of the photographing lens 2 is set to an aperture corresponding to this exposure amount. The AF in step S1 is performed, for example, by the CPU 9 calculating a defocus amount based on a signal from a focus detection sensor (not shown) provided separately from the solid-state image sensor 4, and then by the lens control unit 3 driving the focus of the photographing lens 2 in accordance with this defocus amount to bring the photographing lens 2 into focus. The output signals of the pixels PX of the solid-state image sensor 4 may be read and used as the automatic exposure photometric signal. Alternatively, the solid-state image sensor 4 may be configured to also obtain a focus detection signal, and the AF may be performed using this signal.

[0093] Instead of performing AE and AF in step S1 or step S6 described later, the aperture, focusing, etc. may be set manually in advance by the user.

[0094] Next, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to set all selection control signals φASEL supplied from the area setting circuit 23 to the gates of the selection transistors ASEL of all the predetermined partial areas AR to a high level, thereby setting the entire area of ​​the imaging area 21 as the readout area (step S2).

[0095] In this state, the CPU 9 controls the vertical scanning circuit 22 and the like via the imaging control unit 5 to realize read control in the full-area shooting mode shown in Fig. 14, obtains image data of the full area for one frame, and temporarily stores the data in the memory 7 (step S3). Note that, here, prior to the period T1 in Fig. 14, all pixels PX are simultaneously reset, that is, global reset, and then exposed by a mechanical shutter (not shown).

[0096] Next, the CPU 9 displays the image obtained in step S3 on the display unit 10 (step S4) and prompts the user to specify the desired partial area to be captured. Note that the CPU 9 accepts only permissible area specifications when the constrained partial area setting configuration is employed, and accepts area specifications without constraints when the unconstrained partial area setting configuration is employed. The user inputs a desired partial area using the operation unit 14 while viewing the displayed image, and the CPU 9 accepts the specification. The CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to selectively set the selection control signal φASEL supplied to the gate of the selection transistor ASEL of the predetermined partial area AR corresponding to the specified partial area or areas to a high level, thereby selectively setting the predetermined partial area or areas AR as readout areas (step S5). In this embodiment, the functions of the CPU 9, the display unit 10, and the operation unit 14 constitute a user interface for specifying one or more desired partial areas of the imaging area 21.

[0097] Subsequently, the CPU 9 performs AE and AF in the same manner as in step S1 (step S6). However, unlike step S1, step S6 is performed so that exposure and focusing are optimized for the partial area set in step S5.

[0098] Next, the CPU 9 controls the vertical scanning circuit 22 and the like via the imaging control unit 5 to realize read control in the partial area shooting mode described above, obtains image data of one frame of the partial area and temporarily stores it in the memory 7, and causes the recording unit 11 to record this image as a moving image of the partial area on the recording medium 11a (step S7). Note that step S7 is repeated by the operation shown in Fig. 15, thereby realizing a rolling electronic shutter.

[0099] Thereafter, the CPU 9 determines whether or not a command to end partial area video shooting has been received from the operation unit 14 (step S8), and if no such command has been received, the process returns to step S7, whereas if such a command has been received, the series of operations in the first partial area shooting mode is ended.

[0100] In this first partial area shooting mode, moving images of one or more desired partial areas arbitrarily set by the user can be acquired. According to this embodiment, as described above, the time required to read out one frame's worth of image signals of the desired partial areas can be shortened, and the desired partial areas can be read out at high speed, so that moving images of the desired partial areas arbitrarily set by the user can be acquired at a high frame rate.

[0101] Therefore, in this first partial area photographing mode, by the user specifying a plurality of desired partial areas each including a plurality of arbitrary targets of interest, it is possible to obtain a moving image that captures in detail the process of changes in the plurality of targets of interest in the field of view (for example, changes in shape, size, orientation, color, etc.), and the moving image allows the user to observe changes in the plurality of targets of interest in the field of view without missing any of them. For example, if the electronic camera 1 according to this embodiment is an imaging device incorporated in a microscope and captures microscopic images, when the field of view is a petri dish in which cells are cultured, it is possible to obtain a moving image that captures in detail the process of changes in multiple cells (for example, the state of cell division, the state of pulsation of cardiomyocytes, etc.).

[0102] When the user commands the second partial area shooting mode via the operation unit 14, the electronic camera 1 according to this embodiment performs the operation shown in Fig. 16. Fig. 16 is a schematic flowchart showing an example of the operation of the electronic camera 1 shown in Fig. 1 in the second partial area shooting mode. In the first partial area shooting mode, the partial area is fixed to an area specified by the user, whereas in the second partial area shooting mode, the partial area to be shot automatically follows the movement of the target object.

[0103] When the second partial area photographing mode is instructed by the operation unit 14, the CPU 9 performs steps S11 to S13 which are the same as steps S1 to S3 in FIG. 15, respectively.

[0104] Next, the CPU 9 performs image recognition processing on the image stored in the memory 7 in step S13 using a known image recognition method, recognizes the desired object of interest (e.g., a human body, a human face, a moving object, a cell, etc.), and detects the position, size, etc. on the image (step S14).

[0105] Next, CPU 9 determines whether or not the target of interest has been recognized in step S14 (step S15), and proceeds to step S16 if the target of interest has been recognized, or proceeds to step S27 if the target of interest has not been recognized. In step S27, CPU 9 determines whether or not a command to end partial area moving image shooting has been received from operation unit 14, and if no such command has been received, returns to step S11, or if such command has been received, ends the series of operations in the second partial area shooting mode.

[0106] In step S16, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to selectively set one or more predetermined partial areas AR as readout areas according to the recognition result of step S14. Specifically, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to selectively set to high level the selection control signal φASEL supplied to the gate of the selection transistor ASEL of the predetermined partial area AR corresponding to one or more partial areas including each target object recognized in step S14 and some of its surroundings.

[0107] Subsequently, the CPU 9 performs AE and AF in the same manner as in step S11 (step S17). However, unlike step S11, step S17 is performed so that exposure and focusing are optimized for the partial area set in step S16.

[0108] Thereafter, the CPU 9 resets the count value q to zero (step S18). This count value q indicates the number of frames that have been shot after the partial region has been set to the latest.

[0109] Next, the CPU 9 controls the vertical scanning circuit 22 and the like via the imaging control unit 5 to realize read control in the partial area shooting mode described above, obtains image data of one frame of the partial area and temporarily stores it in the memory 7, and causes the recording unit 11 to record this image on the recording medium 11a as a moving image of the currently set partial area (step S19). Note that step S19 is repeated by the operation shown in Fig. 16, thereby realizing a rolling electronic shutter.

[0110] Next, the CPU 9 increments the count value q by 1 (step S20), and then determines whether or not a command to end partial area video shooting has been received from the operation unit 14 (step S21). If no such command has been received, the CPU 9 proceeds to step S22; if the command has been received, the CPU 9 ends the series of operations in the second partial area shooting mode.

[0111] In step S22, the CPU 9 determines whether the current count value q is equal to or greater than the value Q. If q≧Q, the process returns to step S19. If q≧Q, the process proceeds to step S23. The value Q is a value equal to or greater than 1 that is arbitrarily set by the user via the operation unit 14 before the second partial area shooting mode is started. The value Q determines the timing for resetting the partial area. As will be understood from the following explanation, the partial area is reset when the number of frames captured in the partial area once set reaches the value Q. If the moving speed of the target of interest is high, the value Q is set to a relatively small value to improve tracking of the target of interest. If the moving speed of the target of interest is low, the value Q is set to a relatively large value to reduce the time required for steps S23, S26, etc., and thereby increase the overall frame rate.

[0112] In step S23, image recognition processing is performed using a known image recognition method on the image of each partial region of the frame most recently stored in memory 7 in step S19, recognizing the desired target and detecting its position, size, etc. on the image.

[0113] Subsequently, the CPU 9 determines whether or not the target object has been recognized in step S23 (step S24), and if the target object has been recognized, the process proceeds to step S25, whereas if the target object has not been recognized, the process proceeds to step S27.

[0114] In step S25, the CPU 9 controls the region setting circuit 23 via the imaging control unit 5 to selectively set one or more predetermined partial regions AR as readout regions according to the recognition result in step S23.

[0115] Thereafter, the CPU 9 performs AE and AF in the same manner as in step S17 (step S26), and then returns to step S 18. However, in step S26, unlike step S17, exposure and focusing are performed to optimize the partial area most recently set in step S25.

[0116] In this second partial area shooting mode, moving images of a plurality of partial areas set by automatically following the movement of the target object can be acquired. According to this embodiment, as described above, the time required to read out one frame of image signals of a plurality of desired partial areas can be shortened, and the desired plurality of partial areas can be read out at high speed, so that moving images of the partial areas set by automatically following the movement of the target object can be acquired at a high frame rate, and the time required for AF, etc. can be secured even if the movement speed of the target object is high, so that a moving image in a focused state can be acquired, and tracking ability is improved.

[0117] Therefore, this second partial area capturing mode is effective, for example, when used as a surveillance camera with a target object being a person's whole body or face. Capturing detailed images of the process of changes in the whole body or face of multiple people allows detailed knowledge of the process of changes in posture, facial expression, and lip movement of multiple people, and allows for the acquisition of advanced information from the monitored object. For example, it is possible to get a detailed view of a fight between multiple people, or to use lip reading to understand the content of a conversation between multiple people.

[0118] The second partial area capture mode is also effective, for example, when the electronic camera 1 according to this embodiment is incorporated into a microscope and used as an imaging device for capturing microscopic images. When observing a cell, microorganism, or the like as an object of interest, even if the object of interest moves at an extremely slow speed, the first partial area capture mode may cause the object of interest to move away from the partial area set by the user after a long period of time. In contrast, the second partial area capture mode can automatically track the movement of the object of interest to acquire moving images of multiple partial areas, allowing even such an object of interest to be captured at a high frame rate over a long period of time.

[0119] In the electronic camera 1 according to this embodiment, when the user commands the still image shooting mode via the operation unit 14, the same still image shooting operation as that of a normal electronic camera is performed, and when the user commands the full-area shooting mode for video shooting via the operation unit 14, the corresponding operation is performed, but a description of this will be omitted here.

[0120] [Second embodiment]

[0121] Fig. 17 is a circuit diagram showing a schematic configuration of a solid-state imaging element 41 used in an electronic camera according to a second embodiment of the present invention, and corresponds to Fig. 2. Fig. 18 is a circuit diagram showing a predetermined partial area AR that forms part of the imaging area 21 of the solid-state imaging element 41 shown in Fig. 17, and corresponds to Fig. 4. Fig. 19 is a circuit diagram showing an abstraction of the circuit shown in Fig. 18, and corresponds to Fig. 5. Fig. 20 is a diagram showing a power supply voltage signal φVDD that realizes the same setting as the setting example shown in Fig. 6 in the solid-state imaging element 41 shown in Fig. 17, and corresponds to Fig. 7.

[0122] 17 to 19, elements that are the same as or correspond to elements in Figures 2, 4, and 5 are denoted by the same reference numerals, and redundant explanations will be omitted. The present embodiment differs from the first embodiment in the points described below.

[0123] In this embodiment, a solid-state image sensor 41 is used in place of the solid-state image sensor 4 in the electronic camera 1 according to the first embodiment.

[0124] In the first embodiment, a selection transistor ASEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor ASEL and the control line 33 are removed from each pixel PX of the imaging region 21, and the source of the selection transistor SEL is connected to the vertical signal line 27 corresponding to the pixel PX.

[0125] In the first embodiment, the drains (point b in FIG. 4) of the amplifier transistors AMP of all pixels PX are commonly connected by a power supply line 34, and an effective voltage level VDD that is effective for the operation of the amplifier transistor AMP is fixedly supplied thereto as a power supply voltage for the amplifier transistor AMP. In contrast, in the present embodiment, the power supply line 34 is electrically separated for each predetermined partial area AR, and the drains (point b in FIG. 18) of the amplifier transistor AMP of each pixel PX are commonly connected by the power supply line 34 for each predetermined partial area AR, and a power supply voltage signal φVDD is supplied thereto from the area setting circuit 23 as a power supply voltage for the amplifier transistor AMP. Note that the drain of the reset transistor RST of each pixel PX is connected to the drain (point b in FIG. 18) of the amplifier transistor AMP of that pixel PX by the power supply line 34.

[0126] 19 is an abstract illustration of the circuit shown in FIG. 18, focusing on the connection relationship of the drain (point b) of the amplification transistor AMP of each predetermined partial area AR via the power supply line 34. When each power supply voltage signal φVDD is distinguished for each predetermined partial area AR, the power supply voltage signal φVDD supplied to the drain of the amplification transistor AMP of the pixel PX in the jth row and kth column of the predetermined partial area AR(j,k) is denoted by the symbol φVDD(j,k). Note that the actual arrangement (routing path, etc.) of the power supply line 34 is not limited in any way.

[0127] In this embodiment, the region setting circuit 23 is configured as a power supply control circuit that outputs each power supply voltage signal φVDD instead of each control signal φASEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is either an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or an ineffective voltage level (here, 0 V, but not necessarily limited to 0 V) ​​that is ineffective for the operation of the amplification transistor AMP, and the region setting circuit 23 selectively supplies VDD or 0 V as the power supply voltage of the amplification transistor AMP of each pixel PX.

[0128] In this embodiment, the state in which the power supply voltage signal φVDD in each pixel PX becomes VDD and the amplification transistor AMP operates effectively, and the state in which the power supply voltage signal φVDD becomes 0V and the amplification transistor AMP does not operate effectively are substantially the same as the state in which the control signal φASEL in each pixel PX becomes high level and the selection transistor ASEL is turned on, and the state in which the control signal φASEL becomes low level and the selection transistor ASEL is turned off, in the first embodiment, in terms of whether or not the output signal of each pixel PX is output to the vertical signal line 27.

[0129] Therefore, in this embodiment, the output signal of each pixel PX is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction relative to the pixel PX only when the selection transistor SEL of the pixel PX is in a selected state (on state) and the power supply voltage signal φVDD supplied as the power supply voltage of the amplification transistor AMP of the pixel PX is at the effective voltage level VDD.

[0130] In this embodiment, the region setting circuit 23 supplies an effective voltage level VDD as each power supply voltage signal φVDD instead of supplying a high-level signal as each φASEL in the first embodiment, and supplies 0 V as each power supply voltage signal φVDD instead of supplying a low-level signal as each φASEL in the first embodiment, thereby realizing an operation similar to that of the first embodiment. For example, in this embodiment, to realize the same setting as the region setting example shown in Figure 6, the region setting circuit 23 can output each power supply voltage signal φVDD as shown in Figure 20.

[0131] This embodiment also provides the same advantages as those of the first embodiment. Furthermore, in this embodiment, the selection transistor ASEL is not provided in each pixel PX, and therefore the configuration of each pixel PX is simplified.

[0132] [Third embodiment]

[0133] Fig. 21 is a circuit diagram showing a schematic configuration of a solid-state imaging element 51 used in an electronic camera according to a third embodiment of the present invention, and corresponds to Fig. 2. Fig. 22 is a circuit diagram showing a predetermined partial area AR forming part of the imaging area 21 of the solid-state imaging element 51 shown in Fig. 21, and corresponds to Fig. 4. Fig. 23 is a timing chart showing an example of readout control in partial area shooting mode of the solid-state imaging element 51 shown in Fig. 21, and corresponds to Fig. 8.

[0134] 21 to 23, elements that are the same as or correspond to elements in Figures 2, 4, and 8 are denoted by the same reference numerals, and redundant explanations will be omitted. The present embodiment differs from the first embodiment in the points described below.

[0135] In this embodiment, a solid-state image sensor 51 is used in place of the solid-state image sensor 4 in the electronic camera 1 according to the first embodiment.

[0136] In the first embodiment, a selection transistor SEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor SEL and the connection line 26 are removed from each pixel PX of the imaging region 21, and the drain of the selection transistor ASEL is connected to the source of the amplification transistor AMP of the pixel PX.

[0137] In the first embodiment, the drains of the amplifier transistors AMP of all pixels PX (point b in FIG. 4) are commonly connected by a power supply line 34, and a fixed effective voltage level VDD that is effective for the operation of the amplifier transistors AMP is supplied to the power supply line 34 as a power supply voltage for the amplifier transistors AMP. In contrast, in the present embodiment, the power supply lines 34 are electrically separated for each row of pixels PX, and the drains of the amplifier transistors AMP of each pixel PX (point b in FIG. 22) are commonly connected by the power supply line 34 for each row of pixels PX, and a power supply voltage signal φVDD is supplied to the drains as a power supply voltage for the amplifier transistors AMP from the power supply control circuit 52. When each power supply voltage signal φVDD is distinguished for each row of pixels PX, the power supply voltage signal φVDD supplied to the drain of the amplifier transistor AMP of the pixel PX in the nth row is denoted by the symbol φVDD(n). The drain of the reset transistor RST of each pixel PX is connected to the drain of the amplifier transistor AMP of that pixel PX (point b in FIG. 22) by the power supply line 34.

[0138] In this embodiment, the power supply control circuit 52 is provided as part of the vertical scanning circuit 22, and outputs each power supply voltage signal φVDD in place of each control signal φSEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is either an effective voltage level VDD that is effective for the operation of the amplifier transistor AMP, or an ineffective voltage level (here, 0 V, but not necessarily limited to 0 V) ​​that is ineffective for the operation of the amplifier transistor AMP, and the power supply control circuit 52 selectively supplies VDD or 0 V as the power supply voltage for the amplifier transistor AMP of each pixel PX.

[0139] In this embodiment, the state in which the power supply voltage signal φVDD in each pixel PX becomes VDD and the amplification transistor AMP operates effectively, and the state in which the power supply voltage signal φVDD becomes 0V and the amplification transistor AMP does not operate effectively are substantially the same as the state in which the control signal φSEL in each pixel PX becomes high level and the selection transistor SEL is turned on, and the state in which the control signal φSEL becomes low level and the selection transistor SEL is turned off, in the first embodiment, in terms of whether or not the output signal of each pixel PX is output to the vertical signal line 27.

[0140] Therefore, in this embodiment, the output signal of each pixel PX is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction relative to the pixel PX only when the selection transistor ASEL of the pixel PX is in a selected state (on state) and the power supply voltage signal φVDD supplied as the power supply voltage of the amplification transistor AMP of the pixel PX is at the effective voltage level VDD.

[0141] In this embodiment, the power supply control circuit 52 supplies an effective voltage level VDD as each power supply voltage signal φVDD instead of supplying a high-level signal as each φSEL in the first embodiment, and supplies 0 V as each power supply voltage signal φVDD instead of supplying a low-level signal as each φSEL in the first embodiment, thereby realizing an operation similar to that of the first embodiment. For example, in this embodiment, in the partial area shooting mode, when the partial area to be read out is set as shown in Fig. 6, the vertical scanning circuit 22 may perform readout control as shown in Fig. 23.

[0142] This embodiment also provides the same advantages as those of the first embodiment. Furthermore, in this embodiment, the selection transistor SEL is not provided in each pixel PX, and therefore the configuration of each pixel PX is simplified.

[0143] [Fourth embodiment]

[0144] FIG. 24 is a circuit diagram showing a schematic configuration of a solid-state imaging element 61 used in an electronic camera according to a fourth embodiment of the present invention, and corresponds to FIG. 2. FIG. 25 is a circuit diagram showing a predetermined partial area AR that forms part of the imaging area 21 of the solid-state imaging element 61 shown in FIG. 24, and corresponds to FIG. 4. FIG. 26 is a circuit diagram showing an abstraction of the circuit shown in FIG. 25, and corresponds to FIG. 5. FIG. 27 is a timing chart showing an example of readout control in partial area shooting mode of the solid-state imaging element 61 shown in FIG. 24, and corresponds to FIG. 8. In FIGS. 24 to 27, elements that are the same as or correspond to elements in FIGS. 2, 4, 5, and 8 are designated by the same reference numerals, and redundant explanations will be omitted.

[0145] In this embodiment, a solid-state image sensor 61 is used in place of the solid-state image sensor 4 in the electronic camera 1 according to the first embodiment.

[0146] This embodiment differs from the first embodiment in that for every two adjacent pixels PX in the column direction, the two pixels PX share a set of floating capacitance section FD, amplification transistor AMP, reset transistor RST, and selection transistors SEL, ASEL, and in that the vertical scanning circuit 22 is configured to output control signals φSEL, φRST, φTXA, φTXB as shown in FIG. 27 instead of the control signals φSEL, φRST, φTX as shown in FIG. 8.

[0147] 24 to 26, two pixels PX that share one set of floating capacitance unit FD, amplifier transistor AMP, reset transistor RST, and selection transistors SEL and ASEL are shown as a pixel block BL. Also, in Figures 24 and 25, the photodiode PD and transfer transistor TX of the lower pixel PX in the pixel block BL are indicated by symbols PDA and TXA, respectively, and the photodiode PD and transfer transistor TX of the upper pixel PX in the pixel block BL are indicated by symbols PDB and TXB, respectively, to distinguish between the two. Furthermore, the control signal supplied to the gate of transfer transistor TXA is indicated as φTXA, and the control signal supplied to the gate electrode of transfer transistor TXB is indicated as φTXB, to distinguish between the two.

[0148] In FIGS. 2 and 4, N, n, etc. indicate pixel rows, but in FIGS. 24 and 25, N, n, etc. indicate rows of pixel blocks BL. One row of pixel blocks BL corresponds to two rows of pixels PX. In FIGS. 4 and 5, each predefined partial area AR is made up of A×B pixels PX in A rows and B columns, but in FIGS. 25 and 26, each predefined partial area AR is made up of A×B pixel blocks BL in A rows and B columns (2×A×B pixels PX). Note that the number of rows of photodiodes PD constituting each predefined partial area AR may be two or more, and the number of columns of photodiodes PD may be one or more. In the present embodiment, one pixel block BL has two photodiodes PD, so the number of rows of pixel blocks BL constituting each predefined partial area AR may be one or more, and the number of columns of pixel blocks BL may be one or more.

[0149] In this embodiment, in the partial area shooting mode, when the partial area to be read out is set as shown in Fig. 6 or 9, for example, the read control shown in Fig. 27 is performed instead of the read control shown in Fig. 8. Note that here, n in Fig. 6 and Fig. 9 indicates the row of the pixel block BL, and m in Fig. 6 and Fig. 9 indicates the column of the pixel block BL.

[0150] 27, during a period T1, the vertical scanning circuit 22 simultaneously controls readout of the first, fourth, and seventh pixel blocks BL in the imaging region 21, which correspond to the first pixel block BL in each predetermined partial region AR. During the following period T2, the vertical scanning circuit 22 simultaneously controls readout of the second, fifth, and eighth pixel blocks BL in the imaging region 21, which correspond to the second pixel block BL in each predetermined partial region AR. During the following period T3, the vertical scanning circuit 22 simultaneously controls readout of the third, sixth, and ninth pixel blocks BL in the imaging region 21, which correspond to the third pixel block BL in each predetermined partial region AR, thereby completing readout of one frame. By sequentially repeating the periods T1 to T3, multiple frames are read out by the rolling electronic shutter.

[0151] In this embodiment, in the partial area shooting mode, if it is permitted that the partial area to be read out is set as shown in Fig. 11, the vertical scanning circuit 22 may perform, instead of the read control shown in Fig. 27, for example, read control that is a modification of the read control shown in Fig. 13, in the same way as the read control shown in Fig. 8 is modified to the read control shown in Fig. 27. Note that here, n in Fig. 11 indicates a row of the pixel block BL, and m in Fig. 11 indicates a column of the pixel block BL.

[0152] In this example, the vertical scanning circuit 22 performs read control in accordance with the setting of the partial area to be read out shown in Figure 11, so that read control is performed simultaneously for as many rows of pixel blocks BL as possible, with the necessary condition that the output signals of two or more pixels PX are not read out simultaneously to the same vertical signal line 27.

[0153] In this embodiment, the region setting circuit 23 may be configured to arbitrarily set the region to be read out in partial region shooting mode under the constraint that two or more predefined partial regions AR are not simultaneously set as read out regions in any column of the predefined partial regions AR, and the vertical scanning circuit 22 may be configured to always perform the read control shown in FIG. 27 in partial region shooting mode. In the following description, this configuration will be referred to as a "restricted partial region setting configuration." In this case, the region settings shown in FIG. 6 and FIG. 9 are permitted, but the region setting shown in FIG. 11 is not permitted.

[0154] Alternatively, in this embodiment, the region setting circuit 23 may be configured to arbitrarily set the region to be read out without any restrictions when setting the partial region to be read out in the partial region imaging mode, and the vertical scanning circuit 22 may be configured to simultaneously read out as many rows of pixel blocks BL as possible, depending on the partial region setting, with the necessary condition that output signals of two or more pixels PX are not simultaneously read out to the same vertical signal line 27. In the following description, this configuration will be referred to as a "partial region setting configuration without restrictions." In this case, not only the region setting shown in FIG. 6 or FIG. 9 but also the region setting shown in FIG. 11 is permitted. In the region setting shown in FIG. 6 or FIG. 9, the vertical scanning circuit 22 performs, for example, the read control shown in FIG. 27. In the region setting shown in FIG. 11, the vertical scanning circuit 22 performs, for example, the read control shown in FIG. 13, similar to the read control shown in FIG. 8 modified to the read control shown in FIG. 27.

[0155] In the present embodiment, in the full-area imaging mode, for example, readout control is performed by modifying the readout control shown in FIG. 14 in the same way as modifying the readout control shown in FIG. 8 into the readout control shown in FIG. 27. In this example, the vertical scanning circuit 22 sequentially reads out pixel blocks BL row by row in the imaging area 21, from the first row to the ninth row, thereby completing the readout of one frame. In the full-area imaging mode for still image capture, exposure is performed by a mechanical shutter (not shown) after a so-called global reset in which all pixels PX are simultaneously reset, and then the pixel blocks BL of each row from the first row to the ninth row are read out. In the full-area imaging mode for moving image capture, the readout of pixel blocks BL of each row from the first row to the ninth row is sequentially repeated, and multiple frames are read out by a rolling electronic shutter.

[0156] This embodiment also provides advantages similar to those of the first embodiment. While in this embodiment, every two adjacent pixels PX in the column direction share a set of a floating capacitance unit FD, an amplifier transistor AMP, a reset transistor RST, and selection transistors SEL and ASEL, in the present invention, for example, every predetermined number of three or more adjacent pixels PX in the column direction may share a set of a floating capacitance unit FD, an amplifier transistor AMP, a reset transistor RST, and selection transistors SEL and ASEL. Furthermore, in the present invention, modifications similar to those made by modifying the first embodiment to this embodiment may be applied to the second and third embodiments.

[0157] [Fifth embodiment]

[0158] Fig. 28 is a circuit diagram showing a schematic configuration of a solid-state imaging element 71 used in an electronic camera according to a fifth embodiment of the present invention, and corresponds to Fig. 2. Fig. 29 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging element 71 shown in Fig. 28, and corresponds to Fig. 4.

[0159] 28 and 29, elements that are the same as or correspond to elements in Figures 2 and 4 are denoted by the same reference numerals, and redundant explanations will be omitted. The present embodiment differs from the first embodiment in the points described below.

[0160] In this embodiment, a solid-state image sensor 71 is used in place of the solid-state image sensor 4 in the electronic camera 1 according to the first embodiment.

[0161] In this embodiment, the imaging area 21 is not divided into each of the predetermined partial areas AR. Also, in this embodiment, a row write control circuit 72 and a column write control circuit 73 are provided instead of the area setting circuit 23.

[0162] Furthermore, in this embodiment, a capacitor HC and a write transistor WT are added to each pixel PX. The capacitor HC of each pixel PX is connected between ground and the gate of the select transistor ASEL of the pixel PX, and constitutes a holding unit that holds a selection control signal for selecting or deselecting the select transistor ASEL of the pixel PX. The write transistor WT of each pixel PX constitutes a writing unit that writes the selection control signal into the capacitor HC, which serves as the holding unit of the pixel PX, in response to write control signals φWTR and φWTC.

[0163] In this embodiment, the write transistor WT is an nMOS transistor. The source of the write transistor WT of each pixel PX is connected to the gate of the select transistor ASEL of that pixel PX. The gates of the write transistor WT of each pixel PX are commonly connected for each row of pixels PX by a control line 74, to which a first write control signal φWTR is supplied from a row write control circuit 72. The drains of the write transistor WT of each pixel PX are commonly connected for each column of pixels PX, to which a second write control signal φWTC is supplied from a column write control circuit 73. The write transistor WT of each pixel PX forms an AND circuit that ANDs the first write control signal φWTR supplied to its gate and the second write control signal φWTC supplied to its drain, and outputs the AND output to its source. Instead of the write transistor WT, for example, another AND circuit may be used as the write unit.

[0164] When the first write control signals φWTR are distinguished by row of the pixels PX, the first write control signal φWTR supplied to the gate of the write transistor WT of the pixel PX in the nth row is denoted by the symbol φWTR(n).When the second write control signals φWTC are distinguished by column of the pixels PX, the second write control signal φWTC supplied to the drain of the write transistor WT of the pixel PX in the mth column is denoted by the symbol φWTC(m).

[0165] 30(a) is a diagram showing the write control signals φWTR(n) and φWTC(m) when a high-level signal (H signal) is written to the capacitor HC of the pixel PX in the nth row and mth column in the solid-state imaging device 71 shown in FIG. At time t21, the write control signal φWTR(n) for the nth row rises to a high level, and at time t22, the write control signal φWTC(m) for the mth column rises to a high level. At time t23, the write control signal φWTR(n) falls to a low level, and at time t24, the write control signal φWTC falls. As a result, a high-level signal is written to and retained in the capacitor HC of the pixel PX in the nth row and mth column. As a result, the select transistor ASEL of the pixel PX in the nth row and mth column is retained in an on state (selected state).

[0166] 30(b) is a diagram showing the write control signals φWTR(n) and φWTC(m) when a low-level signal (L signal) is written to the capacitor HC of the pixel PX in the nth row and mth column in the solid-state imaging device 71 shown in FIG. While the write control signal φWTC(m) for the mth column is maintained at a low level, the write control signal φWTR(n) for the nth row is raised to a high level at time t21, and then the write control signal φWTR(n) is lowered to a low level at time t23. As a result, a low-level signal is written to and maintained in the capacitor HC of the pixel PX in the nth row and mth column. As a result, the select transistor ASEL of the pixel PX in the nth row and mth column is maintained in an off state (unselected state).

[0167] The row write control circuit 72 supplies a first write control signal φWTR to each row of the pixels PX under the control of the imaging control unit 5 in Fig. 1. The column write control circuit 73 supplies a second write control signal φWTC to each column of the pixels PX under the control of the imaging control unit 5 in Fig. 1. The row write control circuit 72 and the column write control circuit 73 collectively constitute a write control unit that supplies the write control signals φWTR and φWTC to the write transistors WT serving as the write units of the pixels PX.

[0168] In this embodiment, the row write control circuit 72, the column write control circuit 73, and the write transistor WT and capacitor HC of each pixel PX collectively constitute an area setting unit that selects (turns on) the select transistor ASEL of the pixel PX of one or more desired partial areas to be read out of the imaging area 21.

[0169] Fig. 31 is a timing chart showing write control signals φWTR and φWTC that realize the same setting as the area setting example shown in Fig. 6 in the solid-state imaging device 71 shown in Fig. 28. Here, although the area is not divided into each of the predetermined partial areas AR in Fig. 6, the four hatched partial areas are the four partial areas to be read out.

[0170] In the example shown in Figure 31, first, a low-level signal is written to the capacitors HC of all pixels PX, and then pixels PX are selected row by row and a high-level signal is written to the capacitors HC of the necessary pixels PX in that row, thereby setting the four partial areas hatched in Figure 6 as the areas to be read out.

[0171] Specifically, when the region setting period (the period for setting the read region) starts, first, during period t31-t32, φWTR(1) to φWTR(9) are set to high level, while φWTC(1) to φWTC(12) are set to low level, which causes low-level signals to be written to the capacitors HC of all pixels PX, as can be seen from FIG.

[0172] Next, φWTR(1) is set to high level during the period t33-t35, and φWTC(4)-φWTC(6) and φWTC(10)-φWTC(12) are set to high level during the period t34-t36, which causes a high level signal to be written to the capacitors HC of the pixels PX in the fourth to sixth columns and the tenth to twelfth columns of the pixels PX in the first row, as can be seen from FIG.

[0173] Next, φWTR(2) is set to high level during the period t36-t38, and φWTC(4)-φWTC(6) and φWTC(10)-φWTC(12) are set to high level during the period t37-t39, thereby writing a high level signal to the capacitors HC of the pixels PX in the fourth to sixth columns and the tenth to twelfth columns of the pixels PX in the second row.

[0174] Subsequently, φWTR(3) is set to high level during the period t39-t41, and φWTC(4)-φWTC(6) and φWTC(10)-φWTC(12) are set to high level during the period t40-t42, thereby writing a high level signal to the capacitors HC of the pixels PX in the fourth to sixth columns and the tenth to twelfth columns of the pixels PX in the third row.

[0175] Thereafter, φWTR(4) is set to high level during the period t42-t44, and φWTC(7) to φWTC(9) are set to high level during the period t43-t45, causing high-level signals to be written to the capacitors HC of the pixels PX in the seventh to ninth columns among the pixels PX in the fourth row.

[0176] Next, φWTR(5) is set to high level during the period t45-t47, and φWTC(7) to φWTC(9) are set to high level during the period t46-t48, thereby writing a high level signal to the capacitors HC of the pixels PX in the 7th to 9th columns among the pixels PX in the 5th row.

[0177] Next, φWTR(6) is set to high level during the period t48-t50, and φWTC(7) to φWTC(9) are set to high level during the period t49-t51, causing high-level signals to be written to the capacitors HC of the pixels PX in the 7th to 9th columns among the pixels PX in the 6th row.

[0178] Subsequently, φWTR(7) is set to high level during the period t51-t53, and φWTC(1) to φWTC(3) are set to high level during the period t52-t54, thereby writing high level signals to the capacitors HC of the pixels PX in the first to third columns among the pixels PX in the seventh row.

[0179] Thereafter, φWTR(8) is set to high level during the period t54-t56, and φWTC(1) to φWTC(3) are set to high level during the period t55-t57, causing high level signals to be written to the capacitors HC of the pixels PX in the first to third columns among the pixels PX in the eighth row.

[0180] Finally, φWTR(9) is set to high level during the period t57-t59, and φWTC(1) to φWTC(3) are set to high level during the period t58-t60, causing high-level signals to be written to the capacitors HC of the pixels PX in the ninth row and the first to third columns.

[0181] In this way, a high-level signal is written to the capacitor HC of the hatched pixel PX in Figure 6, causing the selection transistor ASEL of that pixel PX to be maintained in the on state, and a low-level signal is written to the capacitor HC of the non-hatched pixel PX in Figure 6, causing the selection transistor ASEL of that pixel PX to be maintained in the off state, thereby realizing the area setting shown in Figure 6.

[0182] In this embodiment, for example, as in Figure 31, first, a low-level signal is written to the capacitors HC of all pixels PX, and then pixels PX are selected row by row and a high-level signal is written to the capacitors HC of desired pixels PX in that row, thereby making it possible to set any desired one or more partial areas of the imaging area 21, or the entire area of ​​the imaging area 21, as the area to be read out.

[0183] If, after a region setting period has been performed, the next region setting period is not performed for a long time without changing the region setting, the high-level signal written to the capacitor HC may drop and not be properly maintained. Therefore, even if the region setting is not changed, it is preferable to perform a region setting period within a certain period of time after the first region setting period to refresh the signal written to the capacitor HC.

[0184] The read control in this embodiment is the same as that in the first embodiment. Also, in this embodiment, a configuration similar to the configuration of the constrained partial region setting in the first embodiment may be adopted, or a configuration similar to the configuration of the unconstrained partial region setting in the first embodiment may be adopted.

[0185] This embodiment also provides advantages similar to those of the first embodiment. In the first embodiment, the readout area of ​​the imaging region 21 is set depending on whether or not each predetermined partial region AR is included in the readout area, whereas in this embodiment, the readout area of ​​the imaging region 21 is set depending on whether or not each pixel PX is included in the readout area. Therefore, although this embodiment requires a write transistor WT and a capacitor HC in each pixel PX, it provides greater flexibility in setting the readout area of ​​the imaging region 21 than the first embodiment.

[0186] [Sixth embodiment]

[0187] Fig. 32 is a circuit diagram showing a schematic configuration of a solid-state imaging element 81 used in an electronic camera according to a sixth embodiment of the present invention, and corresponds to Fig. 28. Fig. 33 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging element 81 shown in Fig. 32, and corresponds to Fig. 29.

[0188] 32 and 33, elements that are the same as or correspond to elements in Figures 28 and 29 are given the same reference numerals, and redundant explanations will be omitted. This embodiment differs from the fifth embodiment in the points described below.

[0189] In this embodiment, a solid-state image sensor 81 is used in place of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

[0190] In the fifth embodiment, a selection transistor SEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor SEL and the connection line 26 are removed from each pixel PX of the imaging region 21, and the drain of the selection transistor ASEL is connected to the source of the amplification transistor AMP of the pixel PX.

[0191] In the fifth embodiment, the drains of the amplifier transistors AMP of all pixels PX (point b in FIG. 29) are commonly connected by a power supply line 34, and a fixed effective voltage level VDD that is effective for the operation of the amplifier transistors AMP is supplied to the drain as a power supply voltage for the amplifier transistors AMP. In contrast, in the present embodiment, the power supply lines 34 are electrically separated for each row of pixels PX, and the drains of the amplifier transistors AMP of each pixel PX (point b in FIG. 33) are commonly connected by the power supply line 34 for each row of pixels PX, and a power supply voltage signal φVDD is supplied to the drain as a power supply voltage for the amplifier transistors AMP from the power supply control circuit 52. When each power supply voltage signal φVDD is distinguished for each row of pixels PX, the power supply voltage signal φVDD supplied to the drain of the amplifier transistor AMP of the pixel PX in the nth row is denoted by the symbol φVDD(n). The drain of the reset transistor RST of each pixel PX is connected to the drain of the amplifier transistor AMP of that pixel PX (point b in FIG. 33) by the power supply line 34.

[0192] In this embodiment, the power supply control circuit 52 is provided as part of the vertical scanning circuit 22, and outputs each power supply voltage signal φVDD in place of each control signal φSEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is either an effective voltage level VDD that is effective for the operation of the amplifier transistor AMP, or an ineffective voltage level (here, 0 V, but not necessarily limited to 0 V) ​​that is ineffective for the operation of the amplifier transistor AMP, and the power supply control circuit 52 selectively supplies VDD or 0 V as the power supply voltage for the amplifier transistor AMP of each pixel PX.

[0193] In this embodiment, the state in which the power supply voltage signal φVDD in each pixel PX becomes VDD and the amplification transistor AMP operates effectively, and the state in which the power supply voltage signal φVDD becomes 0V and the amplification transistor AMP does not operate effectively are substantially the same as the state in which the control signal φSEL in each pixel PX becomes high level and the selection transistor SEL is turned on, and the state in which the control signal φSEL becomes low level and the selection transistor SEL is turned off, in the fifth embodiment, in terms of whether or not the output signal of each pixel PX is output to the vertical signal line 27.

[0194] Therefore, in this embodiment, the output signal of each pixel PX is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction relative to the pixel PX only when the selection transistor ASEL of the pixel PX is in a selected state (on state) and the power supply voltage signal φVDD supplied as the power supply voltage of the amplification transistor AMP of the pixel PX is at the effective voltage level VDD.

[0195] In this embodiment, the power supply control circuit 52 supplies an effective voltage level VDD as each power supply voltage signal φVDD instead of supplying a high-level signal as each φSEL in the fifth embodiment, and supplies 0 V as each power supply voltage signal φVDD instead of supplying a low-level signal as each φSEL in the fifth embodiment, thereby achieving the same operation as in the fifth embodiment.

[0196] This embodiment also provides the same advantages as those of the fifth embodiment. Furthermore, in this embodiment, the selection transistor ASEL is not provided in each pixel PX, and therefore the configuration of each pixel PX is simplified.

[0197] [Seventh embodiment]

[0198] Fig. 34 is a circuit diagram showing a schematic configuration of a solid-state imaging element 91 used in an electronic camera according to a seventh embodiment of the present invention, and corresponds to Fig. 28. Fig. 35 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging element 91 shown in Fig. 34, and corresponds to Fig. 29. In Figs. 34 and 35, elements that are the same as or correspond to elements in Figs. 28 and 29 are given the same reference numerals, and redundant explanations will be omitted.

[0199] In this embodiment, a solid-state image sensor 91 is used in place of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

[0200] This embodiment differs from the fifth embodiment in that for every two adjacent pixels PX in the column direction, the two pixels PX share a set of floating capacitance section FD, amplification transistor AMP, reset transistor RST, selection transistors SEL and ASEL, write transistor WT, and capacitor HC, and in that the vertical scanning circuit 22 is configured to output control signals φSEL, φRST, φTXA, and φTXB as shown in FIG. 27 instead of the control signals φSEL, φRST, and φTX as shown in FIG. 8.

[0201] 34 and 35, two pixels PX that share one set of floating capacitance unit FD, amplifier transistor AMP, reset transistor RST, select transistors SEL and ASEL, write transistor WT, and capacitor HC are shown as a pixel block BL. In addition, in Figures 34 and 35, the photodiode PD and transfer transistor TX of the lower pixel PX in the pixel block BL are indicated by symbols PDA and TXA, respectively, and the photodiode PD and transfer transistor TX of the upper pixel PX in the pixel block BL are indicated by symbols PDB and TXB, respectively, to distinguish between the two. Furthermore, the control signal supplied to the gate of transfer transistor TXA is indicated as φTXA, and the control signal supplied to the gate electrode of transfer transistor TXB is indicated as φTXB, to distinguish between the two.

[0202] 28 and 29, N, n, etc. indicate pixel rows, but in Figures 34 and 35, N, n, etc. indicate rows of pixel blocks BL. One row of pixel block BL corresponds to two rows of pixels PX.

[0203] The read control in this embodiment is the same as that in the fourth embodiment. Also, in this embodiment, a configuration similar to the configuration of the constrained partial region setting in the fourth embodiment may be adopted, or a configuration similar to the configuration of the unconstrained partial region setting in the fourth embodiment may be adopted.

[0204] This embodiment also provides advantages similar to those of the fifth embodiment. In this embodiment, for every two adjacent pixels PX in the column direction, the two pixels PX share a set of a floating capacitance unit FD, an amplifier transistor AMP, a reset transistor RST, selection transistors SEL and ASEL, a write transistor WT, and a capacitor HC. However, in the present invention, for example, for every predetermined number of pixels PX, three or more adjacent to each other in the column direction, the predetermined number of pixels PX may share a set of a floating capacitance unit FD, an amplifier transistor AMP, a reset transistor RST, selection transistors SEL and ASEL, a write transistor WT, and a capacitor HC. Furthermore, in the present invention, a modification similar to that of the fifth embodiment may be applied to the sixth embodiment.

[0205] [Eighth embodiment]

[0206] Fig. 36 is a circuit diagram showing a schematic configuration of a solid-state imaging device 101 used in an electronic camera according to an eighth embodiment of the present invention, and corresponds to Fig. 28. Fig. 37 is a circuit diagram showing one pixel PX (pixel PX in the nth row and mth column) of the solid-state imaging device 101 shown in Fig. 36, and corresponds to a part of Fig. 29. Fig. 38 is a timing chart showing write control signals that realize the same setting as the setting example shown in Fig. 6 in the solid-state imaging device 101 shown in Fig. 36, and corresponds to Fig. 31.

[0207] 36 to 38, elements that are the same as or correspond to elements in Figures 28, 29 and 31 are given the same reference numerals, and redundant explanations will be omitted. This embodiment differs from the fifth embodiment in the points described below.

[0208] In this embodiment, a solid-state image sensor 101 is used in place of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

[0209] In this embodiment, each pixel PX is provided with an SR latch circuit 103 instead of the capacitor HC as a holding unit that holds a selection control signal for setting the selection transistor ASEL of that pixel PX to a selected state or a non-selected state. Also, in this embodiment, a reset write control circuit 102 is added to the solid-state imaging device 101, which supplies a reset signal φWTRST, which forms part of the write control signal, to a reset input unit R of the SR latch circuit 103. The SR latch circuit 103 can be configured, for example, with a pair of cross-connected NOR gates, but is not limited to this.

[0210] The reset inputs R of the SR latch circuits 103 of all pixels PX are connected in common by a control line 104, to which a reset signal φWTRST is supplied from the reset write control circuit 102. The set input S of the SR latch circuit 103 of each pixel PX is connected to the source of the write transistor WT of that pixel PX. The output Q of the SR latch circuit 103 of each pixel PX is connected to the gate of the select transistor ASEL of that pixel PX.

[0211] 38 and 31, in this embodiment, in order to write a low-level signal as a signal held in the gate of the select transistor ASEL of all pixels PX during period t31-t32, φWTR(1) to φWTR(9) are set to a high level while φWTC(1) to φWTC(12) are set to a low level, so that not only is a high level supplied to the set input terminals S of the SR latch circuits 103 of all pixels PX, but also the reset signal φWTRST supplied to the reset input terminals R of the SR latch circuits 103 of all pixels PX is set to a high level. During other periods, the reset signal φWTRST is maintained at a low level.

[0212] In this embodiment, the row write control circuit 72, the column write control circuit 73, and the reset write control circuit 102 collectively constitute a write control unit that supplies write control signals φWTR, φWTC, and φWTRST to the write transistors WT serving as the write units of the pixels PX.

[0213] In this embodiment, the row write control circuit 72, the column write control circuit 73, the reset write control circuit 102, and the write transistor WT and latch circuit 103 of each pixel PX constitute an area setting unit that selects (turns on) the select transistor ASEL of the pixel PX of one or more desired partial areas to be read out of the imaging area 21.

[0214] This embodiment also provides the same advantages as the fifth embodiment. Note that this embodiment does not require the refresh operation described in the fifth embodiment.

[0215] Note that, in the present invention, modifications similar to those made by modifying the fifth embodiment to this embodiment may be applied to the sixth and seventh embodiments. Furthermore, instead of the capacitor HC or the SR latch circuit 103, other latch circuits or other memories may be used as the holding unit. Furthermore, a nonvolatile memory may be used as the holding unit. In this case, by storing information designating the pixel as a readout area in the nonvolatile memory of all pixels PX when power is turned off, the entire imaging area 21 can be initially set as a readout area immediately after power is turned on. This allows, for example, when still image capture is performed immediately after power is turned on, still image capture can be started quickly, preventing missed shutter opportunities.

[0216] Although the embodiments of the present invention and their modifications have been described above, the present invention is not limited to these.

[0217] For example, in each of the above embodiments, a connecting switch may be provided to turn on / off (electrically connect and disconnect) the gates of the amplification transistors AMP of each two adjacent pixels PX in the column direction or each two adjacent pixel blocks BL in the column direction.

[0218] Furthermore, in each of the above-described embodiments, the output signals of the pixels PX arranged in the same column are configured to be output to the same vertical signal line 27, but the pixels PX arranged in the same column may be divided into multiple groups, and the pixel output signals may be output to different vertical signal lines 27 for each group.

[0219] Furthermore, in the present invention, the solid-state imaging device is not limited to one made up of a single chip, but may have a structure in which a plurality of chips are joined together.

[0220] In the present invention, the features of the above-described embodiments and their modifications may be combined as appropriate. [Explanation of symbols]

[0221] 1. Electronic camera 4. Solid-state imaging element 21 Imaging area 22 Vertical scanning circuit 23 Area setting circuit 72 line write control circuit 73 Column write control circuit PX pixels PD photodiode TX transfer transistor AMP Amplifying Transistor RST Reset transistor FD Floating capacitor SEL, ASEL select transistor AR default subregion BL pixel block WT write transistor HC Capacitor

Claims

[Claim 1] a plurality of pixels each having a photoelectric conversion unit that converts light into an electric charge, a transfer unit that transfers the electric charge converted by the photoelectric conversion unit to a floating diffusion, a first transistor that includes a gate electrically connected to the floating diffusion and outputs a signal, and a second transistor that is electrically connected to the first transistor and outputs the signal; a first transfer control line through which a control signal for controlling the transfer unit is output, the first transfer control line being electrically connected to the transfer unit of a first pixel among the plurality of pixels, the transfer unit of a second pixel among the plurality of pixels that is arranged together with the first pixel in a first direction, and the transfer unit of a third pixel among the plurality of pixels that is arranged alongside the first pixel in the first direction; a second transfer control line that outputs a control signal for controlling the transfer unit, the second transfer control line being electrically connected to the transfer unit of a fourth pixel that is arranged together with the first pixel in a second direction intersecting the first direction among the plurality of pixels, the transfer unit of a fifth pixel that is arranged together with the fourth pixel in the first direction among the plurality of pixels, and the transfer unit of a sixth pixel that is arranged alongside the fourth pixel in the first direction among the plurality of pixels; a first control line through which a control signal for controlling the second transistor is output, the first control line being electrically connected to the second transistor of the first pixel, the second transistor of the second pixel, and the second transistor of the fourth pixel; an imaging element comprising: a control line through which a control signal for controlling the second transistor is output, the second control line being electrically connected to the second transistor of the third pixel and the second transistor of the sixth pixel.

Images