Semiconductor device

Abstract

To provide a semiconductor device capable of improving reliability of an insulator film and suppressing chip warpage in a compatible manner.SOLUTION: A semiconductor device comprises an emitter electrode, a gate electrode, a drift layer, a source layer, a base layer, a collector electrode and a dummy active trench including on an upper stage an upper-stage electrode which is connected to the gate electrode or the emitter electrode or has a floating potential and on a lower stage a lower-stage electrode which is connected to the gate electrode or the emitter electrode or has a floating potential inside of a trench of a semiconductor substrate. The dummy active trench includes an upper-stage insulator film which is formed on a side face of the upper-stage electrode, a lower-stage insulator film which is formed on a side face of the lower-stage electrode, and a boundary insulator film which is formed between the upper-stage electrode and the lower-stage electrode. A film thickness of the upper-stage insulator film in a lateral direction is larger than a film thickness of the lower-stage insulator film in the lateral direction, and an area of the upper-stage electrode is smaller than an area of the lower-stage electrode in a cross-sectional view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal. [Background technology]

[0002] Insulated gate bipolar transistors (IGBTs) are required to reduce both the recovery dv / dt, which is correlated with noise, and the turn-on loss, and an effective way to achieve this is to increase the gate capacitance ratio, Cgc / Cge, where Cgc is the capacitance between the gate electrode and collector electrode, and Cge is the capacitance between the gate electrode and emitter electrode.

[0003] Conventionally, a semiconductor device has been disclosed that aims to increase Cgc / Cge by including a two-stage dummy active trench structure (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-78755 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, a potential difference occurs between the upper dummy section and the lower active section in a two-stage dummy active trench, which can destroy the boundary insulating film formed between the upper dummy section and the lower active section, resulting in an issue with the reliability of the insulating film. To improve the reliability of the insulating film, it is possible to increase the thickness of the lower insulating film formed on the side surface of the lower active section. However, increasing the thickness of the lower insulating film increases the stress applied to the cell section, resulting in greater chip warpage. Therefore, the challenge is to achieve both improved insulating film reliability and suppressed chip warpage.

[0006] The present disclosure has been made to solve such problems, and aims to provide a semiconductor device that can improve the reliability of the insulating film while suppressing chip warpage. [Means for solving the problem]

[0007] In order to solve the above problems, a semiconductor device according to the present disclosure includes a semiconductor substrate, an emitter electrode formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate, a drift layer of a first conductivity type formed in the semiconductor substrate, a source layer of the first conductivity type formed on the upper surface side of the semiconductor substrate, a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate, a collector electrode formed below the semiconductor substrate, and a dummy active trench inside the trench in the semiconductor substrate, the dummy active trench having an upper electrode connected to the gate electrode or the emitter electrode or at a floating potential, and a lower electrode connected to the gate electrode or the emitter electrode or at a floating potential, the dummy active trench having an upper insulating film formed on a side surface of the upper electrode, a lower insulating film formed on a side surface of the lower electrode, and a boundary insulating film formed between the upper electrode and the lower electrode, the thickness of the upper insulating film in the left-right direction being thicker than the thickness of the lower insulating film in the left-right direction, and the area of ​​the upper electrode being smaller than the area of ​​the lower electrode in a cross-sectional view. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to improve the reliability of the insulating film while suppressing chip warpage. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 3] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 5] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh modification of the first embodiment. [Figure 6] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth modification of the first embodiment. [Figure 7] FIG. 13 is a cross-sectional view of a semiconductor device according to a ninth modification of the first embodiment. [Figure 8] FIG. 20 is a cross-sectional view of a semiconductor device according to a tenth modification of the first embodiment. [Figure 9] FIG. 22 is a cross-sectional view of a semiconductor device according to a twelfth modification of the first embodiment. [Figure 10] FIG. 22 is a cross-sectional view of a semiconductor device according to a thirteenth modification of the first embodiment. [Figure 11] FIG. 22 is a cross-sectional view of a semiconductor device according to a fourteenth modification of the first embodiment. [Figure 12] FIG. 23 is a plan view of a semiconductor device according to a fourteenth modification of the first embodiment. [Figure 13] FIG. 20 is a cross-sectional view of a semiconductor device according to a fifteenth modification of the first embodiment. [Figure 14] FIG. 20 is a cross-sectional view of a semiconductor device according to a sixteenth modification of the first embodiment. [Figure 15] FIG. 20 is a cross-sectional view of a semiconductor device according to a seventeenth modification of the first embodiment. [Figure 16] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 17] FIG. 10 is a cross-sectional view of a semiconductor device according to a first modification of the second embodiment. [Figure 18] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification of the second embodiment. [Figure 19] FIG. 10 is a cross-sectional view of a semiconductor device according to a third modification of the second embodiment. [Figure 20] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth modification of the second embodiment. [Figure 21] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth modification of the second embodiment. [Figure 22] FIG. 13 is a plan view of a semiconductor device according to a sixth modification of the second embodiment. [Figure 23] FIG. 10 is a Y1-Y2 cross-sectional view of a semiconductor device according to a sixth modification of the second embodiment. [Figure 24] FIG. 13 is a plan view of a semiconductor device according to a seventh modification of the second embodiment. [Figure 25] FIG. 11 is a cross-sectional view taken along the line Y3-Y4 of the semiconductor device according to the seventh modification of the second embodiment. [Figure 26] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth modification of the second embodiment. [Figure 27] FIG. 13 is a cross-sectional view of another example of a semiconductor device according to Modification 9 of Embodiment 2. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, semiconductor devices according to embodiments will be described with reference to the drawings. Note that the same or corresponding components will be denoted by the same reference numerals, and repeated description may be omitted. In the following description, n and p indicate the conductivity type of a semiconductor, and in this disclosure, the first conductivity type will be referred to as n-type and the second conductivity type will be referred to as p-type. These conductivity types may be reversed.

[0011] <First Embodiment> 1 is a cross-sectional view of a semiconductor device according to embodiment 1. In FIG. 1, the semiconductor substrate extends from source layer 3 to collector layer 14. In FIG. 1, the upper end of source layer 3 on the page is called the upper surface of the semiconductor substrate, and the lower end of collector layer 14 on the page is called the lower surface of the semiconductor substrate. The upper and lower surfaces are opposite to each other.

[0012] As shown in FIG. 1, the semiconductor device has an n-type drift layer 12 between the upper and lower surfaces of a semiconductor substrate.

[0013] An n-type carrier accumulation layer 5 having a higher n-type impurity concentration than the drift layer 12 is provided on the upper surface side of the drift layer 12. The carrier accumulation layer 5 is provided between the base layer 4 and the drift layer 12. By providing the carrier accumulation layer 5, the electric field is concentrated at the lower end of the carrier accumulation layer 5, thereby reducing the electric field strength between the upper electrode 7 and the lower electrode 10 and improving the reliability of the insulating film. Note that the semiconductor device may be configured such that the drift layer 12 is also provided in the region of the carrier accumulation layer 5 shown in FIG. 1 without providing the carrier accumulation layer 5.

[0014] A p-type base layer 4 is provided on the upper surface side of the carrier accumulation layer 5. An n-type source layer 3 is provided on the upper surface side of the base layer 4.

[0015] A dummy active trench 11 is provided in the semiconductor substrate. Inside the trench of the semiconductor substrate, the dummy active trench 11 has an upper electrode 7 on the upper level and a lower electrode 10 on the lower level. The upper electrode 7 is connected to a gate electrode (not shown) or an emitter electrode 1, or is at a floating potential. The lower electrode 10 is connected to a gate electrode (not shown) or an emitter electrode 1, or is at a floating potential. For example, the upper electrode 7 is connected to something other than the gate electrode, and the lower electrode 10 is connected to the gate electrode. Note that a "trench" refers to a hole provided in the semiconductor substrate or a structure formed in the hole.

[0016] The dummy active trench 11 also has an upper insulating film 6 formed on the side surface of the upper electrode 7, a lower insulating film 9 formed on the side surface of the lower electrode 10, and a boundary insulating film 8 formed between the upper electrode 7 and the lower electrode 10. The upper electrode 7 and the lower electrode 10 are electrically isolated from each other via the boundary insulating film 8. The left-right thickness T1 of the upper insulating film 6 is thicker than the left-right thickness T3 of the lower insulating film 9. Here, the left-right direction is the direction perpendicular to the depth direction of the dummy active trench 11 (the width direction of the dummy active trench 11). In a cross-sectional view, the area of ​​the upper electrode 7 is smaller than the area of ​​the lower electrode 10.

[0017] An interlayer insulating film 2 is provided on the dummy active trench 11. An emitter electrode 1 is provided on the source layer 3 and the interlayer insulating film 2.

[0018] An n-type buffer layer 13 having a higher n-type impurity concentration than the drift layer 12 is provided on the lower surface side of the drift layer 12. Note that the semiconductor device may be configured such that the buffer layer 13 is not provided and the drift layer 12 is also provided on the buffer layer 13 shown in FIG.

[0019] A p-type collector layer 14 is provided on the lower surface side of the buffer layer 13. A collector electrode 15 is provided on the lower surface side of the collector layer 14.

[0020] According to the first embodiment, the thickness T3 of the lower insulating film 9 is thin, so that chip warpage can be suppressed. Furthermore, the thickness T1 of the upper insulating film 6 is thick, so that the area of ​​the upper electrode 7 is small, and the reliability of the insulating film can be improved. Furthermore, the area of ​​the upper electrode 7 facing the thick upper insulating film 6, which is subject to high stress, is smaller than the area of ​​the lower electrode 10 facing the thin lower insulating film 9, which is subject to low stress, so that the overall stress is reduced and chip warpage can be suppressed. In other words, according to the first embodiment, it is possible to improve the reliability of the insulating film and suppress chip warpage at the same time.

[0021] <Variation 1> 2 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 1. As shown in FIG. 2, in the semiconductor device according to Modification 1, the thickness T2 of the boundary insulating film 8 in the vertical direction is thicker than the thickness T3 of the lower insulating film 9 in the horizontal direction. In addition, in the cross-sectional view, the area of ​​the upper electrode 7 is smaller than the area of ​​the lower electrode 10. Here, the vertical direction refers to the depth direction of the dummy active trench 11.

[0022] According to the first modification, chip warpage can be suppressed because the thickness T3 in the left-right direction of the lower insulating film 9 is thin. Also, the thickness T2 in the up-down direction of the boundary insulating film 8 is thick, so the distance between the upper electrode 7 and the lower electrode 10 increases, improving the reliability of the insulating film.

[0023] <Variation 2> 3 is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 1. As shown in Fig. 3, the relationship between the left-right thickness T1 of the upper insulating film 6, the top-to-bottom thickness T2 of the boundary insulating film 8, and the left-to-right thickness T3 of the lower insulating film 9 is as follows: top-to-bottom thickness T2 of the boundary insulating film 8 > top-to-bottom thickness T1 of the upper insulating film 6 > top-to-bottom thickness T3 of the lower insulating film 9. That is, the top-to-bottom thickness T2 of the boundary insulating film 8 is the thickest, followed by the top-to-bottom thickness T1 of the upper insulating film 6, and the bottom-to-bottom thickness T3 of the lower insulating film 9.

[0024] According to the second modification, the vertical film thickness T2 of the boundary insulating film 8 is thicker than the horizontal film thickness T1 of the upper insulating film 6, so that it is possible to reduce the aspect ratio (L1 / W1) of the vertical length L1 (depth of the upper electrode 7) to the horizontal length W1 of the upper electrode 7 (width of the upper electrode 7). Therefore, it is possible to improve the embeddability of the upper electrode 7.

[0025] <Variation 3> As in the semiconductor device shown in FIGS. 1 and 3, the boundary insulating film 8 may be located above the center of the dummy active trench 11 in the vertical direction.

[0026] With this configuration, the area of ​​the upper electrode 7 facing the thick upper insulating film 6, which experiences a large stress, is smaller than the area of ​​the lower electrode 10 facing the thin lower insulating film 9, which experiences a small stress, thereby reducing the overall stress and suppressing chip warpage.

[0027] <Variation 4> 4 is a cross-sectional view of a semiconductor device according to Modification 4 of Embodiment 1. As shown in Fig. 4, a length L2 from the upper surface of the semiconductor substrate to the upper end of the lower electrode 10 is longer than a length P1 of the base layer 4 in the up-down direction.

[0028] If the upper end of the lower electrode 10 extends to the base layer 4, Cge increases and Cgc / Cge decreases. According to Modification 4, by making the length L2 from the upper surface of the semiconductor substrate to the upper end of the lower electrode 10 longer than the length P1 in the vertical direction of the base layer 4, Cge can be reduced, and it is possible to achieve both a reduction in recovery dv / dt and a reduction in turn-on loss.

[0029] Although the above example illustrates the case where Modification 4 is applied to the semiconductor device shown in FIG. 3, Modification 4 may also be applied to the semiconductor device shown in FIGS.

[0030] <Variation 5> As in the semiconductor device shown in FIGS. 1 to 3, the boundary insulating film 8 may be located above the lower end of the carrier accumulation layer 5.

[0031] With this configuration, the boundary insulating film 8, which affects the reliability of the insulating film, can be separated from the lower end of the carrier accumulation layer 5, which is a high electric field location, thereby improving the reliability of the insulating film.

[0032] <Variation 6> As in the semiconductor device shown in FIGS. 1 to 3, the boundary insulating film 8 may be located above the center of the carrier accumulation layer 5.

[0033] With this configuration, the boundary insulating film 8, which affects the reliability of the insulating film, can be further separated from the lower end of the carrier accumulation layer 5, which is a high electric field location, thereby improving the reliability of the insulating film.

[0034] <Variation 7> Fig. 5 is a cross-sectional view of a semiconductor device according to Modification 7 of Embodiment 1. Fig. 5 shows the distribution of impurity concentration in carrier accumulation layer 5 in the semiconductor device shown in Fig. 3. As shown in Fig. 5, boundary insulating film 8 may be located above the peak position of the impurity concentration in carrier accumulation layer 5.

[0035] The depletion layer is less likely to extend and the electric field is lower at a position shallower than the peak position of the impurity concentration in the carrier accumulation layer 5 (a position on the upper surface side of the semiconductor substrate) than at a position deeper than the peak position of the impurity concentration in the carrier accumulation layer 5 (a position on the lower surface side of the semiconductor substrate). According to the seventh modification, the boundary insulating film 8, which affects the reliability of the insulating film, can be further separated from the peak position of the impurity concentration in the carrier accumulation layer 5, which is a high electric field position, thereby improving the reliability of the insulating film.

[0036] Although the above example illustrates the case where Modification 7 is applied to the semiconductor device shown in FIG. 3, Modification 7 may also be applied to the semiconductor device shown in FIGS.

[0037] <Variation 8> Fig. 6 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 1. As shown in Fig. 6, the length L3 of the lower electrode 10 in the vertical direction may be longer than the length L1 of the upper electrode 7 in the vertical direction.

[0038] According to variant example 8, the effect of suppressing chip warpage can be increased by making the vertical length L3 of the lower electrode 10, which has a thin lower insulating film on its side that is effective in suppressing chip warpage, longer than the vertical length L1 of the upper electrode 7, which has a thick upper insulating film on its side.

[0039] Although the above example illustrates the case where Modification 8 is applied to the semiconductor device shown in FIG. 3, Modification 8 may also be applied to the semiconductor device shown in FIGS.

[0040] <Variation 9> Fig. 7 is a cross-sectional view of a semiconductor device according to Modification 9 of Embodiment 1. As shown in Fig. 7, the length L1 of the upper electrode 7 in the vertical direction may be shorter than the length P1 of the base layer 4 in the vertical direction.

[0041] According to the ninth modification, by shortening the vertical length L1 of the upper electrode 7, it is possible to reduce the aspect ratio (L1 / W1) of the vertical length L1 (depth of the upper electrode 7) to the horizontal length W1 (width of the upper electrode 7) of the upper electrode 7. Therefore, it is possible to improve the embeddability of the upper electrode 7.

[0042] Although the above example illustrates the case where Modification 9 is applied to the semiconductor device shown in FIG. 3, Modification 9 may also be applied to the semiconductor device shown in FIGS.

[0043] <Modification 10> Fig. 8 is a cross-sectional view of a semiconductor device according to Modification 10 of Embodiment 1. As shown in Fig. 8, the length L1 of the upper electrode 7 in the up-down direction may be shorter than the length W1 of the upper electrode in the left-right direction.

[0044] According to Modification 10, by shortening the vertical length L1 of the upper electrode 7 and lengthening the horizontal length W1 of the upper electrode 7, it is possible to reduce the aspect ratio (L1 / W1) of the vertical length L1 (depth of the upper electrode 7) to the horizontal length W1 of the upper electrode 7 (width of the upper electrode 7). Therefore, it is possible to improve the embeddability of the upper electrode 7.

[0045] Although the above example illustrates the application of Modification 10 to the semiconductor device shown in FIG. 3, Modification 10 may also be applied to the semiconductor device shown in FIGS.

[0046] <Variation 11> In the semiconductor device shown in FIGS. 1 to 3, the material of the lower electrode 10 may be amorphous silicon.

[0047] According to variant example 11, by using amorphous silicon, which has less surface irregularities than polysilicon, as the material for the lower electrode 10, the electric field strength between the upper electrode 7 and the lower electrode 10 can be reduced, thereby improving the reliability of the insulating film.

[0048] <Variation 12> 9 is a cross-sectional view of a semiconductor device according to Modification 12 of Embodiment 1. As shown in Fig. 9, the aspect ratio (L1 / W1) of the vertical length L1 (depth of upper electrode 7) to the horizontal length W1 (width of upper electrode 7) of upper electrode 7 may be smaller than the aspect ratio (L2 / W2) of the vertical length L2 (depth of lower electrode 10) to the horizontal length W2 (width of lower electrode 10) of lower electrode 10.

[0049] According to the twelfth modification, the aspect ratio (L1 / W1) of the upper electrode 7 is made smaller than the aspect ratio (L2 / W2) of the lower electrode 10, thereby improving the embeddability of the upper electrode 7.

[0050] Although the above example illustrates the case where Modification 12 is applied to the semiconductor device shown in FIG. 3, Modification 12 may also be applied to the semiconductor device shown in FIGS.

[0051] <Variation 13> 10 is a cross-sectional view of a semiconductor device according to Modification 13 of Embodiment 1. As shown in FIG.

[0052] According to the modification 13, by not providing the interlayer insulating film 2 above the upper electrode 7, the current flowing in the upper electrode 7 can be immediately discharged to the emitter electrode 1. In other words, the effect of the voltage drop caused by the current flowing in the upper electrode 7 can be reduced, and the stress on the insulating film due to the voltage drop can be reduced. Therefore, the reliability of the insulating film can be improved.

[0053] Although the above example illustrates the case where Modification 13 is applied to the semiconductor device shown in FIG. 3, Modification 13 may also be applied to the semiconductor device shown in FIGS.

[0054] <Variation 14> Fig. 11 is a cross-sectional view of a semiconductor device according to a fourteenth modification of the first embodiment. Fig. 12 is a plan view of the semiconductor device shown in Fig. 11 as viewed from the top surface side. As shown in Fig. 11, the dummy active trench 11 has a side contact 20 whose one side surface contacts the source layer 3 and the base layer 4.

[0055] With this configuration, the source layer 3 and the base layer 4 can be electrically connected to the emitter electrode 1 via the side contact 20. This allows the width between adjacent active trenches (see, for example, FIG. 16 described later) (contact width of the mesa portion) to be reduced, enabling the cell portion to be miniaturized. Miniaturizing the cell portion allows for improved semiconductor device characteristics, such as reduced on-state voltage.

[0056] Although the above example illustrates the case where Modification 14 is applied to the semiconductor device shown in FIG. 3, Modification 14 may also be applied to the semiconductor device shown in FIGS.

[0057] <Variation 15> 13 is a cross-sectional view of a semiconductor device according to Modification 15 of Embodiment 1. As shown in FIG. 13, one side of the side contact 20 may be in contact with the source layer 3 and the base layer 4, and the other side may be in contact with the upper electrode 7.

[0058] By adopting such a configuration, in addition to the effect of variant example 14, the upper electrode 7 can also be connected to the emitter electrode 1 from the side via the side contact 20, thereby increasing the contact area of ​​the upper electrode 7 and improving the stability of the potential relative to the emitter electrode 1.

[0059] Although the above example illustrates the case where Modification 15 is applied to the semiconductor device shown in FIG. 3, Modification 15 may also be applied to the semiconductor device shown in FIGS.

[0060] <Variation 16> 14 is a cross-sectional view of a semiconductor device according to Modification 16 of Embodiment 1. As shown in Fig. 14, the vertical length SC1 of the side contact 20 (the depth of the side contact 20) may be longer than the vertical length SS1 of the source layer 3 (the depth of the source layer 3).

[0061] With this configuration, the contact area between the side contact 20 and the source layer 3 and the base layer 4 can be increased, thereby reducing the contact resistance.

[0062] Although the above example illustrates the case where Modification 16 is applied to the semiconductor device shown in FIG. 3, Modification 16 may also be applied to the semiconductor device shown in FIGS.

[0063] <Variation 17> 15 is a cross-sectional view of a semiconductor device according to Modification 17 of Embodiment 1. As shown in Fig. 15, the upper end of the upper insulating film 6 may be spaced a predetermined distance U1 from the upper surface of the semiconductor substrate. In addition, the upper electrode 7 has a T-shape in cross section.

[0064] With this configuration, the effective aspect ratio of the upper electrode 7 can be reduced, and therefore the embeddability of the upper electrode 7 can be improved.

[0065] Although the above example illustrates the case where Modification 17 is applied to the semiconductor device shown in FIG. 3, Modification 17 may also be applied to the semiconductor device shown in FIGS.

[0066] <Variation 18> In the semiconductor device shown in FIGS. 1 to 3, the material of the upper electrode 7 may be amorphous silicon.

[0067] According to variant 18, by using amorphous silicon, which has less surface irregularities than polysilicon, as the material for the upper electrode 7, the electric field strength between the upper electrode 7 and the lower electrode 10 can be reduced, thereby improving the reliability of the insulating film.

[0068] <Variation 19> In the semiconductor device shown in FIGS. 1 to 3, the material of the upper electrode 7 may be an insulating material.

[0069] According to Modification 19, by using an insulating material for the upper electrode 7, the electric field strength between the upper electrode 7 and the lower electrode 10 can be reduced, and the reliability of the insulating film can be improved.

[0070] <Variation 20> In the semiconductor device shown in FIGS. 1 to 3, the material of the upper electrode 7 may be a metal.

[0071] According to Modification 20, by using a metal material for the upper electrode 7, the resistance of the upper electrode 7 can be reduced, and the current flowing in the upper electrode 7 can be quickly discharged to the emitter electrode 1. In other words, the effect of the voltage drop caused by the current flowing in the upper electrode 7 can be reduced, and the stress on the insulating film due to the voltage drop can be reduced. Therefore, the reliability of the insulating film can be improved.

[0072] <Embodiment 2> 16 is a cross-sectional view of a semiconductor device according to embodiment 2. The semiconductor device according to embodiment 2 is characterized by including dummy active trenches 11 and active trenches 32. Note that the dummy active trenches 11 are similar to the dummy active trenches 11 shown in FIG. 3, and therefore detailed description thereof will be omitted here.

[0073] The semiconductor substrate is provided with a dummy active trench 11 and an active trench 32. The active trench 32 has, inside the trench of the semiconductor substrate, an active portion 31 and an insulating film 30 provided so as to cover the active portion 31. The active portion 31 is connected to a gate electrode.

[0074] According to the second embodiment, in addition to the effect of the first embodiment, the provision of the active trench 32 allows a current to flow in the semiconductor device.

[0075] Although FIG. 16 illustrates a configuration including the dummy active trench 11 shown in FIG. 3, it may also be a configuration including the dummy active trench 11 shown in FIG. 1 or FIG.

[0076] <Variation 1> 17 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 2. Note that the dummy active trenches 11 are similar to the dummy active trenches 11 shown in FIG.

[0077] 17, a semiconductor substrate is provided with dummy active trenches 11 and active trenches 45. Inside the trench of the semiconductor substrate, the active trench 45 has an upper active portion 41 at the upper level and a lower active portion 44 at the lower level. The upper active portion 41 and the lower active portion 44 are connected to gate electrodes.

[0078] The active trench 45 also has an upper insulating film 40 provided on the side surface of the upper active portion 41, a lower insulating film 43 provided on the side surface of the lower active portion 44, and a boundary insulating film 42 provided between the upper active portion 41 and the lower active portion 44. The upper active portion 41 and the lower active portion 44 are electrically isolated from each other via the boundary insulating film 42. The thickness of the upper insulating film 40 in the left-right direction is thicker than the thickness of the lower insulating film 43 in the left-right direction.

[0079] According to variant example 1, by providing a boundary insulating film 42 in the active trench 45, the area of ​​the electrode electrically connected to the gate electrode can be reduced by the area where the boundary insulating film 42 is formed, thereby reducing the gate capacitance.

[0080] 17 illustrates a configuration including the dummy active trench 11 shown in Fig. 3, but a configuration including the dummy active trench 11 shown in Fig. 1 may also be used. In this case, the position and size of the upper-stage active section 41 may be the same as the position and size of the upper-stage electrode 7 shown in Fig. 1.

[0081] <Variation 2> 18 is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 2. Note that the dummy active trenches 11 are similar to the dummy active trenches 11 shown in FIG.

[0082] 18 , in the active trench 45, the thickness of the upper insulating film 40 in the left-right direction may be the same as the thickness of the lower insulating film 43 in the left-right direction. Alternatively, the thickness of the upper insulating film 40 in the left-right direction may be thinner than the thickness of the lower insulating film 43 in the left-right direction.

[0083] By adopting such a configuration, the channel resistance can be reduced, and the on-voltage can be reduced.

[0084] <Variation 3> Fig. 19 is a cross-sectional view of a semiconductor device according to Modification 3 of Embodiment 2. Note that the dummy active trenches 11 are the same as the dummy active trenches 11 shown in Fig. 3, and the active trenches 32 are the same as the active trenches 32 shown in Fig. 16, and therefore detailed description thereof will be omitted here.

[0085] 19, the upper electrode 7 is made of an insulator 50, which may be a chemical vapor deposition (CVD) film. Alternatively, the impurity concentration of the insulator 50 may be higher than the impurity concentration of the lower insulating film 9.

[0086] For the insulator 50, which is the material of the upper electrode 7, a CVD film formed by a CVD method such as HTO (High Temperature Oxide), TEOS (Tetra Eth Oxy Silane), or BPSG (Boron Phospho Silicate Glass), which has a lower formation temperature than a thermal oxide film, can be used to lower the formation temperature of the insulating film, thereby suppressing thermal expansion and reducing stress generated during the formation of the insulating film. Also, CVD films are generally characterized by having a higher impurity concentration than thermal oxide films.

[0087] 19 illustrates a configuration including the dummy active trench 11 shown in Fig. 3, but may also be a configuration including the dummy active trench 11 shown in Fig. 1 or 2. Furthermore, while Fig. 19 illustrates a configuration including the active trench 32 shown in Fig. 16, it may also be a configuration including the active trench 45 shown in Figs. 17 and 18.

[0088] <Variation 4> Fig. 20 is a cross-sectional view of a semiconductor device according to Modification 4 of Embodiment 2. Note that the dummy active trenches 11 are the same as the dummy active trenches 11 shown in Fig. 3, and the active trenches 32 are the same as the active trenches 32 shown in Fig. 16, and therefore detailed description thereof will be omitted here.

[0089] 20, the corners of the lower end of the upper electrode 7 may have a curvature. With this configuration, the electric field concentration at the corners of the upper electrode 7 can be alleviated.

[0090] 20 illustrates a configuration including the dummy active trench 11 shown in Fig. 3, but may also be a configuration including the dummy active trench 11 shown in Fig. 1 or 2. Furthermore, while Fig. 20 illustrates a configuration including the active trench 32 shown in Fig. 16, it may also be a configuration including the active trench 45 shown in Figs. 17 and 18.

[0091] <Variation 5> Fig. 21 is a cross-sectional view of a semiconductor device according to Modification 5 of Embodiment 2. Note that the dummy active trenches 11 are the same as the dummy active trenches 11 shown in Fig. 3, and the active trenches 32 are the same as the active trenches 32 shown in Fig. 16, and therefore detailed description thereof will be omitted here.

[0092] As shown in FIG. 21, the top end of the upper electrode 7 may be spaced a predetermined distance R1 from the top surface of the semiconductor substrate.

[0093] With this configuration, the aspect ratio of the upper electrode 7 becomes small, and the embedding property of the upper electrode 7 can be improved.

[0094] 21 illustrates a configuration including the dummy active trench 11 shown in Fig. 3, but may also be a configuration including the dummy active trench 11 shown in Fig. 1 or 2. Furthermore, while Fig. 21 illustrates a configuration including the active trench 32 shown in Fig. 16, it may also be a configuration including the active trench 45 shown in Figs. 17 and 18.

[0095] <Variation 6> Fig. 22 is a plan view of a semiconductor device according to Modification 6 of Embodiment 2. Fig. 23 is a Y1-Y2 cross-sectional view of the semiconductor device shown in Fig. 22.

[0096] 22 and 23, the dummy active trench 11 having the upper electrode 7 and the lower electrode 10 and the active trench 32 having the active portion 31 may be connected via a trench. The dummy active trench 11 and the active trench 32 are partially connected via the trench.

[0097] According to the sixth modification, the dummy active trenches 11 and the active trenches 32 are electrically connected to each other, thereby making it possible to stabilize the electrical connection to the gate electrode.

[0098] <Variation 7> Fig. 24 is a plan view of a semiconductor device according to Modification 7 of Embodiment 2. Fig. 25 is a cross-sectional view of the semiconductor device shown in Fig. 24 taken along the line Y3-Y4.

[0099] 24 and 25, a dummy active trench 11 having an upper electrode 7 and a lower electrode 10 and an active trench 32 having an active portion 31 may be connected via a trench. The active portion 31 is provided inside the trench connecting the dummy active trench 11 and the active trench 32.

[0100] According to the seventh modification, it is possible to stabilize the electrical connection to the gate electrode by electrically connecting the dummy active trench 11 and the active trench 32. Furthermore, by providing the active part 31 inside the trench that connects the dummy active trench 11 and the active trench 32, the connection area between the dummy active trench 11 and the active trench 32 is increased, making it possible to connect them with lower resistance.

[0101] <Variation 8> Fig. 26 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 2. Note that the dummy active trenches 11 are the same as the dummy active trenches 11 shown in Fig. 3, and the active trenches 32 are the same as the active trenches 32 shown in Fig. 16, and therefore detailed description thereof will be omitted here.

[0102] As shown in FIG. 26, the upper insulating film 6 and the boundary insulating film 8 in the dummy active trench 11 may be a CVD film 60.

[0103] The insulating film may be formed as either a thermal oxide film or a CVD film, but by using a thermal oxide film with excellent electrical stability as the lower insulating film 9 and a CVD film formed by a CVD method such as HTO, TEOS, or BPSG, which has a lower formation temperature than a thermal oxide film, as the thicker upper insulating film 6 and boundary insulating film 8, the insulating film formation temperature can be lowered, thereby reducing the stress generated during the formation of the insulating film. Also, CVD films are generally characterized by a higher impurity concentration than thermal oxide films.

[0104] Alternatively, a thermal oxide film, which has excellent electrical properties, may be combined with a CVD film. Specifically, as shown in FIG. 27, the first layer may be a thermal oxide film 61, and the second layer may be a CVD film 60. By forming the trench interface, where electrical properties are required, as the thermal oxide film 61, good gate properties can be obtained, and the CVD film 60 can reduce thermal stress. The first layer, which is subject to the greatest stress at the trench interface, may be a CVD film 60, and the second layer may be a thermal oxide film 61, thereby reducing the stress generated at the trench interface.

[0105] 26, the upper insulating film 6 and the boundary insulating film 8 are CVD films 60, but at least one of the upper insulating film 6 and the boundary insulating film 8 may be CVD films 60. In addition, it is only necessary that at least one of the impurity concentration of the upper insulating film 6 and the impurity concentration of the boundary insulating film 8 is higher than the impurity concentration of the lower insulating film 9.

[0106] 26 illustrates a configuration including the dummy active trench 11 shown in Fig. 3, but may also be a configuration including the dummy active trench 11 shown in Fig. 1 or 2. Furthermore, while Fig. 26 illustrates a configuration including the active trench 32 shown in Fig. 16, it may also be a configuration including the active trench 45 shown in Figs. 17 and 18.

[0107] Within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0108] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0109] (Appendix 1) a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a first conductivity type source layer formed on the upper surface side of the semiconductor substrate; a second conductivity type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a dummy active trench inside the trench of the semiconductor substrate, the dummy active trench having an upper electrode connected to the gate electrode or the emitter electrode or at a floating potential, and a lower electrode connected to the gate electrode or the emitter electrode or at a floating potential; Equipped with the dummy active trench has an upper insulating film formed on a side surface of the upper electrode, a lower insulating film formed on a side surface of the lower electrode, and a boundary insulating film formed between the upper electrode and the lower electrode, the upper insulating film has a thickness in the left-right direction that is greater than the thickness in the left-right direction of the lower insulating film; A semiconductor device, wherein, in a cross-sectional view, the area of ​​the upper electrode is smaller than the area of ​​the lower electrode. (Appendix 2) a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a first conductivity type source layer formed on the upper surface side of the semiconductor substrate; a second conductivity type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a dummy active trench inside the trench of the semiconductor substrate, the dummy active trench having an upper electrode connected to the gate electrode or the emitter electrode or at a floating potential, and a lower electrode connected to the gate electrode or the emitter electrode or at a floating potential; Equipped with the dummy active trench has an upper insulating film formed on a side surface of the upper electrode, a lower insulating film formed on a side surface of the lower electrode, and a boundary insulating film formed between the upper electrode and the lower electrode, the thickness of the boundary insulating film in the vertical direction is thicker than the thickness of the lower insulating film in the horizontal direction; A semiconductor device, wherein, in a cross-sectional view, the area of ​​the upper electrode is smaller than the area of ​​the lower electrode. (Appendix 3) The semiconductor device according to claim 1 or 2, wherein the relationship between the left-right film thickness of the upper insulating film, the top-bottom film thickness of the boundary insulating film, and the left-right film thickness of the lower insulating film is: top-bottom film thickness of the boundary insulating film > left-right film thickness of the upper insulating film > left-right film thickness of the lower insulating film. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the boundary insulating film is located above the center of the dummy active trench in the vertical direction. (Appendix 5) 5. The semiconductor device according to claim 1, wherein a length from an upper surface of the semiconductor substrate to an upper end of the lower electrode is longer than a length of the base layer in the vertical direction. (Appendix 6) 6. The semiconductor device according to claim 1, further comprising a carrier accumulation layer of a first conductivity type between the base layer and the drift layer. (Appendix 7) 7. The semiconductor device according to claim 6, wherein the boundary insulating film is located above a lower end of the carrier accumulation layer. (Appendix 8) 7. The semiconductor device according to claim 6, wherein the boundary insulating film is located above a center of the carrier accumulation layer. (Appendix 9) 7. The semiconductor device according to claim 6, wherein the boundary insulating film is located above a peak position of the impurity concentration of the carrier accumulation layer. (Appendix 10) 10. The semiconductor device according to claim 1, wherein the lower electrode has a vertical length longer than the upper electrode. (Appendix 11) 11. The semiconductor device according to claim 1, wherein the upper electrode has a vertical length shorter than the vertical length of the base layer. (Appendix 12) 12. The semiconductor device according to claim 1, wherein the upper electrode has a length in the up-down direction that is shorter than a length in the left-right direction of the upper electrode. (Appendix 13) 13. The semiconductor device according to any one of claims 1 to 12, wherein the material of the lower electrode is amorphous silicon. (Appendix 14) 14. A semiconductor device according to any one of claims 1 to 13, wherein the aspect ratio of the vertical length to the horizontal length of the upper electrode is smaller than the aspect ratio of the vertical length to the horizontal length of the lower electrode. (Appendix 15) 15. The semiconductor device according to any one of claims 1 to 14, wherein an interlayer insulating film is not formed above the upper electrode. (Appendix 16) 16. The semiconductor device according to any one of claims 1 to 15, wherein the dummy active trench further comprises a side contact, one side of which contacts the source layer and the base layer. (Appendix 17) 17. The semiconductor device according to claim 16, wherein the other side surface of the side contact is in contact with the upper electrode. (Appendix 18) 17. The semiconductor device according to claim 16, wherein the side contact has a vertical length longer than the source layer. (Appendix 19) 19. The semiconductor device according to any one of claims 1 to 18, wherein an upper end of the upper insulating film is spaced a predetermined distance from an upper surface of the semiconductor substrate. (Appendix 20) 20. The semiconductor device according to any one of claims 1 to 19, wherein the material of the upper electrode is amorphous silicon. (Appendix 21) 20. The semiconductor device according to any one of claims 1 to 19, wherein the upper electrode is made of an insulating material. (Appendix 22) 20. The semiconductor device according to any one of claims 1 to 19, wherein the material of the upper electrode is a metal. (Appendix 23) 23. The semiconductor device according to any one of claims 1 to 22, further comprising an active trench having an active portion inside the trench of the semiconductor substrate. (Appendix 24) 24. The semiconductor device according to claim 23, wherein the active section is divided into an upper active section and a lower active section via a boundary insulating film. (Appendix 25) 22. The semiconductor device according to claim 21, wherein the insulator is a chemical vapor deposition (CVD) film. (Appendix 26) 22. The semiconductor device according to claim 21, wherein the insulator has an impurity concentration higher than an impurity concentration of the lower insulating film. (Appendix 27) 27. The semiconductor device according to any one of claims 1 to 26, wherein a corner of a lower end of the upper electrode has a curvature. (Appendix 28) 28. The semiconductor device according to any one of claims 1 to 27, wherein an upper end of the upper electrode is spaced a predetermined distance from an upper surface of the semiconductor substrate. (Appendix 29) 24. The semiconductor device according to claim 23, wherein the dummy active trench and the active trench are connected via a trench. (Appendix 30) 30. The semiconductor device according to claim 29, wherein the active portion is formed inside the trench. (Appendix 31) 31. The semiconductor device according to any one of appendixes 1 to 30, wherein at least one of the upper insulating film and the boundary insulating film is a chemical vapor deposition (CVD) film. (Appendix 32) 32. The semiconductor device according to any one of appendixes 1 to 31, wherein at least one of the impurity concentration of the upper insulating film and the impurity concentration of the boundary insulating film is higher than the impurity concentration of the lower insulating film. [Explanation of symbols]

[0110] 1 emitter electrode, 2 interlayer insulating film, 3 source layer, 4 base layer, 5 carrier storage layer, 6 upper insulating film, 7 upper electrode, 8 boundary insulating film, 9 lower insulating film, 10 lower electrode, 11 dummy active trench, 12 drift layer, 13 buffer layer, 14 collector layer, 15 collector electrode, 20 side contact, 30 insulating film, 31 active section, 32 active trench, 40 upper insulating film, 41 upper active section, 42 boundary insulating film, 43 lower insulating film, 44 lower active section, 45 active trench, 50 insulator, 60 CVD film, 61 thermal oxide film.

Claims

1. a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a first conductivity type source layer formed on the upper surface side of the semiconductor substrate; a second conductivity type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a dummy active trench inside the trench of the semiconductor substrate, the dummy active trench having an upper electrode connected to the gate electrode or the emitter electrode or at a floating potential, and a lower electrode connected to the gate electrode or the emitter electrode or at a floating potential, Equipped with the dummy active trench has an upper insulating film formed on a side surface of the upper electrode, a lower insulating film formed on a side surface of the lower electrode, and a boundary insulating film formed between the upper electrode and the lower electrode, the upper insulating film has a thickness in the left-right direction that is greater than the thickness in the left-right direction of the lower insulating film; A semiconductor device, wherein, in a cross-sectional view, the area of ​​the upper electrode is smaller than the area of ​​the lower electrode.

2. a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a first conductivity type source layer formed on the upper surface side of the semiconductor substrate; a second conductivity type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a dummy active trench inside the trench of the semiconductor substrate, the dummy active trench having an upper electrode connected to the gate electrode or the emitter electrode or at a floating potential, and a lower electrode connected to the gate electrode or the emitter electrode or at a floating potential, Equipped with the dummy active trench has an upper insulating film formed on a side surface of the upper electrode, a lower insulating film formed on a side surface of the lower electrode, and a boundary insulating film formed between the upper electrode and the lower electrode, the thickness of the boundary insulating film in the vertical direction is thicker than the thickness of the lower insulating film in the horizontal direction; A semiconductor device, wherein, in a cross-sectional view, the area of ​​the upper electrode is smaller than the area of ​​the lower electrode.

3. 3. The semiconductor device according to claim 1, wherein a relationship between a left-right film thickness of the upper insulating film, a top-bottom film thickness of the boundary insulating film, and a left-right film thickness of the lower insulating film is such that a top-bottom film thickness of the boundary insulating film > a left-right film thickness of the upper insulating film > a left-right film thickness of the lower insulating film.

4. 3. The semiconductor device according to claim 1, wherein the boundary insulating film is located above the center of the dummy active trench in the vertical direction.

5. 3. The semiconductor device according to claim 1, wherein a length from the upper surface of said semiconductor substrate to an upper end of said lower electrode is longer than a length of said base layer in the vertical direction.

6. The semiconductor device according to claim 1 , further comprising a carrier accumulation layer of the first conductivity type between the base layer and the drift layer.

7. 7. The semiconductor device according to claim 6, wherein said boundary insulating film is located above a lower end of said carrier accumulation layer.

8. 7. The semiconductor device according to claim 6, wherein said boundary insulating film is located above the center of said carrier accumulation layer.

9. 7. The semiconductor device according to claim 6, wherein said boundary insulating film is located above a peak position of impurity concentration of said carrier accumulation layer.

10. 3. The semiconductor device according to claim 1, wherein the lower electrode has a vertical length longer than the upper electrode.

11. 3. The semiconductor device according to claim 1, wherein the upper electrode has a vertical length shorter than that of the base layer.

12. 3. The semiconductor device according to claim 1, wherein a vertical length of said upper electrode is shorter than a horizontal length of said upper electrode.

13. 3. The semiconductor device according to claim 1, wherein the material of said lower electrode is amorphous silicon.

14. 3. The semiconductor device according to claim 1, wherein an aspect ratio of the vertical length to the horizontal length of said upper electrode is smaller than an aspect ratio of the vertical length to the horizontal length of said lower electrode.

15. 3. The semiconductor device according to claim 1, wherein an interlayer insulating film is not formed above said upper electrode.

16. The semiconductor device according to claim 1 , wherein the dummy active trench further comprises a side contact, one side of which contacts the source layer and the base layer.

17. 17. The semiconductor device according to claim 16, wherein the other side surface of the side contact is in contact with the upper electrode.

18. 17. The semiconductor device according to claim 16, wherein the side contact has a vertical length longer than the source layer.

19. 3. The semiconductor device according to claim 1, wherein an upper end of said upper insulating film is spaced a predetermined distance from an upper surface of said semiconductor substrate.

20. 3. The semiconductor device according to claim 1, wherein the upper electrode is made of amorphous silicon.

21. 3. The semiconductor device according to claim 1, wherein the upper electrode is made of an insulating material.

22. 3. The semiconductor device according to claim 1, wherein the upper electrode is made of a metal.

23. The semiconductor device according to claim 1 , further comprising an active trench having an active portion inside the trench of the semiconductor substrate.

24. 24. The semiconductor device according to claim 23, wherein said active section is divided into an upper active section and a lower active section via a boundary insulating film.

25. 22. The semiconductor device according to claim 21, wherein the insulator is a chemical vapor deposition (CVD) film.

26. 22. The semiconductor device according to claim 21, wherein the impurity concentration of said insulator is higher than the impurity concentration of said lower insulating film.

27. 3. The semiconductor device according to claim 1, wherein a corner of the lower end of said upper electrode has a curvature.

28. 3. The semiconductor device according to claim 1, wherein an upper end of said upper electrode is spaced a predetermined distance from an upper surface of said semiconductor substrate.

29. The semiconductor device according to claim 23 , wherein the dummy active trench and the active trench are connected via a trench.

30. 30. The semiconductor device according to claim 29, wherein the active portion is formed inside the trench.

31. 3. The semiconductor device according to claim 1, wherein at least one of said upper insulating film and said boundary insulating film is a chemical vapor deposition (CVD) film.

32. 3. The semiconductor device according to claim 1, wherein at least one of the impurity concentration of said upper insulating film and the impurity concentration of said boundary insulating film is higher than the impurity concentration of said lower insulating film.

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