Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of reducing leakage current.SOLUTION: A semiconductor device 100 comprises: an iridium layer 12B; a lower electrode 12 provided on the iridium layer 12B and comprising a titanium-containing layer 12C, which is a titanium layer, a titanium nitride layer, or a titanium oxide nitride layer; a PZT layer 14 provided on the lower electrode 12; and an upper electrode 16 provided on the PZT layer 14.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Ferroelectric capacitors are known in which a Pb(Zr,Ti)O3 (PZT) layer is provided as a ferroelectric layer between a lower electrode and an upper electrode (see, for example, Patent Documents 1 and 2). When a PZT layer is formed on a lead titanate growth nucleus layer, the PZT layer has a lower Zr concentration near the interface with the lower electrode than in the center. Therefore, in order to improve the Zr concentration in the PZT layer near the interface with the lower electrode, it is known to form a PZT layer on the lower electrode near the electrode, which has a higher Zr concentration than the center (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-207628 [Patent Document 2] Special Publication No. 2002-521848 Summary of the Invention [Problem to be solved by the invention]

[0004] When a lead titanate growth nucleation layer is not used, if an iridium layer is used as the bottom electrode and a PZT layer is formed on the iridium layer, the Zr concentration in the PZT layer near the interface with the bottom electrode becomes higher than the Zr concentration in the center of the PZT layer, which increases the leakage current between the bottom electrode and the top electrode.

[0005] An object of the present disclosure is to provide a semiconductor device capable of reducing leakage current and a method for manufacturing the same. [Means for solving the problem]

[0006] An embodiment of the present disclosure is a ferroelectric capacitor comprising: a lower electrode including an iridium layer; a titanium-containing layer provided on the iridium layer, the titanium layer being a titanium nitride layer or a titanium nitride oxide layer; a PZT layer provided on the lower electrode; and an upper electrode provided on the PZT layer.

[0007] An embodiment of the present disclosure is a ferroelectric capacitor comprising: a lower electrode including a titanium-containing layer which is a titanium layer, a titanium nitride layer, or a titanium nitride oxide layer, and an iridium layer provided on and in contact with the titanium-containing layer; a PZT layer provided on and in contact with the iridium layer; and an upper electrode provided on the PZT layer.

[0008] An embodiment of the present disclosure is a method for manufacturing a semiconductor device, which includes forming a lower electrode including an iridium layer and a titanium-containing layer provided above or below the iridium layer and which is a titanium layer, a titanium nitride layer, or a titanium nitride oxide layer, forming a PZT layer on the lower electrode, the PZT layer having a Zr concentration relative to the sum of Zr and Ti concentrations in a first region provided on the lower electrode that is higher than the Zr concentration relative to the sum of Zr and Ti concentrations in a second region provided on the first region, heat-treating the PZT layer, and forming an upper electrode on the PZT layer. [Effects of the Invention]

[0009] According to the present disclosure, leakage current can be reduced. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view of the ferroelectric capacitor according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of a ferroelectric capacitor according to a comparative example. [Figure 3] FIG. 3 is a diagram showing Zr / (Zr+Ti) of each sample in Experiment 1. [Figure 4] FIG. 4 is a flowchart showing a method for manufacturing the ferroelectric capacitor of the first embodiment. [Figure 5]5(A) and 5(B) are cross-sectional views showing the manufacturing method of the first embodiment. [Figure 6] 6(A) and 6(B) are diagrams showing the cumulative probability distribution of the leakage current in Experiment 2. FIG. [Figure 7] FIG. 7 is a cross-sectional view of a ferroelectric capacitor according to a first modification of the first embodiment. [Figure 8] FIG. 8 is a flowchart showing a method for manufacturing a ferroelectric capacitor according to the first modified example of the first embodiment. [Figure 9] 9(A) and 9(B) are cross-sectional views showing a manufacturing method of a first modified example of the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present disclosure is not limited to the described configurations and numerical values. In each drawing, the same components are given the same reference numerals, and duplicated explanations may be omitted as appropriate. The size, positional relationship, etc. of each component shown in each drawing may be exaggerated to facilitate understanding of the invention.

[0012] (First embodiment) The first embodiment is an example of a ferroelectric capacitor used in a semiconductor device. FIG. 1 is a cross-sectional view of the ferroelectric capacitor according to the first embodiment. As shown in FIG. 1, the ferroelectric capacitor 10C of the first embodiment includes a lower electrode 12, a PZT layer 14 which is a ferroelectric layer, and an upper electrode 16. The lower electrode 12 has a base layer 12A, an iridium (Ir) layer 12B, and a titanium-containing layer 12C. The iridium layer 12B is provided on the base layer 12A, and the titanium-containing layer 12C is provided on the iridium layer 12B. The base layer 12A is, for example, a titanium aluminum nitride (TiAlN) layer. The titanium-containing layer 12C is a titanium (Ti) layer, a titanium nitride (TiN) layer, or a titanium oxynitride (TiON) layer. The base layer 12A may be a film other than the titanium aluminum nitride layer.

[0013] The PZT layer 14 is provided on the lower electrode 12. The PZT layer 14 is a Pb(Zr x ,Ti 1-x )O3 layer. Here, 0 < x < 1. The crystal structure of PZT is a perovskite structure. The general formula of the perovskite structure is ABO3. In PZT, Pb enters the A site, and Zr or Ti enters the B site. The Zr concentration relative to the total of the Zr concentration and the Ti concentration in the PZT layer 14 is Zr / (Zr + Ti). When Zr / (Zr + Ti) is 50%, x = 0.5. The Zr concentration and the Ti concentration are molar concentrations. The upper electrode 16 is provided on the PZT layer 14. The upper electrode 16 has, for example, an iridium oxide (IrO x ) layer and an iridium layer. The iridium oxide layer is provided on the PZT layer 14. The iridium layer is provided on the iridium oxide layer. The upper electrode 16 may be other than the iridium oxide layer and the iridium layer.

[0014] (Comparative form) Fig. 2 is a cross-sectional view of a ferroelectric capacitor according to a comparative embodiment. As shown in Fig. 2, a titanium-containing layer 12C is not provided in a ferroelectric capacitor 10E according to the comparative embodiment. A first region 14A is formed near the interface of the PZT layer 14 with the lower electrode 12. A second region 14B is formed on the first region 14A. The Zr concentration in the first region 14A is higher than the Zr concentration in the second region 14B.

[0015] (Experiment 1) A PZT layer was formed on an iridium layer, and the composition within the PZT layer was measured. The experimental conditions were as follows: A silicon oxide layer was formed on a silicon wafer. An iridium layer was formed on the silicon oxide layer. A PZT layer was formed on the iridium layer using MOCVD (Metal Organic Chemical Vapor Deposition). The flow rate ratio of the raw material gas was set so that Zr / (Zr + Ti) was 40%. Samples with PZT layer thicknesses of 3 nm and 10 nm were fabricated. The deposition conditions for the two samples were the same except for the deposition time. The Zr / (Zr + Ti) ratio within the PZT layer of the two samples was measured using X-ray Photoelectron Spectroscopy (XPS).

[0016] FIG. 3 shows the Zr / (Zr+Ti) ratio for each sample in Experiment 1. The wafer center represents the measurement result for a sample near the center of the silicon wafer, and the wafer periphery represents the measurement result for a sample near the periphery of the silicon wafer. As shown in FIG. 3, for a sample with a PZT layer thickness of 10 nm, Zr / (Zr+Ti) is approximately 40% at both the wafer center and the wafer periphery. In contrast, for a sample with a PZT layer thickness of 3 nm, Zr / (Zr+Ti) is approximately 48% at both the wafer center and the wafer periphery. Thus, when the PZT layer is formed, the first region 14A is Zr-rich at the initial stage of film formation. The thickness of the Zr-rich layer is less than 10 nm, approximately 3 nm. This phenomenon, in which the first region 14A is Zr-rich at the initial stage of film formation when a PZT layer is formed on an iridium layer, is a phenomenon discovered for the first time by the inventors.

[0017] The PZT layer 14 is formed so that Zr / (Zr+Ti) of the entire PZT layer 14 has a desired value. However, in the ferroelectric capacitor according to the comparative example, the first region 14A is richer in Zr than the second region 14B. A Zr-rich film tends to generate a leak path, increasing the leak current of the ferroelectric capacitor 10E. Furthermore, when the first region 14A is rich in Zr, Ir in the iridium layer 12B diffuses into the first region 14A. This is thought to generate a leak path, increasing the leak current of the ferroelectric capacitor 10E.

[0018] (Manufacturing method of the first embodiment) 4 is a flowchart showing a method for manufacturing the ferroelectric capacitor according to the first embodiment. As shown in FIG. 4, an underlayer 12A is formed on an insulating layer such as a silicon oxide layer (step S10). The underlayer 12A is, for example, a titanium aluminum nitride layer, and is formed by sputtering. The thickness of the underlayer 12A is, for example, 10 nm to 100 nm, and is 50 nm as an example.

[0019] Next, an iridium layer 12B is formed on the underlayer 12A (step S11). The iridium layer 12B is formed by, for example, sputtering. The thickness of the iridium layer 12B is, for example, 30 nm to 100 nm, and is, for example, 50 nm. Next, the iridium layer 12B is heat-treated (step S12). The heat treatment is performed in an inert gas atmosphere. The inert gas is, for example, an 18th element gas or nitrogen gas, and is, for example, argon (Ar). The heat treatment temperature is, for example, 500°C to 800°C, and is, for example, 670°C.

[0020] Next, the titanium-containing layer 12C is formed on the iridium layer 12B (step S13). The titanium-containing layer 12C is formed, for example, by sputtering. When forming a titanium layer as the titanium-containing layer 12C, the titanium layer is formed using a titanium target and a sputtering gas such as argon. When forming a titanium nitride layer as the titanium-containing layer 12C, the titanium nitride layer is formed by reactive sputtering using a titanium target and a sputtering gas such as argon mixed with nitrogen gas. Alternatively, the titanium layer is formed and then heat-treated in a nitrogen atmosphere to nitride the titanium layer, thereby forming the titanium nitride layer. The heat treatment temperature in the nitrogen atmosphere is, for example, 600°C to 700°C, e.g., 650°C. When forming a titanium oxynitride layer as the titanium-containing layer 12C, the reactive sputtering method may be used, or the titanium layer may be formed by heat-treating the titanium layer after it has been formed. The thickness of the titanium-containing layer 12C is, for example, 0.1 nm to 10 nm.

[0021] Next, a PZT layer 14 is formed on the titanium-containing layer 12C (step S14). The PZT layer 14 is formed, for example, by MOCVD. The thickness of the PZT layer 14 is, for example, 20 nm to 200 nm, and is, for example, 75 nm. Next, the PZT layer 14 is heat-treated (step S15). The heat treatment is performed in an oxygen atmosphere. The heat treatment temperature is, for example, 600°C to 800°C, and is, for example, 700°C.

[0022] Next, an upper electrode 16 is formed on the PZT layer 14 (step S16). For example, an iridium oxide layer is formed on the PZT layer 14 in an oxygen atmosphere as the upper electrode 16. The iridium oxide layer is formed, for example, by using a sputtering method. The thickness of the iridium oxide layer is, for example, 50 nm to 250 nm, and for example, 150 nm. An iridium layer is formed on the iridium oxide layer. The iridium layer is formed, for example, by using a sputtering method. The thickness of the iridium layer is, for example, 20 nm to 200 nm, and for example, 80 nm.

[0023] 5(A) and 5(B) are cross-sectional views showing the manufacturing method of the first embodiment. Diffusing titanium atoms are schematically illustrated by black circles. As shown in FIG. 5(A), when the PZT layer 14 is formed on the titanium-containing layer 12C in step S14, the first region 14A becomes Zr-rich, with a Zr concentration higher than the target Zr concentration. The second region 14B above the first region 14A has the target Zr concentration.

[0024] As shown in FIG. 5B, when heat treatment is performed in step S15, titanium 15A diffuses from the titanium-containing layer 12C to the first region 14C. This reduces Zr / (Zr+Ti) in the first region 14C. This reduces the likelihood of a leak path occurring in the first region 14C. Furthermore, when titanium 15B diffuses into the grain boundaries of the iridium layer 12B, the diffusion of iridium from the iridium layer 12B to the first region 14C is suppressed. This reduces the likelihood of a leak path occurring in the first region 14C. Furthermore, when titanium 15B diffuses into the grain boundaries of the iridium layer 12B, the diffusion of lead (Pb) in the PZT layer 14 to the iridium layer 12B is suppressed. This also reduces the likelihood of a leak path due to Pb loss in the first region 14C. In this way, the generation of a leak path is suppressed, and the leakage current of the ferroelectric capacitor 10C is reduced.

[0025] (Experiment 2) Ferroelectric capacitors according to the first embodiment and the comparative embodiment were fabricated and their leakage currents were measured under the following fabrication conditions. Underlayer 12A: titanium aluminum nitride layer with a thickness of 50 nm Iridium layer 12B: 50 nm thick Titanium-containing layer 12C: Sample with OTi: None Sample 1nmTi: 1nm titanium layer Sample 3nmTiN: 3nm titanium nitride layer A 1 nm titanium layer was formed by nitriding at 650°C in a nitrogen gas atmosphere. PZT layer 14: thickness 75 nm The film was formed under the condition that Zr / (Zr+Ti) was 40%. Upper electrode 16: 150 nm thick iridium oxide layer, 80 nm thick iridium layer Other manufacturing conditions are the same as those shown as an example in FIG.

[0026] Figures 6(A) and 6(B) are diagrams showing the cumulative probability distribution of leakage current in Experiment 2. Figures 6(A) and 6(B) show the cumulative probability distribution of leakage current in multiple ferroelectric capacitors fabricated in a silicon wafer. Figure 6(A) shows the cumulative probability distribution of leakage current when +1.95 V is applied to the upper electrode 16 relative to the lower electrode 12. Figure 6(B) shows the cumulative probability distribution of leakage current when -1.95 V is applied to the upper electrode 16 relative to the lower electrode 12.

[0027] In both Figures 6(A) and 6(B), the 1-nm TiN and 3-nm Ti samples have smaller leakage currents than the W / O Ti sample. In Figure 7(A), the 3-nm Ti sample has a smaller leakage current than the 1-nm TiN sample. In Figure 7(B), the 3-nm Ti sample has a leakage current similar to that of the 1-nm TiN sample. The difference between the 3-nm Ti and 1-nm TiN samples is thought to be due to differences in thickness or materials.

[0028] According to the first embodiment, the lower electrode 12 includes an iridium layer 12B and a titanium-containing layer 12C (a titanium layer, a titanium nitride layer, or a titanium oxynitride layer) provided on the iridium layer 12B. When a PZT layer 14 is formed on the lower electrode 12, as shown in FIG. 5A, the PZT layer 14 is formed such that the Zr / (Zr+Ti) ratio in the first region 14A provided on the lower electrode 12 is higher than the Zr / (Zr+Ti) ratio in the second region 14B provided on the first region 14A. However, by heat-treating the PZT layer 14, as shown in FIG. 5B, titanium 15A diffuses into the first region 14A and titanium 15B diffuses into the iridium layer 12B. This allows for suppression of leakage current, as shown in FIGS. 6A and 6B.

[0029] If the titanium-containing layer 12C is too thick, it becomes difficult to form the PZT layer 14. From this viewpoint, the thickness of the titanium-containing layer 12C is preferably 10 nm or less, more preferably 8 nm or less, and even more preferably 5 nm or less. From the viewpoint of diffusing titanium into the first region 14A and the iridium layer 12B, the thickness of the titanium-containing layer 12C is preferably 0.1 nm or more, and more preferably 0.5 nm or more.

[0030] The titanium-containing layer 12C is in contact with the iridium layer 12B and the PZT layer 14. This allows titanium to diffuse into the first region 14A and the iridium layer 12B. Furthermore, when a growth nucleus layer is provided between the lower electrode 12 and the PZT layer 14, as in Patent Document 1, the Zr-rich first region 14A is unlikely to be formed. In this way, when the titanium-containing layer 12C is in contact with the PZT layer 14 without providing a growth nucleus layer, it is preferable to provide the titanium-containing layer 12C in order to reduce leakage current.

[0031] When the lower electrode 12 includes a titanium aluminum nitride layer as the underlayer 12A and an iridium layer 12B is provided on the underlayer 12A, the Zr-rich first region 14A is likely to be formed. Therefore, it is preferable to provide the titanium-containing layer 12C. The lower electrode 12 does not necessarily have to include the underlayer 12A.

[0032] (First Modification of the First Embodiment) Fig. 7 is a cross-sectional view of a ferroelectric capacitor according to a first modification of the first embodiment. As shown in Fig. 7, in a ferroelectric capacitor 10D according to the first modification of the first embodiment, a titanium-containing layer 12C is provided on an underlayer 12A, and an iridium layer 12B is provided on the titanium-containing layer 12C. The other configurations are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0033] FIG. 8 is a flowchart showing a method for manufacturing a ferroelectric capacitor according to a first modified example of the first embodiment. As shown in FIG. 8, after forming an underlayer 12A in step S10, a titanium-containing layer 12C is formed on the underlayer 12A. The method for forming the titanium-containing layer 12C is the same as that shown in FIG. 4. When forming a titanium nitride layer or a titanium nitride oxide layer as the titanium-containing layer 12C, a reactive sputtering method may be used, or after forming the titanium layer, the titanium layer may be heat-treated before step S11 to nitride or nitride and oxidize the titanium layer. Then, steps S11 and S12 are performed. In step S14, a PZT layer 14 is formed on the iridium layer 12B. The other steps are the same as those shown in FIG. 4, and therefore will not be described again.

[0034] 9A and 9B are cross-sectional views showing a manufacturing method of a first modified example of the first embodiment. As shown in FIG. 9A, when the PZT layer 14 is formed on the iridium layer 12B in step S14, the first region 14A becomes Zr-rich, that is, the Zr concentration is higher than the target Zr concentration. The second region 14B on the first region 14A has the target Zr concentration.

[0035] As shown in FIG. 9B, when heat treatment is performed in step S15, titanium 15B diffuses from the titanium-containing layer 12C into the iridium layer 12B. Furthermore, some of the titanium 15A diffuses through the iridium layer 12B and into the first region 14C. This reduces Zr / (Zr+Ti) in the first region 14C. This reduces the likelihood of a leak path occurring in the first region 14C. Furthermore, when titanium 15B diffuses into the grain boundaries of the iridium layer 12B, the diffusion of Ir from the iridium layer 12B into the first region 14C is suppressed. This reduces the likelihood of a leak path occurring in the first region 14C. Furthermore, when titanium 15B diffuses into the grain boundaries of the iridium layer 12B, the diffusion of Pb in the PZT layer 14 into the iridium layer 12B is suppressed. This also reduces the likelihood of a leak path occurring in the first region 14C due to lead loss. In this way, the occurrence of a leak path is suppressed, and the leak current of the ferroelectric capacitor 10C is reduced.

[0036] According to the first modification of the first embodiment, the lower electrode 12 includes a titanium-containing layer 12C (a titanium layer, a titanium nitride layer, or a titanium nitride oxide layer) and an iridium layer 12B disposed on and in contact with the titanium-containing layer 12C. The PZT layer 14 is disposed on and in contact with the iridium layer 12B. When the PZT layer 14 is formed on and in contact with the iridium layer 12B, as shown in FIG. 9A, the PZT layer 14 is formed such that the Zr / (Zr+Ti) ratio in the first region 14A disposed on the lower electrode 12 is higher than the Zr / (Zr+Ti) ratio in the second region 14B disposed on the first region 14A. In this case, by heat-treating the PZT layer 14, titanium 15A diffuses into the first region 14A, and titanium 15B diffuses into the iridium layer 12B, as shown in FIG. 9B. This reduces leakage current.

[0037] When the PZT layer 14 is in contact with the iridium layer 12B, a growth nucleus layer is not provided, as in Patent Document 1. This makes it easier for the Zr-rich first region 14A to form. Therefore, it is preferable to provide the titanium-containing layer 12C to reduce leakage current. Furthermore, if another film exists between the titanium-containing layer 12C and the iridium layer 12B, titanium 15B is less likely to diffuse into the iridium layer 12B. Therefore, the iridium layer 12B is in contact with the titanium-containing layer 12C.

[0038] If the iridium layer 12B is too thick, the titanium 15A diffuses through the iridium layer 12B and is less likely to diffuse into the first region 14A. From this viewpoint, the thickness of the iridium layer 12B is preferably 100 nm or less, more preferably 85 nm or less, and even more preferably 70 nm or less. From the viewpoint of preventing oxidation of the titanium-containing layer 12C, the thickness of the iridium layer 12B is preferably 30 nm or more, and more preferably 40 nm or more.

[0039] When the lower electrode 12 includes a titanium aluminum nitride layer as the underlayer 12A and an iridium layer 12B is provided on the underlayer 12A, the Zr-rich first region 14A is likely to be formed. Therefore, it is preferable to provide the titanium-containing layer 12C. The lower electrode 12 does not necessarily have to include the underlayer 12A.

[0040] In the first embodiment and its first modification, the titanium aluminum nitride layer is a conductive layer whose main component is titanium aluminum nitride, and for example, the sum of the N concentration, Ti concentration, and Al concentration is 90 mol% or more, and 95 mol% or more. The iridium layer 12B is a metal layer whose main component is iridium. The titanium layer is a metal layer whose main component is titanium, and for example, the Ti concentration is 90 mol% or more, and 95 mol% or more. The titanium nitride layer is a conductive layer whose main component is titanium nitride, and for example, the sum of the N concentration and Ti concentration is 90 mol% or more, and 95 mol% or more. The titanium nitride oxide layer is a conductive layer whose main component is titanium nitride oxide, and for example, the sum of the N concentration, O concentration, and Ti concentration is 90 mol% or more, and 95 mol% or more.

[0041] The PZT layer 14 is a ferroelectric layer whose main component is PZT, and the sum of the O concentration, Pb concentration, Zr concentration, and Ti concentration is, for example, 91 mol % or more, or 96 mol % or more. The thickness of the first region 14A is, for example, 0.5 nm to 10 nm, and the Zr / (Zr+Ti) of the first region 14A in FIGS. 5A and 9A is, for example, 38% or more and 52% or less. The Zr / (Zr+Ti) of the second region 14B is, for example, 30% or more and 50% or less. The difference in Zr / (Zr+Ti) between the second region 14B and the first region 14A is, for example, 0.1% or more and 3% or more. The Zr / (Zr+Ti) of the first region 14C in Figures 5(B) and 9(B) after the heat treatment is smaller than the Zr / (Zr+Ti) of the first region 14A in Figures 5(A) and 9(A) before the heat treatment. The Zr / (Zr+Ti) of the first region 14C is, for example, 25% or more and 50% or less. The difference in Zr / (Zr+Ti) between the first region 14A before the heat treatment and the first region 14C after the heat treatment is, for example, 0.1% or more and 3% or more.

[0042] (Second embodiment) The second embodiment is an example of a semiconductor device including the ferroelectric capacitor and transistor of the first embodiment and its first modification example. Fig. 10 is a cross-sectional view of the semiconductor device according to the second embodiment.

[0043] 10, the semiconductor device 100 according to the second embodiment includes transistors Tr1 and Tr2, and ferroelectric capacitors 10A and 10B. The ferroelectric capacitor 10A is connected to the transistor Tr1, and the ferroelectric capacitor 10B is connected to the transistor Tr2.

[0044] The semiconductor device 100 includes a semiconductor substrate 18, a p-type well 20, two n-type source regions 25, and an n-type drain region 26. The semiconductor substrate 18 is, for example, a silicon (Si) substrate. An element isolation insulating film 19 is formed in the well 20, and an element active region is defined by the element isolation insulating film 19. The source region 25 and the drain region 26 are provided within the element active region. The source region 25 and the drain region 26 are provided in the surface layer of the well 20, and the drain region 26 is provided between the two source regions 25. One of the source regions 25 is included in transistor Tr1, the other source region 25 is included in transistor Tr2, and the drain region 26 is shared by transistors Tr1 and Tr2. A silicide layer 27 is formed on the upper surface of the source region 25, and a silicide layer 28 is formed on the upper surface of the drain region 26.

[0045] Each of the transistors Tr1 and Tr2 has a gate insulating film 21, a gate electrode 22, a silicide layer 23, a sidewall insulating film 24, a source region 25, and a drain region 26. The gate insulating film 21 is provided on a channel between the source region 25 and the drain region 26, the gate electrode 22 is provided on the gate insulating film 21, and the silicide layer 23 is formed on the upper surface of the gate electrode 22. The sidewall insulating film 24 covers the side surfaces of the stack of the gate insulating film 21, the gate electrode 22, and the silicide layer 23. The gate insulating film 21 and the sidewall insulating film 24 are insulating films such as silicon oxide (SiO2) films. The gate electrode 22 is, for example, a polycrystalline silicon (polysilicon) film. The gate electrode 22 is electrically connected to a word line.

[0046] The semiconductor device 100 has a cover film 31, an interlayer insulating film 32, an etching stopper film 33, an interlayer insulating film 34, an oxidation prevention film 35, and an interlayer insulating film 36. The cover film 31 covers the transistors Tr1 and Tr2. The cover film 31 is an insulating film such as a silicon nitride (SiN) film. The interlayer insulating film 32 is provided on the cover film 31. The interlayer insulating film 32 is an insulating film such as a silicon oxide (SiO2) film. The etching stopper film 33 is provided on the interlayer insulating film 32. The etching stopper film 33 is an insulating film such as a SiN film. The interlayer insulating film 34 is provided on the etching stopper film 33. The interlayer insulating film 34 is an insulating film such as a silicon oxide film. The oxidation prevention film 35 is provided on the interlayer insulating film 34. The oxidation prevention film 35 is an insulating film such as a silicon nitride film. The interlayer insulating film 36 is provided on the oxidation prevention film 35. The interlayer insulating film 36 is an insulating film such as a silicon oxide film.

[0047] The semiconductor device 100 has two conductive plugs 41 and a conductive plug 42. One conductive plug 41 penetrates the interlayer insulating film 32 and the cover film 31, contacts the silicide layer 27 of the transistor Tr1, and is electrically connected to the source region 25 of the transistor Tr1. The other conductive plug 41 penetrates the interlayer insulating film 32 and the cover film 31, contacts the silicide layer 27 of the transistor Tr2, and is electrically connected to the source region 25 of the transistor Tr2. The conductive plug 42 penetrates the interlayer insulating film 32 and the cover film 31, contacts the silicide layer 28, and is electrically connected to the drain region 26. The conductive plugs 41 and 42 have a conductive film such as a tungsten film.

[0048] The semiconductor device 100 includes a wiring 43 and two conductive plugs 44. The wiring 43 penetrates the interlayer insulating film 34 and the etching stopper film 33, contacts the conductive plug 42, and is electrically connected to the drain region 26. The wiring 43 is covered with an oxidation suppression film 35. One conductive plug 44 penetrates the interlayer insulating film 36, the oxidation suppression film 35, the interlayer insulating film 34, and the etching stopper film 33, contacts one conductive plug 41, and is electrically connected to the source region 25 of the transistor Tr1. The other conductive plug 44 penetrates the interlayer insulating film 36, the oxidation suppression film 35, the interlayer insulating film 34, and the etching stopper film 33, contacts the other conductive plug 41, and is electrically connected to the source region 25 of the transistor Tr2. The wiring 43 and the conductive plugs 44 include a conductive film such as a tungsten film. The wiring 43 is used as a bit line.

[0049] The ferroelectric capacitors 10A and 10B each have a lower electrode 12, a PZT layer 14, and an upper electrode 16. The ferroelectric capacitors 10A and 10B are the ferroelectric capacitors 10C and 10D of the first embodiment or the first modified example of the first embodiment.

[0050] The lower electrode 12 of the ferroelectric capacitor 10A contacts one of the conductive plugs 44 and is electrically connected to the source region 25 of the transistor Tr1. The lower electrode 12 of the ferroelectric capacitor 10B contacts one of the conductive plugs 44 and is electrically connected to the source region 25 of the transistor Tr2.

[0051] The semiconductor device 100 includes a cover film 48, an interlayer insulating film 37, an interlayer insulating film 38, a conductive plug 45, and a wiring 46. The cover film 48 covers the ferroelectric capacitors 10A and 10B. The cover film 48 is an insulating film such as a silicon nitride film. The interlayer insulating film 37 is provided on the cover film 31. The interlayer insulating film 38 is provided on the interlayer insulating film 37. The interlayer insulating films 37 and 38 are insulating films such as silicon oxide films. One conductive plug 45 penetrates the interlayer insulating film 37 and the cover film 48 and is electrically connected to the upper electrode 16 of the ferroelectric capacitor 10A. The other conductive plug 45 penetrates the interlayer insulating film 37 and the cover film 48 and is electrically connected to the upper electrode 16 of the ferroelectric capacitor 10B. The wiring 46 is in contact with the conductive plug 45 and is electrically connected to the upper electrodes 16 of the ferroelectric capacitors 10A and 10B. The wiring 46 and the conductive plug 45 include a conductive film such as a tungsten film. The wiring 46 is used as a plate line.

[0052] The semiconductor device 100 of the second embodiment is, for example, a ferroelectric memory. In this way, the ferroelectric capacitor 10C or 10D of the first embodiment and its first modification may be used in the semiconductor memory device. This makes it possible to suppress leakage current in the semiconductor device 100.

[0053] Although the present disclosure has been described above based on the embodiments, the present invention is not limited to the requirements set forth in the above embodiments. These requirements can be changed without departing from the spirit of the present disclosure, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0054] 10A, 10B, 10C, 10D, 10E: Ferroelectric capacitors 12: Lower electrode 12A: Base layer 12B: Iridium layer 12C: Titanium-containing layer 14:PZT layer 14A: 1st area 14B:Second area 16:Top electrode 18: Semiconductor substrate

Claims

1. a lower electrode including an iridium layer and a titanium-containing layer disposed on the iridium layer, the titanium layer being a titanium nitride layer or a titanium nitride oxide layer; a PZT layer provided on the lower electrode; an upper electrode provided on the PZT layer; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the titanium-containing layer has a thickness of 10 nm or less.

3. 3. The semiconductor device according to claim 1, wherein the titanium-containing layer is in contact with the iridium layer and the PZT layer.

4. 3. The semiconductor device according to claim 1, wherein said lower electrode includes a titanium aluminum nitride layer, and said titanium-containing layer is provided on said titanium aluminum nitride layer.

5. a lower electrode including a titanium-containing layer, which is a titanium layer, a titanium nitride layer, or a titanium nitride oxide layer, and an iridium layer provided on and in contact with the titanium-containing layer; a PZT layer provided on and in contact with the iridium layer; an upper electrode provided on the PZT layer; A semiconductor device comprising:

6. 6. The semiconductor device according to claim 5, wherein the iridium layer has a thickness of 100 nm or less.

7. 7. The semiconductor device according to claim 5, wherein said lower electrode includes a titanium aluminum nitride layer, and said iridium layer is provided on said titanium aluminum nitride layer.

8. forming a lower electrode including an iridium layer and a titanium-containing layer, which is a titanium layer, a titanium nitride layer, or a titanium oxynitride layer, provided above or below the iridium layer; forming a PZT layer on the lower electrode, the Zr concentration relative to the total of the Zr concentration and the Ti concentration in a first region provided on the lower electrode being higher than the Zr concentration relative to the total of the Zr concentration and the Ti concentration in a second region provided on the first region; heat treating the PZT layer; forming a top electrode on the PZT layer; A method for manufacturing a semiconductor device.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein a Zr concentration relative to a sum of a Zr concentration and a Ti concentration in the first region after the heat treatment is lower than a Zr concentration relative to a sum of a Zr concentration and a Ti concentration in the first region before the heat treatment.

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