Mask assembly, apparatus for manufacturing display device, and method for manufacturing display device

Abstract

To provide a display device, a mask assembly, an apparatus for manufacturing the display device, and a method for manufacturing the display device.SOLUTION: There are provided a display device, a mask assembly, an apparatus for manufacturing the display device, and a method for manufacturing the display device. The display device comprises: a substrate including a component area, a main display area, and a peripheral area inside which the component area and the main display area are arranged; an auxiliary pixel group disposed in the component area and including an auxiliary subpixel pixel electrode, an auxiliary subpixel intermediate layer and an auxiliary subpixel opposite electrode; and a main pixel group disposed in the main display area and including a main subpixel pixel electrode, a main subpixel intermediate layer, and a main subpixel opposite electrode. The auxiliary subpixel opposite electrode extends across the component area, is connected to the main subpixel opposite electrode on the main display area, and has a stripe shape.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an apparatus and a method, and more particularly to a display device, a mask assembly, a display device manufacturing apparatus, and a display device manufacturing method. [Background technology]

[0002] Mobile electronic devices are widely used. In addition to small electronic devices such as mobile phones, tablet personal computers (PCs) have recently become widely used as mobile electronic devices.

[0003] Such mobile electronic devices include a display device to provide a user with visual information such as an image or video to support various functions. Recently, as other components for driving the display device have become smaller, the proportion of the display device in the electronic device has gradually increased, and structures that can be bent from a flat state to a predetermined angle have also been developed.

[0004] The display device as described above includes various components disposed on the underside of the display panel. In this case, the display panel may have a region with a different resolution than the other regions where the components are disposed. In such a case, a transmissive region is disposed in the region with a different resolution, and it is necessary to maximize the transmissive region to avoid interfering with the operation of the components. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6117881 Specification Summary of the Invention [Problem to be solved by the invention]

[0006] In order to improve the resolution of a display device and accurately form a transmissive region, it is necessary to form a precise pattern on some of multiple layers during manufacturing of the display device. Embodiments of the present invention provide a display device having a precise pattern, a mask assembly capable of manufacturing a display device having a precise pattern, an apparatus for manufacturing a display device, and a method for manufacturing a display device. [Means for solving the problem]

[0007] One embodiment of the present invention discloses a display device including: a substrate including a component region, a main display region, and a peripheral region in which the component region and the main display region are disposed; an auxiliary pixel group disposed in the component region, the auxiliary pixel group including an auxiliary subpixel pixel electrode, an auxiliary subpixel intermediate layer, and an auxiliary subpixel counter electrode; and a main pixel group disposed in the main display region, the main pixel group including a main subpixel pixel electrode, a main subpixel intermediate layer, and a main subpixel counter electrode, the auxiliary subpixel counter electrode being striped and extending across the component region and connected to the main subpixel counter electrode on the main display region.

[0008] In this embodiment, a plurality of the auxiliary sub-pixel counter electrodes may be arranged in the component region so as to be spaced apart from each other.

[0009] In this embodiment, the auxiliary sub-pixel pixel electrodes and the auxiliary sub-pixel intermediate layers are provided in plural, and the auxiliary sub-pixel pixel electrodes and the auxiliary sub-pixel intermediate layers are arranged to be spaced apart from each other along the longitudinal direction of the auxiliary sub-pixel counter electrode.

[0010] In this embodiment, the component region is also connected to the periphery of the peripheral region.

[0011] In this embodiment, the substrate may include a transmissive region disposed within the component region.

[0012] In this embodiment, the width of the auxiliary sub-pixel counter electrode is wider than the distance between the adjacent auxiliary sub-pixel counter electrodes.

[0013] Another embodiment of the present invention discloses a mask assembly including a mask frame including a frame opening, and a mask sheet disposed on the mask frame, the mask sheet including a sheet body portion including at least one first opening disposed to correspond to the frame opening, and a sheet blocking portion connected to the sheet body portion, disposed inside the first opening, and including a slit-shaped second opening.

[0014] In this embodiment, the sheet blocking portion is also connected to the sheet body portion at the periphery of the first opening.

[0015] In an embodiment, the mask sheet may further include a sheet connecting member that connects the sheet body portion and the sheet blocking portion.

[0016] In this embodiment, the second openings are provided in multiple numbers, the sheet blocking portion includes a sheet blocking rib arranged between adjacent second openings, and the width of the second openings is wider than the width of the sheet blocking rib.

[0017] Yet another embodiment of the present invention discloses a mask assembly including: a mask frame including a frame opening; and sticks arranged in one of a first direction and a second direction and disposed on the mask frame, dividing the frame opening into at least two or more sections, the sticks including: a stick body portion disposed on the mask frame; and a stick blocking portion connected to the stick body portion and disposed inside the frame opening, the stick blocking portion including the stick opening.

[0018] In this embodiment, the stick blocking part may be directly connected to the stick body part.

[0019] In this embodiment, the stick may further include a stick connecting member connecting the stick body portion and the stick blocking portion.

[0020] In this embodiment, the stick opening may be in the form of a slit.

[0021] In this embodiment, a plurality of stick openings are provided, the stick blocking portion includes a stick blocking rib disposed between adjacent stick openings, and the width of the stick opening is wider than the width of the stick blocking rib.

[0022] Yet another embodiment of the present invention discloses an apparatus for manufacturing a display device, including: a chamber in which a substrate can be placed; a mask assembly disposed inside the chamber facing the substrate; and a deposition source disposed inside the chamber facing the mask assembly and supplying a deposition material to the substrate, wherein the mask assembly includes a mask frame including a frame opening; and a mask sheet disposed on the mask frame, the mask sheet including: a sheet body portion including at least one first opening disposed to correspond to the frame opening; and a sheet blocking portion connected to the sheet body portion, disposed inside the first opening, and including a slit-shaped second opening.

[0023] In this embodiment, the sheet blocking portion is also connected to the sheet body portion at the periphery of the first opening.

[0024] In this embodiment, the mask sheet may further include a sheet connecting member connecting the sheet body portion and the sheet blocking portion.

[0025] In this embodiment, the second openings are provided in multiple numbers, the sheet blocking portion includes a sheet blocking rib arranged between adjacent second openings, and the width of the second openings is wider than the width of the sheet blocking rib.

[0026] Yet another embodiment of the present invention discloses an apparatus for manufacturing a display device, comprising: a chamber in which a substrate can be placed; a mask assembly disposed within the chamber to face the substrate; and a deposition source disposed within the chamber to face the mask assembly and supplying a deposition material to the substrate, wherein the mask assembly comprises a mask frame including a frame opening; and sticks disposed in the mask frame and arranged in one of a first direction and a second direction, the sticks dividing the frame opening into at least two or more sections, the sticks comprising: a stick body portion disposed in the mask frame; and a stick blocking portion connected to the stick body portion, disposed within the frame opening, and including the stick opening.

[0027] In this embodiment, the stick blocking part may be directly connected to the stick body part.

[0028] In this embodiment, the stick may further include a stick connecting member connecting the stick body portion and the stick blocking portion.

[0029] In this embodiment, the stick opening may be in the form of a slit.

[0030] In this embodiment, a plurality of stick openings are provided, the stick blocking portion includes a stick blocking rib disposed between adjacent stick openings, and the width of the stick opening is wider than the width of the stick blocking rib.

[0031] In this embodiment, a method for manufacturing a display device is disclosed, the method including the steps of forming an auxiliary sub-pixel pixel electrode in a component region of a substrate and forming a main sub-pixel pixel electrode in a main display region of the substrate; forming an auxiliary sub-pixel intermediate layer on the auxiliary sub-pixel pixel electrode in the component region and forming a main sub-pixel intermediate layer on the main sub-pixel pixel electrode in the main display region; forming an auxiliary sub-pixel counter electrode on the auxiliary sub-pixel intermediate layer and forming a main sub-pixel counter electrode in the main sub-pixel intermediate layer, wherein the auxiliary sub-pixel counter electrode is connected to the main sub-pixel counter electrode.

[0032] In this embodiment, the auxiliary sub-pixel counter electrodes are striped and are also disposed in the component regions.

[0033] In this embodiment, the substrate includes a peripheral region surrounding the component region and the main display region, and the auxiliary sub-pixel counter electrode is also connected to the edge of the peripheral region.

[0034] In this embodiment, the width of the auxiliary sub-pixel counter electrode is wider than the distance between the adjacent auxiliary sub-pixel counter electrodes.

[0035] Yet another embodiment of the present invention discloses a method for manufacturing a mask assembly, including the steps of: placing a base material; removing the remaining portion of the base material except for a frame of the base material and a portion of the base material protruding from the frame of the base material to form a sheet body portion, a sheet blocking portion protruding from the sheet body portion, and at least one first opening on the sheet body portion; and forming striped second openings in the sheet blocking portion to manufacture a mask sheet.

[0036] In this embodiment, the second opening can be formed by irradiating the sheet blocking portion with a laser and removing a part of the sheet blocking portion.

[0037] In this embodiment, a plurality of the second openings are provided, and the width of each of the second openings is narrower than the width between adjacent second openings.

[0038] In this embodiment, the method may further include the steps of: arranging a mask frame having a frame opening; and stretching the mask sheet to accommodate the mask frame.

[0039] Yet another embodiment of the present invention discloses a method for manufacturing a display device, including the steps of manufacturing a stick body portion on a base material and a stick blocking portion protruding from the stick body portion, and irradiating a laser onto the stick blocking portion to form at least one stick opening, thereby manufacturing a stick.

[0040] In this embodiment, the method may further include the steps of manufacturing a mask frame including a frame opening, placing the stick in the mask frame so that it crosses the frame opening, and fixing the stick to the mask frame.

[0041] In this embodiment, the stick opening may be striped.

[0042] Other aspects, features, and advantages of the present invention will become apparent from the following drawings, claims, and detailed description of the invention.

[0043] Such general and specific aspects may be implemented using a system, a method, a computer program, or any combination of systems, methods, and computer programs. [Effects of the Invention]

[0044] A display device according to an embodiment of the present invention can achieve high resolution.

[0045] Furthermore, the display device according to the embodiment of the present invention can also display an image in an area where an electronic component is placed.

[0046] Furthermore, the mask assembly according to the embodiment of the present invention can form a precise pattern during a deposition process.

[0047] Furthermore, the display device manufacturing apparatus and the display device manufacturing method according to the embodiment of the present invention are capable of manufacturing a display device having a precise pattern. [Brief explanation of the drawings]

[0048] [Figure 1] 1 is a perspective view illustrating a display device according to an embodiment. [Figure 2] 1 is an exploded perspective view showing a display device according to an embodiment; [Figure 3] FIG. 1 is a plan view illustrating a display panel according to an embodiment. [Figure 4] 4 is a side view showing an example of the display panel of FIG. 3. FIG. [Figure 5] FIG. 1 is a plan view illustrating a display panel according to an embodiment. [Figure 6] 6 is a side view showing an example of the display panel of FIG. 5. FIG. [Figure 7A] 1 is a cross-sectional view schematically illustrating a portion of a display device according to an embodiment. [Figure 7B] 1 is a cross-sectional view schematically illustrating a portion of a display device according to an embodiment. [Figure 8] FIG. 1 is a plan view schematically illustrating a display panel according to an embodiment. [Figure 9A] FIG. 2 is an equivalent circuit diagram of a pixel circuit for driving a sub-pixel according to one embodiment. [Figure 9B] FIG. 2 is an equivalent circuit diagram of a pixel circuit for driving a sub-pixel according to one embodiment. [Figure 10] 1 is a layout diagram that schematically illustrates a pixel layout structure in a main display area of ​​a display panel according to one embodiment. [Figure 11A] 1 is a layout diagram that schematically illustrates a pixel layout structure in a component area of ​​a display panel, according to one embodiment. [Figure 11B]1 is a layout diagram that schematically illustrates a pixel layout structure in a component area of ​​a display panel, according to one embodiment. [Figure 11C] 1 is a layout diagram that schematically illustrates a pixel layout structure in a component area of ​​a display panel, according to one embodiment. [Figure 12] 1 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment. [Figure 13] 1 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment. [Figure 14] 1 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment. [Figure 15] 1 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment. [Figure 16A] 1 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment. [Figure 16B] 1 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment. [Figure 16C] 1 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment. [Figure 17] 1 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment. [Figure 18] 1 is a cross-sectional view showing a display device manufacturing apparatus according to an embodiment of the present invention. [Figure 19] 1 is a perspective view of a mask assembly according to one embodiment of the present invention; [Figure 20A] 20A to 20C are plan views showing a method for manufacturing the mask sheet shown in FIG. 19. [Figure 20B] 20A to 20C are plan views showing a method for manufacturing the mask sheet shown in FIG. 19. [Figure 20C] 20A to 20C are plan views showing a method for manufacturing the mask sheet shown in FIG. 19. [Figure 20D] FIG. 20D is a cross-sectional view taken along line AA' in FIG. 20C. [Figure 21] FIG. 10 is a perspective view showing a mask assembly according to another embodiment of the present invention. [Figure 22A]22A to 22C are plan views showing a method for manufacturing the stick shown in FIG. 21. [Figure 22B] 22A to 22C are plan views showing a method for manufacturing the stick shown in FIG. 21. [Figure 22C] FIG. 22C is a cross-sectional view taken along line BB' of FIG. 22B. [Figure 23A] 1A-1C are plan views that schematically illustrate a method for patterning a counter electrode, according to one embodiment. [Figure 23B] FIG. 23B is an enlarged plan view of a portion AI of FIG. 23A. [Figure 24] FIG. 10 is a plan view showing a sheet blocking unit according to another embodiment of the present invention. [Figure 25] 10 is a plan view showing a stick blocking unit according to still another embodiment of the present invention; FIG. [Figure 26] 10 is a plan view showing a first stick blocking unit according to still another embodiment of the present invention. FIG. [Figure 27] 10 is a plan view showing a first stick blocking unit according to still another embodiment of the present invention. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0049] The present invention can be modified in various ways and can have various embodiments, but specific embodiments are illustrated in the drawings and will be described in detail in the detailed description. The advantages, features, and methods of achieving the same of the present invention will become clearer with reference to the embodiments described in detail below together with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in various forms.

[0050] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be denoted by the same reference numerals, and duplicate descriptions thereof will be omitted.

[0051] In the following embodiments, terms such as first and second are not used in a limiting sense but are used to distinguish one component from another.

[0052] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0053] In the following embodiments, the terms "comprise" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0054] In the following embodiments, when a part such as a film, region, or component is said to be on or above another part, this does not only mean that it is directly on top of the other part, but also means that there is another film, region, component, etc. interposed between them.

[0055] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience of explanation. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience of explanation, and the present invention is not necessarily limited to what is shown in the drawings.

[0056] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes on a Cartesian coordinate system, but are broadly interpreted as including the three axes. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may not be perpendicular to each other and point in different directions.

[0057] It should be understood that certain embodiments may be implemented differently, and that the order of certain steps may be performed differently than that described. For example, two steps described as successive may be performed substantially simultaneously, or may be performed in the reverse order of that described.

[0058] 1 and 2 are perspective and exploded views of a display device according to an embodiment of the present invention.

[0059] 1 and 2, a display device 1 according to an embodiment is a device for displaying moving and still images and is used not only in portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs), but also as display screens for various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT). The display device 1 according to an embodiment can also be used in wearable devices such as smart watches, watch phones, eyeglass displays, and head-mounted displays (HMDs). The display device 1 according to an embodiment can also be used in automobile dashboards, center information displays (CIDs) located in the center fascia or dashboard of automobiles, room mirror displays that replace automobile side mirrors, and displays located behind the front seats for rear-seat entertainment in automobiles.

[0060] 1 and 2, for convenience of explanation, a display device 1 according to an embodiment is illustrated as being used in a smartphone. The display device 1 according to the embodiment includes a cover window 50, a display panel 10, a display circuit board 30, a display driver 32, a touch sensor driver 33, a bracket 60, a main circuit board 70, a battery 80, and a bottom cover 90.

[0061] In this specification, "upper" refers to the direction in which the cover window 50 is disposed relative to the display panel 10, i.e., the +z direction, and "lower" refers to the direction in which the lower cover 90 is disposed relative to the display panel 10, i.e., the -z direction. Additionally, "left," "right," "up," and "down" refer to directions in a plan view relative to the display panel 10. For example, "left" refers to the -x direction, "right" refers to the +x direction, "up" refers to the +y direction, and "down" refers to the -y direction.

[0062] The display device 1 may have a rectangular shape in a plan view. For example, as shown in FIG. 1, the display device 1 may have a rectangular planar shape having a short side in a first direction (x direction) and a long side in a second direction (y direction). The corner where the short side in the first direction (x direction) and the long side in the second direction (y direction) meet may be rounded to have a predetermined curvature or may be formed at a right angle. The planar shape of the display device 1 is not limited to a rectangle, and may also be formed in other polygonal, elliptical, or irregular shapes.

[0063] The cover window 50 is also disposed on the upper part of the display panel 10 so as to cover the upper surface of the display panel 10. Thus, the cover window 50 can function to protect the upper surface of the display panel 10.

[0064] The cover window 50 may include a transparent cover portion DA50 corresponding to the display panel 10 and a light-shielding cover portion NDA50 corresponding to an area other than the display panel 10. The light-shielding cover portion NDA50 may include an opaque material that blocks light. The light-shielding cover portion NDA50 may include a pattern that can be seen by the user when no image is displayed.

[0065] The display panel 10 is also disposed below the cover window 50. The display panel 10 also overlaps with the transparent cover portion DA50 of the cover window 50.

[0066] The display panel 10 includes a main display area MDA and a component area CA. Both the main display area MDA and the component area CA are areas where images are displayed, and the component area CA may be an area below which components 40, such as sensors or cameras that use visible light, infrared light, or sound, are disposed. In one embodiment, the component area CA may have a higher light transmittance and / or sound transmittance than the main display area MDA. In one embodiment, when light is transmitted through the component area CA, the light transmittance may be approximately 25% or more, 30% or more, and more preferably 50% or more, 75% or more, 80% or more, 85% or more, or 90% or more.

[0067] The display panel 10 may be a light-emitting display panel including light-emitting elements. For example, the display panel 10 may be an organic light-emitting display panel using organic light-emitting diodes including an organic light-emitting layer, a micro-light-emitting diode display panel using micro LEDs, a quantum dot light-emitting display panel using quantum dot light-emitting diodes including a quantum dot light-emitting layer, or an inorganic light-emitting display panel using inorganic light-emitting elements including inorganic semiconductors.

[0068] The display panel 10 may be a rigid display panel that is stiff and does not bend easily, or a flexible display panel that is flexible and can be easily bent, folded, or rolled. For example, the display panel 10 may be a foldable display panel that can be folded and unfolded, a curved display panel whose display surface is curved, a bent display panel whose area other than the display surface is curved, a rollable display panel that can be rolled or unfolded, or a stretchable display panel.

[0069] The display panel 10 may be a transparent display panel that is embodied transparently, allowing objects or backgrounds arranged on the lower surface of the display panel 10 to be seen from the upper surface of the display panel 10. Alternatively, the display panel 10 may be a reflective display panel that can reflect objects or backgrounds arranged on the upper surface of the display panel 10.

[0070] A first flexible film 34 may be attached to one side edge of the display panel 10. One side of the first flexible film 34 may be an anisotropic conductive film and may also be attached to one side edge of the display panel 10. The first flexible film 34 may be a flexible film that can be bent.

[0071] The display driver 32 is also disposed on the first flexible film 34. The display driver 32 receives a control signal and a power supply voltage, and is capable of generating and outputting a signal and voltage for driving the display panel 10. The display driver 32 is also formed by an integrated circuit (IC).

[0072] The display circuit board 30 is also attached to the other side of the first flexible film 34. The other side of the first flexible film 34 is also attached to the top surface of the display circuit board 30 using an anisotropic conductive film. The display circuit board 30 may be a flexible printed circuit board (FPCB), which can be bent, a rigid printed circuit board (rigid PCB), or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board.

[0073] A touch sensor driver 33 may be disposed on the display circuit board 30. The touch sensor driver 33 may also be formed by an integrated circuit. The touch sensor driver 33 is also attached to the display circuit board 30. The touch sensor driver 33 is also electrically connected to the touch electrodes of the touch screen layer of the display panel 10 via the display circuit board 30.

[0074] The touchscreen layer of the display panel 10 can sense a user's touch input using at least one of various touch methods, such as a resistive method or a capacitive method. For example, if the touchscreen layer of the display panel 10 senses a user's touch input using a capacitive method, the touch sensor driver 33 applies a drive signal to a drive electrode among the touch electrodes and detects a voltage charged in a mutual capacitance (hereinafter referred to as "mutual capacitance") between the drive electrode and the sense electrode through the sense electrode among the touch electrodes, thereby determining whether or not a user's touch has occurred. The user's touch may include a contact touch and a proximity touch. The contact touch indicates that an object, such as a user's finger or a pen, directly contacts the cover window 50 disposed on the touchscreen layer. The proximity touch indicates that the user's finger or an object, such as a pen, is positioned at a distance from the cover window 50, such as hovering. The touch sensor driver 33 transmits sensor data to the main processor 710 according to the sensed voltage, and the main processor 710 can calculate touch coordinates where a touch input occurs by analyzing the sensor data.

[0075] A power supply unit may be additionally disposed on the display circuit board 30 to supply driving voltages for driving the pixels of the display panel 10, the scan driver, and the display driver 32. Alternatively, the power supply unit may be integrated with the display driver 32, in which case the display driver 32 and the power supply unit may be formed as a single integrated circuit.

[0076] A bracket 60 for supporting the display panel 10 may be disposed below the display panel 10. The bracket 60 may be made of plastic, metal, or both plastic and metal. The bracket 60 may be formed with a first camera hole CMH1 into which the camera device 731 is inserted, a battery hole BH into which the battery 80 is disposed, and a cable hole CAH through which the cable 35 connected to the display circuit board 30 passes. The bracket 60 may also be formed with a component hole CPH overlapping the component area CA of the display panel 10. The component hole CPH may overlap the component 40 of the main circuit board 70 in the third direction (z direction). As a result, the component area CA of the display panel 10 may overlap the component 40 of the main circuit board 70 in the third direction (z direction). Alternatively, the bracket 60 may not be formed with the component hole CPH, in which case the bracket 60 may be positioned so as not to overlap the component area CA of the display panel 10 in the third direction (z direction).

[0077] The component 40 overlapping the component area CA of the display panel 10 may be multiple. For example, a first component 41 to a fourth component 44 may be arranged to overlap the component area CA. The first component 41 to the fourth component 44 may also be arranged as a proximity sensor, an illuminance sensor, an iris sensor, and a camera (or image sensor), respectively. The component area CA of the display panel 10 may have a predetermined light transmittance. The proximity sensor using infrared rays can detect an object arranged in proximity to the upper surface of the display device 1, and the illuminance sensor can sense the brightness of light incident on the upper surface of the display device 1. The iris sensor can capture the iris of a person arranged on the upper surface of the display device 1, and the camera can capture an object arranged on the upper surface of the display device 1. The component 40 arranged to overlap the component area CA of the display panel 10 is not limited to a proximity sensor, an illuminance sensor, an iris sensor, and a camera, and various sensors described below may be arranged.

[0078] A main circuit board 70 and a battery 80 may be disposed below the bracket 60. The main circuit board 70 may be a printed circuit board or a flexible printed circuit board.

[0079] The main circuit board 70 may include a main processor 710, a camera device 731, a main connector 75, and components 40. The main processor 710 may also be formed by an integrated circuit. The camera device 731 is disposed on both the top and bottom surfaces of the main circuit board 70, and the main processor 710 and the main connector 75 are also disposed on either the top or bottom surface of the main circuit board 70.

[0080] The main processor 710 can control all functions of the display device 1. For example, the main processor 710 can output digital video data to the display driver 32 via the display circuit board 30 so that the display panel 10 displays an image. The main processor 710 also receives sensed data from the touch sensor driver 33. The main processor 710 can determine whether a user has touched the display panel 10 based on the sensed data and perform an operation corresponding to the user's direct touch or proximity touch. For example, the main processor 710 can analyze the sensed data, calculate the coordinates of the user's touch, and then execute an application or an operation indicated by the icon touched by the user. The main processor 710 may be an application processor, a central processing unit, or a system chip implemented by an integrated circuit.

[0081] In camera mode, the camera device 731 processes image frames, such as still or moving images, obtained by an image sensor and outputs them to the main processor 710. The camera device 731 may include at least one of a camera sensor (e.g., a charge coupled device (CCD), a complementary metal oxide semiconductor (CMOS), etc.), a photosensor (or an image sensor), and a laser sensor. The camera device 731 is connected to the image sensor of the component 40 overlapping the component area CA, and can process the image input to the image sensor.

[0082] The cable 35 that passes through the cable hole CAH of the bracket 60 is connected to the main connector 75 , thereby electrically connecting the main circuit board 70 to the display circuit board 30 as well.

[0083] In addition to the main processor 710, the camera device 731, and the main connector 75, the main circuit board 70 may further include at least one wireless communication unit, at least one input unit, at least one sensor unit, at least one output unit, at least one interface unit, memory, and a power supply unit.

[0084] The wireless communication unit may include at least one of a broadcast receiving module, a mobile communication module, a wireless Internet module, a short-range communication module, and a location information module.

[0085] The broadcast receiving module receives broadcast signals and / or broadcast-related information from an external broadcast management server via broadcast channels, which may include satellite channels and terrestrial channels.

[0086] The mobile communication module transmits and receives wireless signals to and from at least one of a base station, an external terminal, and a server on a mobile communication network established in accordance with a technical standard or communication method for mobile communication (e.g., GSM (global system for mobile communication), CDMA (code division multiple access), CDMA2000 (code division multi access 2000), EV-DO (enhanced voice-data optimized or enhanced voice-data only), WCDMA (wideband CDMA, HSDPA (high speed downlink packet access), HSUPA (high speed uplink packet access), LTE (long term evolution), LTE-A (long term evolution-advanced), etc.). The wireless signals may include various types of data such as voice call signals, video call signals, or text / multimedia message transmission / reception.

[0087] The wireless Internet module refers to a module for wireless Internet connection, and is configured to transmit and receive wireless signals in a communication network using wireless Internet technologies, such as WLAN (wireless local area network), Wi-Fi (wireless fidelity), Wi-Fi Direct, and DLNA (Digital Living Network Alliance).

[0088] The short-range communication module is for short-range communication and can support short-range communication using at least one of Bluetooth (registered trademark), RFID (radio frequency identification), IrDA (infrared data association), UWB (ultra-wideband), ZigBee (registered trademark), NFC (near field communication), Wi-Fi, Wi-Fi Direct, and wireless universal serial bus (wireless USB). The short-range communication module can support wireless communication between the display device 1 and a wireless communication system, between the display device 1 and another electronic device, or between the display device 1 and a network in which the other electronic device (or an external server) is located, via a short-range wireless communication network. The short-range wireless communication network may be a wireless personal area network. The other electronic device may be a wearable device that can exchange data with (or be linked to) the display device 1.

[0089] The location information module is a module for acquiring the location (or current location) of the display device 1, and typical examples thereof include a GPS (global positioning system) module or a Wi-Fi module. For example, if the display device 1 utilizes a GPS module, it can acquire the location of the display device 1 using signals sent from GPS satellites. Furthermore, if the display device 1 utilizes a Wi-Fi module, it can acquire the location of the display device 1 based on information from the Wi-Fi module and a wireless AP (wireless access point) that transmits or receives wireless signals. The location information module is a module used to acquire the location (or current location) of the display device 1, and is not limited to a module that directly calculates or acquires the location of the display device 1.

[0090] The input unit may include a video input unit such as a camera device 731 for inputting a video signal, an audio input unit such as a microphone for inputting an audio signal, and an input device (not shown) for inputting information from the user.

[0091] The camera device 731 processes image frames, such as still or moving images, acquired by an image sensor in a video call mode or a photography mode, and the processed image frames are displayed on the display panel 10 or stored in a memory.

[0092] The microphone processes an external acoustic signal into electrical audio data, and the processed audio data can be used in various ways depending on the function (or application) currently running in the display device 1. Meanwhile, the microphone can be implemented with various noise reduction algorithms to remove noise generated during the process of inputting the external acoustic signal.

[0093] The main processor 710 can control the operation of the display device 1 in response to information input via an input device. The input device may include mechanical input means or touch input means, such as buttons, dome switches, jog wheels, and jog switches, located on the rear or side of the display device 1. The touch input means may also be formed from a touchscreen layer of the display panel 10.

[0094] The sensor unit may include one or more sensors that sense at least one of information within the display device 1, information about the environment surrounding the display device 1, and user information, and generate a corresponding sensing signal. Based on such sensing signals, the main processor 710 can control the driving or operation of the display device 1, or perform data processing, functions, or operations related to applications installed on the display device 1. The sensor unit may include at least one of a proximity sensor, an illumination sensor, an acceleration sensor, a magnetic sensor, a gravity sensor (G-sensor), a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor), a finger scan sensor, an ultrasonic sensor, an optical sensor, a battery gauge, an environmental sensor (e.g., a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, a gas detection sensor, etc.), and a chemical sensor (e.g., an electronic nose, a healthcare sensor, a biometric recognition sensor, etc.).

[0095] The proximity sensor is a sensor that detects the presence or absence of an object approaching or nearby a predetermined detection surface without mechanical contact by using electronic force or infrared rays. Examples of proximity sensors include a transmission-type photoelectric sensor, a direct reflection-type photoelectric sensor, a mirror reflection-type photoelectric sensor, a high-frequency oscillation-type proximity sensor, a capacitance-type proximity sensor, a magnetic proximity sensor, and an infrared proximity sensor. The proximity sensor can detect not only proximity touches but also proximity touch patterns such as proximity touch distance, proximity touch direction, proximity touch speed, proximity touch duration, proximity touch position, and proximity touch movement state. The main processor 710 processes data (or information) corresponding to the proximity touch action and proximity touch pattern detected via the proximity sensor and controls the display panel 10 to display visual information corresponding to the processed data.

[0096] The ultrasonic sensor can recognize the position information of an object using ultrasonic waves. The main processor 710 can calculate the position of an object based on the information sensed by the optical sensor and the ultrasonic sensors. Because the speed of light and the speed of ultrasonic waves are different, the position of an object can also be calculated based on the time it takes for light to reach the optical sensor and the time it takes for ultrasonic waves to reach the ultrasonic sensor.

[0097] The output unit is for generating an output related to the visual, auditory, or tactile sense, and may include at least one of the display panel 10, an audio output unit, a haptic module, and an optical output unit.

[0098] The display panel 10 displays (outputs) information processed by the display device 1. For example, the display panel 10 may display execution screen information of an application run on the display device 1, or UI (user interface) information or GUI (graphic user interface) information based on the execution screen information. The display panel 10 may include a display layer that displays images and a touchscreen layer that senses a user's touch input. As a result, the display panel 10 can function as one of the input devices that provides an input interface between the display device 1 and the user, and can also function as one of the output units that provides an output interface between the display device 1 and the user.

[0099] The audio output unit may output audio data received from the wireless communication unit or stored in a memory in a call signal reception mode, a call mode, a recording mode, a voice recognition mode, a broadcast reception mode, etc. The audio output unit may also output audio signals related to functions executed by the display device 1 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit may include a receiver and a speaker. At least one of the receiver and the speaker may be an audio generator attached to the lower part of the display panel 10 and vibrating the display panel 10 to output audio. The audio generator may be a piezoelectric element or a piezoelectric actuator that contracts and expands in response to an electric signal, or an exciter that uses a voice coil to generate magnetic force to vibrate the display panel 10.

[0100] The haptic module generates various haptic effects that can be felt by the user. The haptic module can provide vibrations to the user as haptic effects. The intensity and pattern of the vibrations generated by the haptic module can be controlled by user selection or by settings of the main processor 710. For example, the haptic module can output different vibrations by combining them or sequentially outputting them. In addition to vibrations, the haptic module can generate various haptic effects, such as stimuli such as pin arrangements that move vertically relative to the contacted skin surface, air ejection or suction force through an outlet or inlet, touch on the skin surface, electrode contact, and electrostatic force, as well as effects that simulate a hot or cold sensation using elements capable of absorbing or generating heat. The haptic module can transmit haptic effects not only through direct contact but also through the muscular sensation of the fingers or arms.

[0101] The light output unit uses light from a light source to output a signal to notify the occurrence of an event. Examples of events occurring in the display device 1 include receiving a message, receiving a call signal, an answering machine, an alarm, a schedule notification, receiving an email, and receiving information via an application. The signal output by the light output unit can also be realized by the display device 1 emitting a single color or multiple colors of light on the front or back of the display device 1. The signal output can also be terminated when the display device 1 detects a user's confirmation of an event.

[0102] The interface unit functions as a path for various external devices connected to the display device 1. The interface unit may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (input / output) port, a video I / O port, and an earphone port. When an external device is connected to the interface unit, the display device 1 can perform appropriate control related to the connected external device.

[0103] The memory stores data supporting various functions of the display device 1. The memory may store a number of applications (application programs) run by the display device 1, and data and commands for the operation of the display device 1. At least some of the applications may be downloaded from an external server via wireless communication. The memory may store applications for the operation of the main processor 710 and may also temporarily store input / output data, such as a phone book, messages, still images, and videos. The memory may also store haptic data for various vibration patterns provided to the haptic module and audio data related to various sounds provided to the audio output unit. The memory may include at least one type of recording medium selected from the group consisting of a flash memory type, a hard disk type, a solid state disk type (SSD type), a silicon disk drive type (SDD type), a multimedia card micro type, a card-type memory (such as an SD memory or an XD memory), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, and an optical disk.

[0104] The power supply unit receives an external power source and an internal power source under the control of the main processor 710 and supplies power to each component included in the display device 1. The power supply unit may include a battery 80. The power supply unit may also include a connection port, which serves as an example of an interface unit electrically connected to an external charger that supplies power for charging the battery. Alternatively, the power supply unit may charge the battery 80 wirelessly without using the connection port. Power may be transmitted to the battery 80 from an external wireless power transmission device using one or more of an inductive coupling method based on magnetic induction and a magnetic resonance coupling method based on electromagnetic resonance. The battery 80 may also be positioned so as not to overlap with the main circuit board 70 in the third direction (z direction). The battery 80 may be placed in a battery hole BH of the bracket 60.

[0105] The lower cover 90 is also disposed below the main circuit board 70 and the battery 80. The lower cover 90 is fixed when fastened to the bracket 60. The lower cover 90 may form the bottom surface of the display device 1. The lower cover 90 may include plastic, metal, or both plastic and metal.

[0106] The lower cover 90 may be formed with a second camera hole CMH2 through which the lower surface of the camera device 731 is exposed. The position of the camera device 731 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the camera device 731 are not limited to the embodiments shown in FIGS.

[0107] 3 is a plan view showing a display panel according to an embodiment, and FIG. 4 is a side view showing an example of the display panel of FIG.

[0108] 3 and 4, the display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, an optical function layer OFL, and a panel protection member PB.

[0109] The substrate 100 may be made of an insulating material such as glass, quartz, or a polymer resin. The substrate 100 may be a rigid substrate or a flexible substrate that allows bending, folding, rolling, and the like. For example, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may have a multilayer structure including a layer including the aforementioned polymer resin and an inorganic layer (not shown). For example, the substrate 100 may include two layers including the aforementioned polymer resin and an inorganic barrier layer interposed therebetween.

[0110] A display layer DISL may be disposed on the substrate 100. The display layer DISL may be a layer including pixels and displaying images. The display layer DISL may include a circuit layer including thin film transistors, a display element layer including display elements, and a sealing member for sealing the display element layer.

[0111] The display layer DISL is also divided into a display area DA and a peripheral area DPA. The display area DA may be an area in which pixels are arranged and an image is displayed. The peripheral area DPA may be an area arranged outside the display area DA and not display an image. The peripheral area DPA may also be arranged to surround the display area DA. The peripheral area DPA may be an area from the outside of the display area DA to the edge of the display panel 10. In addition to pixels, pixel circuits for driving the pixels, scan lines, data lines, power lines, etc. connected to the pixel circuits may be arranged in the display area DA. A scan driver for applying scan signals to the scan lines, fan-out lines connecting the data lines to the display driver 32, etc. may be arranged in the peripheral area DPA.

[0112] A touchscreen layer TSL may be disposed on the display layer DISL. The touchscreen layer TSL may include a touch electrode and may be a layer for sensing whether or not a user has touched the display layer DISL. The touchscreen layer TSL may be directly formed on the sealing member of the display layer DISL. Alternatively, the touchscreen layer TSL may be formed separately and then bonded to the sealing member of the display layer DISL via an adhesive layer such as an optically clear adhesive (OCA).

[0113] An optical function layer OFL may be disposed on the touch screen layer TSL. The optical function layer OFL may include an anti-reflection layer. The anti-reflection layer can reduce the reflectance of light (external light) incident from the outside toward the display device 1.

[0114] In some embodiments, the anti-reflection layer is also provided on a polarizing film. The polarizing film may include a linear polarizer and a phase retardation film, such as a quarter-wave plate. The phase retardation film is disposed on the touch screen layer TSL, and the linear polarizer is also disposed on the phase retardation film.

[0115] In some embodiments, the anti-reflection layer may include a filter layer including a black matrix and color filters. The color filters are arranged taking into consideration the hue of light emitted from each pixel of the display device 1. For example, the filter layer may include red, green, or blue color filters.

[0116] In some embodiments, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may destructively interfere, thereby reducing the reflectance of external light.

[0117] A cover window 50 may be disposed on the optically functional layer OFL. The cover window 50 may also be attached onto the optically functional layer OFL by a transparent adhesive member such as an optically clear adhesive (OCA) film.

[0118] A panel protection member PB may be disposed under the display panel 10. The panel protection member PB may also be attached to the bottom surface of the display panel 10 via an adhesive member. The adhesive member may be a pressure sensitive adhesive (PSA). The panel protection member PB may include at least one layer selected from a light absorption layer for absorbing externally incident light, a cushioning layer for absorbing external impact, and a heat dissipation layer for efficiently dissipating heat from the display panel 10.

[0119] The light-absorbing layer is also disposed below the display panel 10. The light-absorbing layer blocks light transmission and prevents components disposed below the light-absorbing member, such as the display circuit board 30, from being visible above the display panel 10. The light-absorbing layer may include a light-absorbing material such as a black pigment or black dye.

[0120] The cushioning layer is also disposed below the light-absorbing member. The cushioning layer absorbs external impacts and prevents damage to the display panel 10. The cushioning layer may be composed of a single layer or multiple layers. For example, the cushioning layer may be formed of a polymer resin such as polyurethane, polycarbonate, polypropylene, or polyethylene, or may include an elastic material such as a sponge foamed from rubber, a urethane-based material, or an acrylic-based material.

[0121] The heat dissipation layer is also disposed under the cushion layer and may include a first heat dissipation layer containing graphite or carbon nanotubes, and a second heat dissipation layer formed of a thin metal film that can shield electromagnetic waves and has excellent thermal conductivity, such as copper, nickel, ferrite, or silver.

[0122] The panel protection member PB can be provided with an opening PB_OP corresponding to the component area CA. By providing the opening PB_OP in the panel protection member PB, the light transmittance of the component area CA can be improved.

[0123] The area of ​​the component area CA may be larger than the area in which the component 40 is arranged. As a result, the area of ​​the opening PB_OP formed in the panel protection member PB does not match the area of ​​the component area CA. The component 40 is also arranged to overlap the opening PB_OP. In one embodiment, the component 40 is also arranged to be inserted inside the opening PB_OP.

[0124] A first flexible film 34 may be disposed in a peripheral area DPA on one edge of the display panel 10. The first flexible film 34 also bends downwardly of the display panel 10, and the display circuit board 30 is also disposed on the lower surface of the panel protection member PB. The display circuit board 30 is attached and fixed to the lower surface of the panel protection member PB via a first adhesive member 39. The first adhesive member 39 may be a pressure-sensitive adhesive.

[0125] The display area DA of the display panel 10 includes a component area CA and a main display area MDA, below which components 40 are arranged. The component area CA is also arranged on one side of the main display area MDA. In one embodiment, FIG. 3 illustrates the component area CA arranged in a bar-type configuration with a width different from the width of the main display area MDA in the x-direction. Such a component area CA is arranged between the peripheral area DPA and the main display area MDA, with the upper, right, and left edges of the component area CA bordering the peripheral area DPA and the lower edge bordering the main display area MDA. In another embodiment, the component area CA may be arranged in a bar-type configuration with the same width as the width of the main display area MDA in the x-direction or y-direction. In yet another embodiment, the component area CA may be bar-type and arranged within the main display area MDA. In yet another embodiment, the component area CA may be circular, but may border the frame of the main display area MDA or may be arranged within the main display area MDA, as described above. In still another embodiment, the component area CA may be polygonal or elliptical and may be disposed adjacent to the frame of the main display area MDA or within the main display area MDA, as described above. However, for the sake of convenience, the following description will focus on an embodiment in which the component area CA is disposed in a bar shape and connected to the frame of the main display area MDA.

[0126] Fig. 5 is a plan view showing a display panel according to an embodiment. Fig. 6 is a side view showing an example of the display panel of Fig. 5. Fig. 5 shows a plan view of the display panel 10 in which the first bending region BA1 is unbent and open.

[0127] 5 and 6 differ from the embodiment of FIGS. 3 and 4 in that the first bending area BA1 on one side of the display panel 10 is bent and the first pad area PDA1 is disposed on the lower surface of the panel protection member PB. That is, the display panel 10 may be a bent display panel with one side bent.

[0128] 5 and 6, the first bending area BA1 and the first pad area PDA1 also protrude in the -y direction from the peripheral area DPA on one side of the display panel 10. As shown in Fig. 6, the length of the first bending area BA1 and the first pad area PDA1 in the x direction is shorter than the length of the display area DA in the x direction.

[0129] The display panel 10 can be bent in the first bending area BA1, and the first pad area PDA1 is also disposed on the lower surface of the panel protection member PB. The first pad area PDA1 can overlap the display area DA in the thickness direction (z direction) of the display panel 10. A display driver 32 and a display circuit board 30 can be disposed in the first pad area PDA1.

[0130] 3 and 5, the component areas CA of the display area DA are illustrated as having a bar shape, but the present invention is not limited thereto. For example, the shape of the component areas CA may be circular, elliptical, or polygonal, such as a triangle or pentagon, and the position of the component areas CA may also be modified in various ways. Furthermore, the display device 1 may have two or more component areas CA, and the shapes and sizes of the multiple component areas CA may differ from each other.

[0131] 7A and 7B are cross-sectional views that schematically illustrate a portion of a display device 1 according to an embodiment.

[0132] 7A and 7B, the display device 1 may include a display panel 10 and a component 40 overlapping the display panel 10. As described above, the display panel 10 includes a component area CA that overlaps the component 40, and a main display area MDA where a main image is displayed.

[0133] The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, an optical function layer OFL, and a panel protection member PB disposed under the substrate 100. The display layer DISL may include a circuit layer PCL including thin film transistors TFT and TFT', a display element layer including light emitting elements ED and ED', which are display elements, and a sealing member ENCM such as a thin film encapsulation layer TFEL or a sealing substrate ENS. Insulating layers IL and IL' may be disposed between the substrate 100 and the display layer DISL and within the display layer DISL.

[0134] The substrate 100 may be made of an insulating material such as glass, quartz, polymer resin, etc. The substrate 100 may be a rigid substrate or a flexible substrate that allows bending, folding, rolling, etc.

[0135] In the main display area MDA of the display panel 10, a main thin film transistor TFT and a main light-emitting element ED connected thereto are arranged to realize a main sub-pixel Pm, and in the component area CA, an auxiliary thin film transistor TFT' and an auxiliary light-emitting element ED' connected thereto are arranged to realize an auxiliary sub-pixel Pa.

[0136] Furthermore, a transmissive area TA in which no display element is arranged may be arranged in the component area CA. The transmissive area TA may be an area through which light / signals emitted from a component 40 arranged corresponding to the component area CA or light / signals incident on the component 40 are transmitted.

[0137] A lower metal layer BML may be disposed in the component area CA. The lower metal layer BML may also be disposed to correspond to the lower portion of the auxiliary thin film transistor TFT′. For example, the lower metal layer BML may also be disposed between the auxiliary thin film transistor TFT′ and the substrate 100. Such a lower metal layer BML may block external light from reaching the auxiliary thin film transistor TFT′. In some embodiments, an electrostatic voltage or signal may be applied to the lower metal layer BML to prevent damage to the pixel circuit due to electrostatic discharge. A plurality of lower metal layers BML may be disposed in the component area CA, and different voltages may be applied to each lower metal layer BML depending on the circumstances. It goes without saying that one lower metal layer BML having a hole corresponding to the transmissive area TA may also be disposed in the component area CA.

[0138] The display element layer EDL is also covered by a thin film encapsulation layer TFEL or is also covered by a sealing substrate ENS. In some embodiments, the thin film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, as shown in Figure 7A. In one embodiment, the thin film encapsulation layer TFEL may include a first inorganic encapsulation layer 131 and a second inorganic encapsulation layer 133, and an organic encapsulation layer 132 therebetween.

[0139] In some embodiments, as shown in FIG. 7B , the sealing substrate ENS is also disposed opposite the substrate 100, sandwiching the display element layer EDL. A gap may exist between the sealing substrate ENS and the display element layer EDL. The sealing substrate ENS may include glass. A sealant such as a frit is disposed between the substrate 100 and the sealing substrate ENS, and the sealant is also disposed in the peripheral area DPA. The sealant disposed in the peripheral area DPA can prevent moisture penetration through the side surfaces while surrounding the display area DA.

[0140] The touch screen layer TSL can acquire coordinate information based on an external input, for example, a touch event. The touch screen layer TSL may include touch electrodes and touch wiring connected to the touch electrodes. The touch screen layer TSL can sense the external input using a magnetic capacitance method or a mutual capacitance method.

[0141] The touchscreen layer TSL may also be formed on the thin film encapsulation layer TFEL. Alternatively, the touchscreen layer TSL may be formed separately on a touch substrate and then bonded to the thin film encapsulation layer TFEL via an adhesive layer such as an optically clear adhesive (OCA). In one embodiment, as shown in Figures 7A and 7B, the touchscreen layer TSL may also be formed directly on the thin film encapsulation layer TFEL, in which case no adhesive layer is interposed between the touchscreen layer TSL and the thin film encapsulation layer TFEL.

[0142] The optical function layer OFL may include an anti-reflection layer, which can reduce the reflectance of light (external light) incident on the display device 1 from the outside.

[0143] In some embodiments, the optically functional layer OFL may be a polarizing film. The optically functional layer OFL may have an opening OFL_OP corresponding to the transmissive region TA. This may significantly improve the light transmittance of the transmissive region TA. The opening OFL_OP may be filled with a transparent material such as an optically clear resin (OCR).

[0144] FIG. 8 is a plan view schematically illustrating a display panel according to an embodiment.

[0145] 8, various components constituting the display panel 10 are disposed on a substrate 100. The substrate 100 includes a display area DA and a peripheral area DPA surrounding the display area DA. The display area DA includes a main display area MDA where a main image is displayed, and a component area CA having a transmissive area TA where an auxiliary image is displayed. The auxiliary image may form a single overall image together with the main image, or the auxiliary image may be an image independent of the main image.

[0146] A plurality of main sub-pixels Pm are arranged in the main display area MDA. Each main sub-pixel Pm may be implemented by a display element such as an organic light emitting diode (OLED) (FIG. 12). Each main sub-pixel Pm may emit, for example, red, green, blue, or white light. The main display area MDA is covered with a sealing member to protect it from external air or moisture.

[0147] As described above, the component area CA is located on one side of the main display area MDA or inside the display area DA and is also surrounded by the main display area MDA. A plurality of auxiliary sub-pixels Pa are arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may be realized by a display element such as an organic light-emitting diode (OLED). Each auxiliary sub-pixel Pa may emit, for example, red, green, blue, or white light. The component area CA is covered with a sealing member to protect it from external air or moisture.

[0148] Meanwhile, the component area CA may have a transmissive area TA. The transmissive area TA may be arranged to surround a plurality of auxiliary sub-pixels Pa. Alternatively, the transmissive area TA may be arranged in a grid pattern with the plurality of auxiliary sub-pixels Pa.

[0149] Because the component area CA has the transmissive area TA, the resolution of the component area CA is lower than that of the main display area MDA. For example, the resolution of the component area CA may be about 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For example, the resolution of the main display area MDA may be about 400 ppi or more, and the resolution of the component area CA may be about 200 ppi or about 100 ppi.

[0150] The pixel circuits for driving the sub-pixels Pm and Pa are also electrically connected to the peripheral circuits arranged in the peripheral area DPA. The first scan driving circuit SDRV1, the second scan driving circuit SDRV2, the terminal unit PAD, the driving voltage supply line 11, and the common voltage supply line 13 may be arranged in the peripheral area DPA.

[0151] The first scan drive circuit SDRV1 can apply scan signals to each pixel circuit driving the subpixels Pm and Pa via the scan lines SL. The first scan drive circuit SDRV1 can apply light-emitting control signals to each pixel circuit via the light-emitting control lines EL. The second scan drive circuit SDRV2 can be located on the opposite side of the main display area MDA from the first scan drive circuit SDRV1 and can be approximately parallel to the first scan drive circuit SDRV1. Some of the pixel circuits of the main subpixel Pm in the main display area MDA are electrically connected to the first scan drive circuit SDRV1, and the rest are electrically connected to the second scan drive circuit SDRV2. Some of the pixel circuits of the auxiliary subpixel Pa in the component area CA are electrically connected to the first scan drive circuit SDRV1, and the rest are electrically connected to the second scan drive circuit SDRV2. The second scan drive circuit SDRV2 can be omitted.

[0152] A terminal part PAD is also disposed on one side of the substrate 100. The terminal part PAD is exposed and not covered by an insulating layer, and is connected to the display circuit board 30. A display driver 32 may be disposed on the display circuit board 30. The display driver 32 may generate control signals transmitted to the first scan driver circuit SDRV1 and the second scan driver circuit SDRV2. The display driver 32 may also supply a drive voltage ELVDD (FIG. 9A) to the drive voltage supply line 11 and a common voltage ELVSS (FIG. 9A) to the common voltage supply line 13. The drive voltage ELVDD is applied to pixel circuits of the subpixels Pm and Pa via the drive voltage line PL connected to the drive voltage supply line 11, and the common voltage ELVSS is connected to the common voltage supply line 13 and is also applied to the counter electrodes of the display elements. The display driver 32 generates a data signal, and the generated data signal is also transmitted to the pixel circuits of the sub-pixels Pm and Pa via the fan-out wiring FW and the data line DL connected to the fan-out wiring FW.

[0153] The driving voltage supply line 11 may be provided below the main display area MDA and extend in the x-direction. The common voltage supply line 13 may have a loop shape with one side open, and may partially surround the main display area MDA.

[0154] 9A and 9B are equivalent circuit diagrams of pixel circuits for driving sub-pixels, according to one embodiment.

[0155] 9A and 9B, a pixel circuit PC is connected to a light emitting element ED to realize light emission of a sub-pixel. The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to a scan line SL and a data line DL, and transfers a data signal Dm input via the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input via the scan line SL.

[0156] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transferred from the switching thin film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL.

[0157] The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the light emitting element ED according to the voltage value stored in the storage capacitor Cst, so that the light emitting element ED can emit light with a predetermined brightness in response to the driving current.

[0158] Although FIG. 9A illustrates a case where the pixel circuit PC includes two thin film transistors and one storage capacitor, the present invention is not limited thereto.

[0159] Referring to FIG. 9B, the pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6 and a second initialization thin film transistor T7.

[0160] 9B illustrates a case in which signal lines SL, SL-1, SL+1, EL, DL, an initialization voltage line VL, and a drive voltage line PL are provided for each pixel circuit PC, but the present invention is not limited to this. In another embodiment, at least one of the signal lines SL, SL-1, SL+1, EL, and DL and / or the initialization voltage line VL is shared by adjacent pixel circuits.

[0161] The drain electrode of the driving thin film transistor T1 is electrically connected to the light-emitting element ED via the light-emitting control thin film transistor T6. The driving thin film transistor T1 receives a data signal Dm through the switching operation of the switching thin film transistor T2 and supplies a driving current to the light-emitting element ED.

[0162] The gate electrode of the switching thin film transistor T2 is connected to the scan line SL, the source electrode is connected to the data line DL, and the drain electrode of the switching thin film transistor T2 is connected to the source electrode of the driving thin film transistor T1 and also to the driving voltage line PL via the operation control thin film transistor T5.

[0163] The switching thin film transistor T2 is turned on by the scan signal Sn transmitted through the scan line SL, and performs a switching operation of transmitting the data signal Dm transmitted to the data line DL to the source electrode of the driving thin film transistor T1.

[0164] The gate electrode of the compensation thin film transistor T3 is also connected to the scan line SL. The source electrode of the compensation thin film transistor T3 is connected to the drain electrode of the driving thin film transistor T1 and also to the pixel electrode of the light-emitting element ED via the light-emitting control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 is also connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on by a scan signal Sn transmitted through the scan line SL, connecting the gate electrode and drain electrode of the driving thin film transistor T1 to each other, making the driving thin film transistor T1 diode-connected.

[0165] The gate electrode of the first initialization thin film transistor T4 is also connected to the previous scan line SL-1. The drain electrode of the first initialization thin film transistor T4 is also connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 is also connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on by the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to transmit the initialization voltage Vint to the gate electrode of the driving thin film transistor T1, thereby performing an initialization operation to initialize the voltage of the gate electrode of the driving thin film transistor T1.

[0166] The gate electrode of the operation control thin film transistor T5 is also connected to the light emission control line EL. The source electrode of the operation control thin film transistor T5 is also connected to the driving voltage line PL. The drain electrode of the operation control thin film transistor T5 is connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0167] The gate electrode of the emission control thin film transistor T6 is also connected to the emission control line EL. The source electrode of the emission control thin film transistor T6 is also connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the emission control thin film transistor T6 is also electrically connected to the pixel electrode of the light-emitting element ED. The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on by the emission control signal En transmitted through the emission control line EL, and the driving voltage ELVDD is transmitted to the light-emitting element ED, causing a driving current to flow through the light-emitting element ED.

[0168] The gate electrode of the second initialization thin film transistor T7 is also connected to the subsequent scan line SL+1. The source electrode of the second initialization thin film transistor T7 is also connected to the pixel electrode of the light emitting element ED. The drain electrode of the second initialization thin film transistor T7 is also connected to the initialization voltage line VL. The second initialization thin film transistor T7 is turned on by the subsequent scan signal Sn+1 transmitted through the subsequent scan line SL+1 to initialize the pixel electrode of the light emitting element ED.

[0169] 9B illustrates the first initialization thin film transistor T4 and the second initialization thin film transistor T7 connected to the previous scan line SL-1 and the subsequent scan line SL+1, respectively, but the present invention is not limited thereto. In another embodiment, the first initialization thin film transistor T4 and the second initialization thin film transistor T7 can both be connected to the previous scan line SLn-1 and driven by the previous scan signal Sn-1.

[0170] Another electrode of the storage capacitor Cst is also connected to the driving voltage line PL, and one electrode of the storage capacitor Cst is also connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0171] A common voltage ELVSS is applied to the counter electrode (eg, cathode) of the light emitting element ED. The light emitting element ED emits light when a driving current is transmitted from the driving thin film transistor T1.

[0172] The pixel circuit PC is not limited to the number and circuit design of the thin film transistors and storage capacitors described with reference to FIGS. 9A and 9B, and the number and circuit design may be variously changed.

[0173] The pixel circuits PC driving the main subpixel Pm and the auxiliary subpixel Pa may be the same or different. For example, the pixel circuit PC driving the main subpixel Pm and the auxiliary subpixel Pa may be the pixel circuit PC shown in FIG. 9B. In another embodiment, the pixel circuit PC driving the main subpixel Pm may be the pixel circuit PC shown in FIG. 9B, and the pixel circuit PC driving the auxiliary subpixel Pa may be the pixel circuit PC shown in FIG. 9A.

[0174] FIG. 10 is a layout diagram that schematically illustrates a pixel layout structure in the main display area of ​​a display panel according to one embodiment.

[0175] 10, a plurality of main sub-pixels Pm may be arranged in the main display area MDA. In this specification, a sub-pixel is a light-emitting area, which is a minimum unit for realizing an image. Meanwhile, when organic light-emitting diodes are used as display elements, the light-emitting area is also defined by openings in a pixel-defining layer, which will be described later.

[0176] 10, the main sub-pixels Pm arranged in the main display area MDA are also arranged in a pentile structure. The red sub-pixels Pr, green sub-pixels Pg, and blue sub-pixels Pb can embody red, green, and blue, respectively.

[0177] In a first row 1N, a plurality of red subpixels Pr and a plurality of blue subpixels Pb are arranged next to each other, in an adjacent second row 2N, a plurality of green subpixels Pg are arranged at a predetermined interval, in an adjacent third row 3N, a blue subpixel Pb and a red subpixel Pr are arranged next to each other, and in an adjacent fourth row 4N, a plurality of green subpixels Pg are arranged at a predetermined interval, and this pixel arrangement is repeated up to the Nth row, where the blue subpixels Pb and the red subpixels Pr are larger than the green subpixels Pg.

[0178] The red subpixels Pr and blue subpixels Pb arranged in the first row 1N and the green subpixels Pg arranged in the second row 2N are offset from one another. Thus, in the first column 1M, the red subpixels Pr and blue subpixels Pb are arranged next to one another, in the adjacent second column 2M, the green subpixels Pg are arranged at a predetermined distance apart, in the adjacent third column 3M, the blue subpixels Pb and red subpixels Pr are arranged next to one another, and in the adjacent fourth column 4M, the green subpixels Pg are arranged at a predetermined distance apart, and this pixel arrangement is repeated up to the Mth column.

[0179] Another way to express this pixel array structure is that the red subpixel Pr is disposed at the first and third vertices of a virtual rectangle VS, with the center point of the green subpixel Pg as the center point of the rectangle, and the blue subpixel Pb is disposed at the second and fourth vertices, which are opposite to each other. In this case, the virtual rectangle VS can be variously modified, such as into a rectangle, a diamond, or a square. Such a virtual rectangle VS may be a main pixel group (not shown).

[0180] Such a pixel arrangement structure is called a pentile matrix structure, or a pentile structure, and by applying a rendering drive that expresses color by sharing adjacent pixels, high resolution can be realized with a small number of pixels.

[0181] 10, the plurality of main sub-pixels Pm are illustrated as being arranged in a pentile matrix structure, but the present invention is not limited thereto. For example, the plurality of main sub-pixels Pm may be arranged in various shapes such as a stripe structure, a mosaic array structure, or a delta array structure.

[0182] 11A-11C are layout diagrams that schematically illustrate pixel layout structures in component regions of a display panel, according to one embodiment.

[0183] 11A to 11C, a plurality of sub-pixels Pa may be arranged in a component region CA, and each of the sub-pixels Pa may emit any one of red, green, blue, and white light.

[0184] A component area CA can have auxiliary pixel groups PGU each including at least one auxiliary sub-pixel Pa, and transmissive regions TA. The auxiliary pixel groups PGU and transmissive regions TA are arranged alternately along the x and y directions, for example, in a grid pattern. In this case, the component area CA can have a plurality of auxiliary pixel groups PGU and a plurality of transmissive regions TA.

[0185] A subpixel group PGU can be defined as a subpixel group consisting of a plurality of subpixels Pa grouped into a predetermined unit. For example, as shown in FIG. 11A, one subpixel group PGU includes eight subpixels Pa arranged in a pentile structure. That is, one subpixel group PGU includes two red subpixels Pr, four green subpixels Pg, and two blue subpixels Pb.

[0186] In the component area CA, basic units U, each of which includes a predetermined number of auxiliary pixel groups PGU and a predetermined number of transmissive regions TA, may be repeatedly arranged in the x and y directions. In FIG. 11A , the basic unit U may have a rectangular shape formed by grouping four auxiliary pixel groups PGU and two transmissive regions TA arranged around them. In this case, the auxiliary pixel groups PGU may be connected to each other, and the two transmissive regions TA may also be connected to each other. The basic unit U is a partition of the repetitive shape and does not represent the end of the configuration.

[0187] A corresponding unit U' having the same area as the basic unit U may be set in the main display area MDA. In this case, the number of main sub-pixels Pm included in the corresponding unit U' is greater than the number of auxiliary sub-pixels Pa included in the basic unit U. For example, the basic unit U includes 32 auxiliary sub-pixels Pa, and the corresponding unit U' includes 48 main sub-pixels Pm, and the ratio of the number of auxiliary sub-pixels Pa to the number of main sub-pixels Pm arranged per area may be 2:3 (see FIG. 10).

[0188] The correspondence units U' as described above are also arranged in a row. For example, the correspondence units U' are also arranged in the y direction in the component area CA in FIGS. 11A and 11B. In such a case, the auxiliary pixel groups PGU are also arranged in a row, and the transmissive regions TA are also arranged in a row. In this case, the width of the transmissive regions TA is narrower than the width of the remaining portion of the correspondence units U' excluding the transmissive regions TA. In this case, each width is also measured in the x-axis direction in FIGS. 11A and 11B.

[0189] 11B, the pixel arrangement structure of the component area CA also has an S-stripe structure. In this embodiment, each sub-pixel group PGU includes three sub-pixels Pa, namely, one red sub-pixel Pr, one green sub-pixel Pg, and one blue sub-pixel Pb.

[0190] In this embodiment, red subpixels Pr and green subpixels Pg are alternately arranged in the first column 1I, and blue subpixels Pb are arranged in the adjacent second column 2I. The red subpixels Pr and green subpixels Pg are arranged in a rectangular shape with their long sides in the x direction, and the blue subpixels Pb are also arranged in a rectangular shape with their long sides in the y direction. The length of the blue subpixel Pb in the y direction may be equal to or longer than the sum of the lengths of the red subpixels Pr and green subpixels Pg in the y direction. This results in the blue subpixel Pb being larger than the red subpixels Pr and green subpixels Pg.

[0191] In this embodiment, the area occupied by one subpixel group PGU in the basic unit U may be approximately ¼ of the area of ​​the basic unit U. Although Fig. 11B illustrates the basic unit U as including only four subpixel groups PGU, in other embodiments, the basic unit U may include one or more subpixel groups PGU. In addition, the area of ​​the subpixel Pa included in the subpixel group PGU may also be modified in various ways.

[0192] 11C, the pixel arrangement structure of the component area CA may also have a stripe structure. That is, the red subpixels Pr, green subpixels Pg, and blue subpixels Pb are also arranged in parallel along the x direction. In this case, the red subpixels Pr, green subpixels Pg, and blue subpixels Pb may have their long sides in the y direction.

[0193] Alternatively, unlike the illustrated example, the red subpixels Pr, green subpixels Pg, and blue subpixels Pb may be arranged parallel to each other along the y direction, with the longer sides of the red subpixels Pr, green subpixels Pg, and blue subpixels Pb extending in the x direction.

[0194] The arrangement and shape of the auxiliary sub-pixels are not limited to those described above, but may be arranged in various forms and have various shapes.

[0195] FIG. 12 is a schematic cross-sectional view showing a part of a display panel 10 according to an embodiment, and is a cross-sectional view that schematically illustrates a main display area MDA and a component area CA.

[0196] 12, the display panel 10 includes a main display area MDA and a component area CA. The main display area MDA includes a main sub-pixel Pm, and the component area CA includes an auxiliary sub-pixel Pa and a transmissive area TA. The main display area MDA may include a main pixel circuit PC including a main thin film transistor TFT and a main storage capacitor Cst, and a main organic light emitting diode OLED as a display element connected to the main pixel circuit PC. The component area CA may include a auxiliary pixel circuit PC' including an auxiliary thin film transistor TFT' and an auxiliary storage capacitor Cst', and an auxiliary organic light emitting diode OLED' as a display element connected to the auxiliary pixel circuit PC'.

[0197] In this embodiment, an organic light emitting diode is used as the display element, but in other embodiments, an inorganic light emitting element or a quantum dot light emitting element may be used as the display element.

[0198] The following describes a structure in which components included in the display panel 10 are stacked. The display panel 10 is also provided with a substrate 100, a buffer layer 111, a circuit layer PCL, and a display element layer EDL stacked together.

[0199] As described above, the substrate 100 may be made of an insulating material such as glass, quartz, polymer resin, etc. The substrate 100 may be a rigid substrate or a flexible substrate that allows bending, folding, rolling, etc.

[0200] The buffer layer 111 is located on the substrate 100 and can reduce or block penetration of foreign matter, moisture, or external air from underneath the substrate 100, and can provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may have a single-layer structure or a multi-layer structure of an inorganic material and an organic material. A barrier layer (not shown) that blocks penetration of external air may further be included between the substrate 100 and the buffer layer 111. In some embodiments, the buffer layer 111 is made of silicon oxide (SiO2) or silicon nitride (SiN x The buffer layer 111 is also provided so that a first buffer layer 111a and a second buffer layer 111b are stacked.

[0201] In the component area CA, a lower metal layer BML may be disposed between the first buffer layer 111a and the second buffer layer 111b. In another embodiment, the lower metal layer BML is also disposed between the substrate 100 and the first buffer layer 111a. The lower metal layer BML is disposed below the auxiliary pixel circuits PC' and can prevent the characteristics of the auxiliary thin film transistors TFT' from being deteriorated by light emitted from components, etc. The lower metal layer BML can also prevent light emitted from components, etc., or directed toward the components, from being diffracted through narrow gaps between the wiring connected to the auxiliary pixel circuits PC'. The lower metal layer BML is not present in the transmissive area TA.

[0202] The lower metal layer BML is also connected to the wiring GCL disposed in another layer through contact holes. The lower metal layer BML may receive static voltages or signals from the wiring GCL. For example, the lower metal layer BML may receive a driving voltage ELVDD or a scan signal. By receiving static voltages or signals, the lower metal layer BML can significantly reduce the probability of electrostatic discharge. The lower metal layer BML may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The lower metal layer BML may be formed as a single layer or multiple layers of the aforementioned materials.

[0203] The circuit layer PCL is disposed on the buffer layer 111 and may include pixel circuits PC, PC', a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 115, and a planarization layer 117. The main pixel circuit PC may include a main thin film transistor TFT and a main storage capacitor Cst, and the auxiliary pixel circuit PC' may include an auxiliary thin film transistor TFT' and an auxiliary storage capacitor Cst'.

[0204] A main thin film transistor TFT and an auxiliary thin film transistor TFT' may be disposed on the buffer layer 111. The main thin film transistor TFT includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1, and the auxiliary thin film transistor TFT includes a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main thin film transistor TFT is connected to the main organic light emitting diode OLED and can drive the main organic light emitting diode OLED. The auxiliary thin film transistor TFT' is connected to the auxiliary organic light emitting diode OLED' and can drive the auxiliary organic light emitting diode OLED'.

[0205] The first semiconductor layer A1 and the second semiconductor layer A2 are disposed on the buffer layer 111 and may include polysilicon. In another embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may include amorphous silicon. In another embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may include an oxide of at least one material selected from the group including indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer A1 and the second semiconductor layer A2 may include a channel region and a source region and a drain region doped with impurities.

[0206] The second semiconductor layer A2 may be overlapped with the lower metal layer BML with the second buffer layer 111b interposed therebetween. In one embodiment, the width of the second semiconductor layer A2 is formed to be narrower than the width of the lower metal layer BML. Therefore, when projected in the vertical direction onto the substrate 100, the second semiconductor layer A2 entirely overlaps with the lower metal layer BML.

[0207] A first gate insulating layer 112 may be provided to cover the first semiconductor layer A1 and the second semiconductor layer A2. The first gate insulating layer 112 may be made of silicon oxide (SiO2), silicon nitride (SiN x The first gate insulating layer 112 may include an inorganic insulator such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The first gate insulating layer 112 may be a single layer or multiple layers including the aforementioned inorganic insulators.

[0208] A first gate electrode G1 and a second gate electrode G2 are disposed on the first gate insulating layer 112 so as to overlap the first semiconductor layer A1 and the second semiconductor layer A2, respectively. The first gate electrode G1 and the second gate electrode G2 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be configured as a single layer or multiple layers. For example, the first gate electrode G1 and the second gate electrode G2 may be a single layer of Mo.

[0209] The second gate insulating layer 113 is also provided to cover the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may be made of silicon oxide (SiO2), silicon nitride (SiN x The second gate insulating layer 113 may include an inorganic insulator such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The second gate insulating layer 113 may be a single layer or multiple layers including the aforementioned inorganic insulators.

[0210] A first upper electrode CE2 of the main storage capacitor Cst and a second upper electrode CE2' of the auxiliary storage capacitor Cst' may be disposed on the second gate insulating layer 113.

[0211] In the main display area MDA, the first upper electrode CE2 may overlap the underlying first gate electrode G1. The first gate electrode G1 and the first upper electrode CE2 overlapping with the second gate insulating layer 113 sandwiched therebetween may form a main storage capacitor Cst. The first gate electrode G1 may be the first lower electrode CE1 of the main storage capacitor Cst.

[0212] In the component region CA, the second upper electrode CE2' may overlap the underlying second gate electrode G2. The second gate electrode G2 and the second upper electrode CE2' overlapping with the second gate insulating layer 113 sandwiched therebetween may form an auxiliary storage capacitor Cst'. The first gate electrode G1 may be a second lower electrode CE1' of the auxiliary storage capacitor Cst'.

[0213] The first and second upper electrodes CE2 and CE2′ may comprise aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may be single or multiple layers of the aforementioned materials.

[0214] The interlayer insulating layer 115 is also formed to cover the first upper electrode CE2 and the second upper electrode CE2′. The interlayer insulating layer 115 may be made of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), etc. The interlayer insulating layer 115 may be a single layer or multiple layers including the aforementioned inorganic insulators.

[0215] The first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as an inorganic insulating layer IIL. The inorganic insulating layer IIL may have a first hole H1 corresponding to the transmissive region TA. The first hole H1 may expose a portion of the buffer layer 111 or the upper surface of the substrate 100. The first hole H1 may be formed by overlapping an opening in the first gate insulating layer 112, an opening in the second gate insulating layer 113, and an opening in the interlayer insulating layer 115, which are formed to correspond to the transmissive region TA. These openings may be formed separately through separate processes or simultaneously through the same process. If these openings are formed through separate processes, the inner surface of the first hole H1 may not be smooth but may have a stepped or other uneven surface.

[0216] Alternatively, it goes without saying that the inorganic insulating layer IIL may have a groove instead of the first hole H1 exposing the buffer layer 111. Alternatively, the inorganic insulating layer IIL may not have the first hole H1 or groove corresponding to the transmissive region TA. The inorganic insulating layer IIL generally includes an inorganic insulating material with excellent light transmittance. However, even if the inorganic insulating layer IIL does not have a hole or groove corresponding to the transmissive region TA, the inorganic insulating layer IIL still has sufficient transmittance to allow the component 40 (FIG. 2) to transmit / receive a sufficient amount of light.

[0217] The source electrodes S1, S2 and the drain electrodes D1, D2 are disposed on the interlayer insulating layer 115. The source electrodes S1, S2 and the drain electrodes D1, D2 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multilayer including the above materials. As an example, the source electrodes S1, S2 and the drain electrodes D1, D2 may be formed as a Ti / Al / Ti multilayer structure.

[0218] A planarization layer 117 may be disposed to cover the source electrodes S1 and S2 and the drain electrodes D1 and D2. The planarization layer 117 may have a flat upper surface so that the first pixel electrode 121 and the second pixel electrode 121′ disposed thereon may be formed flat.

[0219] The planarization layer 117 may include an organic or inorganic material and may have a single-layer structure or a multi-layer structure. The planarization layer 117 may include a general-purpose polymer such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, or a vinyl alcohol-based polymer. Meanwhile, the planarization layer 117 may include silicon oxide (SiO2), silicon nitride (SiN x The planarization layer 117 may include an inorganic insulator such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). When forming the planarization layer 117, after forming the layer, the top surface of the layer may be subjected to chemical mechanical polishing to provide a planar top surface.

[0220] The planarization layer 117 corresponds to the transmissive region TA and may have a second hole H2. The second hole H2 may overlap the first hole H1. In FIG. 12, the second hole H2 is illustrated as being larger than the first hole H1. In another embodiment, the planarization layer 117 is provided to cover the edge of the first hole H1 of the inorganic insulating layer IIL, and the area of ​​the second hole H2 is formed to be smaller than the area of ​​the first hole H1.

[0221] The planarization layer 117 has a via hole exposing one of the first source electrode S1 and the first drain electrode D1 of the main thin film transistor TFT, and the first pixel electrode 121 contacts the first source electrode S1 or the first drain electrode D1 through the via hole and is electrically connected to the main thin film transistor TFT. The planarization layer 117 also has a via hole exposing one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin film transistor TFT', and the second pixel electrode 121' contacts the second source electrode S2 or the second drain electrode D2 through the via hole and is electrically connected to the auxiliary thin film transistor TFT'.

[0222] The first pixel electrode 121 and the second pixel electrode 121' may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The first pixel electrode 121 and the second pixel electrode 121' may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. For example, the first pixel electrode 121 and the second pixel electrode 121' may have a structure in which a film formed of ITO, IZO, ZnO, or In2O3 is disposed above or below the reflective film. In this case, the first pixel electrode 121 and the second pixel electrode 121' may have a laminated structure of ITO / Ag / ITO.

[0223] The pixel defining layer 119 may have a first opening OP1 and a second opening OP2 on the planarization layer 117, covering edges of the first pixel electrode 121 and the second pixel electrode 121′ and exposing central portions of the first pixel electrode 121 and the second pixel electrode 121′. The first opening OP1 and the second opening OP2 define the light-emitting regions of the organic light-emitting diodes OLED and OLED′, i.e., the sizes and shapes of the sub-pixels Pm and Pa.

[0224] The pixel defining layer 119 increases the distance between the edges of the pixel electrodes 121 and 121′ and the opposing electrode 123 on the pixel electrodes 121 and 121′, and can prevent arcing at the edges of the pixel electrodes 121 and 121′. The pixel defining layer 119 is made of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO, and phenolic resin, and can be formed by a method such as spin coating.

[0225] The pixel defining layer 119 may include a third hole H3 located in the transmissive region TA. The third hole H3 may overlap the first hole H1 and the second hole H2. The first to third holes H1 to H3 may improve light transmittance in the transmissive region TA. While the buffer layer 111 is shown in FIG. 12 as being continuously disposed in the transmissive region TA, it should be understood that the buffer layer 111 may include holes located in the transmissive region TA. Portions of the counter electrode 123, which will be described later, may be disposed on inner surfaces of the first to third holes H1 to H3.

[0226] A first light-emitting layer 122b and a second light-emitting layer 122b' are disposed in the first opening OP1 and the second opening OP2 of the pixel defining layer 119, respectively, so as to correspond to the first pixel electrode 121 and the second pixel electrode 121'. The first light-emitting layer 122b and the second light-emitting layer 122b' may include a polymer or a small molecule material and can emit red, green, blue, or white light.

[0227] An organic functional layer 122e may be disposed above and / or below the first light-emitting layer 122b and the second light-emitting layer 122b'. The organic functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. The first functional layer 122a or the second functional layer 122c may be omitted.

[0228] The first functional layer 122a is also disposed below the first light-emitting layer 122b and the second light-emitting layer 122b'. The first functional layer 122a may be a single layer or multiple layers made of an organic material. The first functional layer 122a may be a hole transport layer (HTL) having a single layer structure. Alternatively, the first functional layer 122a may include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer 122a is also integrally formed to correspond to the organic light-emitting diodes OLED and OLED' included in the main display area MDA and the component area CA.

[0229] The second functional layer 122c is also disposed on the first light-emitting layer 122b and the second light-emitting layer 122b'. The second functional layer 122c may be a single layer or multiple layers made of an organic material. The second functional layer 122c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 122c is also integrally formed to correspond to the organic light-emitting diodes OLED and OLED' included in the main display area MDA and the component area CA.

[0230] The counter electrode 123 is disposed on the second functional layer 122c. The counter electrode 123 may include a conductive material with a low work function. For example, the counter electrode 123 may include a (semi-)transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode 123 may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer containing the aforementioned material. The counter electrode 123 is also integrally formed to correspond to the organic light emitting diodes OLED and OLED' included in the main display area MDA and the component area CA.

[0231] The counter electrode 123 as described above may include a main subpixel counter electrode 123-1 disposed in the main subpixel Pm and an auxiliary subpixel counter electrode 123-2 disposed in the auxiliary subpixel Pa.

[0232] The layers from the first pixel electrode 121 to the counter electrode 123 formed in the main display area MDA may form a main organic light emitting diode OLED, and the layers from the second pixel electrode 121′ to the counter electrode 123 formed in the component area CA may form an auxiliary organic light emitting diode OLED′.

[0233] An upper layer 150 containing an organic material may be formed on the counter electrode 123. The upper layer 150 may be a layer provided to protect the counter electrode 123 and increase light extraction efficiency. The upper layer 150 may contain an organic material having a refractive index higher than that of the counter electrode 123. Alternatively, the upper layer 150 may be formed by stacking layers having different refractive indices. For example, the upper layer 150 may be formed by stacking a high refractive index layer / a low refractive index layer / a high refractive index layer. In this case, the refractive index of the high refractive index layer may be 1.7 or more, and the refractive index of the low refractive index layer may be 1.3 or less.

[0234] The upper layer 150 may additionally contain LiF, or the upper layer 150 may additionally contain silicon oxide (SiO), silicon nitride (SiN x ) may be included.

[0235] The first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 may have a transmission hole TAH corresponding to the transmission region TA. That is, the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 may each have an opening corresponding to the transmission region TA. The areas of such openings may be substantially the same. For example, the area of ​​the opening in the counter electrode 123 may be substantially the same as the area of ​​the transmission hole TAH.

[0236] The fact that such a transparent hole TAH corresponds to the transparent region TA can also be understood as meaning that the transparent hole TAH overlaps with the transparent region TA. In this case, the area of ​​the transparent hole TAH is narrower than the area of ​​the first hole H1 formed in the inorganic insulating layer IIL. For this reason, in FIG. 12, the width Wt of the transparent hole TAH is illustrated as being narrower than the width of the first hole H1. Here, the area of ​​the transparent hole TAH is also defined as the area of ​​the opening having the narrowest area among the openings constituting the transparent hole TAH. The area of ​​the first hole H1 is also defined as the area of ​​the opening having the narrowest area among the openings constituting the first hole H1.

[0237] The transmission holes TAH eliminate portions of the counter electrode 123 in the transmission region TA, thereby significantly increasing the light transmittance in the transmission region TA. The counter electrode 123 having the transmission holes TAH can be formed by various methods. In one embodiment, the material for forming the counter electrode 123 is formed over the entire surface of the substrate 100, and then the portion corresponding to the transmission region TA is removed using laser lift-off to form the counter electrode 123 having the transmission holes TAH. In another embodiment, the counter electrode 123 having the transmission holes TAH can be formed using a metal self-patterning (MSP) method. In yet another embodiment, the counter electrode 123 having the transmission holes TAH can be formed by depositing the counter electrode 123 using a fine metal mask (FMM).

[0238] FIG. 13 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment.

[0239] 13, the embodiment differs from the embodiment of FIG. 12 in that the auxiliary pixel circuit PC′ of the display panel 10 includes a thin film transistor made of an oxide semiconductor and a thin film transistor made of polysilicon. Although only the component area CA is shown in FIG. 13, the same applies to the main pixel circuit PC in the main display area MDA and the auxiliary pixel circuit PC′ in the component area CA.

[0240] The pixel circuit PC' of the display panel 10 may include a first thin film transistor TFTp' including a second semiconductor layer A2 made of polycrystalline silicon, and a second thin film transistor TFTo' including a third semiconductor layer A3 made of an oxide semiconductor.

[0241] The first thin film transistor TFTp' includes a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The first thin film transistor TFTp' is configured substantially the same as the auxiliary thin film transistor TFT' described with reference to FIG. 12, and the second semiconductor layer A2 of the first thin film transistor TFTp' is also configured using polycrystalline silicon.

[0242] On the other hand, the circuit layer PCL of this embodiment is different in that the interlayer insulating layer 115 is provided in a first interlayer insulating layer 115a and a second interlayer insulating layer 115b.

[0243] The second thin film transistor TFTo′ may include a third semiconductor layer A3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3. The third semiconductor layer A3 is also disposed on the first interlayer insulating layer 115a. That is, the third semiconductor layer A3 is also disposed on a layer different from the second semiconductor layer A2. The third semiconductor layer A3 may include a channel region and source and drain regions disposed on both sides of the channel region. In some embodiments, the third semiconductor layer A3 is also formed of an oxide semiconductor. For example, the third semiconductor layer A3 is a Zn-oxide-based material, such as Zn oxide, In Zn oxide, or Ga In Zn oxide. Alternatively, the third semiconductor layer A3 may be made of a semiconductor such as IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O), which is ZnO doped with metals such as indium (In), gallium (Ga), or tin (Sn).

[0244] The source and drain regions of the third semiconductor layer A3 can also be formed by adjusting the carrier concentration of an oxide semiconductor to make it conductive. For example, the source and drain regions of the third semiconductor layer A3 can be formed by increasing the carrier concentration of the oxide semiconductor through plasma treatment using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

[0245] A third gate electrode G3 may be disposed so as to overlap the channel region of the third semiconductor layer A3, and a third gate insulating layer 116 may be disposed between the third semiconductor layer A3 and the third gate electrode G3. That is, the third gate electrode G3 is also insulated from the third semiconductor layer A3 by the third gate insulating layer 116. The third gate insulating layer 116 may be provided by being patterned according to the shape of the third gate electrode G3.

[0246] The third gate insulating layer 116 may include an inorganic material including an oxide or a nitride. For example, the third gate insulating layer 116 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), etc. The third gate electrode G3 is disposed on the third gate insulating layer 116 and includes molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be configured as a single layer or multiple layers.

[0247] The second interlayer insulating layer 115b covers the third gate electrode G3 of the third thin film transistor TFT3 and is also disposed on the upper surface of the substrate 100. A third source electrode S3 and a third drain electrode D3 may be disposed on the second interlayer insulating layer 115b.

[0248] The third source electrode S3 and the third drain electrode D3 may be in contact with the source region and the drain region of the third semiconductor layer A3, respectively, through contact holes that penetrate the second interlayer insulating layer 115b. The third source electrode S3 and the third drain electrode D3 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multilayer including the above materials.

[0249] Thin film transistors having semiconductor layers made of polycrystalline silicon have high reliability and are used as driving thin film transistors, enabling high-quality display panels to be realized.

[0250] The oxide semiconductor has high carrier mobility and low leakage current, so it does not cause a large voltage drop even when driven for a long time. That is, even when driven at low frequencies, the image hue does not change significantly due to the voltage drop, making low-frequency driving possible. Because of this advantage of low leakage current, the oxide semiconductor can be used for at least one thin film transistor other than the driving thin film transistor to prevent leakage current and reduce power consumption.

[0251] Fig. 14 is a schematic cross-sectional view showing a part of a display panel according to an embodiment. In Fig. 14, the same reference numerals as in Fig. 12 refer to the same elements, and redundant description thereof will be omitted.

[0252] Referring to Figure 14, the difference from the embodiment of Figure 12 is that the planarization layer 117 is composed of a first planarization layer 117a and a second planarization layer 117b, a first metal layer BML1 is arranged in the main display area MDA, and a transmissive area TA is defined by a lower hole BMLH of the lower metal layer BML.

[0253] The circuit layer PCL of the display panel 10 may include a first planarization layer 117a and a second planarization layer 117b, which allows a conductive pattern such as wiring to be formed between the first planarization layer 117a and the second planarization layer 117b, which is advantageous for high integration.

[0254] The first planarization layer 117a is also disposed to cover the pixel circuits PC and PC'. The second planarization layer 117b is disposed on the first planarization layer 117a and may have a flat upper surface so that the pixel electrodes 121 and 121' can be formed flat. The first planarization layer 117a and the second planarization layer 117b may include an organic or inorganic material and may have a single-layer structure or a multi-layer structure. The first planarization layer 117a and the second planarization layer 117b may include a general-purpose polymer such as BCB·polyimide·HMDSO·polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, or a vinyl alcohol-based polymer. Meanwhile, the first planarization layer 117a and the second planarization layer 117b may be formed of silicon oxide (SiO2), silicon nitride (SiN x The first and second planarization layers 117a and 117b may include inorganic insulators such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). When forming the first and second planarization layers 117a and 117b, chemical mechanical polishing may be performed on the top surfaces of the layers after they are formed to provide flat top surfaces.

[0255] The organic light emitting diodes OLED and OLED' are disposed on the second planarization layer 117b. The pixel electrodes 121 and 121' of the organic light emitting diodes OLED and OLED' are also connected to the pixel circuits PC and PC' via connection electrodes CM and CM' disposed on the planarization layer 117b.

[0256] Connection electrodes CM and CM' may be disposed between the first planarization layer 117a and the second planarization layer 117b. The connection electrodes CM and CM' may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a single layer or multilayer containing the above materials. For example, the connection electrodes CM and CM' may have a Ti / Al / Ti multilayer structure.

[0257] Meanwhile, the display panel 10 may include a first metal layer BML1 disposed in the main display area MDA. The first metal layer BML1 is disposed between the substrate 100 and the main pixel circuit PC to correspond to the main thin film transistor TFT in the main display area MDA. In one embodiment, the first metal layer BML1 is disposed to correspond to a portion of the main display area MDA. Alternatively, the first metal layer BML1 is disposed to correspond to the entire main display area MDA. Alternatively, the first metal layer BML1 is formed integrally with the lower metal layer BML in the component area CA. The first metal layer BML1 receives an electrostatic voltage or signal, thereby preventing damage to the main pixel circuit PC due to electrostatic discharge.

[0258] The first metal layer BML1 may comprise aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu). The first metal layer BML1 may be a single layer or multiple layers of the aforementioned materials.

[0259] The lower metal layer BML of the component area CA may be provided to cover the entire component area CA. In this case, the lower metal layer BML may include a lower hole BMLH overlapping the transmissive area TA. In some embodiments, the shape and size of the transmissive area TA may be defined by the shape and size of the lower hole BMLH.

[0260] The display panel 10 may include the first wiring WL1 to the fourth wiring WL4 arranged on different layers.

[0261] The first wiring WL1 is disposed on the first gate insulating layer 112, which is the same layer as the layer in which the gate electrodes G1 and G2 are disposed, and can function as a scan line that transmits scan signals to the pixel circuits PC and PC', or as a light-emitting control line.

[0262] The second wiring WL2 is arranged on the second gate insulating layer 113, which is the same layer as the layer in which the upper electrodes CE2, CE2' of the storage capacitors Cst, Cst' are arranged, and can function as the scan line SL and / or the light emitting control line EL.

[0263] The third wiring WL3 is disposed on the interlayer insulating layer 115 and can function as a data line DL that transmits a data signal to the pixel circuits PC and PC′, or as a drive voltage line that transmits a drive voltage to the pixel circuits.

[0264] The fourth wiring WL4 is arranged on the planarization layer 117, which is the same layer as the layer in which the connection electrodes CM and CM' are arranged, and can function as a driving voltage line that transmits a driving voltage to the pixel circuit, or a data line that transmits a data signal to the pixel circuit.

[0265] The first through fourth wirings WL1 through WL4 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multilayers including the above materials. Alternatively, the first through fourth wirings WL1 through WL4 may be made of a transparent conductive material. The first through fourth wirings WL1 through WL4 may include the same material or may be made of different materials.

[0266] FIG. 15 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment.

[0267] 15, the same reference numerals as in FIG. 12 refer to the same elements, and redundant explanations will be omitted. The embodiment in FIG. 15 differs from the embodiment in FIG. 12 in that the substrate 100 has a groove 100GR corresponding to the transmissive region TA.

[0268] The display panel substrate 100 may include a first base layer 101, a first inorganic barrier layer 102, a second base layer 103, and a second inorganic barrier layer 104, which are sequentially stacked. The first base layer 101 and the second base layer 103 may each include the polymer resin described above. The first inorganic barrier layer 102 and the second inorganic barrier layer 104 are barrier layers that prevent the penetration of external impurities, and may be made of silicon oxide (SiO2), silicon nitride (SiN x ), and inorganic materials such as silicon oxynitride (SiON), each of which can have a single layer structure or a multilayer structure.

[0269] In this embodiment, the substrate 100 may have a groove 100GR corresponding to the transmissive region TA. The groove 100GR may refer to a region where the substrate 100 is partially removed downward (in the -z direction) and partially remains. For example, the first base layer 101 and the first inorganic barrier layer 102 may be continuous across the transmissive region TA. The second base layer 103 and the second inorganic barrier layer 104 may have openings 103OP and 104OP corresponding to the transmissive region TA. Due to this shape, the substrate 100 may have the groove 100GR. That is, the groove 100GR of the substrate 100 is also provided in the opening 104OP of the second inorganic barrier layer 104, the opening 103OP of the second base layer 103, and the upper surface 102S of the first inorganic barrier layer 102 exposed by the openings 104OP and 103OP.

[0270] The substrate 100 may include the grooves 100GR in various forms. For example, a portion of the upper surface (in the +z direction) of the first inorganic barrier layer 102 may also be removed, while the lower surface (in the -z direction) of the second base layer 103 may remain unremoved. The grooves 100GR in the substrate 100 may reduce the thickness of the substrate 100 in the transmissive region TA, thereby significantly increasing the light transmittance in the transmissive region TA. In addition, in this embodiment, the buffer layer 111 may also include buffer holes 111H corresponding to the transmissive region TA.

[0271] In the above-described embodiment, in order to increase the light transmittance of the transmissive region TA, grooves are formed in the substrate 100, or the buffer layer 111, the inorganic insulating layer IIL, the planarization layer 117, and the pixel defining layer 119 are provided with the buffer hole 111H and the first hole H1 to the third hole H3, respectively, corresponding to the transmissive region TA. However, the present invention is not limited thereto.

[0272] The substrate 100, buffer layer 111, inorganic insulating layer IIL, planarization layer 117, and pixel defining layer 119 of the display panel 10 are each made of a material with high light transmittance, but depending on the type of component 40 (FIG. 2) arranged below the component area CA, the buffer hole 111H and the first to third holes H1 to H3 are not provided.

[0273] Figure 16A is a schematic cross-sectional view of a portion of a display panel according to an embodiment. Figure 16B is a schematic cross-sectional view of a portion of a display panel according to an embodiment. Figure 16C is a schematic cross-sectional view of a portion of a display panel according to an embodiment. Figures 16A to 16C specifically illustrate portions of component areas of the display panel.

[0274] 16A, the inorganic insulating layer IIL may correspond to the transmissive region TA and be continuously disposed. Alternatively, at least one of the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 of the inorganic insulating layer IIL may correspond to the transmissive region TA and be continuously disposed. Meanwhile, the planarization layer 117 and the pixel defining layer 119 may each include a second hole H2 and a third hole H3 that correspond to the transmissive region TA and expose the top surface of the inorganic insulating layer IIL.

[0275] 16B, the inorganic insulating layer IIL and the planarization layer 117 may be disposed continuously in the transmissive region TA, and the pixel defining layer 119 may have a third hole H3 that exposes the top surface of the inorganic insulating layer IIL in the transmissive region TA. Although not shown, the pixel defining layer 119 may also be disposed continuously in the transmissive region TA.

[0276] 16C, the inorganic insulating layer IIL includes a first hole H1 corresponding to the transmissive region TA, and a first planarization layer 117a and a second planarization layer 117b are also provided to fill the first hole H1. In some embodiments, the first planarization layer 117a and the second planarization layer 117b are also provided using a transparent organic material having a refractive index similar to that of the substrate 100 and the buffer layer 111. For example, the first planarization layer 117a and the second planarization layer 117b may be provided using a siloxane-based organic material having high light transmittance. The siloxane-based organic material may include hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecamethylpentasiloxane, and polydimethylsiloxane.

[0277] The planarization layer 117 having a refractive index similar to that of the substrate 100 and the buffer layer 111 is disposed in the transmissive region TA, thereby minimizing the loss of light transmittance due to the difference in refractive index.

[0278] Fig. 17 is a schematic cross-sectional view showing a part of a display panel according to an embodiment, in which the same reference numerals as in Fig. 12 refer to the same elements, and redundant description thereof will be omitted.

[0279] 17, the size of the auxiliary subpixel Pa is larger than the size of the main subpixel Pm that emits the same color as the auxiliary subpixel Pa. That is, the second opening OP2 of the pixel defining layer 119 that defines the size of the auxiliary subpixel Pa is larger than the first opening OP1 of the pixel defining layer 119 that defines the size of the main subpixel Pm.

[0280] The component area CA includes a transmissive area TA. If the auxiliary sub-pixel Pa has the same size as the main sub-pixel Pm, applying the same current to the organic light emitting diodes OLED and OLED′ that implement the auxiliary sub-pixel Pa and the main sub-pixel Pm will result in a decrease in the luminance of the component area CA as a whole. On the other hand, if a larger current is applied to the auxiliary organic light emitting diode OLED′ disposed in the component area CA to compensate for the luminance of the component area CA, the auxiliary organic light emitting diode OLED′ will easily deteriorate.

[0281] In this embodiment, the size of the auxiliary sub-pixel Pa in the component area CA is set to be larger than that of the main sub-pixel Pm that emits the same color, thereby compensating for the luminance of the component area CA while preventing deterioration of the auxiliary organic light emitting diode OLED′. To this end, a pixel arrangement structure that allows the auxiliary sub-pixel Pa to be larger in the component area CA may be adopted.

[0282] FIG. 18 is a cross-sectional view showing an apparatus for manufacturing a display device (not shown) according to an embodiment of the present invention.

[0283] Referring to FIG. 18, the display device is also manufactured through a display device manufacturing apparatus 400 .

[0284] The display device manufacturing apparatus 400 may include a chamber 410, a mask assembly 420, a first support unit 430, a second support unit 440, a deposition source 450, a magnetic force generating unit 460, a vision unit 470, and a pressure adjusting unit 480.

[0285] The chamber 410 has a space formed therein, and a portion of the chamber 410 is formed to be open. In this case, a gate valve 411 may be disposed in the open portion of the chamber 410 so that the open portion can be opened and closed.

[0286] The mask assembly 420 may be selectively disposed inside the chamber 410. In this case, the mask assembly 420 may include a mask frame 421 and a mask sheet 422.

[0287] The mask frame 421 may be formed by connecting a plurality of frames together and may have an opening therein. In this case, the mask frame 421 may have one opening or a plurality of openings separated from each other. In such a case, the mask frame 421 may be formed in a lattice shape like a window frame. For convenience of explanation, the following detailed description will be given focusing on the case where the mask frame 421 has one opening in the center.

[0288] The mask sheet 422 may be fixed to the mask frame 421 in a tensioned state. In this case, an opening may be formed in the mask sheet 422 to allow the deposition material to pass through. A single mask sheet 422 or multiple mask sheets 422 may be provided. When a single mask sheet 422 is provided, the mask sheet 422 is also disposed on the mask frame 421. In another embodiment, when multiple mask sheets 422 are provided, the multiple mask sheets 422 are disposed adjacent to each other along one side of the mask frame 421 and are also disposed on the mask frame 421. For example, the multiple mask sheets 422 may be disposed adjacent to each other in the x direction or y direction of FIG. 18. For convenience of explanation, the following detailed description will focus on the case where a single mask sheet 422 is provided.

[0289] The mask assembly 420 as described above may further include a support frame (not shown) disposed on the mask frame 421 in addition to the mask frame 421 and the mask sheet 422. The support frame may also be disposed in the opening of the mask frame 421. When a plurality of mask sheets 422 are provided, the support frame may shield adjacent mask sheets 422 or may be arranged perpendicular to the longitudinal direction of the mask sheets 422. In another embodiment, when a single mask sheet 422 is provided, the support frame may be disposed so as to overlap a structure disposed inside the mask sheet 422, thereby supporting the mask sheet 422. For convenience of explanation, the mask assembly 420 will be described in detail below, focusing on a case where the support frame is not disposed.

[0290] The mask assembly 420 as described above can also be manufactured by bonding the mask sheet 422 onto the mask frame 421. In this case, the mask sheet 422 may be fixed to the mask frame 421 by welding in a tensioned state.

[0291] The substrate 100 may be placed on the first support part 430. At this time, the first support part 430 may adjust the position of the substrate 100. For example, the first support part 430 may include a UVW stage.

[0292] The mask assembly 420 may be placed on the second support part 440. In this case, the second support part 440 is similar to the first support part 430 and allows the position of the mask assembly 420 to be adjusted.

[0293] At least one of the first support part 430 and the second support part 440 may be raised and lowered within the chamber 410. In such a case, at least one of the first support part 430 and the second support part 440 may adjust the distance between the display substrate D and the mask frame 421.

[0294] The deposition source 450 may store a deposition material, vaporize or sublimate the deposition material, and supply the vaporized material to the chamber 410. The deposition source 450 may include a heater therein, and the heater may be operated to heat the deposition material inside the deposition source 450, thereby vaporizing or sublimating the deposition material. In the above case, the deposition source 450 may be disposed at the center or edge of the chamber 410. For convenience of explanation, the following description will be focused on the case where the deposition source 450 is disposed at the edge of the chamber 410.

[0295] The magnetic force generator 460 is disposed in the chamber 410 and can closely contact the substrate 100 and the mask assembly 420. In this case, the magnetic force generator 460 may include an electromagnet or a permanent magnet that generates a magnetic force.

[0296] The vision unit 470 is disposed in the chamber 410 and can photograph the positions of the mask assembly 420 and the substrate 100. In this case, the vision unit 470 can photograph an alignment mark of at least one of the mask assembly 420 and the substrate 100.

[0297] The pressure adjusting unit 480 is connected to the chamber 410 and can adjust the pressure inside the chamber 410. In this case, the pressure adjusting unit 480 may include a connection pipe 481 connected to the chamber 410 and a pump 482 disposed in the connection pipe 481.

[0298] Regarding the operation of the display device manufacturing apparatus 400 described above, the display substrate D and the mask assembly 420 can be carried into the chamber 410. At this time, the display substrate D may be a structure in which layers from the buffer layer 111 to the organic functional layer 122e are stacked on the substrate 100, as shown in FIGS.

[0299] The vision unit 470 photographs the positions of the display substrate D and the mask assembly 420, and based on the photograph, the positions of at least one of the display substrate D and the mask assembly 420 can be adjusted to align the positions of the display substrate D and the mask assembly 420. Thereafter, the magnetic force generating unit 460 can be used to bring the mask assembly 420 and the display substrate D into close contact with each other.

[0300] When the deposition source 450 supplies a deposition material, the deposition material may pass through the mask assembly 420 and be deposited on the display substrate D. At this time, the deposition material may be deposited on the display substrate D to form a main sub-pixel counter electrode (not shown) and an auxiliary sub-pixel counter electrode (not shown). In this case, the pressure adjusting unit 480 may exhaust gas from the chamber 410 to the outside.

[0301] As described above, when the auxiliary subpixel counter electrodes are formed on the display substrate D, the auxiliary subpixel counter electrodes may be formed in a line shape. In this case, a plurality of the auxiliary subpixel counter electrodes are provided, and the plurality of auxiliary subpixel counter electrodes are arranged to be spaced apart from each other and connected to the main subpixel counter electrode. In such a case, each auxiliary subpixel counter electrode is formed long in one direction and connected to the main subpixel counter electrode.

[0302] As described above, after forming each counter electrode, the upper layer and the sealing member are sequentially formed on the counter electrode, thereby completing the display device.

[0303] Therefore, the display device manufacturing apparatus 400 can form the auxiliary sub-pixel counter electrodes on the display substrate D with a precise pattern by using the mask assembly 420 with minimized deformation.

[0304] Figure 19 is a perspective view showing a mask assembly according to an embodiment of the present invention. Figures 20A to 20C are plan views showing a method for manufacturing the mask sheet shown in Figure 19. Figure 20D is a cross-sectional view taken along line A-A' in Figure 20C.

[0305] 19 to 20D, a mask frame 421 may have a frame opening 421a in the center through which a deposition material passes. A mask sheet 422 may be disposed on the mask frame 421 to cover the frame opening 421a of the mask frame 421.

[0306] The mask sheet 422 may include a sheet body portion 422a that is arranged on the mask frame 421 and includes at least one first opening 422a-1, and a sheet blocking portion 422b that protrudes toward the first opening 422a-1 and is connected to the sheet body portion 422a.

[0307] The seat body portion 422a may have various shapes. For example, the seat body portion 422a may have a shape in which a single first opening 422a-1 is formed in the center. In another embodiment, the seat body portion 422a may have a window frame shape with a plurality of first openings 422a-1. In such a case, the seat body portion 422a may include seat support ribs 422c disposed between adjacent first openings 422a-1. The seat support ribs 422c are disposed between the first openings 422a-1 and are connected to the outermost periphery of the seat body portion 422a.

[0308] The sheet blocking portion 422b may include a slit-shaped second opening 422b-1. In such a case, a plurality of second openings 422b-1 may be provided. Each second opening 422b-1 may be elongated in the first direction (-y direction (FIG. 20B)). The plurality of second openings 422b-1 may also be spaced apart from each other in the second direction (x direction (FIG. 20B)).

[0309] The sheet blocking portion 422b may be located at various positions. For example, it may be located so as to protrude from the outermost edge of the sheet body portion 422a or the outer surface of the sheet support rib 422c. In such a case, the sheet blocking portion 422b may be connected to the outermost edge of the sheet body portion 422a or the sheet support rib 422c arranged in the first or second direction.

[0310] The width of the second opening 422b-1 is wider than the distance (or width) between adjacent second openings 422b-1. In this case, the width of the second opening 422b-1 and the distance (or width) between adjacent second openings 422b-1 are measured in the x-direction with reference to FIG. 20C. A sheet blocking rib 422b-2 may be disposed between the second openings 422b-1. In this case, the width of the sheet blocking rib 422b-2 is narrower than the width of the second opening 422b-1. In this case, the width of the sheet blocking rib 422b-2 may refer to the distance (or width) between adjacent second openings 422b-1. In this case, the distance (or width) between the second openings 422b-1 may be approximately 100 μm or less.

[0311] Meanwhile, in the method of manufacturing the mask assembly 420 described above, a plate-shaped base material MA can be prepared. Then, a portion of the base material MA can be removed to form the first opening 422a-1. In this case, a photoresist can be disposed on the base material MA, and the first opening 422a-1 can be formed through chemical etching. In this case, the photoresist can be either positive or negative. In another embodiment, the first opening 422a-1 can be formed by removing a portion of the base material MA using a laser.

[0312] As described above, when the first openings 422a-1 are formed in the base material MA, the sheet body portion 422a, the sheet support rib 422c, and the sheet blocking portion 422b remain. At this time, as described above, the sheet blocking portion 422b is also positioned so as to protrude into the inside of each first opening 422a-1.

[0313] As described above, once the sheet blocking portion 422b is positioned, the laser irradiation portion LS can be positioned above the sheet blocking portion 422b, and the laser can be emitted from the laser irradiation portion LS to irradiate the laser. In this case, the laser irradiation portion LS can form a second opening 422b-1 on the sheet blocking portion 422b by irradiating the sheet blocking portion 422b with a laser. Such a second opening 422b-1 can also be formed in a slit shape, as described above.

[0314] The mask sheet 422, in which the first opening 422a-1 and the second opening 422b-1 are formed, is placed on the mask frame 421 in a stretched state, and then the mask sheet 422 and the mask frame 421 can be aligned. Thereafter, the sheet body portion 422a is brought into contact with the mask frame 421, and then they can be fixed by welding.

[0315] The mask assembly 420 described above is also used in the manufacturing apparatus for the display device described above. In such a case, the mask assembly 420 can precisely form the pattern of the second openings 422b-1 even when the spacing between adjacent second openings 422b-1 is 100 μm or less. Furthermore, even when the spacing between the second openings 422b-1 is 100 μm or less, the mask assembly 420 can not only completely separate the adjacent second openings 422b-1 but also form the second openings 422b-1 with an accurate shape.

[0316] When forming a counter electrode using the mask assembly 420 described above, the frame (periphery) portion of the sheet blocking portion 422b is formed sufficiently thin so that an auxiliary subpixel counter electrode (not shown) deposited on a display substrate (not shown) can be connected to each other through the second opening 422b-1 located at the outermost edge of the sheet blocking portion 422b and the main subpixel counter electrode (not shown) deposited on the display substrate through the first opening 422a-1. That is, when a deposition material moves from the deposition source 470 shown in FIG. 18 to the mask assembly 420, some of the deposition material is deposited on the display substrate located behind the frame region of the sheet blocking portion 422b, thereby connecting the deposition material deposited on the display substrate through the first opening 422a-1 and the deposition material deposited on the display substrate through the second opening 422b-1. In particular, in this case, the width of the portion of the sheet blocking portion 422b located on the frame is narrower than the width of the sheet blocking rib 422b-2. In this case, the width of the portion of the sheet blocking portion 422b arranged in the frame can be measured in the y direction at the bottom and in the x direction at the left and right sides, based on Fig. 20C. In particular, the width of the portion of the sheet blocking portion 422b arranged in the frame can be the linear distance from the outermost edge of the sheet blocking portion 422b to the second opening 422b-1.

[0317] Figure 21 is a perspective view showing a mask assembly according to another embodiment of the present invention. Figures 22A and 22B are plan views showing a method of manufacturing the stick shown in Figure 21. Figure 22C is a cross-sectional view taken along line BB' in Figure 22B.

[0318] 21 to 22C, the mask assembly 420 may not include a mask sheet (not shown) in addition to the above-mentioned cases. Specifically, the mask assembly 420 may include a mask frame 421 and sticks 423 and 424.

[0319] The mask frame 421 may include a frame opening 421a in the center thereof. In this case, a hole is formed in the center of the mask frame 421, and multiple frames can be connected to each other to form a closed loop.

[0320] The sticks 423 and 424 are connected to the mask frame 421 and may divide the frame opening 421a into at least two or more sections. In this case, the sticks 423 and 424 may be arranged in a first direction and / or a second direction. Specifically, the sticks 423 and 424 may be arranged in a first direction (either the x-direction or the y-direction), for example. The sticks 423 and 424 may be arranged in a second direction (the other of the x-direction or the y-direction), for example. For example, the sticks 423 and 424 may include a first stick 424 arranged in the first direction and a second stick 423 arranged in the second direction. In this case, the first stick 424 and the second stick 423 may have the same or similar shapes. For convenience of explanation, the following detailed description will focus on the first stick 424.

[0321] The first stick 424 may include a first stick body portion 424a and a first stick blocking portion 424b protruding from the first stick body portion 424a. In this case, the first stick body portion 424a is formed in a plate shape and is also disposed on the mask frame 421. In this case, the first stick body portion 424a is also fixed to the mask frame 421 in a tensioned state.

[0322] The first stick blocking portion 424b may protrude from the first stick body portion 424a. In this case, the first stick blocking portion 424b may protrude into the adjacent first stick body portion 424a or into the frame opening 421a defined by the adjacent first stick body portion 424a and the mask frame 421. The first stick blocking portion 424b may include a first stick opening 424b-1. The first stick opening 424b-1 may be formed in a slit shape, similar to that shown in FIG. 20C. In other embodiments, the first stick opening 424b-1 may have various shapes other than a slit shape, such as a square, diamond, rectangle, square, polygon, circle, or ellipse. However, for ease of explanation, the following description will focus on the case where the first stick opening 424b-1 is slit-shaped.

[0323] As described above, when the first stick opening 424b-1 is slit-shaped, the distance (or width) between adjacent first stick openings 424b-1 may be 100 μm or less. In particular, when the first stick opening 424b-1 is slit-shaped, a first stick blocking rib 424b-2 may be disposed between adjacent first stick openings 424b-1. In such a case, the width of the first stick blocking rib 424b-2 is narrower than the width of the first stick opening 424b-1. In this case, the width of the first stick blocking rib 424b-2 may be the distance (or width) between adjacent first stick openings 424b-1.

[0324] Regarding the manufacturing method of the mask assembly 420 as described above, first, the mask assembly 420 can be manufactured by connecting or welding a plurality of frames to each other and manufacturing the mask assembly 420 so as to have a frame opening 421a in the center.

[0325] Thereafter, the first stick 424 and the second stick 423 can be placed in a tensioned state in the mask assembly 420 and fixed to the mask frame 421 by welding. In such a case, the first stick 424 is arranged in the first direction as described above, and the second stick 423 is arranged in the second direction, and they are also arranged so as to define at least two or more frame openings 421a.

[0326] The first stick 424 as described above is manufactured in the form shown in Fig. 21 and is also fixed to the mask frame 421. Specifically, a member including the first stick body portion 424a and the first stick blocking portion 424b is separated from a plate-shaped base material MA (Fig. 20A). At this time, methods for separating the first stick body portion 424a and the first stick blocking portion 424b from the base material MA can be press processing, chemical etching, laser cutting, etc.

[0327] After the above process is completed, the first stick blocking portion 424b is irradiated with laser light through the laser irradiation unit LS to form the first stick opening 424b-1.

[0328] As described above, when the first stick openings 424b-1 are formed using a laser, it is possible to form the first stick openings 424b-1 with an accurate shape. Furthermore, by forming the first stick openings 424b-1 using a laser, defects such as adjacent first stick openings 424b-1 being connected to each other do not occur even when the distance (or width) between adjacent first stick openings 424b-1 is formed to be 100 μm or less.

[0329] The second stick 423 is separated from the base material MA by laser, press processing, etching, etc. At this time, the second stick 423 may be in the shape of a plate.

[0330] The shape of the opening area defined on the outer surface of the first stick 424 and the second stick 423 as described above is also formed to correspond to the frame (periphery) of the main display area MDA. Alternatively, the shape of the opening area defined by the first stick 424, the second stick 423 and the mask frame 421 may be formed to correspond to the frame of the main display area MDA.

[0331] The first stick blocking portion 424b may be the same as or similar to the sheet blocking portion 422b described above with reference to Figures 19 to 20C. Therefore, when a counter electrode is formed on a display substrate (not shown) by depositing a deposition material on the display substrate, the auxiliary subpixel counter electrode formed on the display substrate and the main subpixel counter electrode formed in the main display region (not shown) may be connected to each other by passing through the first stick opening 424b-1.

[0332] Figure 23A is a plan view that schematically illustrates a method for patterning a counter electrode according to one embodiment, and Figure 23B is an enlarged plan view of part AI of Figure 23A.

[0333] 23A and 23B, the counter electrode 123 may be formed using the mask assembly shown in Fig. 19 or 21. For example, the counter electrode 123 may be formed by disposing a display substrate (not shown) including the organic functional layer 122e from the substrate 100 shown in Figs. 12 to 16 in the display device manufacturing apparatus 400 shown in Fig. 18 and depositing the organic functional layer 122e on the display device. In this case, the counter electrode 123 may be formed over the entire main display area MDA or only in a portion of the component area CA using the mask assembly 420 shown in Fig. 19 or the mask assembly 420 shown in Fig. 21.

[0334] Specifically, the counter electrode 123 is deposited so as to cover the main display area MDA and also cover part of the component area CA. At this time, the main subpixel counter electrode 123-1 is also disposed so as to cover the entire surface of the main display area MDA.

[0335] A plurality of auxiliary subpixel counter electrodes 123-2 may be arranged in the component area CA, spaced apart from one another. In such a case, the auxiliary subpixel counter electrodes 123-2 may be formed in a line shape, as shown in FIG. 23A. In the above-described case, the auxiliary subpixel counter electrodes 123-2 are also arranged over adjacent auxiliary subpixels. In particular, the auxiliary subpixel counter electrodes 123-2 are arranged to cover the auxiliary pixel groups PGU shown in FIGS. 11A, 11B, and 11C. Furthermore, the auxiliary subpixel counter electrodes 123-2 are not arranged in the transmissive region TA of FIGS. 11A, 11B, and 11C. In this case, the auxiliary subpixel counter electrodes 123-2 may cover the auxiliary subpixel intermediate layers of the auxiliary subpixels of the subpixel group PGU. In such a case, the auxiliary subpixel counter electrodes 123-2 are also arranged on at least two or more auxiliary subpixel intermediate layers.

[0336] The auxiliary subpixel counter electrode 123-2 described above is also arranged to cover multiple auxiliary pixel groups PGU. In such a case, the width WI1 of the auxiliary subpixel counter electrode 123-2 is wider than the distance (or width WI2) between adjacent auxiliary subpixel counter electrodes 123-2. In this case, the widths WI1 and WI2 described above are also measured in the x direction with reference to FIG. 23B.

[0337] In the case described above, the auxiliary subpixel counter electrodes 123-2 are not arranged in the transmissive area TA of the component area CA. The auxiliary subpixel counter electrodes 123-2 can also be arranged in a striped pattern.

[0338] Therefore, the display device can realize an auxiliary image in the component area CA while ensuring a sufficient transmissive area TA.

[0339] FIG. 24 is a plan view showing a sheet blocking unit according to another embodiment of the present invention.

[0340] 24, the sheet blocking portion 422b is positioned to be completely inserted into the first opening 422a-1. In this case, the sheet blocking portion 422b is also connected to the mask sheet 422 from the periphery (edge) of the first opening 422a-1 via a separate sheet connecting member 422d. In this case, the width of the sheet connecting member 422d is narrower than the width between adjacent second openings 422b-1. In particular, the width of the sheet connecting member 422d is so narrow that when a deposition material is supplied from a deposition source (not shown), the deposition material reaches the rear surface of the sheet connecting member 422d. In this case, even if the deposition material reaches a member positioned below the sheet connecting member 422d depending on the direction of incidence of the deposition material, it is deposited.

[0341] In this case, the manufacturing method of the mask sheet 422 can be similar to that described above with reference to Figures 20A to 20D. That is, the sheet connecting member 422d and the sheet blocking portion 422b can be formed while forming a first opening (not shown) in a base material (not shown). In this case, the sheet connecting member 422d is also disposed within the first opening to connect the sheet blocking portion 422b and the sheet body portion 422a. Then, a second opening 422b-1 can be formed in the sheet blocking portion 422b using a laser.

[0342] FIG. 25 is a plan view showing a stick blocking unit according to still another embodiment of the present invention.

[0343] 25, a mask assembly (not shown) may include a mask frame (not shown) and a stick (not shown). In this case, the stick may include a first stick (not shown) and a second stick (not shown) as described in FIG. 21. In this case, the stick blocking unit may be provided in the first stick and / or the second stick, but for convenience of explanation, the following description will be focused on the case where the stick blocking unit is provided in the first stick.

[0344] The first stick blocking portion 424b is connected to the first stick body portion 424a by the first stick connecting member 424c. In this case, the first stick connecting member 424c is also disposed in a cantilevered manner from the first stick body portion 424a. In this case, for example, the width (measured in the x direction) of the first stick connecting member 424c is so narrow that the deposition material supplied from a deposition source (not shown) can move to the rear surface of the first stick connecting member 424c. In particular, in this case, when the deposition material supplied from the deposition source moves to the mask assembly, a portion of the deposition material that is not obstructed by the first stick connecting member 424c can move to the rear surface of the first stick connecting member 424c.

[0345] In the above-mentioned case, by arranging the first stick blocking portion 424b inside the frame opening 421a defined by the seat support rib 422c, it is possible to form a component area (not shown) inside the main display area (not shown).

[0346] In this case, the first stick may be manufactured in a manner similar to that described above with reference to Figures 22A to 22C. For example, the first stick body portion 424a, the first stick connecting member 424c, and the first stick blocking portion 424b may be separated from a base material (not shown). Then, the first stick opening 424b-1 may be formed in the first stick blocking portion 424b using a laser.

[0347] FIG. 26 is a plan view showing a first stick blocking unit according to still another embodiment of the present invention.

[0348] 26, the first stick blocking portion 424b may include a first stick opening 424b-1. In this case, the first stick opening 424b-1 may also be formed in a serpentine shape. In this case, the auxiliary subpixel counter electrodes (not shown) formed on the display substrate (not shown) passing through the first stick opening 424b-1 may also be arranged in a serpentine shape on the display substrate. In this case, the auxiliary subpixels (not shown) may also be arranged in a serpentine shape. In another embodiment, in the above case, the auxiliary pixel groups shown in FIGS. 11A to 11C may also be arranged in a serpentine shape.

[0349] The first stick opening 424b-1 as described above is also formed via a laser as described above.

[0350] The mask assembly is therefore capable of producing the display device including the component areas with precise patterns.

[0351] FIG. 27 is a plan view showing a first stick blocking unit according to still another embodiment of the present invention.

[0352] 27, the first stick blocking portion 424b may include a first stick opening 424b-1. The first stick opening 424b-1 may include a first subpixel opening 424b-1a formed to correspond to each subpixel and a first connecting opening 424b-1b connecting the first subpixel openings 424b-1a. A plurality of first subpixel openings 424b-1a may be provided, and the plurality of first subpixel openings 424b-1a may be formed to correspond to the shapes of the subpixels illustrated in FIGS. 11A and 11B. In this case, some of the plurality of first subpixel openings 424b-1a, other portions of the plurality of first subpixel openings 424b-1a, and the remainder of the plurality of first subpixel openings 424b-1a may have different shapes and sizes. The first connecting openings 424b-1b may be disposed between a plurality of first subpixel openings 424b-1a to connect the first subpixel openings 424b-1a to one another. In such a case, the first connecting openings 424b-1b may also be disposed between adjacent first subpixel openings 424b-1a. The first connecting openings 424b-1b not only connect the first subpixel openings 424b-1a to one another but also connect them to a frame opening (not shown).

[0353] In the above case, when an auxiliary subpixel counter electrode (not shown) and a main subpixel counter electrode (not shown) are formed on a display substrate (not shown), not only can the auxiliary subpixel counter electrode be arranged to correspond to the position of the auxiliary subpixel arranged in the component region (not shown), but the auxiliary subpixel counter electrode and the main subpixel counter electrode can also be connected to each other.

[0354] The mask assembly is therefore capable of producing the display device including the component areas with precise patterns.

[0355] As described above, the present invention has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Therefore, the true technical scope of protection of the present invention is defined by the technical spirit of the claims. [Explanation of symbols]

[0356] 1 Display device 10 Display panel 30 Display circuit board 40 Components 50 Cover Window 60 Bracket 70 Main Circuit Board 80 Battery 90 Lower cover 100 boards 400 Display device manufacturing equipment 410 Chamber 420 Mask assembly 421 Mask Frame 422 Mask Sheet 423 Second Stick 424 First Stick 430 1st support part 440 Second support part 450 Vapor deposition source 460 Magnetic force generating unit 470 Vision Department 480 Pressure adjustment unit

Claims

[Claim 1] a substrate including a component area, a main display area, and a peripheral area within which the component area and the main display area are disposed; a sub-pixel group disposed in the component region, the sub-pixel group including a sub-sub-pixel pixel electrode, a sub-sub-pixel intermediate layer, and a sub-sub-pixel counter electrode; a main pixel group disposed in the main display area, the main pixel group including a main subpixel pixel electrode, a main subpixel intermediate layer, and a main subpixel counter electrode; The auxiliary sub-pixel counter electrodes are stripe-shaped and extend across the component regions, connected to the main sub-pixel counter electrodes on the main display region.

Images