Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device that improves a switching characteristic and reduces a leakage current.SOLUTION: A semiconductor device includes: a drift region 18 of a first conductivity type provided in a semiconductor substrate; a buffer region 20 of the first conductivity type provided on a back surface side of the semiconductor substrate with respect to the drift region and having a first peak 61 of a doping concentration; and a first lattice defect region 161 provided on a front surface side of the semiconductor substrate with respect to the first peak in a depth direction of the semiconductor substrate and having a recombination center. The buffer region is provided on the front surface side of the semiconductor substrate with respect to the first lattice defect region and has a hydrogen peak 62 having a peak hydrogen chemical concentration distribution, and an integrated concentration obtained by integrating the doping concentration in a direction from an upper end of the drift region to the hydrogen peak in the depth direction of the semiconductor substrate is equal to or higher than a critical integrated concentration.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices having peaks formed by hydrogen ion implantation are known (for example, Patent Documents 1, 2 and 3). [Prior art document] [Patent documents] Patent Document 1: International Publication No. 2019 / 181852 Patent Document 2: JP 2018-107303 A Patent Document 3: JP 2022-035157 A

[0003] [Problem to be solved] It is desirable to improve the switching characteristics of semiconductor devices and reduce leakage current.

[0004] [General Disclosure] In a first aspect of the present invention, there is provided a semiconductor device comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a buffer region of the first conductivity type provided on the back surface side of the semiconductor substrate relative to the drift region and having a first peak of doping concentration; and a first lattice defect region provided on the front surface side of the semiconductor substrate relative to the first peak in the depth direction of the semiconductor substrate and having a recombination center, wherein the buffer region is provided on the front surface side of the semiconductor substrate relative to the first lattice defect region and has a hydrogen peak where the hydrogen chemical concentration distribution is at its peak, and the integrated concentration obtained by integrating the doping concentration in the depth direction of the semiconductor substrate from the top end of the drift region in the direction to the hydrogen peak is equal to or greater than a critical integrated concentration.

[0005] In the semiconductor device, the first peak may be the peak closest to the rear surface of the semiconductor substrate among a plurality of peaks that the buffer region has.

[0006] In any of the above semiconductor devices, the hydrogen peak may include a second peak, which is next to the first peak and closest to the rear surface of the semiconductor substrate, among a plurality of peaks possessed by the buffer region.

[0007] In any of the above semiconductor devices, the first lattice defect region may be provided between the first peak and the second peak in the depth direction of the semiconductor substrate.

[0008] In any of the above semiconductor devices, the recombination center density on the back surface side of the semiconductor substrate relative to the hydrogen peak may be greater than the recombination center density in the drift region on the side adjacent to the hydrogen peak.

[0009] In any of the above semiconductor devices, the distance between the first peak and the second peak in the depth direction of the semiconductor substrate may be 5.0 μm or more and may be half or less of the thickness of the semiconductor substrate in the depth direction.

[0010] In any of the above semiconductor devices, the buffer region may have a first peak and a plurality of hydrogen peaks formed by ion implantation of hydrogen.

[0011] In any of the above semiconductor devices, the first lattice defect region may be provided between a plurality of hydrogen peaks in the depth direction of the semiconductor substrate.

[0012] Any of the above semiconductor devices may include a second lattice defect region located between a plurality of hydrogen peaks and closer to the front surface of the semiconductor substrate than the first lattice defect region in the depth direction of the semiconductor substrate.

[0013] In any of the above semiconductor devices, the doping concentration of the hydrogen peak is 1.0E14 cm -3 Above, 1.0E16cm -3 It may be the following:

[0014] Any of the above semiconductor devices may include a first lifetime control region provided closer to the front surface of the semiconductor substrate than the first peak in the depth direction of the semiconductor substrate.

[0015] In any of the above semiconductor devices, the first lifetime control region may contain helium.

[0016] In any of the above semiconductor devices, the peak position of the first lifetime control region may be closer to the back surface of the semiconductor substrate than the hydrogen peak in the depth direction of the semiconductor substrate.

[0017] In any of the above semiconductor devices, the peak position of the first lifetime control region may be between the first lattice defect region and the hydrogen peak in the depth direction of the semiconductor substrate.

[0018] In any of the above semiconductor devices, the peak position of the first lifetime control region may be located closer to the back surface of the semiconductor substrate than the first lattice defect region in the depth direction of the semiconductor substrate.

[0019] In any of the above semiconductor devices, the peak position of the first lifetime control region may be between the hydrogen peak and the drift region in the depth direction of the semiconductor substrate.

[0020] In any of the above semiconductor devices, the dopant of the first peak may be phosphorus.

[0021] In any of the above semiconductor devices, the dopant of the first peak may be hydrogen.

[0022] A second aspect of the present invention provides a method for manufacturing a semiconductor device, including the steps of forming a drift region of a first conductivity type in a semiconductor substrate, forming a buffer region of the first conductivity type having a first peak of doping concentration on the back surface side of the semiconductor substrate relative to the drift region, and forming a first lattice defect region formed by hydrogen ion implantation on the front surface side of the semiconductor substrate relative to the first peak in the depth direction of the semiconductor substrate. The step of forming the buffer region may include the step of forming a hydrogen peak provided on the front surface side of the semiconductor substrate relative to the first lattice defect region and formed by hydrogen ion implantation. An integrated concentration obtained by integrating the doping concentration in the depth direction of the semiconductor substrate from the top end of the drift region in a direction to the hydrogen peak may be equal to or greater than a critical integrated concentration.

[0023] The method for manufacturing a semiconductor device may include a step of ion-implanting hydrogen to form a first lattice defect region after annealing to form the first peak.

[0024] Any of the above methods for manufacturing a semiconductor device may include a step of simultaneously performing annealing to form the first peak and the first lattice defect region after the ion implantation to form the first lattice defect region.

[0025] Any of the above methods for manufacturing a semiconductor device may include a step of performing annealing to form the first lattice defect region at a temperature lower than that of annealing to form the first peak.

[0026] Any of the above methods for manufacturing a semiconductor device may include a step of performing annealing to form the first lattice defect region for a time shorter than that of annealing to form the first peak.

[0027] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0028] [Figure 1A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 1B] 1B shows an example of a cross section taken along the line aa' in FIG. 1A. [Figure 2A] An example of the doping concentration distribution in the collector region 22, the buffer region 20 and the drift region 18 is shown. [Figure 2B] A modified example of the semiconductor device 100 is shown. [Figure 2C] A modified example of the semiconductor device 100 is shown. [Figure 2D] A modified example of the semiconductor device 100 is shown. [Figure 2E] A modified example of the semiconductor device 100 is shown. [Figure 2F] A modified example of the semiconductor device 100 is shown. [Figure 2G] 10 shows a modified example of the doping concentration distribution of the first lattice defect region 161. [Figure 2H] 10 shows a modified example of the doping concentration distribution of the first lattice defect region 161. [Figure 3A] An example of a semiconductor device 100 including a first lifetime control region 151 is shown. [Figure 3B] 1 shows a modified example of the semiconductor device 100 having a first lifetime control region 151. [Figure 3C] 1 shows a modified example of the semiconductor device 100 having a first lifetime control region 151. [Figure 3D] 1 shows a modified example of the semiconductor device 100 having a first lifetime control region 151. [Figure 3E] 1 shows a modified example of the semiconductor device 100 having a first lifetime control region 151. [Figure 3F] 1 shows a modified example of the semiconductor device 100 having a first lifetime control region 151. [Figure 3G] 1 shows a modified example of the semiconductor device 100 having a first lifetime control region 151. [Figure 3H] 1 shows a modified example of the semiconductor device 100 having a first lifetime control region 151. [Figure 3I]1 shows a modified example of the semiconductor device 100 having a first lifetime control region 151. [Figure 4] An example of a doping concentration distribution in the semiconductor substrate 10 is shown. [Figure 5A] 1 shows a top view of a modified example of the semiconductor device 100. FIG. [Figure 5B] 1 shows a cross section taken along the line bb' of a modified example of the semiconductor device 100. [Figure 6A] 3 is a flowchart showing an example of a manufacturing process for the semiconductor device 100. [Figure 6B] 10 is a flowchart showing a modified example of the manufacturing process of the semiconductor device 100. [Figure 6C] 10 is a flowchart showing a modified example of the manufacturing process of the semiconductor device 100. [Figure 7] 2 is a diagram for explaining the electrical characteristics of the semiconductor device 100. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0030] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0031] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0032] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0033] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0034] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0035] In this specification, the doping concentration refers to the concentration of electrically activated donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D-N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0036] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor. In other words, when hydrogen supplies electrons and the defect functions as a donor, it may be referred to as a hydrogen donor.

[0037] In this specification, N-type bulk donors are distributed throughout the semiconductor substrate. The bulk donors are donors due to dopants that are uniformly contained in the ingot during the production of the ingot that is the basis for the semiconductor substrate. In this example, the bulk donor is an element other than hydrogen. The dopant of the bulk donor is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited to these. In this example, the bulk donor is phosphorus. The bulk donor may also be contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method may be 1×10 15 ~5×10 16 / cm 3The higher the oxygen concentration, the easier it is to generate hydrogen donors. The bulk donor concentration may be expressed using the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of that chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 10 / cm 3 That's it, 5 x 10 12 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 12 / cm 3 The concentrations in the present invention may be values ​​at room temperature. For example, the values ​​at room temperature may be values ​​at 300 K (Kelvin) (approximately 26.9°C). The semiconductor substrate may contain acceptor atoms throughout the semiconductor substrate at a concentration lower than the bulk donor concentration. In this case, the conductivity type of the semiconductor substrate is N-type.

[0038] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0039] As used herein, chemical concentration refers to the atomic density of an impurity measured regardless of its electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance (CV) measurement. The carrier concentration measured by spreading resistance (SR) measurement may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as the value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is significantly greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0040] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3 This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0041] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0042] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is approximately 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI system of units is used. In this specification, distance and length may be expressed in centimeters (cm). In this case, various calculations may be performed by converting them to meters (m).

[0043] 1A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70.

[0044] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT.

[0045] FIG. 1A shows the region around the chip edge, which is the edge side of semiconductor device 100, and omits other regions. For example, an edge termination structure may be provided in the region on the negative side of semiconductor device 100 in the Y-axis direction in this example. The edge termination structure reduces electric field concentration on the upper surface side of semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, this example describes the edge on the negative side of the Y-axis direction, but the same applies to other edges of semiconductor device 100.

[0046] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0047] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on a front surface 21 of a semiconductor substrate 10. The front surface 21 will be described later. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0048] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.

[0049] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium or a titanium compound below the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0050] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0051] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion in the transistor portion 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed.

[0052] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug made of tungsten or the like may be formed.

[0053] The connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material, such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film, such as an oxide film.

[0054] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0055] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0056] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). Like the gate trench portion 40, the dummy trench portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0057] The transistor section 70 of this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a ratio of 2:3. For example, the transistor section 70 has one extension section 31 between two extension sections 41. The transistor section 70 also has two extension sections 31 adjacent to the gate trench section 40.

[0058] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1 or 2:4. Furthermore, the transistor portion 70 may have all trench portions as gate trench portions 40 and no dummy trench portions 30.

[0059] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 described below. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0060] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0061] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0062] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0063] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0064] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0065] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0066] The contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the contact region 15 is, for example, a P+ type. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0067] 1B shows an example of the a-a' cross section in FIG. 1A. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0068] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration D dr may be the doping concentration of the semiconductor substrate 10.

[0069] The buffer region 20 is a region of a first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is, for example, an N-type. The doping concentration of the buffer region 20 is set to a value equal to the doping concentration D dr The doping concentration of the buffer region 20 may be higher than the bulk donor concentration. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type.

[0070] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has the second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0071] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.

[0072] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0073] The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0074] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example is, for example, an N+ type. However, the accumulation region 16 does not necessarily have to be provided.

[0075] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is set to be equal to the doping concentration D dr The dose of the ion implantation in the accumulation region 16 is 1.0E12 cm -2 More than 1.0E13cm -2 The ion implantation dose of the accumulation region 16 may be 3.0E12 cm -2 Above, 6.0E12cm -2 By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced. Note that E represents a power of 10, and for example, 1.0E12 cm -2 is 1.0 x 10 12 cm -2 means.

[0076] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0077] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0078] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0079] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0080] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0081] The first lattice defect region 161 is a region containing lattice defects formed by hydrogen ion implantation from the back surface 23 side. The first lattice defect region 161 functions as a lifetime killer. The first lattice defect region 161 can reduce the turn-off time of the semiconductor device 100 and suppress the tail current, thereby reducing losses during switching. Details of the first lattice defect region 161 will be described later. Whether the first lattice defect region 161 is formed by hydrogen ion implantation can be determined by analyzing the chemical concentration of the semiconductor device 100, for example. For example, a lifetime killer formed by helium ion implantation can be identified by detecting helium.

[0082] A lifetime killer is a recombination center of charge carriers. In this specification, charge carriers may be simply referred to as carriers. A lifetime killer may be a lattice defect. For example, a lifetime killer may be a vacancy, a divacancy, a complex defect of a vacancy or a divacancy with an element constituting the semiconductor substrate 10, or a dislocation. That is, the first lattice defect region 161 is a region including a recombination center.

[0083] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, or may be the concentration of complex defects between these vacancies and elements constituting the semiconductor substrate 10, or may be the concentration of dislocations. In other words, the first lattice defect region 161 may be a region containing lifetime killers.

[0084] The first lifetime control region 151 is a region in which a lifetime killer is intentionally formed by, for example, injecting impurities into the semiconductor substrate 10. A rare gas element such as helium or neon may be used as the lifetime killer. The lifetime killer concentration is the concentration of recombination centers, but it may also be the chemical concentration of a rare gas element such as helium or neon. In this example, the first lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10.

[0085] The first lifetime control region 151 is provided closer to the back surface 23 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the first lifetime control region 151 is provided in the buffer region 20. When the first lifetime control region 151 is formed over the entire surface of the semiconductor substrate 10 in the XY plane, it can be formed without using a mask. The first lifetime control region 151 may also be provided in a part of the semiconductor substrate 10 in the XY plane using a mask of a predetermined shape.

[0086] Furthermore, first lifetime control region 151 in this example is formed by implantation from the back surface 23 side. This makes it possible to avoid any influence on the front surface 21 side of semiconductor device 100. For example, first lifetime control region 151 is formed by irradiating helium from the back surface 23 side. Here, whether first lifetime control region 151 is formed by implantation from the front surface 21 side or the back surface 23 side can be determined by obtaining the state of semiconductor substrate 10 using the SR method or by measuring collector-emitter leakage current. Note that collector-emitter leakage current may also be simply referred to as leakage current.

[0087] 2A shows an example of the doping concentration distribution in the collector region 22, the buffer region 20, and the drift region 18. Note that the doping concentration distribution in the collector region 22, the buffer region 20, and the drift region 18 shows the net doping concentration obtained by combining the concentrations of each impurity.

[0088] The collector region 22 may have a depth of 0.2 μm or more and 1.0 μm or less from the rear surface 23. The peak doping concentration Dc of the collector region 22 is 1.0E17 cm -3 Above, 1.0E19cm -3 It may be the following:

[0089] The buffer region 20 has multiple doping concentration peaks. In this example, the buffer region 20 has two peaks: a first peak 61 and a second peak 62. The lower end of the buffer region 20 may be the boundary between the collector region 22 and the first peak 61. The upper end of the buffer region 20 may be the boundary between the second peak 62 and the drift region 18. In this specification, each peak position is the position where the doping concentration shows a maximum value. The width of the buffer region 20 in the depth direction may be 5.0 μm or more and 50.0 μm or less.

[0090] Boundary position x between the buffer region 20 and the drift region 18 ais the doping concentration of the buffer region 20 on the front surface 21 side of the buffer region 20, and the doping concentration D dr Alternatively, the boundary position x between the buffer region 20 and the drift region 18 may be the depth position where the boundary position x a may be a depth position at which the doping concentration of the buffer region 20 becomes equal to the bulk donor concentration on the front surface 21 side of the buffer region 20 .

[0091] Boundary position x between the buffer region 20 and the collector region 22 b may be the depth position of the PN junction where the net doping concentration becomes substantially zero. In the case of the diode section 80, the boundary position x b may be the boundary position between the buffer region 20 and the cathode region 82.

[0092] The first peak 61 is located closer to the front surface 21 than the collector region 22. The first peak 61 is the peak closest to the back surface 23 among the multiple peaks of the buffer region 20. The first peak 61 may be the peak with the highest doping concentration in the buffer region 20. The dopant of the first peak 61 may be phosphorus, arsenic, or hydrogen. In this example, the dopant of the first peak 61 is phosphorus.

[0093] Depth position L p1 indicates the depth position of the first peak 61 from the rear surface 23. p1 The depth position L may be 0.5 μm or more and 3.0 μm or less. p1 is, for example, 0.7 μm.

[0094] Peak concentration D p1 is the doping concentration of the first peak 61. p1 may be lower than the peak concentration Dc of the doping concentration of the collector region 22. p1 may be determined to adjust the hole concentration or hole current injected from the collector region 22 with the gate turned on to a predetermined magnitude. p1 is 1.0E15cm -3It may be more than 1.0E16cm -3 Peak concentration D p1 is 1.0E17cm -3 May be less than 5.0E16cm -3 For example, the peak concentration D p1 is 2.0E16cm -3 is.

[0095] The second peak 62 is located closer to the front surface 21 than the first peak 61. Of the multiple peaks that the buffer region 20 has, the second peak 62 is the peak that is next closest to the back surface 23 after the first peak 61. The second peak 62 is an example of a hydrogen peak that the buffer region 20 has, and is formed by hydrogen ion implantation from the back surface 23 side. The hydrogen peak is a peak in the doping concentration distribution that corresponds to the hydrogen chemical concentration peak in the hydrogen chemical concentration distribution 170. The hydrogen peak may be a peak in the donor concentration distribution of a hydrogen donor. In this example, the second peak 62 corresponds to the hydrogen chemical concentration peak 172.

[0096] The hydrogen peak is located closer to the front surface 21 of the semiconductor substrate 10 than the first lattice defect region 161. The doping concentration of the hydrogen peak is 1.0E14 cm -3 Above, 1.0E16cm -3 A plurality of hydrogen peaks may be provided on the front surface 21 side of the first lattice defect region 161. As will be described later, the plurality of hydrogen peaks may function as a field stop layer for stopping a depletion layer from spreading from the lower surface side of the base region 14.

[0097] Depth position L p2 indicates the depth position of the second peak 62 from the rear surface 23. p2 The depth position L may be 3.0 μm or more and 50.0 μm or less. p2 is, for example, 10.0 μm.

[0098] Peak concentration D p2 is the doping concentration of the second peak 62. p1 is the peak concentration Dp2 The peak concentration D p2 is 1.0E14cm -3 It may be more than 1.0E15cm -3 Peak concentration D p2 is 1.0E16cm -3 May be less than 5.0E15cm -3 In this example, the peak concentration D p2 is 5.0E15cm -3 is.

[0099] Each peak in the buffer region 20 may be formed by the same dopant or by different dopants. The dopant in all peaks in the buffer region 20 may be hydrogen. The first peak 61 may be formed by ion implantation of phosphorus, and the other peaks may be formed by ion implantation of hydrogen ions. The hydrogen ions may be protons, duthrons, or tritons. In this example, the hydrogen ions are protons.

[0100] The first lattice defect region 161 is located between the first peak 61 and the second peak 62 in the depth direction of the semiconductor substrate 10. In FIG. 2A , the range of the semiconductor substrate 10 in the depth direction where the first lattice defect region 161 is located is indicated by a double-headed arrow. The recombination center density on the back surface 23 side of the hydrogen peak may be higher than the recombination center density in the drift region 18 on the side adjacent to the hydrogen peak. In this example, the recombination center density on the back surface 23 side of the second peak 62 is higher than the recombination center density in the drift region 18 on the side adjacent to the second peak 62. In this example, the first lattice defect region 161 is a region with a lower doping concentration than the drift region 18. The first lattice defect region 161 may be a region with a lower doping concentration than the bulk donor concentration. The bulk donor concentration may be lower than the doping concentration of the drift region. In this example, the bulk donor concentration is equal to the doping concentration of the drift region.

[0101] The reason why the doping concentration of the first lattice defect region 161 is lower than that of the drift region 18 is as follows. The first lattice defect region 161 has a higher concentration of lattice defects than the drift region 18 on the side adjacent to the second peak 62. Therefore, carriers are more likely to be scattered in the first lattice defect region 161, resulting in a lower carrier mobility than in the drift region 18. In the SR measurement, spreading resistance is measured, and the doping concentration is calculated using the carrier mobility. The carrier mobility used in this calculation is the carrier mobility in an ideal crystalline state. However, since the actual carrier mobility in the first lattice defect region 161 is lower, the calculated doping concentration is correspondingly lower. In other words, the doping concentration of the first lattice defect region 161 appears to be lower. Therefore, the doping concentration distribution of the first lattice defect region 161 is lower than the doping concentration D of the drift region 18 on the side adjacent to the second peak 62. dr The actual doping concentration of the first lattice defect region 161 is not lower than it appears to be, and may be substantially equal to that of the drift region 18.

[0102] The doping concentration distribution of the first lattice defect region 161 is rc1 The minimum doping concentration D rc1 The depth position x rc1 The minimum doping concentration D may be located closer to the front surface 21 than the center position of the first lattice defect region 161 (solid line) or closer to the back surface 23 than the center position of the first lattice defect region 161 (dashed dot line). rc1 is the doping concentration D of the drift region 18 dr In this example, the minimum doping concentration D rc1 is the doping concentration D of the drift region 18 dr higher than 10% of

[0103] The first lattice defect region 161 is located closer to the front surface of the semiconductor substrate 10 than the first peak 61 in the depth direction of the semiconductor substrate 10. The second peak 62 in this example is located closer to the front surface 21 than the first lattice defect region 161. This makes it possible to suppress an increase in leakage current.

[0104] In this example, the first lattice defect region 161 is formed in the region through which hydrogen ions pass to form the second peak 62. As the hydrogen ions pass through the semiconductor substrate 10, they collide with semiconductor atoms (silicon in this example), attenuating their energy and damaging the crystal lattice, forming many lattice defects in a region (the passage region) shallower than the range Rp of the hydrogen ions. The lattice defects formed in the passage region are vacancy-type lattice defects primarily composed of vacancies, such as monovacancies (V) and divacancies (VV). Atoms adjacent to the vacancies have dangling bonds. The vacancy-type lattice defects act as recombination centers, promoting the recombination of charge carriers. As a result, the first lattice defect region 161 is formed in the region through which the hydrogen ions pass.

[0105] In this example, the first lattice defect region 161 is formed by extending it in the depth direction through hydrogen ion implantation, thereby preventing a localized high density of defects compared to the first lifetime control region 151. Furthermore, the first lattice defect region 161 can be formed by ion implantation at a lower energy and a deeper depth compared to the first lifetime control region 151. This makes it possible to suppress a decrease in short-circuit resistance and vibration during switching.

[0106] Spacing W p1p2 is the distance between the first peak 61 and the second peak 62 in the depth direction of the semiconductor substrate 10. p1p2 The spacing W may be 5.0 μm or more, or may be 10.0 μm or more. p1p2 The spacing W may be 20.0 μm or more and 30.0 μm or less. p1p2 The spacing W may be 40.0 μm or less, or may be 50.0 μm or less. p1p2 may be 5.0 μm or more in the depth direction of the semiconductor substrate 10 and may be half or less of the thickness of the semiconductor substrate 10 in the depth direction.

[0107] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161is defined as follows: The depth position x where the doping concentration of the first peak 61 coincides with that of the drift region 18 on the front surface 21 side. p1 From the above, the doping concentration of the second peak 62 coincides with that of the drift region 18 on the rear surface 23 side at the depth position x p2 The distance to the width W 161 As mentioned above, the doping concentration D dr The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 may be defined as the bulk donor concentration. 161 is the interval W p1p2 The width of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 may be 1.0 μm or more and 10.0 μm or less.

[0108] Depth position x of the first lattice defect region 161 rc1 and depth position x p1 The distance between the depth position x rc1 and depth position x p2 The doping concentration distribution of the first lattice defect region 161 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x p1 From depth position x rc1 The doping concentration distribution of the first lattice defect region 161 may have a region where the doping concentration decreases at a substantially constant gradient toward the depth position x p2 From depth position x rc1 The gradient may be substantially constant from the depth position x p1 From depth position x rc1 Between or at depth position x p2 From depth position x rc1 The gradient value may be in the range of 50% of the average gradient value over a range of 30% to 70% between.

[0109] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the first peak 61 P1 The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 may be larger than 161is the width W of the second peak 62 P2 The width W of the first peak 61 may be larger than P1 and the width W of the second peak 62 P2 The width W of the first peak 61 may be the full width at half maximum relative to the maximum value of the doping concentration (peak doping concentration) at each peak. P1 and the width W of the second peak 62 P2 The doping concentration D may be a 10% full width relative to the maximum value of the doping concentration (peak doping concentration) at each peak. P2 0.1D, which is 10% of the concentration of P2 The width at

[0110] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the hydrogen chemical concentration peak of the second peak 62 Hp2 The width W of the hydrogen chemical concentration peak of the second peak 62 may be larger than Hp2 is the peak concentration D of the hydrogen chemical concentration of the second peak 62 Hp2 The width W of the hydrogen chemical concentration peak of the second peak 62 may be Hp2 is the peak concentration D of the hydrogen chemical concentration of the second peak 62 Hp2 The 10% full width may be the peak density D Hp2 0.1D, which is 10% of the concentration of Hp2 Since the hydrogen chemical concentration is higher than the doping concentration, the width W of the hydrogen chemical concentration peak of the second peak 62 is Hp2 By using Hp2 can be clearly defined.

[0111] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the buffer region 20 buf It may be 50% or more of the above.

[0112] The sum of the widths of the regions in the buffer region 20 other than the first lattice defect region 161 in the depth direction is W EXIn the example of FIG. 2A, there are two regions other than the first lattice defect region 161 in the buffer region 20. The first region is at a depth position x b From depth position x p1 The width in the depth direction is W ex1 The second is the depth position x p2 From depth position x a The width in the depth direction is W ex2 The sum of the widths of the regions other than the first lattice defect region 161 in the depth direction W EX is W ex1 +W ex2 The sum of the widths of the regions other than the first lattice defect region 161 in the depth direction W EX is the interval W p1p2 to the width W of the first lattice defect region 161 in the depth direction 161 The width W of the first lattice defect region 161 in the depth direction is 161 is the total width W EX The width W of the first lattice defect region 161 in the depth direction may be larger than 161 By increasing the thickness of the first lattice defect region 161, it is possible to improve the trade-off between the turn-off loss, the collector-emitter saturation voltage, and the leakage current. 161 By increasing the thickness, the turn-off loss can be reduced.

[0113] The hydrogen chemical concentration in the first lattice defect region 161 is the doping concentration D dr The hydrogen chemical concentration in the first lattice defect region 161 may be less than 1×10 15 atoms / cm 3 Smaller is better, 5x10 14 atoms / cm 3 Smaller is better, 1 x 10 14 atoms / cm 3The first lattice defect region 161 has many lattice defects. Lattice defects have many dangling bonds that do not contribute to bonding, forming recombination centers. This reduces the carrier lifetime in the first lattice defect region 161. On the other hand, if hydrogen is present in the first lattice defect region 161, the dangling bonds are terminated by the hydrogen. As a result, the recombination center concentration decreases, and the reduction in carrier lifetime in the first lattice defect region 161 is suppressed. Therefore, the hydrogen chemical concentration in the first lattice defect region 161 is made smaller than the doping concentration in the drift region, for example. This suppresses the termination of dangling bonds by hydrogen, allows recombination centers to remain widely in the first lattice defect region 161, and shortens the carrier lifetime. The minimum value of the hydrogen chemical concentration in the first lattice defect region 161 is the peak concentration D of the first peak 61. P1 It may be smaller than the doping concentration of the drift region and may be smaller than the bulk donor concentration.

[0114] In the off state, the depletion layer spreads in the drift region 18 on the front surface 21 side toward the back surface 23. The depletion layer may stop at the second peak 62, which is a hydrogen peak. Furthermore, the position where the integrated concentration reaches the critical integrated concentration may be located inside the second peak 62. The critical integrated concentration will be described later. This prevents the depletion layer from penetrating into the first lattice defect region 161, thereby preventing an increase in leakage current.

[0115] FIG. 2B shows a modified example of the semiconductor device 100. This example differs from the embodiment of FIG. 2A in that the first peak 61 is formed by ion implantation of hydrogen. A hydrogen chemical concentration peak 171 is a peak in the hydrogen chemical concentration distribution 170 that corresponds to the first peak 61. When the dopant of the first peak 61 is hydrogen, the hydrogen chemical concentration is higher than the doping concentration D of the drift region 18 in the intermediate portion between the depth position Lp1 and the depth position Lp2. drOr, it increases to a concentration of the same order as the bulk donor concentration. As a result, from the vicinity of the first peak 61 to the intermediate portion between the depth positions Lp1 and Lp2, hydrogen terminates the dangling bonds present in the lattice defects, or the concentration of hydrogen donors increases. As a result, the defects in the vicinity of the first peak 61 are repaired, and the width of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 is smaller than in the embodiment of FIG. 2A. In this way, by using different dopants for the first peak 61, the width of the first lattice defect region 161 can be adjusted.

[0116] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the interval W p1p2 The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 may be 25% or more, 50% or more, or 75% or more. 161 may be 1.0 μm or more and 10.0 μm or less.

[0117] Depth position x of the first lattice defect region 161 rc1 and depth position x p1 The distance between the depth position x rc1 and depth position x p2 The doping concentration distribution of the first lattice defect region 161 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x p1 From depth position x rc1 Alternatively, the doping concentration distribution of the first lattice defect region 161 may have a region in which the doping concentration decreases at a substantially constant gradient from the depth position x p2 From depth position x rc1 , which may have a region where the gradient decreases at a substantially constant rate towards .

[0118] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the first peak 61 P1 The width W of the second peak 62 may be larger than P2 The width W of the first peak 61 may be larger than P1and the width W of the second peak 62 P2 may be the full width at half maximum of the maximum value of the doping concentration (peak doping concentration) of each peak, or may be 10% full width.

[0119] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the hydrogen chemical concentration peak of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be greater than Hp2 The width W of the hydrogen chemical concentration peak of the first peak 61 may be larger than Hp1 is the peak concentration D of the hydrogen chemical concentration of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be 10% or 10% of the full width at half maximum. Hp2 is the peak concentration D of the hydrogen chemical concentration of the second peak 62 Hp2 It may be a full width at half maximum of 10% or a full width at 10%.

[0120] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the buffer region 20 buf The width W of the first lattice defect region 161 in the depth direction may be 50% or more. 161 is the sum of the widths in the depth direction of the regions other than the first lattice defect region 161 in the buffer region 20, W EX The width W of the first lattice defect region 161 in the depth direction may be larger than 161 By increasing the thickness of the first lattice defect region 161, it is possible to improve the trade-off between the turn-off loss, the collector-emitter saturation voltage, and the leakage current. 161 By increasing the thickness, the turn-off loss can be reduced.

[0121] The minimum value D of the hydrogen chemical concentration in the first lattice defect region 161 Hp1p2 is the peak concentration D of the first peak 61 P1 The peak concentration D of the second peak 62 may be smaller than P2 The doping concentration D of the drift region 18 may be smaller thandr The minimum hydrogen chemical concentration D in the first lattice defect region 161 may be smaller than the bulk donor concentration. Hp1p2 is 5 x 10 15 atoms / cm 3 Smaller is better, 1 x 10 15 atoms / cm 3 The minimum value D of the hydrogen chemical concentration in the first lattice defect region 161 may be smaller than Hp1p2 is 1 x 10 12 atoms / cm 3 Larger is better, 1 x 10 13 atoms / cm 3 By reducing the hydrogen chemical concentration in the first lattice defect region 161, the lattice defects can be made to remain widely.

[0122] FIG. 2C shows a modified example of the semiconductor device 100. The buffer region 20 of this example has three peaks: a first peak 61, a second peak 62, and a third peak 63. The buffer region 20 has the first peak 61 and multiple hydrogen peaks. The second peak 62 and the third peak 63 are each an example of a hydrogen peak. Note that in this example, the first peak 61 is also formed by hydrogen ion implantation. The hydrogen chemical concentration peak 171 is a peak in the hydrogen chemical concentration distribution 170 that corresponds to the first peak 61. The hydrogen chemical concentration peak 173 is a peak in the hydrogen chemical concentration distribution 170 that corresponds to the third peak 63.

[0123] The third peak 63 is located closer to the front surface 21 than the second peak 62 in the depth direction of the semiconductor substrate 10. p3 indicates the depth position of the third peak 63 from the rear surface 23. p3 may be 7.0 μm or more and 13.0 μm or less, for example, 10.0 μm.

[0124] Peak concentration D p3 is the doping concentration of the third peak 63. p3 is the peak concentration D p1 and peak concentration D p2The peak concentration D p3 is 1.0E14cm -3 Above, 1.0E16cm -3 It may be the following:

[0125] The first lattice defect region 161 is provided between the first peak 61 and the second peak 62 in the depth direction of the semiconductor substrate 10, but is not provided between the second peak 62 and the third peak 63. That is, in this example, the distance W between the first peak 61 and the second peak 62 is p1p2 Therefore, the distance W between the second peak 62 and the third peak 63 is p2p3 is smaller. Depth position L p2 and depth position L p3 In the middle of the doping concentration D of the drift region 18, the hydrogen chemical concentration dr Or, the concentration increases to the same order as the bulk donor concentration. As a result, defects are repaired between the second peak 62 and the third peak 63, or the concentration of hydrogen donors increases. In this way, by adjusting the spacing between the peaks, it is possible to control whether or not the first lattice defect region 161 is formed. The spacing W p2p3 may be 1.0 μm or more and less than 5.0 μm.

[0126] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the interval W p1p2 The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 may be 25% or more, 50% or more, or 75% or more. 161 may be 1.0 μm or more and 10.0 μm or less.

[0127] Depth position x of the first lattice defect region 161 rc1 and depth position x p1 The distance between the depth position x rc1 and depth position x p2 The doping concentration distribution of the first lattice defect region 161 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x p1 From depth position x rc1Alternatively, the doping concentration distribution of the first lattice defect region 161 may have a region in which the doping concentration decreases at a substantially constant gradient from the depth position x p2 From depth position x rc1 , which may have a region where the gradient decreases at a substantially constant rate towards .

[0128] The doping concentration distribution of the first lattice defect region 161 is p1 and position x p2 to minimum value D rc1 Towards the position where , there may be a region where the absolute value of the gradient of the doping concentration increases, a region where it decreases, and a region where the doping concentration is substantially constant (dashed two-dot line).

[0129] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the first peak 61 P1 The width W of the second peak 62 may be larger than P2 The width W of the third peak 63 may be larger than P3 The width W of the first peak 61 may be larger than P1 , the width W of the second peak 62 P2 and the width W of the third peak 63 P3 may be the full width at half maximum of the maximum value of the doping concentration (peak doping concentration) of each peak, or may be 10% full width.

[0130] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the hydrogen chemical concentration peak of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be greater than Hp2 The width W of the hydrogen chemical concentration peak of the third peak 63 may be greater than Hp3 The width W of the hydrogen chemical concentration peak of the first peak 61 may be larger than Hp1 is the peak concentration D of the hydrogen chemical concentration of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be the full width at half maximum relative to the first peak 62 or may be 10% full width.Hp2 is the peak concentration D of the hydrogen chemical concentration of the second peak 62 Hp2 The width W of the hydrogen chemical concentration peak of the third peak 63 may be the full width at half maximum relative to the hydrogen chemical concentration peak 63, or may be 10% full width. Hp3 is the hydrogen chemical concentration peak D of the third peak 63 Hp3 It may be a full width at half maximum relative to the maximum, or a 10% full width.

[0131] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the buffer region 20 buf The width W of the first lattice defect region 161 in the depth direction may be 50% or more. 161 is the sum of the widths in the depth direction of the regions other than the first lattice defect region 161 in the buffer region 20, W EX The width W of the first lattice defect region 161 in the depth direction may be larger than 161 By increasing the thickness of the first lattice defect region 161, it is possible to improve the trade-off between the turn-off loss, the collector-emitter saturation voltage, and the leakage current. 161 By increasing the thickness, the turn-off loss can be reduced.

[0132] The minimum value D of the hydrogen chemical concentration in the first lattice defect region 161 Hp1p2 is the peak concentration D of the first peak 61 P1 The peak concentration D of the second peak 62 may be smaller than P2 The peak concentration D of the third peak 63 may be smaller than P3 The doping concentration D of the drift region 18 may be smaller than dr The minimum hydrogen chemical concentration D in the first lattice defect region 161 may be smaller than the bulk donor concentration. Hp1p2 is 5 x 10 14 atoms / cm 3 Smaller is better, 1 x 10 14 atoms / cm 3 The minimum value D of the hydrogen chemical concentration in the first lattice defect region 161 may be smaller than Hp1p2 is 1 x 10 12 atoms / cm 3Larger is better, 1 x 10 13 atoms / cm 3 By reducing the hydrogen chemical concentration in the first lattice defect region 161, the lattice defects can be made to remain widely.

[0133] The depletion layer in the off state may extend to the second peak 62, which is a hydrogen peak, or may extend further toward the surface 21 than the second peak 62. The position where the integrated concentration reaches the critical integrated concentration may be located inside the second peak 62. This prevents the depletion layer from penetrating into the first lattice defect region 161, thereby preventing an increase in leakage current.

[0134] FIG. 2D shows a modified example of the semiconductor device 100. The buffer region 20 of this example has four peaks: a first peak 61, a second peak 62, a third peak 63, and a fourth peak 64. The buffer region 20 has the first peak 61 and multiple hydrogen peaks. The second peak 62, the third peak 63, and the fourth peak 64 are each an example of a hydrogen peak. Note that in this example, the first peak 61 is also formed by hydrogen ion implantation. The hydrogen chemical concentration peak 171, the hydrogen chemical concentration peak 172, the hydrogen chemical concentration peak 173, and the hydrogen chemical concentration peak 174 correspond to the first peak 61, the second peak 62, the third peak 63, and the fourth peak 64, respectively.

[0135] The fourth peak 64 is located closer to the front surface 21 than the third peak 63 in the depth direction of the semiconductor substrate 10. p4 indicates the depth position of the fourth peak 64 from the rear surface 23. p4 may be 10% or more and 20% or less of the thickness of the semiconductor substrate 10. For example, the depth position L p4 is 15.0 μm.

[0136] Peak concentration D p4 is the doping concentration of the fourth peak 64. p4 is the peak concentration D p1 , peak concentration D p2 and peak concentration D p3The peak concentration D p4 is 1.0E14cm -3 Above, 1.0E16cm -3 It may be the following:

[0137] The doping concentrations of the four peaks of the buffer region 20 may gradually decrease toward the front surface 21 of the semiconductor substrate 10. That is, the peak concentration D p2 is the peak concentration D of the first peak 61 p1 The peak concentration D of the third peak 63 may be smaller than p3 is the peak concentration D of the second peak 62 p2 The peak concentration D of the fourth peak 64 may be smaller than p4 is the peak concentration D of the third peak 63 p3 It can be smaller than

[0138] The distance W between the second peak 62 and the third peak 63 p2p3 is the distance W between the first peak 61 and the second peak 62 p1p2 The distance W between the third peak 63 and the fourth peak 64 may be smaller than p3p4 is the distance W between the first peak 61 and the second peak 62 p1p2 The distance W between the third peak 63 and the fourth peak 64 may be smaller than p3p4 is the distance W between the second peak 62 and the third peak 63 p2p3 The distance W between the third peak 63 and the fourth peak 64 in this example may be the same as or different from the distance W p3p4 is the distance W between the second peak 62 and the third peak 63 p2p3 is smaller than.

[0139] The first lattice defect region 161 is provided between the first peak 61 and the second peak 62 in the depth direction of the semiconductor substrate 10. The first lattice defect region 161 is not provided between the second peak 62 and the third peak 63 and between the third peak 63 and the fourth peak 64. That is, in this example, the distance W between the first peak 61 and the second peak 62 is p1p2 Therefore, the distance W between the second peak 62 and the third peak 63 is p2p3 is smaller. Depth position Lp2 and depth position L p3 In the middle of the doping concentration D of the drift region 18, the hydrogen chemical concentration dr Or, the concentration increases to the same order as the bulk donor concentration. As a result, the defects are recovered between the second peak 62 and the third peak 63. Also, the interval W between the first peak 61 and the second peak 62 p1p2 Therefore, the distance W between the third peak 63 and the fourth peak 64 is p3p4 is smaller. Depth position L p3 and depth position L p4 In the middle of the doping concentration D of the drift region 18, the hydrogen chemical concentration dr Or the donor concentration increases to the same order as the bulk donor concentration. This causes the defects to recover between the third peak 63 and the fourth peak 64. The interval W p3p4 may be 1.0 μm or more and less than 5.0 μm.

[0140] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the interval W p1p2 The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 may be 25% or more, 50% or more, or 75% or more. 161 may be 1.0 μm or more and 10.0 μm or less.

[0141] Depth position x of the first lattice defect region 161 rc1 and depth position x p1 The distance between the depth position x rc1 and depth position x p2 The doping concentration distribution of the first lattice defect region 161 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x p1 From depth position x rc1 Alternatively, the doping concentration distribution of the first lattice defect region 161 may have a region in which the doping concentration decreases at a substantially constant gradient from the depth position x p2 From depth position x rc1 , which may have a region where the gradient decreases at a substantially constant rate towards .

[0142] The doping concentration distribution of the first lattice defect region 161 is p1 and position x p2 to minimum value D rc1 Towards the position where , there may be a region where the absolute value of the gradient of the doping concentration increases, a region where it decreases, and a region where the doping concentration is substantially constant (dashed two-dot line).

[0143] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the first peak 61 P1 The width W of the second peak 62 may be larger than P2 The width W of the third peak 63 may be larger than P3 The width W of the fourth peak 64 may be greater than P4 The width W of the first peak 61 may be larger than P1 , the width W of the second peak 62 P2 , the width W of the third peak 63 P3 , the width W of the fourth peak 64 P4 may be the full width at half maximum of the maximum value of the doping concentration (peak doping concentration) of each peak, or may be 10% full width.

[0144] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the hydrogen chemical concentration peak of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be greater than Hp2 The width W of the hydrogen chemical concentration peak of the third peak 63 may be greater than Hp3 The width W of the hydrogen chemical concentration peak of the fourth peak 64 may be greater than Hp4 The width W of the hydrogen chemical concentration peak of the first peak 61 may be larger than Hp1 is the peak concentration D of the hydrogen chemical concentration of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be the full width at half maximum relative to the first peak 62 or may be 10% full width. Hp2 is the peak concentration D of the hydrogen chemical concentration of the second peak 62 Hp2The width W of the hydrogen chemical concentration peak of the third peak 63 may be the full width at half maximum relative to the hydrogen chemical concentration peak 63, or may be 10% full width. Hp3 is the hydrogen chemical concentration peak D of the third peak 63 Hp3 The width W of the hydrogen chemical concentration peak of the fourth peak 64 may be the full width at half maximum relative to the fourth peak 64 or may be 10% full width. Hp4 is the hydrogen chemical concentration peak D of the fourth peak 64 Hp4 It may be a full width at half maximum relative to the maximum, or a 10% full width.

[0145] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the buffer region 20 buf The width W of the first lattice defect region 161 in the depth direction may be 50% or more. 161 is the sum of the widths in the depth direction of the regions other than the first lattice defect region 161 in the buffer region 20, W EX The width W of the first lattice defect region 161 in the depth direction may be larger than 161 By increasing the thickness of the first lattice defect region 161, it is possible to improve the trade-off between the turn-off loss, the collector-emitter saturation voltage, and the leakage current. 161 By increasing the thickness, the turn-off loss can be reduced.

[0146] The minimum value D of the hydrogen chemical concentration in the first lattice defect region 161 Hp1p2 is the peak concentration D of the first peak 61 P1 The peak concentration D of the second peak 62 may be smaller than P2 The peak concentration D of the third peak 63 may be smaller than P3 The peak concentration D of the fourth peak 64 may be smaller than P4 The doping concentration D of the drift region 18 may be smaller than dr The minimum hydrogen chemical concentration D in the first lattice defect region 161 may be smaller than the bulk donor concentration. Hp1p2 is 5 x 10 15 atoms / cm 3 Smaller is better, 1 x 10 15 atoms / cm 3The minimum value D of the hydrogen chemical concentration in the first lattice defect region 161 may be smaller than Hp1p2 is 1 x 10 12 atoms / cm 3 Larger is better, 1 x 10 13 atoms / cm 3 By reducing the hydrogen chemical concentration in the first lattice defect region 161, the lattice defects can be made to remain widely.

[0147] 2E shows a modified example of the semiconductor device 100. In this example, the distance W between the first peak 61 and the second peak 62 is shorter than in the example of FIG. p1p2 is the spacing W in the example of FIG. 2D p1p2 2D , and differs in that the first peak 61 is formed by phosphorus ion implantation. When the dopant of the first peak 61 is phosphorus, defects are not recovered in the vicinity of the first peak 61, and the distance between the first peak 61 and the first lattice defect region 161 is smaller than in the example of FIG. 2D .

[0148] In this example, the distance W between the first peak 61 and the second peak 62 is p1p2 is the spacing W in the example of FIG. 2D p1p2 In this way, by forming the first peak 61 with phosphorus, the interval W p1p2 Even when the distance W is small, the first lattice defect region 161 can be formed between the first peak 61 and the second peak 62. p1p2 The spacing W may be 2.0 μm or more, or may be 3.0 μm or more. p1p2 may be less than 10.0 μm, and may be less than 5.0 μm.

[0149] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the interval W p1p2 It may be 25% or more, 50% or more, or 75% or more of the total.

[0150] Depth position x of the first lattice defect region 161 rc1 and depth position x p1The distance between the depth position x rc1 and depth position x p2 The doping concentration distribution of the first lattice defect region 161 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x p1 From depth position x rc1 Alternatively, the doping concentration distribution of the first lattice defect region 161 may have a region in which the doping concentration decreases at a substantially constant gradient from the depth position x p2 From depth position x rc1 , which may have a region where the gradient decreases at a substantially constant rate towards .

[0151] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the first peak 61 P1 The width W of the second peak 62 may be larger than P2 The width W of the third peak 63 may be larger than P3 The width W of the fourth peak 64 may be greater than P4 The width W of the first peak 61 may be larger than P1 , the width W of the second peak 62 P2 , the width W of the third peak 63 P3 , the width W of the fourth peak 64 P4 may be the full width at half maximum of the maximum value of the doping concentration (peak doping concentration) of each peak, or may be 10% full width.

[0152] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the hydrogen chemical concentration peak of the second peak 62 Hp2 The width W of the hydrogen chemical concentration peak of the third peak 63 may be greater than Hp3 The width W of the hydrogen chemical concentration peak of the fourth peak 64 may be greater than Hp4 The width W of the hydrogen chemical concentration peak of the second peak 62 may be larger than Hp2 is the peak concentration D of the hydrogen chemical concentration of the second peak 62 Hp2 The width W of the hydrogen chemical concentration peak of the third peak 63 may be the full width at half maximum relative to the hydrogen chemical concentration peak 63, or may be 10% full width. Hp3is the hydrogen chemical concentration peak D of the third peak 63 Hp3 The width W of the hydrogen chemical concentration peak of the fourth peak 64 may be the full width at half maximum relative to the fourth peak 64 or may be 10% full width. Hp4 is the hydrogen chemical concentration peak D of the fourth peak 64 Hp4 It may be a full width at half maximum relative to the maximum, or a 10% full width.

[0153] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the buffer region 20 buf The width W of the first lattice defect region 161 in the depth direction may be 50% or more. 161 is the sum of the widths in the depth direction of the regions other than the first lattice defect region 161 in the buffer region 20, W EX The width W of the first lattice defect region 161 in the depth direction may be larger than 161 By increasing the thickness of the first lattice defect region 161, it is possible to improve the trade-off between the turn-off loss, the collector-emitter saturation voltage, and the leakage current. 161 By increasing the thickness, the turn-off loss can be reduced.

[0154] The minimum value of the hydrogen chemical concentration in the first lattice defect region 161 is the peak concentration D P1 The peak concentration D of the second peak 62 may be smaller than P2 The peak concentration D of the third peak 63 may be smaller than P3 The peak concentration D of the fourth peak 64 may be smaller than P4 The doping concentration D of the drift region 18 may be smaller than dr The hydrogen chemical concentration in the first lattice defect region 161 may be less than 1×10 15 atoms / cm 3 Smaller is better, 5x10 14 atoms / cm 3 Smaller is better, 1 x 10 14 atoms / cm 3By reducing the hydrogen chemical concentration in the first lattice defect region 161, the lattice defects can be made to remain widely.

[0155] 2F shows a modified example of semiconductor device 100. Buffer region 20 of this example has two lattice defect regions: first lattice defect region 161 and second lattice defect region 162. Buffer region 20 of this example has four peaks: first peak 61, second peak 62, third peak 63, and fourth peak 64. First peak 61 of this example is formed by hydrogen ion implantation.

[0156] The first lattice defect region 161 is provided between a plurality of hydrogen peaks in the depth direction of the semiconductor substrate 10. In this example, the first lattice defect region 161 is provided between the second peak 62 and the third peak 63. The distance W between the second peak 62 and the third peak 63 is p2p3 is the distance W between the first peak 61 and the second peak 62 p1p2 The spacing W can be larger than p2p3 The spacing W may be 3.0 μm or more, or 5.0 μm or more. p2p3 may be less than 10.0 μm, and may be less than 7.0 μm.

[0157] The doping concentration distribution of the first lattice defect region 161 is rc1 The minimum doping concentration D rc1 The depth position x rc1 The minimum doping concentration D may be located closer to the front surface 21 than the center position of the first lattice defect region 161 (solid line) or may be located closer to the back surface 21 than the center position of the first lattice defect region 161 (dashed dot line). rc1 is the doping concentration D of the drift region 18 dr In this example, the minimum doping concentration D rc1 is the doping concentration D of the drift region 18 dr higher than 10% of

[0158] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the interval Wp1p2 The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 may be 25% or more, 50% or more, or 75% or more. 161 may be 1.0 μm or more and 10.0 μm or less.

[0159] Depth position x of the first lattice defect region 161 rc1 and depth position x 1p2 The distance between the depth position x rc1 and depth position x 1p3 The doping concentration distribution of the first lattice defect region 161 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x 1p2 From depth position x rc1 Alternatively, the doping concentration distribution of the first lattice defect region 161 may have a region in which the doping concentration decreases at a substantially constant gradient from the depth position x 1p3 From depth position x rc1 , which may have a region where the gradient decreases at a substantially constant rate towards .

[0160] The doping concentration distribution of the first lattice defect region 161 is 1p2 and position x 1p3 to minimum value D rc1 Towards the position where , there may be a region where the absolute value of the gradient of the doping concentration increases, a region where it decreases, and a region where the doping concentration is substantially constant (dashed two-dot line).

[0161] Depth position x of the first lattice defect region 161 rc1 and depth position x 1p2 The distance between the depth position x rc1 and depth position x 1p3 The doping concentration distribution of the first lattice defect region 161 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x 1p2 From depth position x rc1 The doping concentration distribution of the first lattice defect region 161 may have a region where the doping concentration decreases at a substantially constant gradient toward the depth position x 1p3 From depth position x rc1The gradient may be substantially constant from the depth position x 1p2 From depth position x rc1 Between or at depth position x 1p3 From depth position x rc1 The gradient value may be in the range of 50% of the average gradient value over a range of 30% to 70% between.

[0162] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the first peak 61 P1 The width W of the second peak 62 may be larger than P2 The width W of the third peak 63 may be larger than P3 The width W of the fourth peak 64 may be greater than P4 The width W of the first peak 61 may be larger than P1 , the width W of the second peak 62 P2 , the width W of the third peak 63 P3 , the width W of the fourth peak 64 P4 may be the full width at half maximum of the maximum value of the doping concentration (peak doping concentration) of each peak, or may be 10% full width.

[0163] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the hydrogen chemical concentration peak of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be greater than Hp2 The width W of the hydrogen chemical concentration peak of the third peak 63 may be greater than Hp3 The width W of the hydrogen chemical concentration peak of the fourth peak 64 may be greater than Hp4 The width W of the hydrogen chemical concentration peak of the first peak 61 may be larger than Hp1 is the peak concentration D of the hydrogen chemical concentration of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be the full width at half maximum relative to the first peak 62 or may be 10% full width. Hp2 is the peak concentration D of the hydrogen chemical concentration of the second peak 62 Hp2The width W of the hydrogen chemical concentration peak of the third peak 63 may be the full width at half maximum relative to the hydrogen chemical concentration peak 63, or may be 10% full width. Hp3 is the hydrogen chemical concentration peak D of the third peak 63 Hp3 The width W of the hydrogen chemical concentration peak of the fourth peak 64 may be the full width at half maximum relative to the fourth peak 64 or may be 10% full width. Hp4 is the hydrogen chemical concentration peak D of the fourth peak 64 Hp4 It may be a full width at half maximum relative to the maximum, or a 10% full width.

[0164] The width W of the first lattice defect region 161 in the depth direction of the semiconductor substrate 10 161 is the width W of the buffer region 20 buf The width W of the first lattice defect region 161 in the depth direction may be 50% or more. 161 is the sum of the widths in the depth direction of the regions other than the first lattice defect region 161 in the buffer region 20, W EX The width W of the first lattice defect region 161 in the depth direction may be larger than 161 By increasing the thickness of the first lattice defect region 161, it is possible to improve the trade-off between the turn-off loss, the collector-emitter saturation voltage, and the leakage current. 161 By increasing the thickness, the turn-off loss can be reduced.

[0165] The minimum value D of the hydrogen chemical concentration in the first lattice defect region 161 1Hp1p2 is the peak concentration D of the first peak 61 P1 The peak concentration D of the second peak 62 may be smaller than P2 The peak concentration D of the third peak 63 may be smaller than P3 The peak concentration D of the fourth peak 64 may be smaller than P4 The doping concentration D of the drift region 18 may be smaller than dr The minimum hydrogen chemical concentration D in the first lattice defect region 161 may be smaller than the bulk donor concentration. 1Hp1p2 is 5 x 10 14 atoms / cm 3 Smaller is better, 1 x 10 14 atoms / cm 3The minimum value D of the hydrogen chemical concentration in the first lattice defect region 161 may be smaller than 1Hp1p2 is 1 x 10 12 atoms / cm 3 Larger is better, 1 x 10 13 atoms / cm 3 By reducing the hydrogen chemical concentration in the first lattice defect region 161, the lattice defects can be made to remain widely.

[0166] The second lattice defect region 162 is a lattice defect region different from the first lattice defect region 161 provided in the buffer region 20. The second lattice defect region 162 is formed in a region through which hydrogen ions pass during hydrogen ion implantation, similar to the first lattice defect region 161. The second lattice defect region 162 is located closer to the front surface 21 of the semiconductor substrate 10 than the first lattice defect region 161 in the depth direction of the semiconductor substrate 10, and is located between a plurality of hydrogen peaks. The second lattice defect region 162 in this example is located between the third peak 63 and the fourth peak 64. The distance W between the third peak 63 and the fourth peak 64 is p3p4 is the distance W between the first peak 61 and the second peak 62 p1p2 The distance W between the third peak 63 and the fourth peak 64 may be larger than p3p4 is the distance W between the second peak 62 and the third peak 63 p2p3 may be the same as the interval W p2p3 The spacing W may be smaller than p3p4 The spacing W may be 3.0 μm or more, or 5.0 μm or more. p3p4 may be less than 10.0 μm, and may be less than 7.0 μm.

[0167] Similar to the first lattice defect region 161, the doping concentration distribution of the second lattice defect region 162 is rc2 The minimum doping concentration D rc2 The depth position x rc2 The minimum doping concentration D may be located closer to the front surface 21 than the middle position of the second lattice defect region 162 (solid line) or closer to the back surface 23 (dashed dot line). rc2is the doping concentration D of the drift region 18 dr In this example, the minimum doping concentration D rc2 is the doping concentration D of the drift region 18 dr The minimum doping concentration D is higher than 10% of rc2 is the minimum value D of the doping concentration of the first lattice defect region 161 in this example. rc1 It may be higher or lower than that.

[0168] The width W of the second lattice defect region 162 in the depth direction of the semiconductor substrate 10 162 is the interval W p3p4 The width W of the second lattice defect region 162 in the depth direction of the semiconductor substrate 10 may be 25% or more, 50% or more, or 75% or more. 162 may be 1.0 μm or more and 10.0 μm or less.

[0169] Depth position x of the second lattice defect region 162 rc2 and depth position x 2p3 The distance between the depth position x rc2 and depth position x 2p4 The doping concentration distribution of the second lattice defect region 162 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x 2p3 From depth position x rc2 Alternatively, the doping concentration distribution of the second lattice defect region 162 may have a region in which the doping concentration decreases at a substantially constant gradient from the depth position x 2p4 From depth position x rc2 , which may have a region where the gradient decreases at a substantially constant rate towards .

[0170] The doping concentration distribution of the second lattice defect region 162 is 2p3 and position x 2p4 to minimum value D rc2 Towards the position where , there may be a region where the absolute value of the gradient of the doping concentration increases, a region where it decreases, and a region where the doping concentration is substantially constant (dashed two-dot line).

[0171] Depth position x of the second lattice defect region 162 rc2 and depth position x 2p3 The distance between the depth position x rc2 and depth position x 2p4 The doping concentration distribution of the second lattice defect region 162 may be larger (solid line) or smaller (dashed line) than the distance from the depth position x 2p3 From depth position x rc2 The doping concentration distribution of the second lattice defect region 162 may have a region where the doping concentration decreases at a substantially constant gradient toward the depth position x 2p4 From depth position x rc2 The gradient may be substantially constant from the depth position x 2p3 From depth position x rc2 Between or at depth position x 2p4 From depth position x rc2 The gradient value may be in the range of 50% of the average gradient value over a range of 30% to 70% between.

[0172] The width W of the second lattice defect region 162 in the depth direction of the semiconductor substrate 10 162 is the width W of the first peak 61 P1 The width W of the second peak 62 may be larger than P2 The width W of the third peak 63 may be larger than P3 The width W of the fourth peak 64 may be greater than P4 The width W of the first peak 61 may be larger than P1 , the width W of the second peak 62 P2 , the width W of the third peak 63 P3 , the width W of the fourth peak 64 P4 may be the full width at half maximum of the maximum value of the doping concentration (peak doping concentration) of each peak, or may be 10% full width.

[0173] The width W of the second lattice defect region 162 in the depth direction of the semiconductor substrate 10 162 is the width W of the hydrogen chemical concentration peak of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be greater than Hp2The width W of the hydrogen chemical concentration peak of the third peak 63 may be greater than Hp3 The width W of the hydrogen chemical concentration peak of the fourth peak 64 may be greater than Hp4 The width W of the hydrogen chemical concentration peak of the first peak 61 may be larger than Hp1 is the peak concentration D of the hydrogen chemical concentration of the first peak 61 Hp1 The width W of the hydrogen chemical concentration peak of the second peak 62 may be the full width at half maximum relative to the first peak 62 or may be 10% full width. Hp2 is the peak concentration D of the hydrogen chemical concentration of the second peak 62 Hp2 The width W of the hydrogen chemical concentration peak of the third peak 63 may be the full width at half maximum relative to the hydrogen chemical concentration peak 63, or may be 10% full width. Hp3 is the hydrogen chemical concentration peak D of the third peak 63 Hp3 The width W of the hydrogen chemical concentration peak of the fourth peak 64 may be the full width at half maximum relative to the fourth peak 64 or may be 10% full width. Hp4 is the hydrogen chemical concentration peak D of the fourth peak 64 Hp4 It may be a full width at half maximum relative to the maximum, or a 10% full width.

[0174] The width W of the second lattice defect region 162 in the depth direction of the semiconductor substrate 10 162 is the width W of the buffer region 20 buf The width W of the second lattice defect region 162 in the depth direction may be 50% or more. 162 is the sum of the widths in the depth direction of the regions other than the second lattice defect region 162 in the buffer region 20, W EX The width W of the second lattice defect region 162 in the depth direction may be larger than 162 By increasing the thickness of the second lattice defect region 162, it is possible to improve the trade-off between the turn-off loss, the collector-emitter saturation voltage, and the leakage current. 162 By increasing the thickness, the turn-off loss can be reduced.

[0175] The minimum value D of the hydrogen chemical concentration in the second lattice defect region 162 2Hp1p2 is the peak concentration D of the first peak 61 P1 The peak concentration D of the second peak 62 may be smaller than P2The peak concentration D of the third peak 63 may be smaller than P3 The peak concentration D of the fourth peak 64 may be smaller than P4 The doping concentration D of the drift region 18 may be smaller than dr The minimum hydrogen chemical concentration D in the first lattice defect region 161 may be smaller than the bulk donor concentration. 2Hp1p2 is 5 x 10 14 atoms / cm 3 Smaller is better, 1 x 10 14 atoms / cm 3 The minimum value D of the hydrogen chemical concentration in the second lattice defect region 162 may be smaller than 2Hp1p2 is 1 x 10 12 atoms / cm 3 Larger is better, 1 x 10 13 atoms / cm 3 By reducing the hydrogen chemical concentration in the second lattice defect region 162, the lattice defects can be made to remain widely.

[0176] If the depletion layer in the off state passes over the fourth peak 64 toward the rear surface 23 and penetrates into the second lattice defect region 162, the leakage current increases. Therefore, the depletion layer may stop inside the fourth peak 64, which is the hydrogen peak. The position where the integrated concentration reaches the critical integrated concentration may be located inside the fourth peak 64. This prevents the depletion layer from penetrating into the second lattice defect region 162, thereby preventing an increase in the leakage current.

[0177] 2G shows a modified example of the doping concentration distribution of the first lattice defect region 161. In addition to the above, the doping concentration distribution of the first lattice defect region 161 has a doping concentration distribution at the depth position x p2 to minimum value D rc1 Position x where rc1 The absolute value of the gradient of the doping concentration may increase toward the depth position x (solid line). p2 is the central position x of the first lattice defect region 161 center The depth position x is closer to the front surface 21 than the depth position x. rc1is the central position x of the first lattice defect region 161 center The gradient of the diagonal line of the right-angled triangle shown in FIG. 2G indicates the degree of the absolute value of the gradient of the doping concentration. The longer the length of the vertical line of the right-angled triangle, the greater the absolute value of the gradient of the doping concentration. The shape of the doping concentration distribution of the first lattice defect region 161 may be upwardly convex. The absolute value of the gradient of the doping concentration of the first lattice defect region 161 is determined by the depth position x of the end of the first lattice defect region 161. p2 From the minimum depth position x rc1 The absolute value of the gradient of the doping concentration may increase in a region of 50% to 100% of the width to the first region.

[0178] As shown by the dashed line in FIG. 2G, the position x of the edge of the first lattice defect region 161 p1 The position x where the minimum value Drc1 is rc2 The doping concentration gradient may have a portion where the absolute value of the gradient increases toward the depth position x p1 is the central position x of the first lattice defect region 161 center It is located on the rear surface 23 side of the depth position x rc2 is the central position x of the first lattice defect region 161 center The depth position x is closer to the front surface 21 than the depth position x. p1 is the depth position x p2 It is located on the rear surface 23 side of the depth position x rc1 is the depth position x rc2 It is located closer to the back surface 23 than the

[0179] As shown by the dashed double-dashed line in FIG. 2G, the position x p1 and position x p2 The position x where the minimum value Drc1 is center The doping concentration distribution of the first lattice defect region 161 may have a portion where the absolute value of the gradient of the doping concentration increases toward the depth position x. The doping concentration distribution of the first lattice defect region 161 may follow a distribution obtained by inverting a Gaussian distribution. center The distribution may be symmetric in the depth direction.

[0180] 2H shows a modified example of the doping concentration distribution of the first lattice defect region 161. The doping concentration distribution of the first lattice defect region 161 is as follows: p1 to minimum value D rc1 Position x where rc2 , the absolute value of the gradient of the doping concentration may decrease or may have a portion where the absolute value of the gradient is substantially constant (solid line). p1 is the central position x of the first lattice defect region 161 center It is located on the rear surface 23 side of the depth position x rc2 is the central position x of the first lattice defect region 161 center The gradient of the diagonal line of the right-angled triangle shown in FIG. 2H indicates the degree of the absolute value of the gradient of the doping concentration. The longer the length of the vertical line of the right-angled triangle, the greater the absolute value of the gradient of the doping concentration. The shape of the doping concentration distribution of the first lattice defect region 161 may be downwardly convex. The absolute value of the gradient of the doping concentration of the first lattice defect region 161 is determined by the depth position x p1 From the minimum depth position x rc2 The absolute value of the gradient of the doping concentration may be substantially constant from the depth position x p1 From depth position x rc2 Over a range of 30% to 70% between the absolute values ​​of the gradients, the absolute values ​​of the gradients may be in a range of 50% of the average value of the gradients.

[0181] As shown by the dashed-dotted line in FIG. 2H, the position x of the edge of the first lattice defect region 161 p2 to minimum value D rc1 Position x where rc1 The absolute value of the gradient of the doping concentration may decrease toward the depth position x, or the absolute value of the gradient may be substantially constant. p2 is the central position x of the first lattice defect region 161 center The depth position x is closer to the front surface 21 than the depth position x. rc1 is the central position x of the first lattice defect region 161 center It is located on the rear surface 23 side of the depth position x p1is the depth position x p2 It is located on the rear surface 23 side of the depth position x rc1 is the depth position x rc2 It is located closer to the back surface 23 than the

[0182] As shown by the dotted line in FIG. 2H, the position x of the edge of the first lattice defect region 161 p1 and position x p2 to minimum value D rc1 Position x where center , the doping concentration gradient may have a region where the absolute value of the doping concentration gradient increases, a region where it decreases, and a region where the doping concentration is substantially constant. That is, the doping concentration distribution of the first lattice defect region 161 may be convex downward and have a bowl or bathtub shape (dotted line). The doping concentration distribution of the first lattice defect region 161 may have a gradient of the doping concentration gradient from the depth position x center The region where the doping concentration of the first lattice defect region 161 is substantially constant may be a region at a depth position x center The region where the doping concentration is substantially constant may include the minimum value Drc1 and the minimum value D rc1 The region where the doping concentration is substantially constant may be within a range of ±50% of the depth position x p1 From depth position x p2 The depth may range from 30% to 70% of the width.

[0183] FIG. 3A shows an example of a semiconductor device 100 including a first lifetime control region 151. In this example, a case where the first lifetime control region 151 is provided in the embodiment shown in FIG. 2A will be described, but the first lifetime control region 151 may also be combined with a semiconductor device 100 disclosed in another embodiment. The first lifetime control region 151 may be provided at any position in the buffer region 20 in the depth direction of the semiconductor substrate 10. Note that although the hydrogen peak hydrogen chemical concentration distribution 170 may be omitted in the drawings, the hydrogen chemical concentration distribution 170 may be present as shown in any of the embodiments of FIGS. 2A to 2F.

[0184] The peak position of first lifetime control region 151 is located closer to front surface 21 of semiconductor substrate 10 than first peak 61. Furthermore, the peak position of first lifetime control region 151 is closer to back surface 23 than the hydrogen peak of buffer region 20 in the depth direction of semiconductor substrate 10. In this example, the peak position of first lifetime control region 151 is located between first lattice defect region 161 and second peak 62, which is the hydrogen peak, in the depth direction of semiconductor substrate 10.

[0185] Peak concentration D k1 is the lifetime killer concentration of the first lifetime control region 151. The lifetime killer concentration may be the concentration of recombination centers. The recombination centers may be complexes of vacancies such as monovacancies and divacancies, interstitial atoms (silicon in this example) of the atoms that make up the semiconductor substrate, atoms of a rare gas element such as helium, or metal atoms such as platinum or gold. The peak concentration D k1 is the peak concentration D of the doping concentration of the first peak 61 p1 The peak concentration D k1 is the peak concentration D p1 In one example, the peak concentration D k1 is 1.0E15cm -3 More than 1.0E17cm -3 The peak concentration D k1 may be less than the peak concentration Dc of the doping concentration of the collector region 22.

[0186] Peak concentration D k1 , the peak concentration D p1 By making the concentration of hydrogen greater than 1 / 2, the influence of hydrogen for forming the buffer region 20 is reduced. That is, hydrogen for forming the buffer region 20 may terminate dangling bonds of lattice defects and eliminate the introduced lattice defects, but the peak concentration D k1The disappearance of lattice defects can be suppressed by making the concentration higher than the peak concentration of the buffer region 20. This makes it possible to sufficiently reduce excess carriers on the rear surface 23 side during reverse recovery operation.

[0187] 3B shows a modified example of semiconductor device 100 including first lifetime control region 151. In this example, first lifetime control region 151 is provided in the same region as first lattice defect region 161. In this example, first lifetime control region 151 is provided in the center of first lattice defect region 161 in the depth direction of semiconductor substrate 10, but is not limited to this. First lifetime control region 151 may be provided closer to back surface 23 than the center of first lattice defect region 161, or closer to front surface 21. Furthermore, first lifetime control region 151 may be provided at the boundary between first peak 61 and first lattice defect region 161, or at the boundary between first lattice defect region 161 and second peak 62.

[0188] 3C shows a modified example of semiconductor device 100 including first lifetime control region 151. In this example, a case where first lifetime control region 151 is provided in the embodiment shown in FIG. 2B will be described, but first lifetime control region 151 may also be combined with semiconductor device 100 disclosed in other embodiments.

[0189] The first lifetime control region 151 is provided closer to the back surface 23 than the first lattice defect region 161 in the depth direction of the semiconductor substrate 10. In this example, the first lifetime control region 151 is provided between the first peak 61 and the first lattice defect region 161. The first lifetime control region 151 may be provided in a region closer to the front surface 21 than the first peak 61, where the doping concentration is approximately the same as that of the drift region 18. Furthermore, a portion of the first lifetime control region 151 may be provided in the first lattice defect region 161.

[0190] FIG. 3D shows a modified example of semiconductor device 100 including first lifetime control region 151. In this example, the position of first lifetime control region 151 differs from the embodiment of FIG. 3C. In this example, the differences from the embodiment of FIG. 3C will be particularly described. First lifetime control region 151 in this example is provided at the base of first peak 61, between first peak 61 and first lattice defect region 161. In other words, the peak position of first lifetime control region 151 is located closer to front surface 21 than first peak 61. In this way, first lifetime control region 151 may be provided so as to partially overlap first peak 61.

[0191] FIG. 3E shows a modified example of semiconductor device 100 including first lifetime control region 151. In this example, the position of first lifetime control region 151 differs from the embodiment shown in FIGS. 3C and 3D. The differences from the embodiment shown in FIGS. 3C and 3D will be particularly described. First lifetime control region 151 in this example is located closer to back surface 23 than first peak 61 in the depth direction of semiconductor substrate 10. The peak position of first lifetime control region 151 in this example is located between collector region 22 and first peak 61.

[0192] FIG. 3F shows a modified example of the semiconductor device 100 including a first lifetime control region 151. In this example, the position of the first lifetime control region 151 differs from that of the embodiment shown in FIGS. 3A and 3B. In this example, the differences from the embodiment shown in FIGS. 3A and 3B will be particularly described. The first lifetime control region 151 of this example is located at a depth position L p2 In addition, when the buffer region 20 has multiple hydrogen peaks such as the third peak 63 or the fourth peak 64, the first lifetime control region 151 may be provided at the same depth position as any of the hydrogen peaks.

[0193] 3G shows a modified example of semiconductor device 100 including first lifetime control region 151. In this example, the position of first lifetime control region 151 differs from the embodiments of FIGS. 3A, 3B, and 3F. In this example, differences from the embodiments of FIGS. 3A, 3B, and 3F will be particularly described.

[0194] The peak position of first lifetime control region 151 in this example is between the hydrogen peak of buffer region 20 and drift region 18 in the depth direction of semiconductor substrate 10. That is, the peak position of first lifetime control region 151 in this example is located closer to front surface 21 than second peak 62 in the depth direction of semiconductor substrate 10. In addition, the peak position of first lifetime control region 151 is located closer to back surface 23 than drift region 18.

[0195] Here, even if the peak position of first lifetime control region 151 is located closer to front surface 21 than second peak 62, it is located close to second peak 62, so that dangling bonds of lattice defects in first lifetime control region 151 are terminated with hydrogen, thereby suppressing an increase in leakage current. "Close to second peak 62" means, for example, that the peak position of first lifetime control region 151 is located between second peak 62 and drift region 18. That is, the peak position of first lifetime control region 151 may be located inside the skirt of second peak 62 on the front surface 21 side.

[0196] 3H shows a modified example of semiconductor device 100 including first lifetime control region 151. The peak position of first lifetime control region 151 in this example is located in drift region 18, away from the hydrogen peak of buffer region 20 in the depth direction of semiconductor substrate 10. Even when the peak position of first lifetime control region 151 is located on front surface 21 away from second peak 62, lifetime control is also performed by first lattice defect region 161, so that first lifetime control region 151 can be formed by low-dose ion implantation rather than high-dose helium ion implantation, and an increase in leakage current can be suppressed.

[0197] Fig. 3I shows a modified example of semiconductor device 100 including first lifetime control region 151. In this example, a case where first lifetime control region 151 is provided in the embodiment shown in Fig. 2F will be described, but first lifetime control region 151 may also be combined with semiconductor device 100 disclosed in other embodiments.

[0198] The first lifetime control region 151 is provided between the second lattice defect region 162 and the fourth peak 64. In this case, the fourth peak 64 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type, as will be described later.

[0199] Furthermore, the first lifetime control region 151 may be provided between the first lattice defect region 161 and the third peak 63. In this case, the third peak 63 and the fourth peak 64 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type.

[0200] 3A to 3I may be used in appropriate combination with the multiple peaks of the buffer region 20 shown in FIGS. 2A to 2F. By appropriately changing the positions of the first lifetime control region 151 and the first lattice defect region 161, it is possible to improve the switching characteristics while suppressing an increase in leakage current.

[0201] 4 shows an example of the doping concentration distribution in the semiconductor substrate 10. This figure also shows the distribution of the doping concentration in the first lifetime control region 151. This figure also shows the integrated concentration from the upper end of the drift region 18.

[0202] In this specification, the value obtained by integrating the doping concentration along the depth direction of the semiconductor substrate 10 from the lower surface of the base region 14 to a specific position in the semiconductor substrate 10 is referred to as the "integral concentration." Furthermore, in this specification, when a forward bias is applied between the collector electrode 24 and the emitter electrode 52, the maximum value of the electric field strength reaches the critical electric field strength, causing avalanche breakdown, and the semiconductor substrate 10 is depleted from the lower surface of the base region 14 to a specific position in the depth direction, the integrated concentration is said to reach the critical integrated concentration Nc. In the semiconductor device 100, when a forward bias is applied between the collector electrode 24 and the emitter electrode 52, this means that the potential of the collector electrode 24 is higher than the potential of the emitter electrode 52 when the gate is in an off state. When avalanche breakdown occurs in the semiconductor device 100, an avalanche current flows between the collector electrode 24 and the emitter electrode 52, and the voltage V between the collector electrode 24 and the emitter electrode 52 increases. CE In this case, the depletion layer reaches the position L where the integrated concentration reaches the critical integrated concentration Nc. Nc It will not spread further towards the back side than the

[0203] In this example, the integral concentration obtained by integrating the doping concentration in the depth direction of the semiconductor substrate 10 from the top end of the drift region 18 to the hydrogen peak of the buffer region 20 is equal to or greater than the critical integral concentration Nc. More specifically, the first lattice defect region 161 is provided closer to the back surface 23 than the second peak 62, and the integral concentration in the depth direction of the semiconductor substrate 10 from the top end of the drift region 18 to the second peak 62 may be equal to or greater than the critical integral concentration Nc. The position L at which the critical integral concentration Nc is reached Nc is the depth position L of the second peak 62 p2 This allows the depletion layer spreading from the lower surface side of the base region 14 to be stopped by the second peak 62, so that the peak of the first lattice defect region 161 can be located in a region that is not depleted. This also makes it possible to suppress an increase in leakage current due to the formation of the first lattice defect region 161. For the same reason, the first lifetime control region 151 may be provided closer to the back surface 23 than the second peak 62.

[0204] Position L where the critical integral concentration Nc is reached Nc and the peak position of the buffer region 20 (in this example, the depth position L of the second peak 62 p2 ) do not have to coincide. The position L where the critical integral concentration Nc is reached Nc is the depth position L of the second peak 62 p2 The position L at which the critical integral concentration Nc is reached may be closer to the front surface 21 than the position L at which the depletion layer reaches the first lattice defect region 161. That is, it is sufficient if the depletion layer is stopped by any of the hydrogen peaks in the buffer region 20 before it reaches the first lattice defect region 161. Nc is the depth position L of the third peak 63 p3 or the depth position L of the fourth peak 64 p4 It may be.

[0205] 5A shows a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

[0206] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the rear surface 23 of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is an N+ type, for example. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0207] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15. In this example, the boundary portion 90 does not have an emitter region 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0208] The contact holes 54 are provided above the base region 14 in the diode section 80. The contact holes 54 are provided above the contact regions 15 in the boundary section 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0209] The mesa portion 91 is provided between the multiple trench portions at the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0210] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0211] The emitter region 12 is provided in the mesa portion 71, but may not be provided in the mesa portion 81 or the mesa portion 91. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but may not be provided in the mesa portion 81.

[0212] 5B shows a cross section taken along the line b-b' of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a first lifetime control region 151 and a second lifetime control region 152. The buffer region 20 may have the configuration of any of the embodiments. That is, the number and positions of the peaks in the buffer region 20 are not particularly limited.

[0213] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0214] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 does not have to be provided in the diode section 80.

[0215] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 in this example.

[0216] The first lattice defect region 161 is provided in both the transistor portion 70 and the diode portion 80. This allows the semiconductor device 100 of this example to speed up recovery in the diode portion 80 and further improve switching loss. The position of the first lattice defect region 161 in the depth direction may be the position described in any of the examples.

[0217] The first lifetime control region 151 is provided in both the transistor portion 70 and the diode portion 80. This allows the semiconductor device 100 of this example to speed up recovery in the diode portion 80 and further improve switching loss. The first lifetime control region 151 may be formed at a position described in any of the examples.

[0218] The second lifetime control region 152 is a region in which a lifetime killer is intentionally formed by, for example, implanting impurities into the semiconductor substrate 10. The second lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the second lifetime control region 152 is provided in the drift region 18. The second lifetime control region 152 may be provided in the diode section 80. Alternatively, the second lifetime control region 152 may be provided in both the transistor section 70 and the diode section 80. In this example, the second lifetime control region 152 is provided in both the transistor section 70 and the diode section 80. The second lifetime control region 152 may be formed by implanting impurities from the front surface 21 side or from the back surface 23 side. The second lifetime control region 152 is provided between the diode section 80 and the boundary section 90, and may not be provided in a part of the transistor section 70.

[0219] The second lifetime control region 152 may be formed by any method. The elements and doses used to form the first lifetime control region 151 and the second lifetime control region 152 may be the same or different. The second lifetime control region 152 may be formed by ion implantation of hydrogen, helium, or the like, or by electron beam irradiation.

[0220] 6A is a flowchart showing an example of a manufacturing process for semiconductor device 100. In step S100, a structure is formed on the front surface side of semiconductor device 100. Also, in step S100, after the structure on the front surface side is formed, the back surface 23 side of semiconductor substrate 10 is ground to adjust the thickness of semiconductor substrate 10 according to the required withstand voltage.

[0221] In step S102, ions are implanted from the rear surface 23 side of the semiconductor substrate 10 to form the first peak 61. The first peak 61 may be formed by ion implantation of phosphorus, by ion implantation of hydrogen, or by any other method.

[0222] For example, if the first peak 61 is phosphorus, the dose of the dopant in the first peak 61 is 1.0E12 cm -2 It may be more than 2.0E12cm -2 The dose of the dopant at the first peak 61 may be 1.0E13 cm -2 May be less than 5.0E12cm -2 The dose of the dopant in the first peak 61 in this example may be 3.0E12 cm -2 The acceleration energy of the dopant of the first peak 61 may be 500 keV or more, or may be 700 keV or more. The acceleration energy of the dopant of the first peak 61 may be 4000 keV or less, or may be 3000 keV or less. In this example, the acceleration energy of the dopant of the first peak 61 is 2000 keV.

[0223] In step S104, the semiconductor substrate 10 is annealed to form the first peak 61. That is, in this example, the semiconductor substrate 10 is annealed after the ion implantation of the first peak 61 and before the ion implantation of the lattice defect region. For example, in step S104, the back surface 23 of the semiconductor substrate 10 is heated by laser annealing. Alternatively, in step S104, the semiconductor substrate 10 may be heated in an annealing furnace in a nitrogen atmosphere or the like. The annealing temperature in the annealing furnace may be 350° C. or higher and 420° C. or lower. The annealing time may be 10 minutes or higher and 20 hours or shorter.

[0224] In step S106, ions are implanted from the back surface 23 side of the semiconductor substrate 10 to form a lattice defect region. In this example, after annealing to form the first peak 61, hydrogen ions are implanted to form the first lattice defect region 161. The first lattice defect region 161 is formed by implanting hydrogen ions deeper into the semiconductor substrate 10 than the first peak 61 toward the front surface 21. To form multiple hydrogen peaks in the buffer region 20, hydrogen ions may be implanted multiple times with different acceleration energies.

[0225] The first lattice defect region 161 may be formed by ion implantation for forming any of the hydrogen peaks in the buffer region 20. That is, the first lattice defect region 161 may be formed by ion implantation for forming the second peak 62, the third peak 63, or the fourth peak 64.

[0226] As an example, the dose of hydrogen ions corresponding to the second peak 62 is 7.0×10 12 / cm 2 The acceleration energy is 1100 keV. The dose of hydrogen ions corresponding to the third peak 63 is 1.0 × 10 13 / cm 2 The acceleration energy is 800 keV. The dose of hydrogen ions corresponding to the fourth peak 64 is 3.0 × 10 14 / cm 2 The acceleration energy is 300 keV.

[0227] In step S108, the semiconductor substrate 10 is annealed to form a lattice defect region. The semiconductor substrate 10 may be heated in an annealing furnace in an atmosphere of hydrogen and nitrogen, for example. In one example, the annealing to form the first lattice defect region 161 is performed at a temperature lower than that of the annealing to form the first peak 61. Alternatively, the annealing to form the first lattice defect region 161 may be performed for a shorter time than that of the annealing to form the first peak 61. For example, the annealing temperature to form the first lattice defect region 161 may be 350° C. or higher and 380° C. or lower. The annealing time may be 10 minutes or higher and 3 hours or lower.

[0228] In step S110, the collector electrode 24 is formed. The collector electrode 24 may be formed on the entire back surface 23. For example, the collector electrode 24 is formed by a sputtering method. The collector electrode 24 may be a laminated electrode in which an aluminum layer, a titanium layer, a nickel layer, etc. are laminated. The semiconductor device 100 can be manufactured through these steps.

[0229] Note that steps S102 and S104 may be interchanged with steps S106 and S108, i.e., steps S100, S106, S108, S102, S104 and S110 may be executed in this order.

[0230] Fig. 6B is a flowchart showing a modified example of the manufacturing process of the semiconductor device 100. In this example, differences from the embodiment of Fig. 6A will be particularly described. The semiconductor device 100 of this example differs from that of Fig. 6A in that annealing of the first peak 61 and the lattice defect region is performed simultaneously.

[0231] In step S102, hydrogen ions may be implanted to form the first peak 61. By implanting the first peak 61 with hydrogen ions, it becomes easier to share the annealing process with the lattice defect region. In this example, the annealing process dedicated to the first peak 61 in step S104 in FIG. 6A is omitted. In step S106, the conditions for implanting hydrogen ions to form the lattice defect region may be the same as the conditions for implanting hydrogen ions in step S106 in FIG. 6A.

[0232] In step S108, after ion implantation to form the lattice defect region, annealing to form the first peak 61 and the lattice defect region is performed simultaneously. In this example, the annealing step for the first peak 61 and the first lattice defect region 161 is shared. If the semiconductor device 100 includes the second lattice defect region 162, the annealing step for the first peak 61, the first lattice defect region 161, and the second lattice defect region 162 may be shared. This can simplify the annealing step for forming the buffer region 20.

[0233] Fig. 6C is a flowchart showing a modified example of the manufacturing process of the semiconductor device 100. In this example, differences from the embodiment of Fig. 6A will be particularly described. This example differs from the embodiment of Fig. 6A in that a lifetime control region is further formed.

[0234] In step S107, ion implantation is performed to form the lifetime control region. For example, helium is ion implanted to form the first lifetime control region 151. The dose of the impurity to form the first lifetime control region 151 is 0.5E10 cm -2 More than 1.0E13cm -2 Even if it is less than 5.0E10cm -2 Above, 5.0E11cm -2 The acceleration energy for forming the first lifetime control region 151 may be 50 keV or more and 2000 keV or less. In this example, the ion implantation for the lifetime control region is performed after the ion implantation for the lattice defect region in step S106, but the ion implantation for the lifetime control region may be performed after the ion implantation for the lifetime control region.

[0235] In step S108, the semiconductor substrate 10 is annealed to form the lattice defect region and the lifetime control region. By sharing the annealing process for the lattice defect region and the lifetime control region in this way, the annealing process for forming the buffer region 20 can be simplified. For example, in step S108, the semiconductor substrate 10 is heated in an annealing furnace in a nitrogen atmosphere or the like.

[0236] 7 is a diagram illustrating the electrical characteristics of the semiconductor device 100. This diagram shows three axes: turn-off loss Eoff (mJ), collector-emitter saturation voltage Vce(sat), and leakage current Ileak (A). The semiconductor device 100 of this example has a hydrogen peak for stopping the depletion layer spreading from the lower surface side of the base region 14, and has a lattice defect region on the back surface 23 side of the hydrogen peak, so the electrical characteristics of the semiconductor device 100 can be improved.

[0237] For example, the trade-off between turn-off loss Eoff and collector-emitter saturation voltage Vce can be improved by adjusting the position of first lifetime control region 151 or first lattice defect region 161. By using first lifetime control region 151 and first lattice defect region 161 in combination, it becomes easier to reduce leakage current at any position of turn-off loss Eoff and collector-emitter saturation voltage Vce than when first lattice defect region 161 is used alone.

[0238] Furthermore, the semiconductor device 100 includes a hydrogen peak for stopping the depletion layer closer to the front surface 21 than the first lattice defect region 161, thereby suppressing an increase in the leakage current Ileak. In other words, even when the defect density in the buffer region 20 is increased, the connection between the depletion layer and the first lattice defect region 161 can be avoided, thereby suppressing an increase in the leakage current Ileak while improving the trade-off between the turn-off loss Eoff and the collector-emitter saturation voltage Vce. That is, the trade-off on the three axes, the saturation voltage Vce axis, the turn-off loss Eoff axis, and the leakage current Ileak axis, can be simultaneously improved. In this way, the semiconductor device 100 can improve the trade-off among the turn-off loss Eoff, the collector-emitter saturation voltage Vce, and the leakage current Ileak by adjusting the structure of the buffer region 20 according to the desired electrical characteristics.

[0239] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0240] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0241] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 connection portion, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 41 extension portion, 42 gate insulating film, 43 connection portion, 44 gate conductive portion, 50 gate metal layer, 52 emitter electrode, 54 contact Hole, 55...contact hole, 56...contact hole, 61...first peak, 62...second peak, 63...third peak, 64...fourth peak, 70...transistor portion, 71...mesa portion, 80...diode portion, 81...mesa portion, 82...cathode region, 90...boundary portion, 91...mesa portion, 100...semiconductor device, 151...first lifetime control region, 152...second lifetime control region, 161...first lattice defect region, 162...second lattice defect region, 170...hydrogen chemical concentration distribution, 171...hydrogen chemical concentration peak, 172...hydrogen chemical concentration peak, 173...hydrogen chemical concentration peak, 174...hydrogen chemical concentration peak

Claims

[Claim 1] A method for manufacturing a semiconductor device including: a drift region of a first conductivity type; a base region of a second conductivity type provided on a front surface side of a semiconductor substrate relative to the drift region; and a buffer region of the first conductivity type provided on a back surface side of the semiconductor substrate relative to the drift region, a first ion implantation step of implanting hydrogen or phosphorus from the backside of the semiconductor substrate; a first annealing step of heating the semiconductor substrate to form a first peak in a doping concentration distribution in the buffer region; a second ion implantation step of implanting hydrogen from the backside of the semiconductor substrate to form a lattice defect region; a second annealing step in which the semiconductor substrate is heated at a temperature lower than that of the first annealing step to form the buffer region including the lattice defect region; A method for manufacturing a semiconductor device comprising:

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