Control circuit and semiconductor device

Abstract

To provide a control circuit that is able to adjust a time taken to stop an operation, according to a degree of stress on a switching element when an input voltage drops.SOLUTION: A control circuit 10 of a resonant converter 1 includes: an off-resonance detection circuit 30 that detects an off-resonance, based on a resonant current; a counter 40 that stops an operation of the resonant converter 1 when a count time elapses in a state where the off-resonance is detected by the off-resonance detection circuit 30; and a low input voltage protection circuit 20 that switches the count time of the counter 40 according to a voltage Vin input to the resonant converter.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments of the present disclosure relate to a control circuit and a semiconductor device. [Background technology]

[0002] When the input voltage drops in a resonant converter, an out-of-resonance phenomenon occurs, causing a through current to flow through the switch elements that make up the current resonant circuit, placing excessive stress on them. Therefore, resonant converters set an out-of-resonance detection level to monitor the current value of the resonant current, and when a drop in the current value is detected due to a drop in the input voltage, the converter stops operation (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6849143 Summary of the Invention [Problem to be solved by the invention]

[0004] However, since there are a wide variety of power supply specifications, and the input voltage at which off-resonance occurs varies, it has been necessary to vary the off-resonance detection level according to the input voltage in order to detect off-resonance that occurs when the input voltage drops and quickly stop operation.

[0005] The present disclosure aims to provide a control circuit that can adjust the time until operation stops depending on the degree of stress on the switch element when the input voltage drops. [Means for solving the problem]

[0006] The control circuit of the present disclosure is a control circuit for a resonant converter, and is characterized by comprising: an out-of-resonance detection circuit that detects out-of-resonance based on a resonant current; a counter that stops operation of the resonant converter when a count time has elapsed while the out-of-resonance detection circuit has detected the out-of-resonance; and a low input voltage protection circuit that switches the count time of the counter depending on the input voltage to the resonant converter. [Effects of the Invention]

[0007] The control circuit of the present disclosure can adjust the time until operation stops depending on the degree of stress on the switch element when the input voltage drops. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing a configuration of a resonant converter using a control circuit according to the present invention; [Figure 2] FIG. 2 is a diagram illustrating a configuration of a common control circuit shown in FIG. [Figure 3] 10A and 10B are diagrams illustrating the operation of the low input voltage protection circuit. [Figure 4] 10A and 10B are diagrams illustrating the operation of an off-resonance detection circuit. [Figure 5] FIG. 10 illustrates an example of the configuration of a counter. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

[0010] The control circuit 10 of this embodiment is a semiconductor device such as an IC that is integrated on a substrate and sealed in a package made of resin, and is a control circuit that drives the LLC type resonant converter 1 shown in Figure 1.

[0011] The resonant converter 1 includes an X capacitor Cx connected between phases of an AC input power line, a full-wave rectifier circuit 2 that full-wave rectifies the AC input, a smoothing capacitor C1 connected across the output of the full-wave rectifier circuit 2, and a PFC circuit 3 that improves the power factor of the DC voltage rectified by the full-wave rectifier circuit 2 and smoothed by the smoothing capacitor C1. A control circuit 10 uses the output of the PFC circuit 3 as an input voltage Vin to drive a high-side switching element QH and a low-side switching element QL that are connected in series between the input voltage Vin and ground.

[0012] The control circuit 10 includes a VS (high-side ground) terminal, a VGH (high-side output) terminal, a GND (ground) terminal, and a VGL (low-side output) terminal. The switching element QH is connected between the input voltage Vin and the VS terminal and is driven by a high-side drive signal output from the VGH terminal. The switching element QL is connected between the VS terminal and the GND terminal and is driven by a low-side drive signal output from the VGL terminal. In the control circuit 10, the VB terminal is a terminal for inputting high-side drive power, and the REG terminal is a terminal for outputting power for the drive circuit.

[0013] The control circuit 10 has an ST (startup current input) terminal to which a startup current from a power supply input is input via a resistor R1 at startup, an FB_PFC (power supply signal input) terminal to which a divided voltage value obtained by dividing the input voltage Vin by a voltage divider circuit 4 is input as an input voltage detection signal, and a detection resistor R OCP and an RC (current detection signal input) terminal to which a current detection signal detected by the current detection signal input terminal is input.

[0014] The control circuit 10 includes a startup circuit (not shown) connected to an ST (startup current input) terminal, and when the ST terminal voltage rises, a capacitor Cvcc connected across the auxiliary winding of the transformer T1 is charged with a constant current. When the VCC terminal voltage rises to a predetermined value, the PFC circuit 3 starts operating.

[0015] 2, the control circuit 10 includes an oscillator OSC and a low input voltage protection circuit 20 connected to the FB_PFC terminal, an off-resonance detection circuit 30 connected to the RC terminal, and a counter 40. Referring to Fig. 3, the oscillator OSC outputs a high-side control signal Vho and a low-side control signal Vlo when the voltage Vfb of the FB_PFC terminal becomes equal to or greater than a first FB threshold voltage (VLLCuvlo_th1). That is, the first FB threshold voltage is a drive start voltage that starts the drive of the resonant converter 1.

[0016] The high-side control signal Vho and the low-side control signal Vlo are complementary signals with a dead time sandwiched between them, as shown in Fig. 4. As shown in Fig. 3, the high-side control signal Vho is output from the VGH terminal as a high-side drive signal that drives the switching element QH via the AND circuit AND1, the level shift circuit 11, and a driver. The low-side control signal Vlo is output from the VGL terminal as a low-side drive signal that drives the switching element QL via the AND circuit AND2, the level shift circuit 11, and a driver.

[0017] The low input voltage protection circuit 20 includes a comparator COMP21 that compares the voltage Vfb at the FB_PFC terminal with a first FB threshold voltage (VLLCuvlo_th1), and a comparator COMP22 that compares the voltage Vfb at the FB_PFC terminal with a second FB threshold voltage (VLLCuvlo_th2) that is lower than the first FB threshold voltage. When the voltage Vfb exceeds the first FB threshold voltage, the output uvlo1 of the comparator COMP21 goes high, setting the RS flip-flop FF21. When the voltage Vfb falls below the second FB threshold voltage, the output uvlo2 of the comparator COMP22 goes high, resetting the RS flip-flop FF21.

[0018] The output VLLC_uvlo of the RS flip-flop FF21 is input to one input terminal of an AND circuit AND1, and the high-side control signal Vho is input to the other input terminal of the AND circuit AND1. The output VLLC_uvlo of the RS flip-flop FF21 is input to one input terminal of an AND circuit AND2, and the low-side control signal Vlo is input to the other input terminal of the AND circuit AND2. Therefore, the high-side drive signal and the low-side drive signal are output from the control circuit 10 when the RS flip-flop FF21 is set, and are cut off when the RS flip-flop FF21 is reset. That is, the second FB threshold voltage becomes a drive stop voltage.

[0019] The output VLLC_uvlo of the RS flip-flop FF21 is input to one input terminal of an AND circuit AND21, and the output uvlo2 of the comparator COMP22 is input to the other input terminal of the AND circuit AND21 via an inverter INV. The output of the AND circuit AND21 is input to one inverting input terminal of an OR circuit OR1 as a timer switching signal Tm_chg that switches the count time, and the output of this signal is output to the counter 40.

[0020] The off-resonance detection circuit 30 includes a negative-side detection circuit 31 and a positive-side detection circuit 32. The negative-side detection circuit 31 detects when the voltage Vrc at the RC terminal falls below a negative-side threshold Vrc_mth. The negative-side detection circuit 31 includes a comparator COMP31 whose output COMP31_O falls when the voltage Vrc at the RC terminal falls below a negative-side threshold Vrc_mth, and a one-shot circuit 311 that detects the falling edge of the output COMP31_O and outputs a pulse signal Vrc_l. The positive-side detection circuit 32 detects when the voltage Vrc at the RC terminal exceeds a positive-side threshold Vrc_pth. The positive-side detection circuit 32 includes a comparator COMP31 whose output COMP32_O falls when the voltage Vrc at the RC terminal exceeds a positive-side threshold Vrc_pth, and a one-shot circuit 321 that detects the falling edge of the output COMP32_O and outputs a pulse signal Vrc_h.

[0021] The pulse signal Vrc_l is input to the set terminal S of the RS flip-flop FF32, and the timing signal Vdhl from the oscillator OSC is input to the reset terminal R of the RS flip-flop FF32. The timing signal Vdhl is a signal that notifies the dead time from when the high-side drive signal falls until when the low-side drive signal rises. The pulse signal Vrc_h is input to the set terminal S of the RS flip-flop FF31, and the timing signal Vdlh from the oscillator OSC is input to the reset terminal R of the RS flip-flop FF31. The timing signal Vdlh is a signal that notifies the dead time from when the low-side drive signal falls until when the high-side drive signal rises.

[0022] The output Q32 of the RS flip-flop FF32 is input to one input terminal of a NOR circuit NOR, and the output Q31 of the RS flip-flop FF31 is input to the other input terminal of the NOR circuit NOR. The output Vrc_det of the NOR circuit NOR is input to the reset terminal of the counter 40 as a timer reset signal Tm_R via an OR circuit OR1.

[0023] The off-resonance detection circuit 30 detects an off-resonance state by comparing the rising timing of the high-side drive signal VGH with the timing when the voltage Vrc falls below the positive threshold Vrc_pth. The off-resonance detection circuit 30 also detects an off-resonance state by comparing the falling timing of the low-side drive signal VGL with the timing when the voltage Vrc exceeds the negative threshold Vrc_mth.

[0024] 4A shows a state when current resonance is not detected. When not detected, after the high-side drive signal VGH rises, the voltage Vrc falls below the positive threshold Vrc_pth, and after the low-side drive signal VGL falls, the voltage Vrc exceeds the negative threshold Vrc_mth. When not detected, the output Vrc_det input as the timer reset signal Tm_R to the reset terminal of the counter 40 is a pulse signal that goes high at the falling edges of the high-side drive signal VGH and the low-side drive signal VGL. That is, the counter 40 is instructed to reset for each oscillation frequency of the oscillator OSC by the output Vrc_det (timer reset signal Tm_R).

[0025] 4(b) shows the state when an off-current resonance state is detected. When detected, the high-side drive signal VGH rises after the voltage Vrc falls below the positive threshold Vrc_pth, and the low-side drive signal VGL falls after the voltage Vrc exceeds the negative threshold Vrc_mth. When not detected, the output Vrc_det input as the timer reset signal Tm_R to the reset terminal of the counter 40 is maintained at a low level. That is, the counter 40 does not instruct the oscillator OSC to reset by the output Vrc_det (timer reset signal Tm_R).

[0026] The counter 40 outputs the LLC operation stop signal Vosc_off to the oscillator unit OSC when the count time set by the timer switching signal Tm_chg has elapsed without being instructed to be reset by the output Vrc_det (timer reset signal Tm_R). Referring to FIG. 3, the timer switching signal Tm_chg goes high when the voltage Vfb at the FB_PFC terminal drops and is in the range from the first FB threshold voltage (VLLCuvlo_th1) to the second FB threshold voltage (VLLCuvlo_th2). The count time of the counter 40 is set to a first count time when the timer switching signal Tm_chg is low level, and is switched to a second count time that is shorter than the first count time when the timer switching signal Tm_chg is high level.

[0027] The counter 40 can be configured, for example, as shown in Fig. 5, with D-type flip-flops F1 to F12 connected in multiple stages. In the example shown in Fig. 5, when the timer switching signal Tm_chg is at a low level, the AND circuit AMD42 opens, and the output of the D-type flip-flop F12 is output as the LLC operation stop signal Vosc_off via the OR circuit OR41. When the timer switching signal Tm_chg is at a high level, the AND circuit AMD41 opens, and the output of the D-type flip-flop F1 is output as the LLC operation stop signal Vosc_off via the OR circuit OR41. In this case, if the Vclk input to the Set terminal is 20 kHz, the first count time (output of the D-type flip-flop F12) is approximately 100 ms, and the second count time (output of the D-type flip-flop F1) is approximately 100 µs.

[0028] The features of the above embodiment are summarized below. As described above, this embodiment is a control circuit 10 of a resonant converter 1, and includes an off-resonance detection circuit 30 that detects out-of-resonance based on the resonant current, a counter 40 that stops the operation of the resonant converter 1 when the count time has elapsed while the off-resonance detection circuit 30 has detected out-of-resonance, and a low input voltage protection circuit 20 that switches the count time of the counter 40 in accordance with the input voltage Vin to the resonant converter. With this configuration, when the input voltage drops, the time until the operation stops can be adjusted according to the degree of stress on the switch element.

[0029] Furthermore, according to this embodiment, when the input voltage Vin falls below a second threshold voltage (second FB threshold voltage VLLCuvlo_th2) that is lower than the first threshold voltage (first FB threshold voltage VLLCuvlo_th1), the low input voltage protection circuit 20 immediately stops the operation of the resonant converter 1, and when the input voltage Vin drops to a range below the first threshold voltage and above the second threshold voltage, switches the count time to a shorter time. With this configuration, when an off-resonance state is detected due to a drop in the input voltage, operation can be stopped quickly.

[0030] Furthermore, according to this embodiment, the first threshold voltage is a drive start voltage that causes the resonant converter 1 to start driving. With this configuration, the input voltage at which the count time is switched to a shorter time can be set within a practical range.

[0031] It is clear that the present invention is not limited to the above-described embodiments, and that each embodiment can be appropriately modified within the scope of the technical concept of the present invention. Furthermore, the number, position, shape, etc. of the above-described components are not limited to the above-described embodiments, and the number, position, shape, etc. can be set to be suitable for implementing the present invention. Note that the same components are denoted by the same reference numerals in each drawing. [Explanation of symbols]

[0032] 1. Resonant converter 2 Full wave rectifier circuit 3 PFC circuit 4 Voltage divider circuit 10 Control circuit 11 Level shift circuit 20 Low input voltage protection circuit 30 Off-resonance detection circuit 31 Minus side detection circuit 32 Positive side detection circuit 40 Counters 311, 321 One-shot circuit

Claims

1. A control circuit for a resonant converter, comprising: an off-resonance detection circuit that detects off-resonance based on the resonance current; a counter that stops operation of the resonant converter when a count time has elapsed in a state where the off-resonance detection circuit has detected the off-resonance; a low input voltage protection circuit that switches the count time of the counter in accordance with the input voltage to the resonant converter.

2. 2. The control circuit according to claim 1, wherein the low input voltage protection circuit immediately stops operation of the resonant converter when the input voltage falls below a second threshold voltage that is lower than the first threshold voltage, and switches the count time to a shorter time when the input voltage is within a range of less than the first threshold voltage and greater than or equal to the second threshold voltage.

3. 3. The control circuit according to claim 2, wherein the first threshold voltage is a drive start voltage that starts driving the resonant converter.

4. 3. A semiconductor device comprising the control circuit according to claim 1 or 2 integrated on a substrate.

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