Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a useless region of an element region while improving an off-breakdown voltage.SOLUTION: One of a source region 33 and a drain region 36 is formed on an inner edge side in an element region 14 to constitute an inner edge region 32 while the other of them is formed on an outer edge side of a trench separation portion side 20 in the element region 14 to constitute an outer edge region 37. When one direction in a surface direction of a main surface 10a is defined as a first direction and a direction intersecting the first direction is defined as a second direction, the device region 14 and the inner edge region 32 are formed such that a first element region length L1 along the first direction from the inner edge region 32 to the trench separation portion 20 is longer than a second element region length L2 along the second direction from the inner edge region 32 to the trench separation portion 20. The outer edge region 37 is formed only in a portion located in the first direction from the inner edge region 32.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices have been proposed in which a source region and a drain region are formed in a surface layer portion of an element region in a semiconductor substrate (see, for example, Patent Document 1). Specifically, in this semiconductor device, the element region has a substantially rectangular shape in plan view. An n-type drain region is formed in the substantially central portion of the element region, and an n-type source region is formed in the outer edge portion. More specifically, if a direction along one direction in the surface direction is defined as a first direction and a direction perpendicular to the first direction in the surface direction is defined as a second direction, the element region and the drain region are formed so that the length in the first direction to the outer edge of the element region is longer than the length in the second direction. The source region is formed in a position in the element region that is in the second direction from the drain region, but is not formed in a position in the first direction from the drain region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 06261122 Summary of the Invention [Problem to be solved by the invention]

[0004] In such a semiconductor device, the source region is formed in a position in the second direction from the drain region, which tends to shorten the distance between the drain region and the source region. Therefore, in such a semiconductor device, the off-state breakdown voltage, which is the breakdown voltage when the device is off, may be easily reduced. Furthermore, the region located in the first direction from the drain region does not have a source region, so it does not become a part through which current flows. Therefore, in such a semiconductor device, the region through which no current flows becomes large, which may easily increase wasted area.

[0005] An object of the present disclosure is to provide a semiconductor device that can reduce wasted area in the element region while improving the off-state breakdown voltage. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, a semiconductor device includes a semiconductor substrate (10) having an active layer (13), in which an element region (14) is defined by a trench isolation (20), the surface of the active layer being a main surface (10a), a body layer (31) of a first conductivity type formed in a surface portion of the active layer in the element region, a source region (32) of a second conductivity type formed in a surface portion of the body layer, a drift region (35) of the second conductivity type formed in a surface portion of the active layer in the element region, a drain region (36) of the second conductivity type formed in a surface portion of the drift region, a gate insulating film (61) formed on the body layer, and a gate electrode (62) arranged on the gate insulating film. , one of the source region and the drain region is formed on the inner edge side of the element region to form an inner edge region (32), and the other is formed on the outer edge side of the element region on the trench isolation side to form an outer edge region (37), and if one direction in the planar direction of the main surface is defined as a first direction and a direction intersecting the first direction is defined as a second direction, the element region and the inner edge region are formed such that the first element region length (L1) along the first direction from the inner edge region to the trench isolation is longer than the second element region length (L2) along the second direction from the inner edge region to the trench isolation, and the outer edge region is formed only in the portion located from the inner edge region in the first direction.

[0007] According to this, the outer edge region is formed only in a portion located in the first direction from the inner edge region. Therefore, it is possible to prevent the region between the inner edge region, which has a longer length in the element region, and the trench isolation from being wasted. In addition, it is possible to prevent the length between the inner edge region and the outer edge region (i.e., the source region and the drain region) from being shortened, and it is possible to prevent a decrease in the off-state breakdown voltage.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 10 is a schematic diagram showing equipotential lines in an off state. [Figure 5] FIG. 10 is a graph showing the relationship between GFY / DLY and off-state breakdown voltage. [Figure 6] FIG. 10 is a diagram showing the relationship between trench depth and off-state breakdown voltage. [Figure 7] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. [Figure 9] FIG. 8 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a schematic diagram showing equipotential lines in an off state. [Figure 11] FIG. 10 is a diagram showing the relationship between DDY / DLY and off-state breakdown voltage. [Figure 12] FIG. 10 is a diagram showing the relationship between trench depth and off-state breakdown voltage. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0011] (First embodiment) A first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is suitable for use in, for example, configuring a battery monitoring system that monitors the state of a battery such as a lithium-ion battery mounted on a vehicle. In this embodiment, a semiconductor device having a p-channel LDMOS formed therein will be described below with reference to FIGS. 1 to 3.

[0012] The semiconductor device of this embodiment is constructed using an SOI (abbreviation of Silicon On Insulator) substrate 10 in which an active layer 13 is stacked on a support substrate 11 via a buried insulating film 12. In this embodiment, the SOI substrate 10 corresponds to the semiconductor substrate. The support substrate 11 is made of a silicon substrate or the like, and the buried insulating film 12 is made of an oxide film or the like. The active layer 13 is made of n-type silicon with a predetermined impurity concentration. - The SOI substrate 10 is configured using a silicon substrate or the like. Hereinafter, the surface of the SOI substrate 10 including the surface of the active layer 13 is also referred to as the main surface 10a of the SOI substrate 10. In the following description, one direction in the planar direction of the main surface 10a of the SOI substrate 10 is referred to as a first direction, and a direction intersecting the first direction is referred to as a second direction. For example, in FIG. 1, the up-down direction on the paper surface is the first direction, and the left-right direction on the paper surface is the second direction.

[0013] The active layer 13 is separated into an element region 14 and a field ground region 15 by the trench isolation 20. In this embodiment, the active layer 13 is separated by the trench isolation 20 so that the element region 14 is surrounded by the field ground region 15. The element region 14 in this embodiment has a substantially rectangular shape in plan view. That is, the trench isolation 20 in this embodiment is formed in a rectangular frame shape, and is configured such that first portions 20a facing each other along the first direction and second portions 20b facing each other along the second direction are connected to each other.

[0014] The trench isolation portion 20 is configured by disposing an insulating film 22 in a trench 21 formed so as to extend from the main surface 10a of the SOI substrate 10 to the buried insulating film 12, so as to fill the trench 21. The insulating film 22 is disposed in the trench 21 by filling an insulating material by thermal oxidation or deposition.

[0015] As described above, the element region 14 has a generally rectangular shape in plan view, and an n-type body layer 31 having a higher impurity concentration than the active layer 13 is formed in the center of the surface layer of the active layer 13. An inner edge region 32 is formed in the surface layer of the body layer 31 so as to be exposed from the main surface 10a of the SOI substrate 10.

[0016] The inner edge region 32 of this embodiment is p + type source region 33 and n + The body layer 31 is formed to include a contact region 34. In this embodiment, the source region 33 and the contact region 34 are alternately arranged in a ladder shape along the second direction, with the contact regions 34 arranged at both ends in the second direction. The contact region 34 functions as an extraction region that extracts minority carriers while stabilizing the potential of the body layer 31.

[0017] The element region 14 and the inner edge region 32 (i.e., the source region 33) are formed so that the first element region length L1 along the first direction from the inner edge region 32 to the second portion 20b in the trench isolation portion 20 is longer than the second element region length L2 along the second direction from the inner edge region 32 to the first portion 20a in the trench isolation portion 20.

[0018] In this embodiment, a metal silicide layer 41 is formed on the source region 33 and the contact region 34. More specifically, the metal silicide layer 41 is formed so as to straddle the source region 33 and the contact region 34. The source region 33 and the contact region 34 are connected to the metal silicide layer 41, respectively.

[0019] The surface layer of the active layer 13 is provided with a p - A drift region 35 having a shape similar to that of the body layer 31 is formed. In this embodiment, the drift region 35 is formed in a frame shape so as to surround the body layer 31 in the normal direction (hereinafter simply referred to as the normal direction) to the main surface 10a of the SOI substrate 10. That is, the drift region 35 is formed in a frame shape along the first portion 20a and the second portion 20b of the trench isolation 20. The normal direction to the main surface 10a of the SOI substrate 10, in other words, is the direction along the stacking direction of the support substrate 11 and the active layer 13. In addition, "in the normal direction" can also be referred to as when viewed from the normal direction. In this embodiment, the drift region 35 is formed to a depth substantially equal to that of the body layer 31.

[0020] The surface layer of the drift region 35 is exposed from the main surface 10a of the SOI substrate 10, and has a p + A p-type drain region 36 is formed in the drift region 35. Specifically, the drain region 36 is formed in a surface layer portion of the drift region 35 located in a first direction from the inner edge region 32, but is not formed in a surface layer portion of the drift region 35 located in a second direction from the inner edge region 32. That is, the drain region 36 is formed along the second portion 20b of the trench isolation 20, but is not formed along the first portion 20a of the trench isolation 20. In this embodiment, a p-type buffer layer 38 is formed between the drift region 35 and the drain region 36 as a buffer layer that buffers the drain voltage. In this embodiment, a metal silicide layer 42 is formed on the drain region 36. In this embodiment, the drain region 36 corresponds to the outer edge region.

[0021] Furthermore, an STI (short for Shallow Trench Isolation) isolation portion 50 is formed in the surface layer portion of the active layer 13. The STI isolation portion 50 is configured by forming a trench 51 of a predetermined depth in the surface layer portion of the active layer 13 and burying an insulating film 52 in this trench 51. Note that the insulating film 52 is formed, for example, by burying the trench 51 after the trench 51 is formed, and then planarizing it by a CMP (short for Chemical Mechanical Polishing) method or the like. The insulating film 52 of the STI isolation portion 50 can also be said to be an isolation insulating film.

[0022] A first opening 50a and a second opening 50b are formed in the STI isolation unit 50. Specifically, the first opening 50a is formed to expose a central portion of the main surface 10a of the SOI substrate 10. In this embodiment, the first opening 50a is formed to expose the metal silicide layer 41 formed on the source region 33 and the contact region 34, the body layer 31, a portion of the drift region 35 on the body layer 31 side, and the active layer 13 located between the body layer 31 and the drift region 35. That is, the drift region 35 in this embodiment is formed to protrude toward the body layer 31 side beyond the STI isolation unit 50. The second opening 50b is formed to expose an outer edge of the main surface 10a of the SOI substrate 10. In this embodiment, the second opening 50b is formed to expose the metal silicide layer 42 formed on the drain region 36.

[0023] A gate electrode 62 is disposed on the main surface 10a of the SOI substrate 10 via a gate insulating film 61. Specifically, the gate electrode 62 is formed from above the body layer 31 to above the STI isolation 50, and is formed in a substantially circular ring shape. In this embodiment, the gate electrode 62 has a second gate electrode length G2 measured in the second direction from the end on the inner edge region 32 side, which is longer than a first gate electrode length G1 measured in the first direction from the end on the inner edge region 32 side. The gate electrode 62 is made of doped polysilicon or the like. In this embodiment, the gate electrode 62 corresponds to an electric field relaxation structure. The portion of the gate electrode 62 located above the STI isolation 50 functions as a field plate.

[0024] Furthermore, an underlying insulating film 70 is formed on the main surface 10a of the SOI substrate 10 so as to cover the gate electrode 62. The underlying insulating film 70 is made of a nitride film or the like. A wiring layer 80 is formed on the underlying insulating film 70. In this embodiment, the wiring layer 80 is configured to include an interlayer insulating film 91 and a wiring portion 101.

[0025] The interlayer insulating film 91 is made of a tetraethoxysilane (tetra ethyl orthosilicate) film or the like, and is formed on the base insulating film 70. The wiring portion 101 has an inner edge region wiring portion 101a located on the inner edge region 32 and an outer edge region wiring portion 101b located on the outer edge region 37. The inner edge region wiring portion 101a is electrically connected to the inner edge region 32 through an inner edge region via 91a formed in the interlayer insulating film 91. In this embodiment, as described above, the metal silicide layer 41 is formed on the source region 33 and the contact region 34. Therefore, the inner edge region wiring portion 101a is electrically connected to the source region 33 and the contact region 34 by being connected to the metal silicide layer 41 through the inner edge region via 91a.

[0026] The outer edge region wiring portion 101b is electrically connected to the outer edge region 37 through the outer edge region via 91b formed in the interlayer insulating film 91. In this embodiment, as described above, the metal silicide layer 42 is formed on the drain region 36. Therefore, the outer edge region wiring portion 101b is electrically connected to the drain region 36 by being connected to the metal silicide layer 42 through the outer edge region via 91b. Note that each of the vias 91a, 91b is formed by filling tungsten into a contact hole formed in each of the interlayer insulating films 91.

[0027] The above is the configuration of the semiconductor device in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. Next, the operation and effects of the semiconductor device will be explained, and the configuration will be explained in more detail.

[0028] In the semiconductor device described above, when a negative voltage is applied to the gate electrode 62, holes are attracted to the body layer 31 and the active layer 13, which are located on the opposite side of the gate electrode 62 with the gate insulating film 61 interposed therebetween, to form an inversion layer. This results in an on-state in which current flows between the source and the drain. At this time, the drain region 36 is formed in a portion extending in the first direction from the inner edge region 32, but not in a portion extending in the second direction. Therefore, current flows in the portion extending in the first direction from the inner edge region 32. This prevents the region of the element region 14 between the inner edge region 32, which has a longer length, and the second portion 20b of the trench isolation 20 from being wasted.

[0029] When the application of voltage to the gate electrode 62 is stopped, the inversion layer disappears, resulting in an off state in which no current flows between the source and drain, and the potential of the source region 33 becomes higher than the potential of the drain region 36. In this case, in this embodiment, the drain region 36 is formed in the portion extending in the first direction from the inner edge region 32, but not in the portion extending in the second direction. This prevents the length between the source region 33 and the drain region 36 from becoming shorter, and prevents a decrease in the off-state breakdown voltage.

[0030] Furthermore, since the second element region length L2 of the element region 14 is shorter than the first element region length L1, electric field concentration may occur between the inner edge region 32 and the first portion 20a of the trench isolation 20. For this reason, in this embodiment, the gate electrode 62 is extended onto the STI isolation 50, and the portion of the gate electrode 62 located above the STI isolation 50 functions as a field plate. The second gate electrode length G2 of the gate electrode 62 is longer than the first gate electrode length G1, and the region of the gate electrode 62 that functions as a field plate in the second direction is elongated. Therefore, as shown in FIG. 4 , the equipotential line EL (i.e., the electric field) between the inner edge region 32 and the first portion 20a of the trench isolation 20 is easily extended toward the first portion 20a of the trench isolation 20. Therefore, electric field concentration between the inner edge region 32 and the first portion 20a of the trench isolation 20 can be suppressed, and a decrease in the off-state breakdown voltage can be suppressed.

[0031] 2, the inventors obtained the following results using the end of the STI isolation 50 on the inner edge region 32 side (i.e., the first opening 50a) as a reference. That is, the inventors conducted extensive research into the relationship between the ratio of the length GFY of the gate electrode 62 located on the STI isolation 50 in the second direction to the length DLY in the second direction from the end of the STI isolation 50 on the inner edge region 32 side to the trench isolation 20 (hereinafter simply referred to as GFY / DLY) and the off-breakdown voltage, and obtained the results shown in FIG. 5. Note that in this embodiment, the length DLY in the second direction from the end of the STI isolation 50 on the inner edge region 32 side to the trench isolation 20 can also be referred to as the length DLY of the STI isolation 50 in the second direction.

[0032] As shown in FIG. 5, it is confirmed that the off-state breakdown voltage increases sharply as GFY / DLY increases when GFY / DLY is less than 0.16, and decreases sharply as GFY / DLY increases when GFY / DLY is greater than 0.70. For example, when a semiconductor device is used in a battery monitoring system, as in this embodiment, the off-state breakdown voltage is desired to be 250 V or higher. Therefore, in the semiconductor device of this embodiment, GFY / DLY is set to be 0.15 or more and 0.73 or less. This allows the semiconductor device to have an off-state breakdown voltage of 250 V or higher.

[0033] Furthermore, in this embodiment, since the drain region 36 is not formed along the first portion 20a as described above, an electric field is also applied to the first portion 20a of the trench isolation 20 during the off-state, as shown in FIG. 4. Therefore, it is preferable that the trench isolation 20 has a structure that is resistant to breakdown even when an electric field is applied during the off-state. For example, the inventors of the present invention have conducted extensive research into the relationship between the depth of the trench 21 and the off-state breakdown voltage in the semiconductor device of this embodiment, and obtained the results shown in FIG. 6. Note that FIG. 6 shows the simulation results when GFY is 9.0 μm and DLY is 15 μm.

[0034] As shown in FIG. 6, it has been confirmed that the deeper the trench 21, the higher the off-state breakdown voltage. For example, when GFY is 9.0 μm and DLY is 15 μm, it has been confirmed that an off-state breakdown voltage of 250 V or more can be obtained by making the depth of trench 21 4.6 μm or more. Thus, it is preferable that the depth of trench 21 is set to a depth that is less likely to be broken down even when an electric field is applied to the first portion 20a of trench isolation 20 in the off state, depending on the lengths of GFY and DLY. While an example in which the depth of trench 21 is changed has been described here, the off-state breakdown voltage may also be changed by changing the width of trench 21.

[0035] According to the present embodiment described above, the drain region 36 as the outer edge region 37 is formed only in the portion located in the first direction from the inner edge region 32. This prevents the region between the inner edge region 32, which has a longer length in the element region 14, and the second portion 20b of the trench isolation 20 from being wasted. Furthermore, it prevents the length between the source region 33 and the drain region 36 from being shortened, thereby preventing a decrease in the off-state breakdown voltage.

[0036] (1) In this embodiment, an electric field relaxation structure is formed in the gate electrode 62. Therefore, there is no need to provide a separate member to relax the electric field between the inner edge region 32 and the first portion 20a of the trench isolation 20, and an increase in the number of components can be suppressed.

[0037] (2) In this embodiment, the second gate electrode length G2 of the gate electrode 62 is longer than the first gate electrode length G1. This makes it easier to extend the equipotential line EL (i.e., the electric field) between the inner edge region 32 and the first portion 20a of the trench isolation 20 toward the first portion 20a of the trench isolation 20. This makes it possible to prevent electric field concentration between the inner edge region 32 and the first portion 20a of the trench isolation 20, and to prevent a decrease in the off-state breakdown voltage.

[0038] (3) In this embodiment, by setting GFY / DLY to 0.15 or more and 0.73 or less, a semiconductor device having an off-state breakdown voltage of 250 V or more can be obtained.

[0039] (Second embodiment) A second embodiment will be described. This embodiment is an n-channel semiconductor device, unlike the first embodiment. As the other features are the same as those of the first embodiment, a description thereof will be omitted here.

[0040] 7 to 9, in the semiconductor device of this embodiment, the drift region 35 is of n-type and is formed in the center of the surface layer of the active layer 13. The drain region 36 is of n +The drain region 36 is formed in a surface layer of the drift region 35 so as to be exposed from the main surface 10a of the SOI substrate 10. A metal silicide layer 42 is formed on the drain region 36. In this embodiment, the drain region 36 forms the inner edge region 32, and the drift region 35 corresponds to the electric field relaxation structure. In this embodiment, an n-type buffer layer 38 is disposed between the drift region 35 and the drain region 36 as a relaxation layer that relaxes the drain voltage. The buffer layer 38 has a higher impurity concentration than the drift region 35 and a lower impurity concentration than the drain region 36.

[0041] The body layer 31 is of p-type and is formed in a surface layer portion of the active layer 13 at a position away from the drift region 35. In this embodiment, the body layer 31 is formed so as to contact the second portion 20b of the trench isolation portion 20, but not so as to contact the first portion 20a. In other words, the body layer 31 is not formed in a portion located in the second direction from the drain region 36. The source region 33 and the contact region 34 are formed such that the source region 33 is n-type. + The contact region 34 is p + The source region 33 and the contact region 34 are formed in a surface layer portion of the body layer 31 so as to be exposed from the main surface 10a of the SOI substrate 10. That is, the source region 33 and the contact region 34 are formed in a surface layer portion of the body layer 31 located in the first direction from the inner edge region 32. In other words, the source region 33 and the contact region 34 are formed along the second portion 20b of the trench isolation 20, but not along the first portion 20a of the trench isolation 20. Note that, as in the first embodiment, the source region 33 and the contact region 34 are alternately arranged in a ladder shape along the second direction, with the contact regions 34 arranged at both ends in the second direction. In this embodiment, the source region 33 and the contact region 34 correspond to the outer edge region. A metal silicide layer 41 is formed on the source region 33 and the contact region 34.

[0042] The STI isolation portion 50 is formed so that the metal silicide layer 42 on the drain region 36 is exposed through the first opening 50a, and the metal silicide layer 41 on the outer edge region 37 is exposed through the second opening 50b. In the drift region 35 of this embodiment, the second drift region length N2 from the first opening 50a along the second direction is longer than the first drift region length N1 from the first opening 50a along the first direction.

[0043] The gate electrode 62 is formed on the main surface 10a of the SOI substrate 10 at a position facing the body layer 31.

[0044] The wiring layer 80 has an interlayer insulating film 91, a wiring portion 101, etc., similar to the first embodiment. The inner edge region wiring portion 101a is connected to the metal silicide layer 42 through the inner edge region via 91a, and is thereby electrically connected to the drain region 36. The outer edge region wiring portion 101b is connected to the metal silicide layer 41 through the outer edge region via 91b, and is thereby electrically connected to the source region 33 and the contact region 34.

[0045] The above is the configuration of the semiconductor device in this embodiment. In this embodiment, p-type corresponds to the first conductivity type, and n-type corresponds to the second conductivity type. Next, the operation of the semiconductor device will be described.

[0046] In this embodiment, when a positive voltage is applied to the gate electrode 62, electrons are attracted to form an inversion layer in the body layer 31 located on the opposite side of the gate electrode 62 across the gate insulating film 61. This results in an on-state in which a current flows between the source and drain.

[0047] When the application of voltage to the gate electrode 62 is stopped, the inversion layer disappears, resulting in an off-state in which no current flows between the source and drain, and the potential of the drain region 36 becomes higher than the potential of the source region 33. In this case, in this embodiment, the drift region 35 functions similarly to the field plate of the gate electrode 62 in the first embodiment. In the drift region 35 of this embodiment, the second drift region length N2 is longer than the first drift region length N1. Therefore, as shown in FIG. 10 , the equipotential line EL (i.e., the electric field) between the inner edge region 32 and the first portion 20a of the trench isolation 20 is easily extended toward the first portion 20a of the trench isolation 20. This prevents electric field concentration between the inner edge region 32 and the first portion 20a of the trench isolation 20, thereby preventing a decrease in the off-state breakdown voltage.

[0048] In this embodiment, compared to the first embodiment, the off-state breakdown voltage is improved by increasing the second drift region length N2 in the drift region 35 that is on the high potential side during off-state. Therefore, compared to the first embodiment, the length along the second direction of the region that is on the high potential side during off-state is longer. Therefore, compared to the first embodiment, the off-state breakdown voltage can be increased without forming the body layer 31 along the first portion 20a, so in this embodiment, the body layer 31 is not formed along the first portion 20a.

[0049] 8, the inventors obtained the following results using the end of the STI isolation 50 on the inner edge region 32 side (i.e., the first opening 50a) as a reference. That is, the inventors conducted extensive research into the relationship between the ratio of the length DDY of the drift region 35 along the second direction from the first opening 50a to the length DLY in the second direction from the end of the STI isolation 50 on the inner edge region 32 side to the trench isolation 20 (hereinafter simply referred to as DDY / DLY), and the off-breakdown voltage, and obtained the results shown in FIG. 11. Note that in this embodiment, the length DLY in the second direction from the end of the STI isolation 50 on the inner edge region 32 side to the trench isolation 20 can also be referred to as the length DLY of the STI isolation 50 in the second direction. Furthermore, in this embodiment, the length DDY of the drift region 35 along the second direction from the first opening 50a is the same as the second drift region length N2.

[0050] As shown in FIG. 11, it is confirmed that the off-state breakdown voltage increases sharply as DDY / DLY increases when DDY / DLY is less than 0.54, and decreases sharply as DDY / DLY increases when DDY / DLY is greater than 0.76. For example, when a semiconductor device is used in a battery monitoring system, as in this embodiment, the off-state breakdown voltage is desired to be 250 V or higher. Therefore, in the semiconductor device of this embodiment, DDY / DLY is set to be 0.28 or more and 0.83 or less. This allows the semiconductor device to have an off-state breakdown voltage of 250 V or higher.

[0051] Furthermore, in this embodiment, since the source region 33 is not formed along the first portion 20a as described above, an electric field is also applied to the first portion 20a of the trench isolation 20 during the off-state, as shown in FIG. 10 . For this reason, it is preferable that the trench isolation 20 has a structure that is less likely to be broken down even when an electric field is applied during the off-state. For example, the inventors of the present invention have conducted extensive research into the relationship between the depth of the trench 21 and the off-state breakdown voltage in the semiconductor device of this embodiment, and obtained the results shown in FIG. 12 . Note that FIG. 12 shows the simulation results when DDY is 9.5 μm and DLY is 15 μm.

[0052] 12, it has been confirmed that the deeper the trench 21, the higher the off-state breakdown voltage. For example, when DDY is 9.5 μm and DLY is 15 μm, it has been confirmed that an off-state breakdown voltage of 250 V or more can be obtained by making the depth of the trench 21 4.0 μm or more. Thus, it is preferable that the depth of the trench 21 is set to a depth that is less likely to be broken down even when an electric field is applied to the first portion 20a of the trench isolation 20 in the off state, depending on the lengths of DDY and DLY. While an example in which the depth of the trench 21 is changed has been described here, the breakdown voltage may also be changed by changing the width of the trench 21.

[0053] According to the present embodiment described above, the source region 33 as the outer edge region 37 is formed only in the portion located in the first direction from the inner edge region 32. Therefore, the same effects as those of the first embodiment can be obtained.

[0054] (1) In this embodiment, an electric field relaxation structure is formed in the drift region 35. Therefore, there is no need to provide a separate member for relaxing the electric field between the inner edge region 32 and the first portion 20a of the trench isolation 20, and an increase in the number of components can be suppressed.

[0055] (2) In this embodiment, the second drift region length N2 of the drift region 35 is longer than the first drift region length N1. This makes it easier to extend the equipotential line EL (i.e., the electric field) between the inner edge region 32 and the first portion 20a of the trench isolation 20 toward the first portion 20a of the trench isolation 20. This makes it possible to prevent electric field concentration between the inner edge region 32 and the first portion 20a of the trench isolation 20, and to prevent a decrease in the off-state breakdown voltage.

[0056] (3) In this embodiment, by setting DDY / DLY to 0.28 or more and 0.83 or less, a semiconductor device having an off-state breakdown voltage of 250 V or more can be obtained.

[0057] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0058] For example, in each of the above embodiments, the semiconductor device may be provided with a LOCOS insulating film as an isolation insulating film instead of the STI isolation portion 50.

[0059] In the first embodiment, the gate electrode 62 may not be disposed on the STI isolation part 50, and the second gate electrode length G2 may be equal to or shorter than the first gate electrode length G1. Similarly, in the second embodiment, the drift region 35 may have a second drift region length N2 equal to or shorter than the first drift region length N1.

[0060] Furthermore, in each of the above embodiments, it is possible to appropriately change the configuration of the wiring layer 80. For example, the wiring layer 80 may be configured by alternately stacking a plurality of interlayer insulating films 91 and a plurality of wiring portions 101.

[0061] In each of the above embodiments, the semiconductor device may be configured using a silicon substrate or a compound substrate instead of the SOI substrate 10.

[0062] Furthermore, in each of the above embodiments, the arrangement of the source region 33 and the contact region 34 can be changed as appropriate. Also, in each of the above embodiments, the contact region 34 does not necessarily have to be provided.

[0063] In the first embodiment, the gate electrode 62 is used as an electric field relaxation structure. However, in the first embodiment, the inner edge region wiring portion 101a may also be used as a field plate. Therefore, in the first embodiment, the length, shape, etc. of the inner edge region wiring portion 101a may be adjusted to prevent electric field concentration from occurring between the inner edge region 32 and the first portion 20a of the trench isolation 20.

[0064] [Disclosure of the Invention] The present disclosure described above can be understood from the following viewpoints, for example. [First viewpoint] A semiconductor device, a semiconductor substrate (10) having an active layer (13), in which an element region (14) is defined by a trench isolation portion (20) in the active layer, the surface of the active layer being a main surface (10a); a body layer (31) of a first conductivity type formed on a surface layer portion of the active layer in the element region; a second conductivity type source region (32) formed in a surface layer portion of the body layer; a second conductivity type drift region (35) formed in a surface layer portion of the active layer in the element region; a drain region (36) of a second conductivity type formed in a surface layer portion of the drift region; a gate insulating film (61) formed on the body layer; a gate electrode (62) disposed on the gate insulating film; one of the source region and the drain region is formed on the inner edge side of the element region to form an inner edge region (32), and the other is formed on the outer edge side of the element region on the trench isolation side to form an outer edge region (37); where one direction in the planar direction of the main surface is defined as a first direction and a direction intersecting the first direction is defined as a second direction, the element region and the inner edge region are formed such that a first element region length (L1) along the first direction from the inner edge region to the trench isolation portion is longer than a second element region length (L2) along the second direction from the inner edge region to the trench isolation portion, The semiconductor device wherein the outer edge region is formed only in a portion located in the first direction from the inner edge region. [Second perspective] The semiconductor device according to the first aspect, further comprising an electric field relaxation structure (35, 62) extending in the second direction from the inner edge region side. [Third Perspective] the inner edge region includes the source region, the outer edge region includes the drain region, The semiconductor device according to a second aspect, wherein the electric field relaxation structure is configured by the gate electrode being extended in the second direction. [Fourth viewpoint] an isolation insulating film (52) extending from the inner edge region side to the trench isolation portion located in the second direction; A semiconductor device according to a third aspect, wherein, taking an end of the isolation insulating film on the inner edge region side as a reference, the ratio of a length (GFY) of a portion of the gate electrode along the second direction from the reference to a length (DLY) along the second direction from the reference to the trench isolation is 0.15 or more and 0.73 or less. [Fifth viewpoint] the inner edge region includes the drain region, the outer edge region includes the source region, The semiconductor device according to a second aspect, wherein the electric field relaxation structure is configured by the drift region extending in the second direction. [Sixth viewpoint] an isolation insulating film (52) extending from the inner edge region side to the trench isolation portion located in the second direction; A semiconductor device according to a fifth aspect, wherein, taking an end of the isolation insulating film on the inner edge region side as a reference, a ratio of a length (DDY) of a portion of the drift region along the second direction from the reference to a length (DLY) along the second direction from the reference to the trench isolation portion is 0.28 or more and 0.83 or less. [Seventh viewpoint] A semiconductor device according to any one of the second to sixth aspects, wherein the length (G2, N2) of the electric field relaxation structure along the second direction from the end on the inner edge region side is longer than the length (G1, N1) of the electric field relaxation structure along the first direction from the end on the inner edge region side. [Eighth viewpoint] The semiconductor device according to any one of the first to seventh aspects, wherein the semiconductor substrate is an SOI substrate in which the active layer is disposed on a support substrate (11) with an insulating film (12) interposed therebetween. [Ninth viewpoint] The semiconductor device according to any one of the first to eighth aspects, used to configure a battery monitoring system. [Explanation of symbols]

[0065] 10. Semiconductor substrate 13 Active layer 14 Element Area 20 Trench isolation 31 Body Layer 32 Inner border region 33 Source Region 35 Drift Region 36 Drain region 37 Peripheral Region 61 Gate insulating film 62 gate electrode L1 Length of the first element region L2 Second element region length

Claims

1. A semiconductor device, a semiconductor substrate (10) having an active layer (13), in which an element region (14) is defined by a trench isolation portion (20) in the active layer, the surface of the active layer being a main surface (10a); a body layer (31) of a first conductivity type formed on a surface layer portion of the active layer in the element region; a second conductivity type source region (32) formed in a surface layer portion of the body layer; a second conductivity type drift region (35) formed in a surface layer portion of the active layer in the element region; a drain region (36) of a second conductivity type formed in a surface layer portion of the drift region; a gate insulating film (61) formed on the body layer; a gate electrode (62) disposed on the gate insulating film; one of the source region and the drain region is formed on the inner edge side of the element region to form an inner edge region (32), and the other is formed on the outer edge side of the element region on the trench isolation side to form an outer edge region (37); where one direction in the planar direction of the main surface is defined as a first direction and a direction intersecting the first direction is defined as a second direction, the element region and the inner edge region are formed such that a first element region length (L1) along the first direction from the inner edge region to the trench isolation portion is longer than a second element region length (L2) along the second direction from the inner edge region to the trench isolation portion, The semiconductor device in which the outer edge region is formed only in a portion located in the first direction from the inner edge region.

2. 2. The semiconductor device according to claim 1, further comprising an electric field relaxation structure (35, 62) extending in the second direction from the inner edge region side.

3. the inner edge region includes the source region, the outer edge region includes the drain region, 3. The semiconductor device according to claim 2, wherein the electric field relaxation structure is configured by extending the gate electrode in the second direction.

4. an isolation insulating film (52) extending from the inner edge region side to the trench isolation portion located in the second direction; 4. The semiconductor device according to claim 3, wherein a ratio of a length (GFY) of a portion of the gate electrode along the second direction from a reference point to a length (DLY) along the second direction from the reference point to the trench isolation portion is 0.15 or more and 0.73 or less, taking an end of the isolation insulating film on the inner edge region side as a reference point.

5. the inner edge region includes the drain region, the outer edge region includes the source region, The semiconductor device according to claim 2 , wherein the electric field relaxation structure is configured by extending the drift region in the second direction.

6. an isolation insulating film (52) extending from the inner edge region side to the trench isolation portion located in the second direction; 6. The semiconductor device according to claim 5, wherein a ratio of a length (DDY) of a portion of the drift region along the second direction from an end of the isolation insulating film on the inner edge region side to a length (DLY) along the second direction from the reference to the trench isolation portion is 0.28 or more and 0.83 or less.

7. 3. The semiconductor device according to claim 2, wherein the length (G2, N2) of the electric field relaxation structure along the second direction from the end on the inner edge region side is longer than the length (G1, N1) of the electric field relaxation structure along the first direction from the end on the inner edge region side.

8. 8. The semiconductor device according to claim 1, wherein the semiconductor substrate is an SOI substrate in which the active layer is disposed on a support substrate (11) via an insulating film (12).

9. 8. The semiconductor device according to claim 1, which is used to configure a battery monitoring system.

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