Semiconductor device

Abstract

To suppress a displacement current in a semiconductor device having a two-stage gate structure and a carrier accumulation layer.SOLUTION: An IGBT 101 includes a carrier accumulation layer 3 of a first conductivity type formed on a first main surface S1 side of a drift layer 2, a base layer 4 of a second conductivity type formed on the first main surface S1 side of the carrier accumulation layer 3, and a gate electrode 9 buried in a trench 7 through an oxide film. The gate electrode 9 includes a lower gate electrode 9D and an upper gate electrode 9U formed closer to the first main surface S1 than the lower gate electrode 9D. In the carrier accumulation layer 3, an impurity concentration of the first conductivity type has a Gaussian distribution in a depth direction, and a depth D1 of an interface between the base layer 4 and the carrier accumulation layer 3 in a vicinity of the sidewall of the trench 7 satisfies D1≥(D2-1.0) [μm] with respect to a depth D2 of the deepest part of an upper gate electrode 9U.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, in an IGBT (Insulated Gate Bipolar Transistor) structure with a carrier accumulation layer (CS layer), there was a problem that displacement current flowed into the trench gate during switching operation or in a short-circuit state, causing the gate-emitter voltage to overshoot and resulting in an overcurrent.

[0003] To address this problem, Patent Document 1 discloses a structure that suppresses displacement current by employing a two-stage gate structure in which the upper stage is at gate potential and the lower stage is at emitter potential. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-116894 Summary of the Invention [Problem to be solved by the invention]

[0005] However, simply adopting a two-stage gate structure is insufficient to suppress displacement current, a problem that is not limited to IGBTs, but also applies to other semiconductor devices with carrier accumulation layers, such as MOSFETs.

[0006] The present disclosure has been made to solve the above-mentioned problems, and has an object to suppress displacement current in a semiconductor device having a two-stage gate structure and a carrier accumulation layer. [Means for solving the problem]

[0007] a first conductivity type drift layer formed on the semiconductor substrate; a first conductivity type carrier accumulation layer formed on the first principal surface side of the drift layer; a second conductivity type base layer formed on the first principal surface side of the carrier accumulation layer; a trench extending from the first principal surface through the base layer and the carrier accumulation layer to reach the drift layer; and a gate electrode embedded in the trench with an oxide film interposed therebetween, the gate electrode including a lower gate electrode and an upper gate electrode formed closer to the first principal surface than the lower gate electrode, the carrier accumulation layer having a first conductivity type impurity concentration with a Gaussian distribution in the depth direction, and a depth D1 of an interface between the base layer and the carrier accumulation layer near a sidewall of the trench, where D2 is a depth D of the deepest part of the upper gate electrode, satisfies D1≧(D2−1.0) [μm]. [Effects of the Invention]

[0008] In the semiconductor device of the present disclosure, the depth D1 of the interface between the base layer and the carrier accumulation layer near the sidewall of the trench, relative to the depth D2 of the deepest part of the upper gate electrode, satisfies D1≧(D2−1.0) [μm]. In this way, the thickness of the overlapping region between the carrier accumulation layer and the upper gate electrode is reduced, making it difficult for displacement current to flow into the upper gate electrode, thereby suppressing overcurrent. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a diagram showing the relationship between boron drive time and displacement current charge amount. [Figure 3] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following description, regarding the conductivity type of the semiconductor, the N-type is the first conductivity type and the P-type is the second conductivity type. However, these may be reversed. That is, the N-type may be the second conductivity type and the P-type may be the first conductivity type.

[0011] <A. Embodiment 1> FIG. 1 is a cross-sectional view showing the configuration of an IGBT 101 which is a semiconductor device according to Embodiment 1. The IGBT 101 includes a semiconductor substrate 1. The semiconductor substrate 1 includes a first main surface S1 and a second main surface S2 which is the main surface on the opposite side of the first main surface S1. In FIG. 1, the first main surface S1 is the upper main surface and the second main surface S2 is the lower main surface.

[0012] The semiconductor substrate 1 includes an N-type drift layer 2. An N-type carrier accumulation layer (CS layer) 3 is provided on the first main surface S1 side of the N-type drift layer 2. A P-type base layer 4 is provided on the first main surface S1 side of the CS layer 3. A P+-type contact layer 5 and an N-type source layer 6 are provided on the first main surface S1 side of the base layer 4. The surfaces of the contact layer 5 and the source layer 6 on the side opposite to the base layer 4, that is, the upper surfaces, constitute the first main surface S1. Although not shown, an emitter electrode which is a surface electrode is formed on the first main surface S1.

[0013] An N+-type buffer layer 10 is provided on the second main surface S2 side of the drift layer 2. A P-type collector layer 11 is provided on the second main surface S2 side of the buffer layer 10. The surface of the collector layer 11 on the side opposite to the buffer layer 10, that is, the lower surface of the collector layer 11 in FIG. 1, constitutes the second main surface S2. Although not shown, a collector electrode which is a back surface electrode is provided on the second main surface S2.

[0014] A trench 7 is formed extending from the first main surface S1 through the source layer 6, the base layer 4, and the CS layer 3 to reach the drift layer 2. A gate electrode 9 is buried in the trench 7 with an oxide film 8 interposed therebetween. The gate electrode 9 includes a lower gate electrode 9D and an upper gate electrode 9U located above the lower gate electrode 9D, i.e., on the first main surface S1 side. In other words, the IGBT 101 has a two-stage gate structure. The lower gate electrode 9D and the upper gate electrode 9U are insulated from each other by the oxide film 8.

[0015] The CS layer 3 makes it easier for hole carriers from the second main surface S2 to remain in the drift layer 2. This makes it easier for conductivity modulation to occur, reducing current loss. Note that although an IGBT is described in this embodiment, the configuration of the present disclosure is also applicable to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that does not have a collector layer 11.

[0016] The IGBT 101 has a two-stage gate structure with two gate electrodes: a lower gate electrode 9D and an upper gate electrode 9U. The depth of the interface between the CS layer 3 and the base layer 4 near the sidewall of the trench 7 (hereinafter simply referred to as "near the trench 7") is designated D1, and the depth of the deepest part of the upper gate electrode 9U is designated D2. Hereinafter, the interface between the CS layer 3 and the base layer 4 will also be referred to as the CD / CS interface. Herein, D1≦D2 must be satisfied. If D1>D2, the portion of the base layer 4 near the trench 7 that faces the CS layer 3 does not face the upper gate electrode 9U, so the base layer 4 is not inverted to n-type and no on-current flows. Unless otherwise specified, the depth of each part in this specification is the depth from the first main surface S1.

[0017] The CS layer 3 must face the upper gate electrode 9U, but it is desirable to make the thickness of the facing portion as small as possible. Specifically, it is desirable to satisfy D1≧(D2−1.0) μm. In other words, it is desirable that the thickness of the portion of the CS layer 3 facing the upper gate electrode 9U be 1.0 μm or more.

[0018] Thus, by reducing the thickness of the overlapping region between the CS layer 3 and the upper gate electrode 9U, the displacement current is less likely to flow into the upper gate electrode 9U, so overcurrent is suppressed.

[0019] Figure 2 shows the relationship between the boron drive time [min] and the displacement current charge amount [nC]. The boron drive time is the heat treatment time when forming the base layer 4. By this heat treatment, boron, which is the implanted p-type impurity, diffuses and the base layer 4 is formed. Therefore, the deeper the CD / CS interface becomes as the boron drive time is longer.

[0020] The triangle marks indicate the case where the n-type impurity concentration of the CS layer 3 is 3.0×10 12 [cm-3], and the diamond marks indicate the case where the n-type impurity concentration of the CS layer 3 is 6.0×10 12 [cm-3]. Boron drive times of 30 [min] and 60 [min] correspond to the case where the depth D1 of the CD / CS interface is less than (D2 - 1.0) [μm]. Also, boron drive times of 90 [min], 120 [min], and 180 [min] correspond to the case where the depth D1 of the CD / CS interface is (D2 - 1.0) [μm] or more. From Figure 2, it can be seen that by setting D1 ≧ (D2 - 1.0) [μm], the displacement current charge amount becomes smaller, that is, the displacement current is reduced.

[0021] As shown in Figure 1, it is desirable that the depth direction distribution of the n-type impurity in the CS layer 3 of the IGBT101 is a Gaussian distribution. And when the depth of the peak position of the n-type impurity concentration in the CS layer 3 is D3, it is desirable to satisfy D2 < D3. Thereby, holes at the peak position of the CS layer 3, which is the region where holes are most likely to accumulate, can be drawn out from the lower gate electrode 9D, and the displacement current flowing into the upper gate electrode 9U is further suppressed.

[0022] The lower gate electrode 9D has the same potential as the emitter electrode, that is, the emitter potential, and it is desirable that the upper gate electrode 9U has a gate potential different from the emitter potential. Thereby, holes flowing into the lower gate electrode 9D can escape to the emitter electrode.

[0023] It is desirable that the n-type impurity concentration of the lower gate electrode 9D is higher than the n-type impurity concentration of the upper gate electrode 9U. Thereby, the parasitic resistance of the lower gate electrode 9D is reduced, and the displacement current flowing into the upper gate electrode 9U is suppressed.

[0024] As described above, the IGBT (Insulated Gate Bipolar Transistor) 101 which is a semiconductor device according to the first embodiment includes a semiconductor substrate 1, an n-type drift layer 2, an n-type CS layer 3, a p-type base layer 4, a trench 7, and a gate electrode 9. The semiconductor substrate 1 has a first main surface S1 and a second main surface S2 which is the main surface on the opposite side of the first main surface S1. The drift layer 2 is formed on the semiconductor substrate 1. The CS layer 3 is formed on the first main surface S1 side of the drift layer 2. The base layer 4 is formed on the first main surface S1 side of the CS layer 3. The trench 7 penetrates the base layer 4 and the CS layer 3 from the first main surface S1 and reaches the drift layer 2. The gate electrode 9 is embedded in the trench 7 via an oxide film 8. The gate electrode 9 includes a lower gate electrode 9D and an upper gate electrode 9U formed on the first main surface S1 side of the lower gate electrode 9D. The CS layer 3 has a Gaussian distribution in the depth direction of the impurity concentration of the first conductivity type. The depth D1 of the CD / CS interface in the vicinity of the side wall of the trench 7 satisfies D1≧(D2 - 1.0) [μm] with respect to the depth D2 of the deepest part of the upper gate electrode 9U.

[0025] In this way, by reducing the thickness of the overlapping region between the CS layer 3 and the upper gate electrode 9U, it becomes difficult for the displacement current to flow into the upper gate electrode 9U, so overcurrent is suppressed.

[0026] <B. Second Embodiment> 3 is a cross-sectional view showing the configuration of an IGBT 102 which is a semiconductor device according to embodiment 2. The IGBT 102 differs from the IGBT 101 in the shapes of an upper gate electrode 9U and a lower gate electrode 9D. The shapes of the upper gate electrode 9U and the lower gate electrode 9D in embodiment 2 will be described below.

[0027] The upper gate electrode 9U includes an upper first portion 9U1 and an upper second portion 9U2 that protrudes toward the second main surface S2 from the lower surface of the upper first portion 9U1, which is the surface on the second main surface S2 side of the upper gate electrode 9U, and is concave toward the second main surface S2. The lower surface of the upper second portion 9U2 is the deepest part of the upper gate electrode 9U, and its depth is D2.

[0028] The lower gate electrode 9D includes a lower first portion 9D1 and a lower second portion 9D2 that protrudes toward the first main surface S1 from the upper surface, which is the surface on the first main surface S1 side of the lower first portion 9D1, and has a convex shape toward the first main surface S1.

[0029] All other features described in the first embodiment also apply to the second embodiment.

[0030] The downwardly concave shape of the upper gate electrode 9U reduces the volume of the upper gate electrode 9U. Also, the resistance of the hole intrusion opening of the upper gate electrode 9U increases. This suppresses the displacement current flowing into the upper gate electrode 9U.

[0031] The volume of the lower gate electrode 9D increases because the lower gate electrode 9D has an upwardly convex shape, thereby reducing the parasitic resistance of the lower gate electrode and suppressing the displacement current flowing into the upper gate electrode 9U.

[0032] The convex portion of the upper gate electrode 9U may extend into the concave portion of the lower gate electrode 9D. That is, the top surface of the lower second portion 9D2 may be shallower than the bottom surface of the upper second portion 9U2. This increases the volume of the lower gate electrode 9D. As a result, the parasitic resistance of the lower gate electrode is reduced, and the displacement current flowing into the upper gate electrode 9U is suppressed.

[0033] The width W2 of the upper second part 9U2 may be narrower than the width W1 of the lower first part 9D1. As a result, the cross-sectional area of the upper second part 9U2 decreases, and the parasitic resistance increases. Consequently, the displacement current flowing into the upper gate electrode 9U is suppressed.

[0034] Either the upper gate electrode 9U or the lower gate electrode 9D may have the same shape as in the first embodiment.

[0035] <C. Embodiment 3> FIG. 4 is a cross-sectional view showing the configuration of an IGBT 103 which is a semiconductor device according to the third embodiment. The IGBT 103 is different from the IGBT 102 of the second embodiment in that the depth of the CD / CS interface is not uniform.

[0036] In the IGBT 103, the CD / CS interface is shallow near the trench 7 and becomes deeper as it moves away from the trench 7, and has a convex shape toward the first main surface S1. That is, the depth of the CD / CD interface is D1 near the trench 7 and deeper than D1 at a location away from the trench 7. As a result, the base layer 4 in the central part of the mesa becomes thicker. Consequently, carrier accumulation near the upper gate electrode 9U is suppressed, and the displacement current flowing into the upper gate electrode 9U is further suppressed.

[0037] In addition, the features regarding the depths D1, D2, and D3 of each part described in the first embodiment are similarly applicable to the third embodiment. Also, in FIG. 4, the IGBT 103 has been described as having a configuration in which the CD / CS interface in the IGBT of the second embodiment is convex downward. However, the IGBT 103 may have a configuration in which the CD / CS interface in the IGBT 101 of the first embodiment is convex downward.

[0038] When creating the base layer 4, acceptor ions are implanted, and the implanted acceptor ions are activated by heat treatment. When the acceptor is boron, this heat treatment is referred to as boron drive. The longer the heat treatment time, the more the acceptor ions diffuse downward, and the deeper the CD / CS interface becomes. <Q

[0039] Here, the acceptor ions diffused near the trench 7 are absorbed into the oxide film 8. Therefore, the acceptor ion concentration is low near the trench 7. On the other hand, the donor ions of the CS layer are not absorbed into the oxide film 8. Therefore, the CD / CS interface becomes deeper with increasing distance from the trench sidewall and shallower near the trench 7, resulting in a downward convex shape.

[0040] If the conductivity types are reversed, that is, the CS layer is p-type and the base layer is n-type, a CD / CS interface with a downward concave shape can be obtained by a similar process.

[0041] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims.

[0042] Various aspects of the present disclosure are summarized below as appendices.

[0043] (Appendix 1) a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first conductivity type drift layer formed on the semiconductor substrate; a carrier accumulation layer of a first conductivity type formed on the first main surface side of the drift layer; a second conductivity type base layer formed on the first principal surface side of the carrier accumulation layer; a trench extending from the first principal surface through the base layer and the carrier accumulation layer to reach the drift layer; a gate electrode embedded in the trench via an oxide film; Equipped with The gate electrode is a lower gate electrode; an upper gate electrode formed closer to the first main surface than the lower gate electrode; the carrier accumulation layer has a first conductivity type impurity concentration that has a Gaussian distribution in a depth direction; The depth D1 of the interface between the base layer and the carrier accumulation layer near the sidewall of the trench satisfies D1≧(D2-1.0) [μm] with respect to the depth D2 of the deepest part of the upper gate electrode. Semiconductor device.

[0044] (Appendix 2) The depth D3 of the peak position of the first-conductivity-type impurity concentration of the carrier accumulation layer satisfies D3>D2 with respect to the depth D2 of the deepest part of the upper gate electrode. The semiconductor device according to Appendix 1.

[0045] (Appendix 3) The depth D1 of the interface between the base layer and the carrier accumulation layer near the sidewall of the trench satisfies D1<D2 with respect to the depth D2 of the deepest part of the upper gate electrode. The semiconductor device according to Appendix 1 or Appendix 2.

[0046] (Appendix 4) Further comprising a surface electrode formed on the first main surface, <00001​​​​​​​​​​​​​​​​​​​​​​​​​​​

[0049] (Appendix 7) The lower gate electrode is The first part of the lower section and a lower stage second portion protruding toward the first main surface from an upper surface of the lower stage first portion, the upper surface being a surface on the first main surface side, The lower first portion and the lower second portion form a convex shape toward the first main surface. 7. The semiconductor device according to claim 6.

[0050] (Appendix 8) an upper surface of the lower second portion, which is a surface on the first main surface side, is shallower than a lower surface of the upper second portion, which is a surface on the second main surface side; 8. The semiconductor device according to claim 7.

[0051] (Appendix 9) The width of the upper second section is narrower than the width of the lower first section. 9. The semiconductor device according to claim 7 or 8.

[0052] (Appendix 10) an interface between the base layer and the carrier accumulation layer that is convex toward the second main surface; 10. The semiconductor device according to claim 1. [Explanation of symbols]

[0053] 1 semiconductor substrate, 2 drift layer, 3 carrier accumulation layer, 4 base layer, 5 contact layer, 6 source layer, 7 trench, 8 oxide film, 9 gate electrode, 9D lower gate electrode, 9D1 lower first part, 9D2 lower second part, 9U upper gate electrode, 9U1 upper first part, 9U2 upper second part, 10 buffer layer, 11 collector layer, 101, 102, 103 IGBT, S1 first main surface, S2 second main surface.

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first conductivity type drift layer formed on the semiconductor substrate; a carrier accumulation layer of a first conductivity type formed on the first main surface side of the drift layer; a second conductivity type base layer formed on the first principal surface side of the carrier accumulation layer; a trench extending from the first principal surface through the base layer and the carrier accumulation layer to reach the drift layer; a gate electrode embedded in the trench via an oxide film; Equipped with The gate electrode is a lower gate electrode; an upper gate electrode formed closer to the first main surface than the lower gate electrode; the carrier accumulation layer has a first conductivity type impurity concentration that has a Gaussian distribution in a depth direction; a depth D1 of the interface between the base layer and the carrier accumulation layer near the sidewall of the trench, where D2 is a depth of the deepest part of the upper gate electrode, satisfies D1≧(D2−1.0) [μm]; Semiconductor device.

2. a depth D3 of a peak position of the first conductivity type impurity concentration in the carrier accumulation layer, and a depth D2 of the deepest part of the upper gate electrode, satisfy the relationship D3>D2; The semiconductor device according to claim 1 .

3. a depth D1 of an interface between the base layer and the carrier accumulation layer near a sidewall of the trench, where D2 is a depth of the deepest part of the upper gate electrode, satisfies D1<D2; The semiconductor device according to claim 1 .

4. further comprising a surface electrode formed on the first main surface; the lower gate electrode is at the same potential as the surface electrode; the upper gate electrode is at a different potential from the lower gate electrode; The semiconductor device according to claim 1 .

5. a first conductivity type impurity concentration of the lower gate electrode is higher than a first conductivity type impurity concentration of the upper gate electrode; The semiconductor device according to claim 1 .

6. The upper gate electrode is The first part of the upper row and an upper stage second portion protruding from a lower surface of the upper stage first portion toward the second main surface, the lower surface being a surface on the second main surface side; The upper first portion and the upper second portion form a concave shape toward the second main surface. The semiconductor device according to claim 1 .

7. The lower gate electrode is The first part of the lower section and a lower stage second portion protruding toward the first main surface from an upper surface of the lower stage first portion, the upper surface being a surface on the first main surface side, The lower first portion and the lower second portion form a convex shape toward the first main surface. The semiconductor device according to claim 6.

8. an upper surface of the lower second portion, which is a surface on the first main surface side, is shallower than a lower surface of the upper second portion, which is a surface on the second main surface side; The semiconductor device according to claim 7 .

9. The width of the upper second section is narrower than the width of the lower first section. The semiconductor device according to claim 7 .

10. an interface between the base layer and the carrier accumulation layer that is convex toward the second main surface; The semiconductor device according to claim 1 .

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