Control system, control device, and control method

Abstract

To enable appropriate input of a signal generated by a second control device from a communication unit to a first control device at a period that is shorter than an input period from the communication unit at the first control device.SOLUTION: A control system comprises: a first control device; a second control device; and a communication unit to / from which a predetermined signal is input / output between the first control device and the second control device. The second control device comprises: a delay unit that outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal by a plurality of different delayed times; and an output unit that outputs the plurality of output signals of the delay unit to the communication unit. The first control device comprises: an input unit that accepts input of the plurality of output signals from the communication unit at a time interval longer than the shortest delayed time; and a storage unit that stores the plurality of output signals having been input.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present disclosure relates to a control system, a control device, and a control method. [Background technology]

[0002] Patent Document 1 describes, as background art (see FIG. 6 and the like), a configuration for oversampling in which a sampling clock obtained by multiplying a system clock is input to a series circuit in which a plurality of delay elements having a predetermined delay time are connected in series, thereby generating a plurality of clocks, which are then supplied to the clock terminals of a plurality of D-type flip-flops. With this configuration, it is possible to obtain a time resolution higher than that of a cycle obtained by multiplying the system clock, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-264827 Summary of the Invention [Problem to be solved by the invention]

[0004] In a distributed control system that is configured from a higher-level control device, one or more lower-level control devices, and a communication unit between the higher-level control device and the lower-level control devices, there is a need for the higher-level control device to acquire data generated in the lower-level control devices at a cycle shorter than the data input cycle from the communication unit in the higher-level control device. In this case, due to the constraints imposed by the communication unit, it is not effective to provide the higher-level control device with a configuration for acquiring data by oversampling, as described in Patent Document 1, for example.

[0005] The present disclosure has been made in consideration of the above circumstances, and aims to provide a control system, a control device, and a control method that can appropriately input signals generated by a lower control device from a communication unit in a higher control device at a cycle shorter than the input cycle from the communication unit in the higher control device. [Means for solving the problem]

[0006] In order to solve the above problem, the control system of the present disclosure comprises a first control device, a second control device, and a communication unit that inputs and outputs predetermined signals between the first control device and the second control device, wherein the second control device comprises a delay unit that outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal by a plurality of different delay times, and an output unit that outputs the plurality of output signals of the delay unit to the communication unit, and the first control device comprises an input unit that inputs the plurality of output signals from the communication unit at time intervals longer than the shortest delay time, and a memory unit that stores the input plurality of output signals.

[0007] The control method of the present disclosure is a control method for a control system including a first control device, a second control device, and a communication unit that inputs and outputs predetermined signals between the first control device and the second control device, wherein the second control device includes a delay unit that outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal by a plurality of different delay times, and an output unit that outputs the plurality of output signals of the delay unit to the communication unit, and includes the steps of inputting the plurality of output signals from the communication unit in the first control device at time intervals longer than the shortest delay time, and storing the input plurality of output signals. [Effects of the Invention]

[0008] According to the control system, control device, and control method disclosed herein, a signal generated by a second control device can be appropriately input from a communication unit in a first control device at a cycle shorter than the input cycle from the communication unit in the first control device. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating a configuration example of a control system according to an embodiment of the present disclosure. [Figure 2A] FIG. 2 is a block diagram illustrating an example configuration of a recording data processing unit and the like according to an embodiment of the present disclosure. [Figure 2B] FIG. 10 is a block diagram showing another example configuration of a recording data processing unit and the like according to an embodiment of the present disclosure. [Figure 3] 10 is a flowchart illustrating an example of the operation of the low-speed calculation control device according to the embodiment of the present disclosure. [Figure 4] 10 is a timing chart illustrating an example of operation of a control system according to an embodiment of the present disclosure. [Figure 5] FIG. 1 is a schematic block diagram illustrating a configuration of a computer according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] A control system and a control method according to an embodiment of the present disclosure will be described below with reference to FIGS. 1 to 4. Note that the same or corresponding components in each drawing are designated by the same reference numerals, and descriptions thereof will be omitted as appropriate. FIG. 1 is a block diagram showing an example configuration of a control system according to an embodiment of the present disclosure. FIG. 2A is a block diagram showing an example configuration of a recording data processing unit and the like according to an embodiment of the present disclosure. FIG. 2B is a block diagram showing another example configuration of a recording data processing unit and the like according to an embodiment of the present disclosure.

[0011] As shown in FIG. 1 , the control system 1 includes a low-speed calculation control device 2, a communication unit 3, a high-speed calculation module 4, and field equipment 5. The field equipment 5 includes a control valve 51, which is a servo valve using high-pressure EH (Electro Hydraulic) oil, a servo valve actuator 52 that drives the control valve 51, and an LVDT (Linear Variable Differential Transformer) 53, which is a sensor that detects mechanical linear motion and converts it into a voltage or the like for output. The control valve 51 is used, for example, as a fuel control valve in a gas turbine or a steam control valve in a steam turbine. The LVDT 53 outputs a signal (a voltage signal in this embodiment) indicating the valve opening of the control valve 51. The servo valve actuator 52 adjusts the valve opening based on the control signal indicating the valve opening (%) output by the high-speed calculation module 4. Note that in this embodiment, digital signals (or signals, input signals, output signals, control signals, etc.) that are not analog signals are considered to have the same meaning as data.

[0012] The communication unit 3 includes a communication cable connecting the low-speed arithmetic control device 2 and the high-speed arithmetic module 4, a communication interface that is partly or entirely included in the low-speed arithmetic control device 2 and the high-speed arithmetic module 4, and transmits (transmits and receives) a predetermined signal between the low-speed arithmetic control device 2 and the high-speed arithmetic module 4, for example, at a communication cycle TC (which is set to 20 ms (milliseconds) as an example in this embodiment). In this embodiment, the low-speed arithmetic control device 2 transmitting a signal to the high-speed arithmetic module 4 via the communication unit 3 and the high-speed arithmetic module 4 receiving a signal from the low-speed arithmetic control device 2 via the communication unit 3 are also referred to as the low-speed arithmetic control device 2 outputting a signal to the communication unit 3 and the high-speed arithmetic module 4 inputting a signal from the communication unit 3. In addition, the high-speed arithmetic control device 4 transmitting a signal to the low-speed arithmetic control device 2 via the communication unit 3 and the low-speed arithmetic control device 2 receiving a signal from the high-speed arithmetic module 4 via the communication unit 3 are also referred to as the high-speed arithmetic module 4 outputting a signal to the communication unit 3 and the low-speed arithmetic control device 2 inputting a signal from the communication unit 3. The communication unit 3 can be configured using, for example, a LAN (local area network).

[0013] The high-speed calculation module 4, for example, sets a basic control period to a high-speed period TH (which is set to 4 ms in this embodiment as an example) and performs feedback control of the control valve 51 in accordance with instructions from the low-speed calculation control device 2. The high-speed calculation module 4 includes, for example, a microcontroller, an FPGA (Field Programmable Gate Array), an A / D (Analog / Digital) converter, a D / A converter, an amplifier circuit, a photocoupler, a power supply circuit, etc., and includes an adjustment unit 41, an LVDT voltage processing unit 42, and a recorded data processing unit 43 as functional blocks configured using these components.

[0014] The LVDT voltage processing unit 42 converts the analog voltage signal indicating the measured value of the valve opening output by the LVDT 53 into a digital signal indicating the valve opening as a percentage (%) and outputs it. The adjustment unit 41 outputs a control signal indicating the valve opening (%) based on the offset (OFFSET) DA1, gain (GAIN) DA2, and valve opening command value (target value) DA3 received from the low-speed calculation control device 2 via the communication unit 3, and the valve opening (%) output by the LVDT voltage processing unit 42. In the example shown in FIG. 1, the adjustment unit 41 includes a subtractor 411, a multiplier 412, and an adder 413. The subtractor 411 outputs the result (deviation) of subtracting the valve opening (%) output by the LVDT voltage processing unit 42 from the command value DA3. The multiplier 412 outputs a value obtained by multiplying the deviation output by the subtractor 411 by the gain DA2. Adder 413 adds offset DA1 to the value output by multiplier 412 and outputs the resulting value as a control signal (valve opening (%)). In this case, adjuster 41 performs feedback control of the valve opening by proportional control (P control) so that it matches the command value. The signal output period of LVDT voltage processing unit 42 and the calculation period (signal output period, etc.) in adjuster 41 are both high-speed period TH.

[0015] The recording data processing unit 43 performs signal processing to transmit the signal indicating the valve opening degree (%) output by the LVDT voltage processing unit 42 as recording data (data to be recorded by the low-speed calculation control device 2) to the low-speed calculation control device 2 via the communication unit 3 (details will be described later).

[0016] The low-speed calculation control device 2 includes, for example, a CPU (Central Processing Unit), memory, an input / output interface, a communication interface, and the like. For example, the low-speed period TL (100 ms, for example, in this embodiment) is used as a basic control period. Based on control signals received from a higher-level control device (not shown), the low-speed period TL and the high-speed period TH are controlled by signals such as interrupt signals that take priority over the control period, and the periods are not necessarily constant. The low-speed calculation control device 2 includes a calculation unit 21 and a storage device 22. The calculation unit 21 generates an offset DA1, a gain DA2, and a command value DA3 based on control signals received from a higher-level control device (not shown) and outputs them to the high-speed calculation module 4, and reconstructs recorded data stored in the storage device 22 into time-series data. The storage device 22 stores recorded data received from the high-speed calculation module 4 and stores the reconstructed recorded data.

[0017] In this embodiment, the low-speed calculation control device 2 is an example of a configuration of a "first control device" according to the present disclosure, and the high-speed calculation module 4 is an example of a configuration of a "second control device" according to the present disclosure.

[0018] Next, with reference to Fig. 2A, a configuration example of the recording data processing unit 43 shown in Fig. 1 will be described. As shown in Fig. 2A, the recording data processing unit 43 shown in Fig. 1 includes a recording data input unit 431, a delay unit 432, a counter 433, and an output unit 434.

[0019] The record data input unit 431 is, for example, a register, which receives the signal (record data) indicating the valve opening output from the LVDT voltage processing unit 42 at a high speed cycle TH, holds it until the next receiving timing, and outputs it.

[0020] The delay unit 432 outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal (input signal of the delay unit 432 (= output of the record data input unit 431)) by a plurality of different delay times. The delay unit 432 shown in FIG. 2A includes five delay circuits 4321 to 4325 connected in series in multiple stages. Each of the delay circuits 4321 to 4325 delays the input signal by the same predetermined unit delay time TD before outputting it. In the present embodiment, as an example, the unit delay time TD is assumed to be 20 ms. The delay circuit 4321 receives the output signal of the record data input unit 431 as an input signal, delays it by the unit delay time TD, and outputs it. The delay circuit 4322 receives the output signal of the delay circuit 4321 as an input signal, delays it by the unit delay time TD, and outputs it. The delay circuit 4323 receives the output signal of the delay circuit 4322 as an input signal, delays it by the unit delay time TD, and outputs it. Delay circuit 4324 receives the output signal of delay circuit 4323 as an input signal, delays it by unit delay time TD, and outputs the signal. Delay circuit 4325 receives the output signal of delay circuit 4324 as an input signal, delays it by unit delay time TD, and outputs the signal. The signal input to delay circuit 4321 is delayed by unit delay time TD, twice the unit delay time TD, three times the unit delay time TD, four times the unit delay time TD, and five times the unit delay time TD, and then output from delay circuits 4322, 4323, 4324, and 4325, respectively. Each delay circuit 4321 to 4325 operates at a high-speed cycle TH. The output signals of each delay circuit 4321 to 4325 are updated every high-speed cycle TH. Data acquisition in each delay circuit 4321 to 4325 is performed in the order of delay circuits 4325 to 4321, with a predetermined time delay. In this embodiment, the output signals of the delay circuits 4321 to 4325 become valid 100 ms after the start of operation of the delay unit 432. In this embodiment, the delay unit 432 has a configuration in which delay circuits 4321 to 4325 are connected in series in multiple stages, and each delays an input signal by a predetermined unit delay time TD before outputting the signal.The delay unit 432 may have the same function as a configuration in which delay circuits that delay an input signal by a predetermined unit delay time TD and output the delayed signal are connected in series in multiple stages. For example, a plurality of delay circuits that delay the signal by a unit delay time TD may be provided in parallel, and the output signal of the record data input unit 431 may be input to each of the delay circuits as an input signal. Alternatively, the delay unit 432 may be configured using a plurality of storage areas and an arithmetic circuit that manages the updating of data in each storage area. Figure 2B shows an example in which the delay unit 432 is configured by connecting in parallel a plurality of delay circuits 4321, 4322a, 4323a, 4324a, and 4325a with different delay times. In this case, by setting the delay times of delay circuits 4321, 4322a, 4323a, 4324a, and 4325a to unit delay time TD, double unit delay time TD, triple unit delay time TD, quadruple unit delay time TD, and five times unit delay time TD, the delay unit 432 and each output signal in FIG. 2A can be made identical to the output signal of delay unit 432 in FIG. 2B. As will be described in detail later, in this embodiment, the number of stages of delay circuits 4321-4325 shown in FIG. 2A is equal to or greater than the value obtained by dividing the slow period TL (the "time interval" in this disclosure) by the unit delay time TD plus 1. A common feature of both the configurations in FIG. 2A and FIG. 2B is that the longest delay time in the output signal of delay unit 432 is equal to or greater than the value obtained by multiplying the shortest delay time by the value obtained by dividing the "time interval" by the shortest delay time in the output signal of delay unit 432 plus 1. In the following, an example of operation will be described with respect to delay unit 432 shown in FIG. 2A.

[0021] As shown in FIG. 2A, the counter 433 counts up by "4" at the high-speed period TH. When it counts up to 9999, it returns to 0 and starts counting up again. The counter 433 includes a signal generating circuit 4331, a gate 4332, an adding circuit 4333, a signal generating circuit 4334, and a comparing circuit 4335. The output signal of the adding circuit 4333 indicates the count value. The signal generating circuit 4331 outputs a signal indicating the constant "0." The signal generating circuit 4334 outputs a signal indicating the constant "4." The comparing circuit 4335 compares the count value with the constant "9999." If the count value is equal to or greater than the constant "9999," the output of the gate 4332 is reset to "0." The adding circuit 4333 adds "4" to the output of the gate 4332 and outputs the result of the addition as the count value at the next high-speed period TH. In this case, the count value "4" corresponds to 4 ms (=high-speed period TH).

[0022] The output unit 434 is a buffer (or buffer memory), and each piece of data stored in the output unit 434 is transmitted to the low-speed calculation control device 2 by the communication unit 3 at a communication cycle TC. The output unit 434 stores the output signal of the recording data input unit 431 (the input signal of the delay circuit 4321), the output signals of the delay circuits 4321 to 4325, and the count value as data DA11 to DA17 at a high-speed cycle TH, and holds the data until the next storage timing. In this embodiment, the output unit 434 outputs the input signal of the delay circuit 4321 and the multiple output signals of the delay circuits 4321 to 4325 to the communication unit 3. The output unit 434 also outputs count values ​​corresponding to the transmission times of the output signals of the multiple delay circuits 4321 to 4325 that it outputs. However, the output unit 434 may not output the output signal of the recording data input unit 431 to the communication unit 3. In this case, for example, a delay circuit that further delays the output signal of delay circuit 4325 by unit delay time TD and outputs the delayed signal, is added to delay unit 432, and output unit 434 outputs the output of this added delay circuit to communication unit 3. In this case, similar to the case where the output signal of record data input unit 431 is not output to communication unit 3, output unit 434 can output six pieces of data DA11 to DA16 that are shifted by unit delay time TD to communication unit 3. That is, output unit 434 may pass delayed outputs of −20 ms, −40 ms, −60 ms, −80 ms, −100 ms, and −120 ms to communication unit 3. That is, in this embodiment, delay unit 432 and output unit 434 can output a plurality of output signals that are signals obtained by delaying the input signal by a plurality of different delay times in delay unit 432, and output unit 434 can output the input signal of delay unit 432 and the plurality of output signals of delay unit 432 to communication unit 3 in output unit 434.

[0023] On the other hand, the low-speed calculation control device 2 includes an input unit 23, as shown in FIG. 2A (not shown in FIG. 1). The input unit 23 is a buffer (or buffer memory), and receives, in a low-speed cycle TL, the data DA11 to DA17 transmitted from the high-speed calculation module 4 in a communication cycle TC, and stores the data DA21 to DA27. In this case, the communication unit 3 transmits the data DA11 to DA17 in the communication cycle TC, but the input unit 23 does not receive the data DA11 to DA17 in synchronization with the communication cycle TC, but receives, in a low-speed cycle TL, the data DA11 to DA17 transmitted most recently by the communication unit 3, and stores the data DA21 to DA27. In this case, the data DA21 to DA27 are updated in the low-speed cycle TL. In this embodiment, the input unit 23 receives the multiple input or output signals of the multiple delay circuits 4321 to 4325 output by the output unit 434 to the communication unit 3 at time intervals longer than the delay time TD and stores them as data DA21 to DA27.

[0024] Furthermore, the storage device 22 stores, at a low speed cycle TL, the multiple input or output signals DA11-DA16 of the multiple delay circuits 4321-4325 and the count value DA17, which are stored in the input unit 23 as data DA21-DA27. The storage of recorded data in the storage device 22 may be performed, for example, by constantly holding the most recent data for a certain period of time, or by using the generation (or input) of a predetermined signal as a trigger to continue the process for a predetermined period of time and then entering a standby state again after the predetermined period of time has elapsed. The storage device 22 is one example of the configuration of the "storage unit" according to the present disclosure.

[0025] Next, an operation example of the control system 1 will be described with reference to Fig. 3 and Fig. 4. Fig. 3 is a flowchart showing an operation example of the low-speed calculation control device 2 according to an embodiment of the present disclosure. Fig. 4 is a timing chart showing an operation example of the control system 1 according to an embodiment of the present disclosure. Note that the following operation example is an example in which some of the multiple pieces of record data generated in the high-speed calculation module 4 at a high-speed cycle TH (4 ms) are transmitted from the high-speed calculation module 4 to the low-speed calculation control device 2 at a communication cycle TC (20 ms) in the communication unit 3, and some of the transmitted multiple pieces of record data are received by the low-speed calculation control device 2 as record data D1 to D21 at a low-speed cycle TL (100 ms).

[0026] 4 shows, with time on the horizontal axis, the correspondence relationship between the count value, high-speed cycle TH (4 ms), unit delay time TD (20 ms), communication cycle TC (20 ms), and low-speed cycle TL (100 ms), as well as an image of the graph of recorded data by calculation unit 21. Note that for the recorded data, the vertical axis represents the valve opening and the horizontal axis represents time. Furthermore, it is assumed that 100 ms or more has elapsed since the start of operation of delay unit 432, and that the output signals of delay circuits 4321 to 4325 are all valid.

[0027] Also, at time t0, the count value is "0." At time t1, 100 ms (= 25 × TH) after time t0, the count value is "100." At time t2, 200 ms (= 50 × TH) after time t0, the count value is "200." At time t3, 320 ms (= 80 × TH) after time t0, the count value is "320." At time t4, 400 ms (= 100 × TH) after time t0, the count value is "400."

[0028] Furthermore, the values ​​of data DA11 to DA16 at time t1 are recorded data D6 to D1. In Fig. 4, the black circles correspond to the timing at which recorded data D1 to D21 were output from LVDT voltage processing unit 42. Recorded data D6 to D1 stored in output unit 434 at time t1 is transmitted by communication unit 3 at time t1t of the next communication cycle TC after time t1, and input by input unit 23 at time t1r of the next low-speed cycle TL after time t1t. At time t1r, data group G1 including recorded data D6 to D1 and the count value (100) are received by low-speed calculation control device 2.

[0029] Furthermore, the values ​​of data DA11-DA16 at time t2 are record data D11-D6. The record data D11-D6 stored in the output unit 434 at time t2 are transmitted by the communication unit 3 at time t2t of the next communication cycle TC after time t2, and input by the input unit 23 at time t2r of the next low-speed cycle TL after time t2t. At time t2r, a data group G2 including the record data D11-D6 is received by the low-speed calculation control device 2.

[0030] Furthermore, the values ​​of data DA11-DA16 at time t3 are record data D17-D12. The record data D17-D12 stored in the output unit 434 at time t3 are transmitted by the communication unit 3 at time t3t of the next communication cycle TC after time t3, and input by the input unit 23 at time t3r of the next low-speed cycle TL after time t3t. At time t3r, a data group G3 including the record data D17-D12 is received by the low-speed calculation control device 2.

[0031] Furthermore, the values ​​of data DA11-DA16 at time t4 are record data D21-D16. The record data D21-D16 stored in the output unit 434 at time t4 is transmitted by the communication unit 3 at time t4t of the next communication cycle TC after time t4, and input by the input unit 23 at time t4r of the next low-speed cycle TL after time t4t. At time t4r, a data group G4 including the record data D21-D16 is received by the low-speed calculation control device 2.

[0032] 4, the recorded data D6 overlaps between the data group G1 and the data group G2. Therefore, for example, by discarding the recorded data D6 in the data group G2, each recorded data included in the data group G1 and each recorded data included in the data group G2 can be configured as time-series data with the unit delay time TD as a sampling period without overlap or loss.

[0033] 4, there is no overlap of recorded data between data group G2 and data group G3. Therefore, for example, without discarding the recorded data, each recorded data included in data group G2 and each recorded data included in data group G3 can be configured as time series data with the unit delay time TD as a sampling period without overlap or loss.

[0034] 4, two pieces of recorded data D16 and D17 overlap between data group G3 and data group G4. Therefore, for example, by discarding the recorded data D16 and D17 in data group G4, each piece of recorded data included in data group G3 and each piece of recorded data included in data group G4 can be configured as time-series data with the unit delay time TD as a sampling period without overlap or loss.

[0035] The reconstruction of the recorded data D1 to D21 as time-series data may be performed, for example, within the low-speed calculation control device 2 or outside the low-speed calculation control device 2. When the reconstruction is performed within the low-speed calculation control device 2, it may be performed within the same or next low-speed period TL after the times T1r to T4r.

[0036] FIG. 3 shows an example of operation when the calculation unit 21 performs reconfiguration in the low-speed calculation control device 2. The process shown in FIG. 3 is executed at a low-speed cycle TL. In the process shown in FIG. 3, first, the input unit 23 receives (n+1) pieces of record data and a count value (step S11). Here, n is a value obtained by dividing the time interval (low-speed cycle TL in this embodiment) of input by the input unit 23 by the unit delay time TD in the delay unit 432. In this embodiment, n is the value "5" obtained by dividing 100 ms by 20 ms. In this case, in step S11, (5+1) pieces of record data and a count value are input to the input unit 23.

[0037] Next, the storage device 22 stores the (n+1) pieces of record data and the count value input by the input unit 23 (step S12). Next, the calculation unit 21 calculates the difference by subtracting the previous count value from the current count value (step S13).

[0038] Next, the calculation unit 21 determines whether the difference is equal to or less than (slow cycle TL - unit delay time TD) (step S14). If the difference is equal to or less than (slow cycle TL - unit delay time TD) (step S14: YES), the calculation unit 21 discards the earliest and next recorded data of the received (5 + 1) recorded data (step S15), and ends the process shown in FIG. 3. In the example shown in FIG. 4, the count value received at time t4r is 400, and the previous count value is 320. In this case, the difference "80" is equal to 80 ms, which is the value obtained by subtracting the unit delay time TD = 20 ms from the slow cycle TL = 100 ms. Therefore, of the recorded data D21 to D16 received at time t4r, the earliest recorded data D16 and the next recorded data D17 are discarded.

[0039] On the other hand, if the difference is not equal to or less than (slow cycle TL - unit delay time TD) (step S14: NO), the calculation unit 21 determines whether the difference is equal to or greater than (slow cycle TL + unit delay time TD) (step S16). If the difference is equal to or greater than (slow cycle TL + unit delay time TD) (step S16: YES), the calculation unit 21 ends the process shown in FIG. 3 without discarding the recorded data. In the example shown in FIG. 4, the count value received at time t3r is 320, and the previous count value is 200. In this case, the difference "120" is equal to 120 ms, which is the sum of the slow cycle TL = 100 ms and the unit delay time TD = 20 ms. Therefore, none of the recorded data D17 to D12 received at time t3r is discarded.

[0040] If the difference is not equal to or greater than (low-speed cycle TL+unit delay time TD) (step S16: NO), the calculation unit 21 determines whether the recorded data is the first data (step S17). If the recorded data is the first data (step S17: YES), the calculation unit 21 ends the process shown in FIG. 3 without discarding the recorded data. If the recorded data is not the first data (step S17: NO), the calculation unit 21 discards the first recorded data (step S18) and ends the process shown in FIG. 3. In the example shown in FIG. 4, if the recorded data received at time t1r is the first recorded data, none of the recorded data D6 to D1 received at time t1r is discarded. Furthermore, in the example shown in FIG. 4, if the recorded data received at time t2r is not the first recorded data, the earliest recorded data D6 is discarded from the recorded data D11 to D6 received at time t2r.

[0041] As described above, in this embodiment, the control system 1 includes the low-speed calculation control device 2 (first control device), the high-speed calculation module 4 (second control device), and the communication unit 3 that inputs and outputs predetermined signals between the low-speed calculation control device 2 and the high-speed calculation module 4. The high-speed calculation module 4 includes a delay unit 432 that outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal by a plurality of different delay times, and an output unit 434 that outputs the input signal and the plurality of output signals of the delay unit 432 to the communication unit 3. The low-speed calculation control device 2 also includes an input unit 23 that inputs the input signal and the plurality of output signals of the delay unit 432 from the communication unit 3 at time intervals (low-speed period TL) longer than the shortest delay time (unit delay time TD), and a storage unit (storage device 22) that stores the input input signal and the plurality of output signals of the delay unit 432. According to this embodiment, a signal generated by the high-speed calculation module 4 (second control device) can be appropriately input to the low-speed calculation control device 2 (first control device) from the communication unit 3 at a period (high-speed period TH) shorter than the input period (low-speed period TL) from the communication unit 3 in the low-speed calculation control device 2 (first control device). Note that the longest delay time (a delay time five or six times the unit delay time TD) is preferably equal to or greater than the value obtained by multiplying the shortest delay time (unit delay time TD) by the value obtained by dividing the time interval (low-speed period TL) by the shortest delay time (unit delay time TD), plus 1.

[0042] In this embodiment, the high-speed calculation module 4 includes, for example, a delay unit 432 including delay circuits 4321-4325 connected in series in multiple stages, each delaying an input signal by a predetermined unit delay time TD before outputting the signal, and an output unit 434 outputting the input or output signals of the delay circuits 4321-4325 to the communication unit 3. The low-speed calculation control device 2 includes an input unit 23 that receives the input or output signals from the communication unit 3 at a time interval (low-speed period TL) longer than the unit delay time TD, and a storage device 22 that stores the received input or output signals. Here, the term "a time interval longer than the unit delay time TD" means that the unit delay time TD is shorter than the time interval at which the input unit 23 receives the input (i.e., receives the recording data). If the time interval at which the input unit 23 receives the input is equal to the unit delay time TD, the number of pieces of recording data that can be received in that time interval will be the same whether the delay unit 432 is provided or not. On the other hand, if the time interval at which the input unit 23 receives data is greater than the unit delay time TD, the number of record data that can be received in that time interval will remain the same or increase when the delay unit 432 is provided. Therefore, according to this embodiment, a signal generated by the high-speed calculation module 4 (second control device) can be appropriately input from the communication unit 3 in the low-speed calculation control device 2 (first control device) at a period shorter than the input period from the communication unit 3 in the low-speed calculation control device 2 (first control device).

[0043] In addition, when the input unit 23 receives multiple input or output signals from the communication unit 3 at a time interval (low speed period TL) longer than twice the unit delay time TD, when the delay unit 432 is provided, the number of recording data that can be received in that time interval will necessarily increase.

[0044] Furthermore, if the number of stages of the delay circuits 4321 to 4325 is equal to or greater than the value obtained by dividing the time interval (low speed period TL) at which the input unit 23 inputs (i.e., receives the recording data) by the unit delay time TD and adding 1 to it, the recording data can be transmitted without any loss.

[0045] Moreover, the output unit 434 further outputs count values ​​corresponding to the sending times of the input signals and output signals of the delay circuits 4321 to 4325. In this case, it is possible to determine whether or not the recording data is being received in duplicate based on the count values, and the recording data can be transmitted without loss even if the operations of the low-speed calculation control device 2 and the high-speed calculation module 4 are not synchronized.

[0046] Furthermore, in this embodiment, among the input signals or output signals of the plurality of delay circuits 4321 to 4325 stored in the storage device 22 (storage unit), signals corresponding to the same count value are discarded.

[0047] (Action and effect) According to the control system and control method configured as described above, a signal generated by the high-speed calculation module 4 (second control device) can be appropriately input from the communication unit 3 in the low-speed calculation control device 2 (first control device) at a period shorter than the input period from the communication unit 3 in the low-speed calculation control device 2 (first control device).

[0048] (Other embodiments) The above describes in detail the embodiments of the present disclosure with reference to the drawings, but the specific configuration is not limited to this embodiment, and design changes and the like are also included within the scope that does not deviate from the gist of the present disclosure.

[0049] <Computer Configuration> FIG. 5 is a schematic block diagram illustrating the configuration of a computer according to at least one embodiment. The computer 90 includes a processor 91 , a main memory 92 , a storage 93 , and an interface 94 . The above-described low-speed calculation control device 2 and high-speed calculation module 4 are implemented in a computer 90. The operations of the above-described processing units are stored in the form of a program in a storage 93. A processor 91 reads the program from the storage 93, loads it into a main memory 92, and executes the above-described processing in accordance with the program. The processor 91 also allocates storage areas in the main memory 92 corresponding to the above-described storage units in accordance with the program.

[0050] The program may be for realizing some of the functions to be performed by the computer 90. For example, the program may be combined with other programs already stored in storage or other programs implemented in other devices to perform the functions. In other embodiments, the computer may include a custom LSI (Large Scale Integrated Circuit) such as a PLD (Programmable Logic Device) in addition to or instead of the above configuration. Examples of PLDs include PAL (Programmable Array Logic), GAL (Generic Array Logic), CPLD (Complex Programmable Logic Device), and FPGA (Field Programmable Gate Array). In this case, some or all of the functions realized by the processor may be realized by the integrated circuit.

[0051] Examples of storage 93 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disk, a compact disc read-only memory (CD-ROM), a digital versatile disc read-only memory (DVD-ROM), and a semiconductor memory. Storage 93 may be an internal medium directly connected to the bus of computer 90, or an external medium connected to computer 90 via interface 94 or a communication line. Furthermore, when this program is distributed to computer 90 via a communication line, computer 90 that receives the program may load the program into main memory 92 and execute the above-described processing. In at least one embodiment, storage 93 is a non-transitory tangible storage medium.

[0052] <Additional Notes> For example, an embodiment of the present disclosure can be understood as follows.

[0053] (1) A control system according to a first aspect includes a first control device, a second control device, and a communication unit that inputs and outputs predetermined signals between the first control device and the second control device, the second control device including a delay unit that outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal by a plurality of different delay times, and an output unit that outputs the plurality of output signals of the delay unit to the communication unit, and the first control device including an input unit that inputs the plurality of output signals from the communication unit at time intervals longer than the shortest delay time, and a storage unit that stores the plurality of input output signals. According to this aspect and each of the following aspects, a signal generated by a high-speed calculation module 4 (second control device) at a cycle shorter than the input cycle from the communication unit 3 in the low-speed calculation control device 2 (first control device) can be appropriately input from the communication unit 3 to the low-speed calculation control device 2 (first control device).

[0054] (2) A control system according to a second aspect is a control system according to (1), in which the longest delay time is equal to or greater than the value obtained by multiplying the shortest delay time by the value obtained by dividing the time interval by the shortest delay time plus 1.

[0055] (3) A control system according to a third aspect is the control system of (1) or (2), wherein the output unit further outputs a count value corresponding to the sending time of the output signal.

[0056] (4) A control system according to a fourth aspect is the control system of (1) to (3), in which, of the output signals stored in the storage unit, signals corresponding to the same count value are discarded.

[0057] (5) A control device according to a fifth aspect is a first control device included in the control system of (1) to (4).

[0058] (6) A control device according to a sixth aspect is a second control device included in the control system of (1) to (4).

[0059] (7) A seventh aspect of the control method is a control method for a control system including a first control device, a second control device, and a communication unit that inputs and outputs predetermined signals between the first control device and the second control device, wherein the second control device includes a delay unit that outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal by a plurality of different delay times, and an output unit that outputs the plurality of output signals of the delay unit to the communication unit, and the control method includes the steps of: inputting the plurality of output signals from the communication unit in the first control device at time intervals longer than the shortest delay time; and storing the input plurality of output signals. [Explanation of symbols]

[0060] 1. Control system 2...Low-speed calculation control device 3. Communications Department 4...High-speed calculation module 21...Arithmetic section 22...Storage device 23...Input section 432...Delay section 434...Output section 4321~4325...Delay circuit

Claims

1. a first control device, a second control device, and a communication unit that inputs and outputs predetermined signals between the first control device and the second control device; The second control device is a delay unit that outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal by a plurality of different delay times; an output unit that outputs the plurality of output signals of the delay unit to the communication unit; Equipped with The first control device an input unit that inputs the plurality of output signals from the communication unit at time intervals longer than the shortest delay time; a storage unit that stores the plurality of input output signals; Equipped with Control system.

2. The longest delay time is equal to or greater than the value obtained by dividing the time interval by the shortest delay time, adding 1 to the value obtained by multiplying the value obtained by dividing the time interval by the shortest delay time, and then multiplying the value obtained by ... time interval by the shortest delay time. The control system of claim 1 .

3. The output unit further outputs a count value corresponding to the sending time of the output signal. The control system of claim 2 .

4. Among the output signals stored in the storage unit, signals corresponding to the same count value are discarded. The control system of claim 3 .

5. The first control device is provided in the control system according to any one of claims 1 to 4. Control device.

6. The second control device is provided in the control system according to any one of claims 1 to 4. Control device.

7. A control method for a control system including a first control device, a second control device, and a communication unit that inputs and outputs predetermined signals between the first control device and the second control device, The second control device is a delay unit that outputs a plurality of output signals, each of which is a signal obtained by delaying an input signal by a plurality of different delay times; an output unit that outputs the plurality of output signals of the delay unit to the communication unit; Equipped with In the first control device, inputting the plurality of output signals from the communication unit at time intervals longer than the shortest delay time; storing the inputted plurality of output signals; A control method comprising:

Images