Image sensor and optical detection device

Abstract

To improve an image quality in an image sensor in which all pixels are exposed simultaneously.SOLUTION: A conversion efficiency control transistor opens and closes a path between a floating diffusion (FD) and an additional capacitor. The discharge transistor discharges charges from a photoelectric conversion element. A reset transistor is interposed between a power supply voltage and the discharge transistor. A transfer transistor transfers charges from the photoelectric conversion element to the FD. An FD link gate transistor opens and closes a path between a connection point of the additional capacitance and the conversion efficiency control transistor and a connection point of the reset transistor and the discharge transistor. A plurality of capacitive elements hold a level corresponding to the voltage of the FD.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present technology relates to an image sensor, and more particularly to a voltage domain image sensor and a photodetector. [Background technology]

[0002] In recent years, attention has been focused on voltage-domain global shutter CMOS (Complementary MOS) image sensors, which convert signal charges into voltages and hold them. Such sensors are hereinafter referred to as "VD.GS." For example, a VD.GS has been proposed, which switches the conversion efficiency when converting charges into voltages between multiple stages and samples the signals at each conversion efficiency using a sample-and-hold circuit (see, for example, Patent Document 1). In this image sensor, two conversion efficiency control transistors are inserted between a floating diffusion (FD) and an additional capacitor in the upstream stage of the sample-and-hold circuit. An overflow drain is inserted between the junction of the additional capacitor and the conversion efficiency control transistor and the photoelectric conversion element, and a reset transistor is inserted between the junction of the two conversion efficiency control transistors and the power supply voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 062947 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned conventional technology aims to expand the dynamic range by switching the conversion efficiency. However, in the above-mentioned image sensor, when the illuminance is relatively high, there is a risk that the charge overflowing from the photoelectric conversion element will leak into the FD between the time the charge is transferred to the floating diffusion layer and the time the signal is sampled by the sample-and-hold circuit. As a result, the signal level held in the FD changes, resulting in a problem of degradation in the image quality.

[0005] This technology was developed in light of these circumstances, and aims to improve image quality in image sensors that expose all pixels simultaneously. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an image sensor comprising: a conversion efficiency control transistor that opens and closes a path between an FD and an additional capacitance, a drain transistor that drains charge from a photoelectric conversion element, a reset transistor inserted between a power supply voltage and the drain transistor, a transfer transistor that transfers charge from the photoelectric conversion element to the FD, an FD link gate transistor that opens and closes a path between a connection point between the additional capacitance and the conversion efficiency control transistor and a connection point between the reset transistor and the drain transistor, and a plurality of capacitance elements that maintain a level according to the voltage of the FD, thereby providing the effect of preventing charge leakage to the FD.

[0007] In addition, in this first aspect, the level may include a reset level when the FD is initialized and a signal level when the charge is transferred to the FD, the reset level may include a first reset level when the conversion efficiency control transistor is in an off state and a second reset level when the conversion efficiency control transistor is in an on state, the signal level may include a first signal level when the conversion efficiency control transistor is in an off state and a second signal level when the conversion efficiency control transistor is in an on state, and the plurality of capacitive elements may include a first capacitive element that holds the first reset level, a second capacitive element that holds the first signal level, a third capacitive element that holds the second reset level, and a fourth capacitive element that holds the second signal level. This brings about an effect that the conversion efficiency of converting charge into voltage can be switched in two stages.

[0008] Also, in this first aspect, the conversion efficiency control transistor includes first and second conversion efficiency control transistors connected in series, and the levels include a reset level when the FD is initialized and a signal level when the charge is transferred to the FD, and the reset levels include a first reset level when both the first and second conversion efficiency control transistors are in an off state, a second reset level when only one of the first and second conversion efficiency control transistors is in an on state, and a third reset level when both the first and second conversion efficiency control transistors are in an on state, and the signal level is a reset level when the first and second conversion efficiency control transistors are in an on state. The conversion efficiency control transistors may include a first signal level when both the first and second conversion efficiency control transistors are in an off state, a second signal level when only one of the first and second conversion efficiency control transistors is in an on state, and a third signal level when both the first and second conversion efficiency control transistors are in an on state, and the plurality of capacitive elements may include a first capacitive element that holds the first reset level, a second capacitive element that holds the first signal level, a third capacitive element that holds the second reset level, a fourth capacitive element that holds the second signal level, a fifth capacitive element that holds the third reset level, and a sixth capacitive element that holds the third signal level, thereby providing the effect of switching the conversion efficiency in three stages.

[0009] In addition, in the first aspect, the amplifier may further include a pre-amplifying transistor that outputs the level to a pre-node to which one end of each of the plurality of capacitive elements is commonly connected, and a selection circuit that connects the other end of any of the plurality of capacitive elements to a predetermined post-node, thereby providing the effect of sampling and holding a signal.

[0010] In addition, in this first aspect, the amplifier may further include a pre-amplifying transistor that outputs the level to a predetermined node, and a selection circuit that connects one end of one of the plurality of capacitive elements to the node, and the other end of each of the plurality of capacitive elements is grounded, thereby providing the effect of sample-holding a signal.

[0011] In addition, in this first aspect, a vertical scanning circuit may be further provided, and the vertical scanning circuit may turn off the FD link gate transistor and turn on the reset transistor and the discharge transistor immediately after turning on the transfer transistor to transfer the charge, thereby providing an effect that charge due to blooming can be released via the reset transistor and the discharge transistor.

[0012] In addition, in this first aspect, the conversion efficiency control transistor, the reset transistor, the drain transistor, the transfer transistor, and the FD link gate transistor may be arranged on a predetermined pixel chip, and the plurality of capacitive elements may be arranged on a predetermined circuit chip, thereby providing an effect of facilitating miniaturization.

[0013] A second aspect of the present technology is a photodetector device including: a conversion efficiency control transistor that opens and closes a path between an FD and an additional capacitance; a drain transistor that drains charge from a photoelectric conversion element; a reset transistor inserted between a power supply voltage and the drain transistor; a transfer transistor that transfers charge from the photoelectric conversion element to the FD; an FD link gate transistor that opens and closes a path between a connection point of the additional capacitance and the conversion efficiency control transistor and a connection point of the reset transistor and the drain transistor; a plurality of capacitance elements that maintain a level according to the voltage of the FD; and a signal processing circuit that processes signals of the level. This prevents charge leakage to the FD, resulting in an effect of improving the image quality of image data. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment of the present technology. [Figure 2] 1 is a block diagram showing an example of the configuration of an image sensor according to a first embodiment of the present technology. [Figure 3]1 is a circuit diagram showing a configuration example of a pixel according to a first embodiment of the present technology. [Figure 4] 1 is a block diagram showing a configuration example of a load MOS circuit block and a column signal processing circuit according to a first embodiment of the present technology; [Figure 5] 4 is a timing chart showing an example of a global shutter operation according to the first embodiment of the present technology. [Figure 6] 4 is a timing chart showing an example of a read operation according to the first embodiment of the present technology. [Figure 7] FIG. 10 is a circuit diagram showing a configuration example of a pixel in a comparative example. [Figure 8] 5 is a flowchart showing an example of an operation of the image sensor according to the first embodiment of the present technology. [Figure 9] FIG. 10 is a circuit diagram showing a configuration example of a pixel according to a second embodiment of the present technology. [Figure 10] 10 is a timing chart showing an example of a global shutter operation according to the second embodiment of the present technology. [Figure 11] 10 is a timing chart showing an example of a read operation according to the second embodiment of the present technology. [Figure 12] FIG. 11 is a circuit diagram showing a configuration example of a pixel according to a third embodiment of the present technology. [Figure 13] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 14] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example in which the connection destination of the reset transistor is changed and an FD link gate transistor is added) 2. Second embodiment (example in which the connection destination of the reset transistor is changed and an FD link gate transistor is added to switch the conversion efficiency between three levels) 3. Third embodiment (example in which the connection destination of the reset transistor is changed and an FD link gate transistor is added to change the circuit configuration of the sample-and-hold circuit) 4. Mobile application examples

[0016] <1. First embodiment> [Configuration example of imaging device] 1 is a block diagram showing an example configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes an imaging lens 110, an image sensor 200, a recording unit 120, and an imaging control unit 130. The imaging device 100 is assumed to be a digital camera or an electronic device with an imaging function (such as a smartphone or a personal computer).

[0017] The image sensor 200 captures image data under the control of the imaging control unit 130. The image sensor 200 supplies the image data to the recording unit 120 via a signal line 209. The image sensor 200 can be provided in a light detection device such as a sensing element or a light receiving element, in addition to the imaging device 100. The imaging device 100 is an example of a light detection device as defined in the claims.

[0018] The imaging lens 110 collects light and guides it to the image sensor 200. The imaging control unit 130 controls the image sensor 200 to capture image data. The imaging control unit 130 supplies an imaging control signal including, for example, a vertical synchronization signal VSYNC to the image sensor 200 via a signal line 139. The recording unit 120 records the image data.

[0019] Here, the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a fixed frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0020] It should be noted that although the imaging device 100 records image data, the image data may be transmitted to an external device. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging device 100 may further display the image data. In this case, a display unit is further provided.

[0021] [Image sensor configuration example] 2 is a block diagram showing an example configuration of an image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a vertical scanning circuit 211, a pixel array unit 220, a timing control circuit 212, a DAC (Digital to Analog Converter) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array unit 220, a plurality of pixels 300 are arranged in a two-dimensional lattice pattern.

[0022] Hereinafter, a group of pixels 300 arranged in the horizontal direction will be referred to as a "row," and a group of pixels 300 arranged in a direction perpendicular to the rows will be referred to as a "column."

[0023] The timing control circuit 212 controls the operation timing of the vertical scanning circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with a vertical synchronization signal VSYNC from the imaging control unit .

[0024] The DAC 213 generates a sawtooth ramp signal by DA (Digital to Analog) conversion and supplies the generated ramp signal to the column signal processing circuit 260.

[0025] The vertical scanning circuit 211 sequentially selects and drives rows to output analog pixel signals. The pixels 300 photoelectrically convert incident light to generate analog pixel signals. The pixels 300 supply pixel signals to the column signal processing circuit 260 via the load MOS circuit block 250.

[0026] The load MOS circuit block 250 includes a MOS (Metal-Oxide-Semiconductor) transistor for supplying a constant current, which is provided for each column.

[0027] The column signal processing circuit 260 performs signal processing such as AD (Analog to Digital) conversion processing and CDS (Correlated Double Sampling) processing on pixel signals for each column. The column signal processing circuit 260 supplies image data made up of the processed signals to the recording unit 120.

[0028] [Pixel configuration example] 3 is a circuit diagram showing a configuration example of a pixel 300 according to the first embodiment of the present technology. The pixel 300 includes a front-stage circuit 310, a switching transistor 329, capacitance elements 321, 322, 323, and 324, a selection circuit 330, a rear-stage reset transistor 341, and a rear-stage circuit 350. Note that, for example, nMOS (n-channel MOS) transistors are used as various transistors in the pixel 300.

[0029] The pre-stage circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, a reset transistor 313, an FD 314, a pre-stage amplification transistor 315, a current source transistor 316, and a drain transistor 317. The pre-stage circuit 310 further includes a conversion efficiency control transistor 361, an FD link gate transistor 363, and an additional capacitor 365.

[0030] The photoelectric conversion element 311 generates electric charges by photoelectric conversion. The transfer transistor 312 transfers electric charges from the photoelectric conversion element 311 to the FD 314 in accordance with a transfer signal TRG from the vertical scanning circuit 211.

[0031] The reset transistor 313 is turned on and off in accordance with a reset signal RST from the vertical scanning circuit 211, and initializes the FD 314 by drawing charge from it. The FD 314 accumulates charge and generates a voltage according to the amount of charge. The reset transistor 313 is also inserted between the power supply voltage VDD and the discharge transistor 317.

[0032] The pre-amplifying transistor 315 constitutes a source follower circuit, and outputs a signal at a level corresponding to the voltage of the FD 314 to the pre-node 320 .

[0033] The source of the pre-amplification transistor 315 is connected to the power supply voltage VDD. The current source transistor 316 is connected to the drain of the pre-amplification transistor 315. The current source transistor 316 supplies a current id1 under the control of the vertical scanning circuit 211.

[0034] The discharge transistor 317 is turned on and off in accordance with a discharge signal OFG from the vertical scanning circuit 211 , and functions as an overflow drain that discharges charges from the photoelectric conversion element 311 .

[0035] The conversion efficiency control transistor 361 is turned on and off in accordance with a control signal FCG from the vertical scanning circuit 211 to open and close the path between the FD 314 and the additional capacitor 365 .

[0036] The FD link gate transistor 363 opens and closes a path between the connection point of the additional capacitor 365 and the conversion efficiency control transistor 361 and the connection point of the reset transistor 313 and the drain transistor 317. The FD link gate transistor 363 is turned on and off in accordance with a control signal FLG from the vertical scanning circuit 211.

[0037] The switching transistor 329 short-circuits the source and drain of the pre-amplification transistor 315 in accordance with a switching signal SW from the vertical scanning circuit 211 .

[0038] One end of each of the capacitance elements 321 , 322 , 323 , and 324 is commonly connected to the previous-stage node 320 , and the other end of each is connected to the selection circuit 330 .

[0039] The selection circuit 330 connects the other end of any one of the capacitance elements 321, 322, 323, and 324 to a subsequent node 340. The selection circuit 330 includes selection transistors 331, 332, 333, and 334. The selection transistor 331 opens and closes the path between the capacitance element 321 and the subsequent node 340 in accordance with a selection signal S1 from the vertical scanning circuit 211. The selection transistor 332 opens and closes the path between the capacitance element 322 and the subsequent node 340 in accordance with a selection signal S2 from the vertical scanning circuit 211.

[0040] The selection transistor 333 opens and closes the path between the capacitance element 323 and the subsequent node 340 in accordance with a selection signal S3 from the vertical scanning circuit 211. The selection transistor 334 opens and closes the path between the capacitance element 324 and the subsequent node 340 in accordance with a selection signal S4 from the vertical scanning circuit 211.

[0041] The capacitive elements 321, 322, 323, and 324 are examples of the first, second, third, and fourth capacitive elements set forth in the claims.

[0042] The subsequent reset transistor 341 initializes the level of the subsequent node 340 in accordance with a subsequent reset signal RB from the vertical scanning circuit 211.

[0043] The subsequent circuit 350 includes a subsequent amplifier transistor 351 and a selection transistor 352. The subsequent amplifier transistor 351 forms a source follower circuit and outputs a signal at a level corresponding to the level of the subsequent node 340. The selection transistor 352 outputs the signal from the subsequent amplifier transistor 351 as a pixel signal to a vertical signal line 309 in accordance with a selection signal SEL from the vertical scanning circuit 211. A load MOS transistor 251, which will be described later, is connected to the vertical signal line 309.

[0044] Furthermore, the circuits and elements in the image sensor 200 are distributed and arranged on the stacked pixel chip 201 and circuit chip 202. For example, the circuit preceding the pre-stage amplification transistor 315 and the switching transistor 329 are arranged on the pixel chip 201. Furthermore, the current source transistor 316 and the circuits following the pre-stage node 320 are arranged on the circuit chip 202. Note that the circuits and elements arranged on the pixel chip 201 and the circuit chip 202 are not limited to those illustrated in the figure. Furthermore, the circuits and elements in the image sensor 200 can also be arranged on a single semiconductor chip. Furthermore, the circuits and elements in the image sensor 200 can also be distributed and arranged on three or more semiconductor substrates.

[0045] The vertical scanning circuit 211 initializes the FDs 314 and photoelectric conversion elements 311 of all pixels at the start of exposure, and controls the transfer transistors 312 of all pixels at the end of exposure to transfer signal charges from the photoelectric conversion elements 311 to the FDs 314. This type of exposure control, in which exposure starts and ends simultaneously for all pixels, is called a global shutter method.

[0046] The level of the FD 314 when the FD 314 is initialized and the level corresponding to that level (the retention level of the capacitive element and the level of the vertical signal line 309) will hereinafter be collectively referred to as the "P phase" or "reset level."

[0047] The level of the FD 314 when transferring the signal charge and the level corresponding to that level (the retention level of the capacitive element and the level of the vertical signal line 309) will hereinafter be collectively referred to as the "D phase" or "signal level."

[0048] Furthermore, the conversion efficiency when the conversion efficiency control transistor 361 is in the off state is higher than when the conversion efficiency control transistor 361 is in the on state. Hereinafter, the higher conversion efficiency is referred to as the "HCG (High Conversion Gain)" and the lower conversion efficiency is referred to as the "LCG (Low Conversion Gain)." When exposure using the global shutter method is completed, the pre-stage circuit 310 converts charges into voltages using the HCG and LCG, and outputs them sequentially to the pre-stage node 320. Since a reset level or signal level voltage is generated, the reset level and signal level generated by the HCG and the reset level and signal level generated by the LCG are output sequentially.

[0049] When a reset level corresponding to HCG is output, only the selection transistor 331 in the selection circuit 330 transitions to the ON state, and the reset level is held in the capacitance element 321. When a signal level corresponding to HCG is output, only the selection transistor 332 in the selection circuit 330 transitions to the ON state, and the signal level is held in the capacitance element 322. In this way, the capacitance elements 321 and 322 hold a voltage corresponding to HCG.

[0050] Furthermore, when a reset level corresponding to LCG is output, only the selection transistor 333 in the selection circuit 330 transitions to the ON state, and the reset level is held in the capacitance element 323. When a signal level corresponding to LCG is output, only the selection transistor 334 in the selection circuit 330 transitions to the ON state, and the signal level is held in the capacitance element 324. In this way, the capacitance elements 323 and 324 hold a voltage corresponding to LCG.

[0051] Here, the capacitance values ​​of the capacitive elements 321 and 322 corresponding to the HCG are assumed to be the same. The capacitance values ​​of the capacitive elements 323 and 324 corresponding to the LCG are also assumed to be the same. The total capacitance value of the capacitive elements 321 and 322 corresponding to the HCG is assumed to be greater than the total capacitance value of the capacitive elements 323 and 324 corresponding to the LCG. When the LCG is set, optical shot noise becomes dominant compared to when the HCG is set, and the kTC noise generated during sample and hold does not significantly contribute to image quality. On the other hand, when the HCG is set, the adverse effects of the kTC noise become relatively greater. Furthermore, typically, when sampling a signal into a capacitive element, the larger the capacitance value, the more effectively the kTC noise can be reduced during sampling. Therefore, by relatively increasing the capacitance value of the capacitive element corresponding to the HCG that is more affected by the kTC noise, the kTC noise can be suppressed and image quality can be improved.

[0052] The subsequent circuit 350 sequentially reads out the levels (reset level and signal level) corresponding to the HCG and the levels corresponding to the LCG via the subsequent node 340 after the exposure is completed.

[0053] The column signal processing circuit 260 at the subsequent stage performs CDS processing to determine the difference between the reset level corresponding to the HCG and the signal level corresponding to the HCG, and generates a digital signal corresponding to the HCG. Also, the column signal processing circuit 260 performs CDS processing to determine the difference between the reset level corresponding to the LCG and the signal level corresponding to the LCG, and generates a digital signal corresponding to the LCG.

[0054] The column signal processing circuit 260 also determines whether the illuminance is higher than a predetermined value on a frame-by-frame or pixel-by-pixel basis. When the illuminance is high, the column signal processing circuit 260 outputs a digital signal corresponding to LCG as the pixel signal for that pixel, and when the illuminance is low, the column signal processing circuit 260 outputs a digital signal corresponding to HCG as the pixel signal.

[0055] When the conversion efficiency is switched in accordance with the illuminance on a frame-by-frame basis, it is possible to suppress a saturation charge amount and a lack of sensitivity, thereby improving image quality. Furthermore, when the conversion efficiency is switched in accordance with the illuminance on a pixel-by-pixel basis, it is possible to expand the dynamic range. Furthermore, since it is not necessary to capture two frames with different conversion efficiencies for each frame, it is possible to suppress a decrease in frame rate. Therefore, when the conversion efficiency is switched in accordance with the pixel, it is possible to improve image quality while suppressing a decrease in frame rate.

[0056] As mentioned above, when exposure is complete, the vertical scanning circuit 211 controls the transfer transistor 312 to transfer the signal charge. However, if the illuminance is relatively high, the charge overflowing from the photoelectric conversion element 311 may leak out via the drain transistor 317. This phenomenon is called blooming. The period from the transfer of the signal charge to the sampling of the signal level is relatively long in VD.GS, ranging from several microseconds to several hundred microseconds. If the charge generated by blooming leaks into the FD 314 during this period, the signal level may change and be destroyed, resulting in a deterioration in the image quality of the image data.

[0057] Therefore, immediately after the charge transfer, the vertical scanning circuit 211 changes the FD link gate transistor 363 from the on state to the off state, and changes the reset transistor 313 and the drain transistor 317 from the off state to the on state. This control allows the charge generated by blooming to be released to the power supply side via the on-state drain transistor 317 and reset transistor 313. The thick dotted line in the figure indicates the path along which the charge is released. Also, at this time, because the FD link gate transistor 363 is in the off state, no charge leaks to the FD 314. Therefore, contamination between the signal charge transferred by the transfer transistor 312 and the charge leaked due to blooming can be prevented. This can improve the image quality of the image data.

[0058] [Column signal processing circuit configuration example] FIG. 4 is a block diagram showing an example of the configuration of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0059] A vertical signal line 309 is wired for each column in the load MOS circuit block 250. If the number of columns is I (I is an integer), then I vertical signal lines 309 are wired. Furthermore, a load MOS transistor 251 that supplies a constant current id2 is connected to each vertical signal line 309.

[0060] The column signal processing circuit 260 includes a plurality of ADCs (Analog to Digital Converters) 261 and a digital signal processing unit 262. An ADC 261 is provided for each column. If the number of columns is I, then I ADCs 261 are provided.

[0061] The ADC 261 converts analog pixel signals from the corresponding columns into digital signals using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signals to the digital signal processing unit 262. For example, a single-slope ADC including a comparator and a counter is disposed as the ADC 261.

[0062] The digital signal processing unit 262 performs predetermined signal processing such as CDS processing on each of the digital signals for each column. The digital signal processing unit 262 supplies image data made up of the processed digital signals to the recording unit 120.

[0063] [Image sensor operation example] 5 is a timing chart showing an example of a global shutter operation according to the first embodiment of the present technology. In the figure, TRG_[1:N] and the like indicate signals from the first row to the Nth row, where N is an integer indicating the total number of rows.

[0064] Before the start of exposure, the control signal FLG is controlled to a high level. The vertical scanning circuit 211 supplies a high-level transfer signal TRG, reset signal RST, control signal FCG, and discharge signal OFG to all rows (in other words, all pixels) over a pulse period starting from timing T0 immediately before the start of exposure. This initializes all pixels, and exposure begins simultaneously for all pixels.

[0065] Then, the vertical scanning circuit 211 sets the subsequent reset signals RB for all rows to high level at timing T1 immediately before the end of exposure. Also, the vertical scanning circuit 211 supplies a high-level control signal FCG to all rows over a pulse period from timing T1.

[0066] Furthermore, after timing T1, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to supply a current id1. If the current id1 becomes large, the IR drop will become large, so the current id1 needs to be on the order of several nanoamperes (nA) to several tens of nanoamperes (nA). Meanwhile, the load MOS transistors 251 of all columns are in the off state, and no current id2 is supplied to the vertical signal line 309.

[0067] Then, the vertical scanning circuit 211 supplies a high-level selection signal S1 to all rows over the pulse period from timing T2. At this time, since the conversion efficiency control transistor 361 is in the off state, the P-phase level (reset level) generated by the HCG is maintained. Note that this reset level is an example of the first reset level described in the claims.

[0068] Then, the vertical scanning circuit 211 supplies a high-level transfer signal TRG to all rows over the pulse period starting from timing T3 at the end of exposure. This causes the signal charges of all pixels to be transferred to the FD 314, completing exposure for all pixels. Here, each pixel must sequentially sample two signal levels: the signal level generated by the HCG and the signal level generated by the LCG. However, as illustrated in the figure, there is only one transfer pulse, and the potential within the pixel is adjusted so that the charge of the photoelectric conversion element 311 can be transferred with just this one transfer.

[0069] At timing T4, immediately after timing T3, the vertical scanning circuit 211 sets the control signal FLG for all rows to low level, and immediately thereafter at timing T5, sets the reset signal RST and discharge signal OFG for all rows to high level. This turns off the FD link gate transistor 363, and turns on the reset transistor 313 and the discharge transistor 317. This control allows the charge generated by blooming to escape to the power supply via the discharge transistor 317 and the reset transistor 313, preventing the charge from leaking to the FD 314.

[0070] Then, the vertical scanning circuit 211 supplies a high-level selection signal S2 to all rows over the pulse period from timing T6. At this time, since the conversion efficiency control transistor 361 is in the off state, the D-phase level (signal level) generated by the HCG is maintained. Note that this reset level is an example of the first signal level described in the claims.

[0071] The vertical scanning circuit 211 then sets the control signal FCG for all rows to a high level at timing T7, and immediately thereafter, at timing T8, supplies a high-level selection signal S4 to all rows over a pulse period. At this time, the conversion efficiency control transistor 361 is in an on state, so the signal level generated by LCG is maintained. This signal level is an example of the second signal level described in the claims.

[0072] Then, the vertical scanning circuit 211 supplies a high-level control signal FLG to all rows over a pulse period from timing T9, thereby initializing the FD 314 in all rows.

[0073] Then, the vertical scanning circuit 211 supplies a high-level selection signal S3 to all rows over the pulse period from timing T10. At this time, the conversion efficiency control transistor 361 is in the on state, so the reset level generated by the LCG is maintained. Note that this reset level is an example of the second reset level described in the claims.

[0074] Then, at timing T11, the vertical scanning circuit 211 sets the reset signal RST and the control signal FCG for all rows to low level, and sets the switching signal SW for all rows to high level.

[0075] Furthermore, at timing T11, the vertical scanning circuit 211 stops supplying the current id1 to all pixels and starts supplying the current id2 to all columns.

[0076] 6 is a timing chart showing an example of a readout operation according to the first embodiment of the present technology. During a readout period for the nth row (n is an integer from 1 to N) from timing T20 to timing T28, the vertical scanning circuit 211 sets the selection signal SEL for the nth row to high level. SEL_[n] and the like in the figure indicate signals to pixels in the nth row.

[0077] From timing T20 through the pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the nth row, thereby erasing the history of the previous signal held in the parasitic capacitance when the subsequent node 340 has parasitic capacitance.

[0078] From timing T21 over a pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S1 to the n-th row, and then the P-phase level (reset level) generated by the HCG is read out.

[0079] From timing T22 through a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T23 through a pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S2 to the n-th row. Then, the D-phase level (signal level) generated by the HCG is read out.

[0080] From timing T24 through the pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T25 through the pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S3 to the n-th row. Then, the reset level generated by the LCG is read out.

[0081] From timing T26 through a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T27 through a pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S4 to the n-th row. Then, the signal level generated by the LCG is read out.

[0082] During the readout period, the vertical scanning circuit 211 also sets the switching signals SW for all rows to high level, stopping the current id1 for all pixels and supplying the current id2 for all columns.

[0083] The read order is not limited to that shown in the figure.

[0084] Here, a comparative example is assumed in which the FD link gate transistor 363 is not provided and the destination of the reset transistor 313 is different.

[0085] 7 is a circuit diagram showing an example of the configuration of a pixel 300 in a comparative example. As shown in the figure, the FD link gate transistor 363 is not arranged in the pixel 300, and the drain transistor 317 is inserted between the additional capacitor 365 and the photoelectric conversion element 311. In addition, the reset transistor 313 is inserted between the connection point of the conversion efficiency control transistor 361 and the FD 314 and the power supply voltage VDD. The pixel 300 in this comparative example can be driven, for example, by the method shown in FIG. 46 of Patent Document 1. In the figure, the control signal FDG can be replaced with the control signal FCG.

[0086] 7, let us consider a case in which blooming occurs in the comparative example during the period from when the signal charge is transferred until the conversion efficiency control transistor 361 is turned on and the signal level corresponding to LCG is sampled. In the circuit configuration of the comparative example, there is a risk that charge generated by blooming may leak to the FD 314 via the drain transistor 317 and the conversion efficiency control transistor 361. The thick dotted lines in the figure indicate the paths along which charge leaks due to blooming.

[0087] 3, the reset transistor 313 is moved to the power supply side of the drain transistor 317, and an FD link gate transistor 363 is added. As a result, as described above, the charge generated by blooming can be released to the power supply side via the drain transistor 317 and reset transistor 313, which are in the ON state. Also, at this time, because the FD link gate transistor 363 is in the OFF state, no charge leaks to the FD 314. This prevents contamination and improves the image quality of the image data.

[0088] 8 is a flowchart showing an example of the operation of the image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.

[0089] The vertical scanning circuit 211 exposes all pixels (step S901). Then, the vertical scanning circuit 211 selects a row to read (step S902). The column signal processing circuit 260 sequentially reads pixel signals (i.e., reset levels and signal levels) corresponding to the LCGs of that row (step S903). Next, the column signal processing circuit 260 sequentially reads pixel signals (reset levels and signal levels) corresponding to the HCGs (step S904).

[0090] The image sensor 200 determines whether or not the readout of all rows has been completed (step S905). If the readout of all rows has not been completed (step S905: No), the image sensor 200 repeats step S902 and subsequent steps. On the other hand, if the readout of all rows has been completed (step S905: Yes), the image sensor 200 executes CDS processing and the like, and ends the operation for imaging. When capturing multiple frames of image data consecutively, steps S901 to S905 are repeatedly executed in synchronization with a vertical synchronization signal.

[0091] As described above, in the first embodiment of the present technology, the reset transistor 313 is inserted between the power supply voltage and the drain transistor 317 in the pixel 300, and the FD link gate transistor 363 is added. This allows the charge generated by blooming to escape to the power supply side via the drain transistor 317 and the reset transistor 313, preventing the charge from leaking to the FD 314, and improving the image quality of the image data.

[0092] <2. Second embodiment> In the first embodiment described above, the image sensor 200 switches the conversion efficiency between two stages, but it can also switch between three stages. The image sensor 200 in this second embodiment differs from the first embodiment in that it switches the conversion efficiency between three stages.

[0093] 9 is a circuit diagram showing a configuration example of a pixel 300 according to a second embodiment of the present technology. The pixel 300 according to the second embodiment differs from the pixel 300 according to the first embodiment in that it further includes a conversion efficiency control transistor 362, capacitance elements 325 and 326, and selection transistors 335 and 336.

[0094] The conversion efficiency control transistor 362 is inserted between the conversion efficiency control transistor 361 and the FD 314, and is turned on and off in accordance with a control signal FDG from the vertical scanning circuit 211. The conversion efficiency control transistor 362 is, for example, an nMOS transistor.

[0095] One end of each of the capacitance elements 325 and 326 is commonly connected to the previous-stage node 320. The selection transistor 335 opens and closes a path between the capacitance element 325 and the next-stage node 340 in accordance with a selection signal S5 from the vertical scanning circuit 211. The selection transistor 336 opens and closes a path between the capacitance element 326 and the next-stage node 340 in accordance with a selection signal S6 from the vertical scanning circuit 211. The selection transistors 335 and 336 are, for example, nMOS transistors.

[0096] Of the conversion efficiency control transistors 361 and 362, when only the conversion efficiency control transistor 362 is in the on state, the conversion efficiency is lower than when both the conversion efficiency control transistors 361 and 362 are in the off state. Also, when both the conversion efficiency control transistors 361 and 362 are in the on state, the conversion efficiency is lower than when only the conversion efficiency control transistor 362 is in the on state. In this way, the conversion efficiency is controlled in three stages. Of the three stages, the highest conversion efficiency is referred to as HCG, and the lowest conversion efficiency is referred to as LCG. Also, the conversion efficiency between HCG and LCG is referred to as "MCG (Middle Conversion Gain)." By switching the conversion efficiency in three stages, it is possible to control the conversion efficiency to a more appropriate level compared to switching in two stages.

[0097] The capacitance values ​​of the capacitance elements 321 and 322 corresponding to the HCG are assumed to be larger than those of the capacitance elements corresponding to the MCG and LCG. The capacitance values ​​of the capacitance elements 323 and 324 corresponding to the MCG are assumed to be the same as those of the capacitance elements 325 and 326 corresponding to the LCG. The capacitance elements 325 and 326 are examples of the fifth and sixth capacitance elements set forth in the claims.

[0098] Although the conversion efficiency is set to three stages, it can also be set to four or more stages. In this case, conversion efficiency control transistors, capacitance elements, and selection transistors can be added according to the number of stages.

[0099] FIG. 10 is a timing chart showing an example of a global shutter operation according to the second embodiment of the present technology.

[0100] Before exposure begins, the control signal FLG is controlled to a high level. The vertical scanning circuit 211 supplies a high-level transfer signal TRG, reset signal RST, control signal FCG, control signal FDG, and discharge signal OFG to all rows (all pixels) over a pulse period starting from timing T0 immediately before exposure begins. This initializes all pixels, and exposure begins simultaneously for all pixels.

[0101] Then, the vertical scanning circuit 211 sets the subsequent reset signal RB and the control signal FDG to high level for all rows at timing T1 immediately before the end of exposure, and also supplies a high-level control signal FCG to all rows over a pulse period from timing T1.

[0102] Furthermore, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) after timing T1 to supply the current id1. Meanwhile, the load MOS transistors 251 of all columns are in the off state, and the current id2 is not supplied to the vertical signal line 309.

[0103] Then, the vertical scanning circuit 211 supplies a high-level selection signal S3 to all rows over the pulse period from timing T2. At this time, since only the conversion efficiency control transistor 362 is in the on state, the P-phase level (reset level) generated by the MCG is maintained. Note that this reset level is an example of the second reset level described in the claims.

[0104] Then, the vertical scanning circuit 211 sets the control signal FDG of all rows to low level at timing T3, and supplies a high-level selection signal S1 to all rows over a pulse period from timing T4. At this time, since both the conversion efficiency control transistors 361 and 362 are in the off state, the reset level generated by HCG is maintained.

[0105] Then, the vertical scanning circuit 211 supplies a high-level transfer signal TRG to all rows over a pulse period from timing T5 at the end of exposure, which causes signal charges in all pixels to be transferred to the FD 314, completing exposure of all pixels.

[0106] At timing T6 immediately after timing T5, the vertical scanning circuit 211 sets the control signal FLG for all rows to low level, and immediately thereafter at timing T7, sets the reset signal RST and discharge signal OFG for all rows to high level.

[0107] Then, the vertical scanning circuit 211 supplies a high-level selection signal S2 to all rows over the pulse period from timing T8. At this time, since both the conversion efficiency control transistors 361 and 362 are in the off state, the D-phase level (signal level) generated by the HCG is maintained.

[0108] The vertical scanning circuit 211 then sets the control signal FDG for all rows to a high level at timing T9, and immediately thereafter, from timing T10, supplies a high-level selection signal S4 to all rows over a pulse period. At this time, since only the conversion efficiency control transistor 362 is in the on state, the signal level generated by MCG is maintained. This signal level is an example of the second signal level described in the claims.

[0109] The vertical scanning circuit 211 then sets the control signal FCG for all rows to a high level at timing T11, and immediately thereafter, at timing T12, supplies a high-level selection signal S6 to all rows over a pulse period. At this time, because both the conversion efficiency control transistors 361 and 362 are on, the signal level generated by LCG is maintained. This signal level is an example of the third signal level described in the claims.

[0110] The vertical scanning circuit 211 then supplies a high-level control signal FLG to all rows over a pulse period starting from timing T13, and supplies a high-level selection signal S5 to all rows over a pulse period starting from timing T14. At this time, both the conversion efficiency control transistors 361 and 362 are on, so the reset level generated by the LCG is maintained. This reset level is an example of the third reset level described in the claims.

[0111] Then, at timing T15, the vertical scanning circuit 211 sets the reset signal RST and the control signal FCG of all rows to low level, and sets the switching signal SW of all rows to high level.

[0112] Furthermore, at timing T15, the vertical scanning circuit 211 stops supplying the current id1 to all pixels and starts supplying the current id2 to all columns.

[0113] 11 is a timing chart showing an example of a readout operation according to the first embodiment of the present technology. During a readout period for the n-th row from timing T20 to timing T32, the vertical scanning circuit 211 sets the selection signal SEL for the n-th row to high level.

[0114] From timing T20 through a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T21 through a pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S1 to the n-th row. Then, the P-phase level (reset level) generated by the HCG is read out.

[0115] From timing T22 through a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T23 through a pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S2 to the n-th row. Then, the D-phase level (signal level) generated by the HCG is read out.

[0116] From timing T24 through a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T25 through a pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S3 to the n-th row. Then, the reset level generated by the MCG is read out.

[0117] From timing T26 through a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T27 through a pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S4 to the n-th row. Then, the signal level generated by the MCG is read out.

[0118] From timing T28 through the pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T29 through the pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S5 to the n-th row. Then, the reset level generated by the LCG is read out.

[0119] From timing T30 through a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row, and from timing T31 through a pulse period, the vertical scanning circuit 211 supplies a high-level selection signal S6 to the n-th row. Then, the signal level generated by the LCG is read out.

[0120] During the readout period, the vertical scanning circuit 211 also sets the switching signals SW for all rows to high level, stopping the current id1 for all pixels and supplying the current id2 for all columns.

[0121] The read order is not limited to that shown in the figure.

[0122] As described above, according to the second embodiment of the present technology, the conversion efficiency control transistor 362, the capacitance elements 325 and 326, and the selection transistors 335 and 336 are added, so that the conversion efficiency can be switched between three stages.

[0123] <3. Third Embodiment> In the second embodiment described above, one end of each of the six capacitance elements is connected to the preceding node 320, and the selection circuit 330 connects one of the other ends to the subsequent node 340. However, the circuit for sampling and holding a signal is not limited to this circuit configuration. The image sensor 200 in this third embodiment differs from the second embodiment in that the circuit configurations of the capacitance elements and the selection circuit 330 are different.

[0124] 12 is a circuit diagram showing a configuration example of a pixel 300 according to a third embodiment of the present technology. In this third embodiment, a selection circuit 330 connects one end of any of capacitance elements 321, 322, 323, 324, 325, and 326 to a previous-stage node 320. The other end of each of capacitance elements 321, 322, 323, 324, 325, and 326 is grounded. A subsequent-stage reset transistor 341 is inserted between the previous-stage node 320 and a power supply voltage VDD.

[0125] In the selection circuit 330, the selection transistor 331 opens and closes the path between the capacitive element 321 and the previous node 320 in accordance with a selection signal S1. The selection transistor 332 opens and closes the path between the capacitive element 322 and the previous node 320 in accordance with a selection signal S2. The selection transistor 333 opens and closes the path between the capacitive element 323 and the previous node 320 in accordance with a selection signal S3, and the selection transistor 334 opens and closes the path between the capacitive element 324 and the previous node 320 in accordance with a selection signal S4. The selection transistor 335 opens and closes the path between the capacitive element 325 and the previous node 320 in accordance with a selection signal S5, and the selection transistor 336 opens and closes the path between the capacitive element 326 and the previous node 320 in accordance with a selection signal S6.

[0126] The method of driving the pixel 300 in the third embodiment is the same as that in the second embodiment.

[0127] Although the conversion efficiency is set to three stages, it can also be set to four or more stages. To set it to four or more stages, it is sufficient to add a conversion efficiency control transistor, a capacitance element, or a selection transistor according to the number of stages. The conversion efficiency can also be set to two stages. When set to two stages, the conversion efficiency control transistor 362, the capacitance elements 325 and 326, and the selection transistors 335 and 336 are eliminated.

[0128] As described above, according to the third embodiment of the present technology, the selection circuit 330 connects any one of the six capacitance elements to the previous node 320, and the other ends of the capacitance elements are grounded, thereby making it possible to hold reset levels and signal levels corresponding to each of the multi-stage conversion efficiencies.

[0129] <4. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0130] FIG. 13 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0131] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 13, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0132] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0133] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0134] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0135] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0136] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0137] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0138] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0139] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0140] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 13, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0141] FIG. 14 is a diagram showing an example of the installation position of the imaging unit 12031.

[0142] In FIG. 14, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0143] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0144] 14 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0145] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0146] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0147] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0148] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0149] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, for example, the image capturing device 100 of FIG. 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue. Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0150] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0151] The present technology can also be configured as follows. (1) a conversion efficiency control transistor that opens and closes a path between the FD and the additional capacitance; a drain transistor that drains charges from the photoelectric conversion element; a reset transistor inserted between a power supply voltage and the drain transistor; a transfer transistor that transfers charges from the photoelectric conversion element to the FD; an FD link gate transistor that opens and closes a path between a connection point of the additional capacitance and the conversion efficiency control transistor and a connection point of the reset transistor and the drain transistor; a plurality of capacitance elements that hold a level according to the voltage of the FD; An image sensor comprising: (2) the level includes a reset level when the FD is initialized and a signal level when the charge is transferred to the FD; the reset level includes a first reset level when the conversion efficiency control transistor is in an off state and a second reset level when the conversion efficiency control transistor is in an on state; the signal level includes a first signal level when the conversion efficiency control transistor is in an off state and a second signal level when the conversion efficiency control transistor is in an on state; The plurality of capacitive elements include a first capacitive element that holds the first reset level, a second capacitive element that holds the first signal level, a third capacitive element that holds the second reset level, and a fourth capacitive element that holds the second signal level. The image sensor according to (1) above. (3) the conversion efficiency control transistor includes first and second conversion efficiency control transistors connected in series; The level includes a reset level when the FD is initialized and a signal level when the charge is transferred to the FD, the reset levels include a first reset level when both the first and second conversion efficiency control transistors are in an off state, a second reset level when only one of the first and second conversion efficiency control transistors is in an on state, and a third reset level when both the first and second conversion efficiency control transistors are in an on state; the signal levels include a first signal level when both the first and second conversion efficiency control transistors are in an off state, a second signal level when only one of the first and second conversion efficiency control transistors is in an on state, and a third signal level when both the first and second conversion efficiency control transistors are in an on state; The plurality of capacitive elements include a first capacitive element that holds the first reset level, a second capacitive element that holds the first signal level, a third capacitive element that holds the second reset level, a fourth capacitive element that holds the second signal level, a fifth capacitive element that holds the third reset level, and a sixth capacitive element that holds the third signal level. The image sensor according to (1) above. (4) a pre-amplifying transistor that outputs the level to a pre-node to which one end of each of the plurality of capacitive elements is commonly connected; a selection circuit that connects the other end of any one of the plurality of capacitance elements to a predetermined subsequent node; The image sensor according to any one of (1) to (3) above, further comprising: (5) a pre-amplification transistor that outputs the level to a predetermined node; a selection circuit that connects one end of any one of the plurality of capacitance elements to the node; Further comprising: The other end of each of the plurality of capacitance elements is grounded. The image sensor according to any one of (1) to (3). (6) further comprising a vertical scanning circuit; Immediately after turning on the transfer transistor to transfer the charge, the vertical scanning circuit turns off the FD link gate transistor and turns on the reset transistor and the discharge transistor. The image sensor according to any one of (1) to (5). (7) the conversion efficiency control transistor, the reset transistor, the drain transistor, the transfer transistor, and the FD link gate transistor are arranged on a predetermined pixel chip; The plurality of capacitive elements are disposed on a predetermined circuit chip. The image sensor according to any one of (1) to (6). (8) A conversion efficiency control transistor that opens and closes a path between the FD and the additional capacitance; a drain transistor that drains charges from the photoelectric conversion element; a reset transistor inserted between a power supply voltage and the drain transistor; a transfer transistor that transfers charges from the photoelectric conversion element to the FD; an FD link gate transistor that opens and closes a path between a connection point of the additional capacitance and the conversion efficiency control transistor and a connection point of the reset transistor and the drain transistor; A plurality of capacitance elements that hold a level according to the voltage of the FD; a signal processing circuit that processes a signal of said level; A light detection device comprising: [Explanation of symbols]

[0152] 100 Imaging device 110 Imaging lens 120 Storage section 130 Imaging control unit 200 image sensors 201 pixel chip 202 Circuit Chip 211 Vertical scanning circuit 212 Timing control circuit 213 DAC 220 Pixel array section 250 Load MOS circuit block 251 Load MOS transistor 260 Column signal processing circuit 261 ADC 262 Digital Signal Processing Unit 300 pixels 310 Front stage circuit 311 Photoelectric conversion element 312 Transfer transistor 313 Reset Transistor 314FD 315 Preamplifier Transistor 316 Current Source Transistor 317 Emission Transistor 320 Previous Node 321, 322, 323, 324, 325, 326 Capacitor elements 329 Switching Transistor 330 Selection circuit 331, 332, 333, 334, 335, 336 Select transistors 340 Backward Node 341 Post-stage reset transistor 350 Post-stage circuit 351 Post-amplification transistor 352 Select Transistor 361, 362 Conversion efficiency control transistor 363 FD link gate transistor 365 additional capacity 12031 Imaging unit

Claims

1. a conversion efficiency control transistor that opens and closes a path between the FD (Floating Diffusion) and the additional capacitance; a drain transistor that drains charges from the photoelectric conversion element; a reset transistor inserted between a power supply voltage and the drain transistor; a transfer transistor that transfers charges from the photoelectric conversion element to the FD; an FD link gate transistor that opens and closes a path between a connection point of the additional capacitance and the conversion efficiency control transistor and a connection point of the reset transistor and the drain transistor; a plurality of capacitance elements that hold a level according to the voltage of the FD; An image sensor comprising:

2. the level includes a reset level when the FD is initialized and a signal level when the charge is transferred to the FD, the reset level includes a first reset level when the conversion efficiency control transistor is in an off state and a second reset level when the conversion efficiency control transistor is in an on state; the signal level includes a first signal level when the conversion efficiency control transistor is in an off state and a second signal level when the conversion efficiency control transistor is in an on state; The plurality of capacitive elements include a first capacitive element that holds the first reset level, a second capacitive element that holds the first signal level, a third capacitive element that holds the second reset level, and a fourth capacitive element that holds the second signal level.

2. The image sensor of claim 1.

3. the conversion efficiency control transistor includes first and second conversion efficiency control transistors connected in series; the level includes a reset level when the FD is initialized and a signal level when the charge is transferred to the FD, the reset levels include a first reset level when both the first and second conversion efficiency control transistors are in an off state, a second reset level when only one of the first and second conversion efficiency control transistors is in an on state, and a third reset level when both the first and second conversion efficiency control transistors are in an on state; the signal levels include a first signal level when both the first and second conversion efficiency control transistors are in an off state, a second signal level when only one of the first and second conversion efficiency control transistors is in an on state, and a third signal level when both the first and second conversion efficiency control transistors are in an on state; The plurality of capacitive elements include a first capacitive element that holds the first reset level, a second capacitive element that holds the first signal level, a third capacitive element that holds the second reset level, a fourth capacitive element that holds the second signal level, a fifth capacitive element that holds the third reset level, and a sixth capacitive element that holds the third signal level.

2. The image sensor of claim 1.

4. a front-stage amplifying transistor that outputs the level to a front-stage node to which one ends of the plurality of capacitive elements are commonly connected; a selection circuit that connects the other end of any one of the plurality of capacitance elements to a predetermined subsequent node; 10. The image sensor of claim 1, further comprising:

5. a pre-amplifying transistor that outputs the level to a predetermined node; a selection circuit that connects one end of any one of the plurality of capacitance elements to the node; Further comprising: The other end of each of the plurality of capacitance elements is grounded.

2. The image sensor of claim 1.

6. further comprising a vertical scanning circuit; Immediately after turning on the transfer transistor to transfer the charge, the vertical scanning circuit turns off the FD link gate transistor and turns on the reset transistor and the discharge transistor.

2. The image sensor of claim 1.

7. the conversion efficiency control transistor, the reset transistor, the drain transistor, the transfer transistor, and the FD link gate transistor are disposed on a predetermined pixel chip, The plurality of capacitive elements are disposed on a predetermined circuit chip.

2. The image sensor of claim 1.

8. a conversion efficiency control transistor that opens and closes a path between the FD and the additional capacitance; a drain transistor that drains charges from the photoelectric conversion element; a reset transistor inserted between a power supply voltage and the drain transistor; a transfer transistor that transfers charges from the photoelectric conversion element to the FD; an FD link gate transistor that opens and closes a path between a connection point of the additional capacitance and the conversion efficiency control transistor and a connection point of the reset transistor and the drain transistor; a plurality of capacitance elements that hold a level according to the voltage of the FD; a signal processing circuit that processes a signal of said level; A light detection device comprising:

Images