Manufacturing method of semiconductor device and manufacturing method of semiconductor package

Abstract

To reduce fillets.SOLUTION: A manufacturing method of a semiconductor device includes: a stacking step of disposing an adhesive layer 9 on a first base material surface 7a of a base material layer 7; a dicing step of cutting the base material layer 7 by dicing to manufacture a plurality of adhesive-attached semiconductor chips 200 in which an adhesive 6A is disposed on a first chip surface 5a of a semiconductor chip 5, and a bonding step of bonding the adhesive-attached semiconductor chips 200 to a base body 1. In the stacking step, the adhesive layer 9 is formed so that the adhesive layer 9 is not disposed on at least a part of an edge part of a chip scheduled region 7b to be the semiconductor chip 5 by the dicing step on the first base material surface 7a.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a method for manufacturing a semiconductor package. [Background technology]

[0002] Patent Document 1 describes a method for manufacturing a semiconductor device in which an adhesive-coated semiconductor chip, in which an adhesive is laminated on a first chip surface of the semiconductor chip, is thermocompression-bonded to a base. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6483500 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when a semiconductor chip with adhesive is thermocompression bonded to a substrate, a portion of the adhesive protrudes from between the semiconductor chip and the substrate, forming a fillet that protrudes from between the semiconductor chip and the substrate. The fillet is a portion of the adhesive that protrudes from between the semiconductor chip and the substrate. If the protruding length of the fillet increases, the semiconductor chip becomes more susceptible to breakage due to the fillet. For this reason, there is a demand for reducing the fillet.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device and a method for manufacturing a semiconductor package that can reduce fillets. [Means for solving the problem]

[0006] [1] The method for manufacturing a semiconductor device according to the present disclosure includes a lamination step of placing an adhesive layer on a first substrate surface of a substrate layer, a dicing step of cutting the substrate layer by dicing to produce a plurality of adhesive-attached semiconductor chips, each having an adhesive placed on its first chip surface, and a bonding step of bonding the adhesive-attached semiconductor chips to a base, wherein in the lamination step, the adhesive layer is formed so that the adhesive layer is not placed on at least a portion of the edge of the chip-planned area on the first substrate surface that will become the semiconductor chip by the dicing step.

[0007] In this semiconductor device manufacturing method, the substrate layer is cut by dicing to produce multiple adhesive-backed semiconductor chips, and the adhesive-backed semiconductor chips are bonded to a substrate, thereby manufacturing a semiconductor device in which the semiconductor chips are bonded to the substrate. In the stacking process, the adhesive layer is formed so that it is not disposed on at least a portion of the edge of the chip-prepared region on the first substrate surface, thereby preventing the adhesive from being disposed on at least a portion of the edge of the first chip surface of the semiconductor chip. This reduces the amount of adhesive that protrudes from between the semiconductor chip and the substrate when bonding the adhesive-backed semiconductor chip to the substrate, thereby reducing fillets.

[0008] [2] In the method for manufacturing a semiconductor device according to [1], in the laminating step, the adhesive layer may be formed so as not to be positioned at the center of each side of the chip-planned region on the first substrate surface. In this method for manufacturing a semiconductor device, by forming the adhesive layer so as not to be positioned at the center of each side of the chip-planned region on the first substrate surface, it is possible to reduce the maximum protrusion amount of the fillet.

[0009] [3] In the method for manufacturing a semiconductor device according to [1] or [2], in the laminating step, an adhesive layer may be formed on the first substrate surface so that the adhesive layer is disposed at the four corners of the chip-planned region. In this method for manufacturing a semiconductor device, by forming the adhesive layer on the first substrate surface so that the adhesive layer is disposed at the four corners of the chip-planned region, it is possible to prevent the four corners of the semiconductor chip from being unglued and floating.

[0010] [4] In the method for manufacturing a semiconductor device according to any one of [1] to [3], in the laminating step, the adhesive layer may be formed so as not to be positioned on the four sides of the chip-planned region on the first base material surface. In this method for manufacturing a semiconductor device, by forming the adhesive layer so as not to be positioned on the four sides of the chip-planned region on the first base material surface, it is possible to reduce the amount of adhesive that protrudes from the four sides of the semiconductor chip.

[0011] [5] In the method for manufacturing a semiconductor device according to any one of [1] to [4], the laminating step may include a disposing step of disposing an adhesive layer on the first substrate surface, and a removing step of removing a portion of the adhesive layer from the first substrate surface. In this method for manufacturing a semiconductor device, after disposing the adhesive layer on the first substrate surface, the portion of the adhesive layer is removed from the first substrate surface, so that the adhesive layer is formed so as not to be disposed on at least a portion of the edge of the chip-planned region on the first substrate surface.

[0012] [6] In the method for manufacturing a semiconductor device according to [5], the removing step may include irradiating a portion of the adhesive layer with a laser to remove the portion of the adhesive layer from the first substrate surface. In this method for manufacturing a semiconductor device, irradiating a portion of the adhesive layer with a laser can easily remove the portion of the adhesive layer from the first substrate surface.

[0013] [7] In the method for manufacturing a semiconductor device according to [5], the removing step may include irradiating a portion of the adhesive layer with plasma to remove the portion of the adhesive layer from the surface of the first substrate. In this method for manufacturing a semiconductor device, irradiating a portion of the adhesive layer with plasma makes it possible to easily remove the portion of the adhesive layer from the surface of the first substrate.

[0014] [8] In the method for manufacturing a semiconductor device described in [5], the adhesive layer may be photosensitive, and in the removing step, a portion of the adhesive layer may be exposed to light using a photomask and then developed to remove the portion of the adhesive layer from the surface of the first substrate. In this method for manufacturing a semiconductor device, a portion of the photosensitive adhesive layer may be exposed to light using a photomask and then developed to easily remove the portion of the adhesive layer from the surface of the first substrate.

[0015] [9] In the method for manufacturing a semiconductor device according to any one of [1] to [4], the laminating step may include a molding step of molding the adhesive layer into a shape such that when the adhesive layer is disposed on the first substrate surface, the adhesive layer is not disposed on a part of the first substrate surface, and an arranging step of arranging the adhesive layer molded in the molding step on the first substrate surface. In this method for manufacturing a semiconductor device, by molding the adhesive layer into a shape such that when the adhesive layer is disposed on the first substrate surface, the adhesive layer is not disposed on a part of the first substrate surface, and then arranging the adhesive layer on the first substrate surface, the adhesive layer can be formed so that the adhesive layer is not disposed on at least a part of the edge of the chip-planned region on the first substrate surface.

[0016]

[10] A method for manufacturing a semiconductor package according to the present disclosure includes an encapsulation step of manufacturing a semiconductor package by covering with an encapsulant the semiconductor chip of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of [1] to [9]. In this method for manufacturing a semiconductor package, fillets can be reduced because the semiconductor package is manufactured by covering with an encapsulant the semiconductor chip of a semiconductor device manufactured by the method for manufacturing a semiconductor device described above. [Effects of the Invention]

[0017] According to the present disclosure, fillets can be reduced. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a cross-sectional view schematically illustrating an example of a semiconductor package manufactured by the semiconductor package manufacturing method of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 3] FIG. 3 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 4] FIG. 4 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 5] FIG. 5 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 7] FIG. 7 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 8] FIG. 8 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 10] FIG. 10 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 11] FIG. 11 is a cross-sectional view schematically showing one step of the method for manufacturing a semiconductor package according to the present disclosure. [Figure 12] FIG. 12 is a plan view schematically showing an example of a chip-planned region after the stacking step. [Figure 13] FIG. 13 is a plan view schematically showing an example of a chip-planned region after the stacking step. [Figure 14]FIG. 14 is a plan view schematically showing an example of a chip-planned region after the stacking step. [Figure 15] FIG. 15 is a cross-sectional view schematically showing one step of a manufacturing method for a semiconductor package according to a modified example. [Figure 16] FIG. 16 is a cross-sectional view schematically showing one step of a manufacturing method for a semiconductor package according to a modified example. [Figure 17] FIG. 17(a) is a photograph of Comparative Example 1 taken before dicing, and FIG. 17(b) is a photograph of Comparative Example 1 taken after dicing. [Figure 18] FIG. 18 is a photograph of Comparative Example 1 after bonding. [Figure 19] FIG. 19(a) is a photograph of Example 1 taken before dicing, and FIG. 19(b) is a photograph of Example 1 taken after dicing. [Figure 20] FIG. 20 is a photograph of Example 1 after bonding. [Figure 21] FIG. 21 is a graph showing the measurement results of Comparative Example 1 and Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following description, identical or equivalent parts will be designated by the same reference numerals, and duplicate explanations will be omitted. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0020] In this specification, the term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed on a portion of the surface. Furthermore, in this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. Furthermore, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively.

[0021] <Semiconductor package> Fig. 1 is a cross-sectional view schematically illustrating an example of a semiconductor package manufactured by the semiconductor package manufacturing method of the present disclosure. The semiconductor package 100 shown in Fig. 1 includes a base 1, a semiconductor element 2 provided on a mounting surface 1a of the base 1, and an encapsulant 3 that encapsulates the semiconductor element 2 on the mounting surface 1a of the base 1.

[0022] The semiconductor package 100 is a semiconductor device (semiconductor package) such as a processor or a memory. The processor may be a processor unit such as a GPU (Graphics Processing Unit) or a CPU (Central Processing Unit). The memory may be a memory unit such as an HBM (High Bandwidth Memory).

[0023] The base 1 is composed of, for example, a circuit board having a main body and a circuit part provided on the surface of the main body. Examples of the circuit part include a circuit pattern and an interposer. The base 1 may be a semiconductor wafer. The semiconductor wafer is, for example, a thin semiconductor wafer having a thickness of 50 to 700 μm. The semiconductor wafer may be made of single crystal silicon, polycrystalline silicon, various ceramics, or a compound semiconductor such as gallium arsenide. From the viewpoint of suppressing warpage, the thickness of the base 1 may be, for example, 50 to 500 μm, or may be 200 to 900 μm.

[0024] The semiconductor element 2 is formed by stacking multiple semiconductor chips 4 with adhesive layers in a direction away from the mounting surface 1a. The semiconductor chip 4 with adhesive layers includes a semiconductor chip 5 and an adhesive layer 6 disposed on a first chip surface 5a of the semiconductor chip 5 facing the base 1. The first chip surface 5a is one of the front and back surfaces of the semiconductor chip 5. The adhesive layer 6 is formed by curing an adhesive containing a thermosetting resin. The base 1 and the semiconductor chips 5 are electrically connected to each other, and the semiconductor chips 5 are also electrically connected to each other. The semiconductor chips 5 have, for example, through electrodes, which enable electrical connection between the semiconductor chips 5.

[0025] <Semiconductor package manufacturing method> Next, a method for manufacturing the above-described semiconductor package 100 will be described.

[0026] 2 to 11 are cross-sectional views schematically illustrating a series of steps in the method for manufacturing a semiconductor package according to the present disclosure. As shown in FIGS. 2 to 11, the method for manufacturing a semiconductor package according to the present disclosure includes, in this order, a base layer preparation step of preparing a base layer 7, a lamination step of arranging an adhesive layer 9 on a first base surface 7a of the base layer 7, a dicing step of dicing the base layer 7 to produce a plurality of adhesive-attached semiconductor chips 200, a bonding step of bonding the adhesive-attached semiconductor chips 200 to a base 1, and a package fabrication step of covering, with an encapsulant 3, the semiconductor chip 5 of the semiconductor device 300 in which the adhesive-attached semiconductor chip 200 is bonded to the base 1, to produce a semiconductor package 100. The first base surface 7a is one of the front and back surfaces of the base layer 7.

[0027] As shown in FIG. 2, in the base layer preparation step, for example, the base layer 7 is attached to and fixed on a dicing tape 8.

[0028] As shown in FIGS. 3 and 4, the lamination step includes a placement step and a removal step, which are carried out in this order.

[0029] As shown in FIG. 3, in the placement step, an adhesive layer 9 made of an adhesive for forming the adhesive layer 6 is placed on a first base material surface 7a of a base material layer 7 for forming the semiconductor chip 5.

[0030] The substrate layer 7 is diced into individual pieces to form the semiconductor chips 5 in a subsequent dicing process. The substrate layer 7 includes, for example, a main body portion and connection portions provided on the first substrate surface 7a side (adhesive layer 9 side) or both sides of the main body portion. When the substrate layer 7 has connection portions on both sides of the main body portion, the substrate layer 7 may have through electrodes that electrically connect the connection portions on both sides. The main body portion of the substrate layer 7 is made of, for example, a semiconductor wafer. The connection portions are made of, for example, bumps. The bump material mainly contains, for example, a metal such as gold, silver, copper, solder (main component of which is, for example, tin-silver, tin-lead, tin-bismuth, tin-copper, tin-silver-copper), tin, or nickel. The bump may be made of only a single component, or may be made of multiple components. The bump may have a structure in which these metals are laminated.

[0031] The adhesive layer 9 may be either non-conductive or conductive. The adhesive constituting the adhesive layer 9 may be any adhesive containing a thermosetting resin. The thermosetting resin is not particularly limited as long as it is a resin that hardens when heated, and may include, for example, an epoxy resin and a resin that can act as a curing agent for the epoxy resin. The adhesive may further contain a high molecular weight component, an inorganic filler, a coupling agent, a curing accelerator, etc. Note that when the adhesive layer 9 is non-conductive, the adhesive may further contain a fluxing agent.

[0032] Here, the region of the base material layer 7 that will become the semiconductor chip 5 in a subsequent dicing process is referred to as the chip planned region 7b. The chip planned region 7b on the first base material surface 7a has a rectangular shape. In the placement process, an adhesive layer 9 is placed over the entire surface of the chip planned region 7b on the first base material surface 7a.

[0033] The adhesive layer 9 can be formed by either applying a varnish of an adhesive composition containing an adhesive and a solvent onto the base layer 7 and heating and drying it, or by attaching an adhesive film containing an adhesive onto the base layer 7.

[0034] 4, in the removing step, a portion of the adhesive layer 9 is removed from the first substrate surface 7a of the base layer 7, thereby forming the adhesive layer 9 so that the adhesive layer 9 is not disposed on at least a portion of the edge of the chip-intended region 7b on the first substrate surface 7a. In other words, at least a portion of the edge of the chip-intended region 7b on the first substrate surface 7a is exposed from the adhesive layer 9. The region of the chip-intended region 7b on the first substrate surface 7a where the adhesive layer 9 is not disposed is referred to as an adhesive layer-free region 7c. The adhesive layer-free region 7c is located on at least a portion of the edge of the chip-intended region 7b on the first substrate surface 7a.

[0035] 12 to 14 are plan views schematically showing examples of the chip-planned region after the lamination step. In the removal step, as shown in Fig. 12 to 14, by removing a portion of the adhesive layer 9 from the first base material surface 7a of the base material layer 7, the adhesive layer 9 may be formed so that the adhesive layer 9 is not positioned in the center of each side of the chip-planned region 7b on the first base material surface 7a. In other words, the center of each side of the chip-planned region 7b on the first base material surface 7a may be left as an adhesive layer-free region 7c.

[0036] 12, the adhesive layer 9 may be formed so that the adhesive layer 9 is not disposed on the four sides of the chip planned region 7b on the first base material surface 7a. In other words, the four sides of the chip planned region 7b on the first base material surface 7a may be formed as adhesive layer-free regions 7c.

[0037] 13, the adhesive layer 9 may be formed so that the adhesive layer 9 is disposed at the four corners of the chip planned region 7b on the first base material surface 7a. In other words, no adhesive layer-free region 7c may be provided at the four corners of the chip planned region 7b on the first base material surface 7a.

[0038] As shown in FIG. 14, the adhesive layer 9 may be formed so that the width of the adhesive layer-free region 7c increases from the edge of each side of the chip-prepared region 7b toward the center on the first substrate surface 7a.

[0039] 4, the maximum width W of the adhesive-free region 7c is not particularly limited, but is, for example, 10 μm to 500 μm, preferably 20 μm to 400 μm, and more preferably 30 μm to 300 μm. The width of the adhesive-free region 7c is the length from each side of the chip-intended region 7b on the first substrate surface 7a.

[0040] The method for removing a portion of the adhesive layer 9 from the first substrate surface 7a is not particularly limited. For example, the method may be a laser method in which a portion of the adhesive layer 9 is irradiated with laser light, a plasma method in which a portion of the adhesive layer 9 is irradiated with plasma through a mask, or a photolithography method in which a photosensitive adhesive layer 9 is used, a portion of the adhesive layer is exposed to light using a photomask, and then the adhesive is developed.

[0041] In the laser method, a laser beam is irradiated onto a portion of the first substrate surface 7a from which the adhesive layer 9 is to be removed, thereby removing the adhesive layer 9 at the portion irradiated with the laser beam. This allows a portion of the adhesive layer 9 to be removed from the first substrate surface 7a.

[0042] In the plasma method, the adhesive layer 9 is irradiated with plasma through a mask having openings corresponding to the areas where the adhesive layer 9 is to be removed, thereby removing the areas of the adhesive layer 9 irradiated with plasma. This allows a portion of the adhesive layer 9 to be removed from the first substrate surface 7a.

[0043] In the photolithography method, a photosensitive adhesive layer 9 is used, and the adhesive layer is irradiated with light such as UV light through a mask with openings in the areas where the adhesive layer 9 is to be removed. The adhesive is then developed, and the adhesive layer 9 in the areas irradiated with light can be removed. This allows a portion of the adhesive layer 9 to be removed from the first substrate surface 7a.

[0044] As shown in FIG. 5, in the dicing step, the base material layer 7 is cut by dicing to produce a plurality of adhesive-attached semiconductor chips 200, each having an adhesive 6A disposed on the first chip surface 5a of the semiconductor chip 5. The semiconductor chips 5 and adhesive 6A are formed by dividing the base material layer 7 and adhesive layer 9 into individual pieces. Dicing can be performed by, for example, blade dicing, laser dicing, or stealth dicing. In this way, the adhesive-attached semiconductor chips 200 are obtained. The adhesive-attached semiconductor chips 200 include the semiconductor chip 5 and the adhesive 6A disposed on the first chip surface 5a of the semiconductor chip 5 (see FIG. 6).

[0045] The semiconductor chip 5 of the adhesive-attached semiconductor chip 200 obtained in the dicing process is obtained by cutting the base material layer 7, and like the base material layer 7, has a main body portion and connection portions provided on one side (adhesive side) or both sides of the main body portion. When the semiconductor chip 5 has connection portions on both sides of the main body portion, the semiconductor chip 5 may have through electrodes that electrically connect the connection portions on both sides. The main body portion of the semiconductor chip 5 is a portion obtained by cutting the main body portion of the base material layer 7. The connection portions are composed of, for example, bumps. The material of the bumps mainly contains, for example, metals such as gold, silver, copper, solder (main component being, for example, tin-silver, tin-lead, tin-bismuth, tin-copper, tin-silver-copper), tin, and nickel. The bumps may be composed of only a single component or multiple components. The bumps may have a structure in which these metals are laminated.

[0046] Here, in the previous lamination process, the adhesive layer 9 is formed so that the adhesive layer 9 is not disposed on at least a portion of the edge of the chip-intended region 7b on the first substrate surface 7a. Therefore, in the adhesive-attached semiconductor chip 200, the adhesive 6A is not disposed on at least a portion of the edge of the first chip surface 5a of the semiconductor chip 5. In other words, at least a portion of the edge of the first chip surface 5a of the semiconductor chip 5 is exposed from the adhesive 6A. Therefore, an adhesive-free region 5b corresponding to the adhesive-free region 7c is formed on the first chip surface 5a. The adhesive-free region 5b is an area of ​​the first chip surface 5a where the adhesive 6A is not disposed, and is located on at least a portion of the edge of the first chip surface 5a.

[0047] As shown in FIG. 6, in the bonding process, first, the adhesive-attached semiconductor chip 200 is picked up using a pickup tool P (pickup process). The pickup tool P is a device that picks up the adhesive-attached semiconductor chip 200. After the dicing process, the dicing tape 8 may be expanded before the adhesive-attached semiconductor chip 200 is picked up (expanding process). After the expanding process, the adhesive-attached semiconductor chip 200 may be pushed upward from the back surface side of the dicing tape 8 by a push-up tool A. Furthermore, a heat shrinking process may be further performed after the expanding process and before the pick-up process. The pickup tool P is a device that picks up the adhesive-attached semiconductor chip 200.

[0048] As shown in FIG. 7, in the bonding process, the picked-up adhesive-backed semiconductor chip 200 is then transferred from the pickup tool P to a bonding tool B. The transfer of the adhesive-backed semiconductor chip 200 can be performed, for example, as follows. First, the pickup tool P is rotated so that the attachment part P1 faces upward, thereby placing the picked-up adhesive-backed semiconductor chip 200 facing upward. Then, the bonding tool B is attached to the upper side of the adhesive-backed semiconductor chip 200. Specifically, the attachment part B1 of the bonding tool B is attached to the semiconductor chip 5 of the adhesive-backed semiconductor chip 200. The bonding tool B is a device that has the function of applying heat and pressure to the adhesive-backed semiconductor chip 200.

[0049] As shown in FIG. 8, in the bonding process, next, the adhesive-attached semiconductor chip 200 is placed on the mounting surface 1a of the base 1. Specifically, the adhesive 6A of the adhesive-attached semiconductor chip 200 is brought into contact with the base 1. Then, the adhesive-attached semiconductor chip 200 is heated and pressurized with a bonding tool B to thermocompression bond it to the base 1. When the adhesive-attached semiconductor chip 200 is thermocompression bonded to the base 1 in this way, the adhesive 6A is hardened to form an adhesive layer 6. As a result, the adhesive-attached semiconductor chip 200 becomes an adhesive layer-attached semiconductor chip 4.

[0050] At this time, in the adhesive-attached semiconductor chip 200, the adhesive 6A is sandwiched between the semiconductor chip 5 and the base 1. Therefore, when the adhesive 6A is pressed by the semiconductor chip 5, the adhesive 6A tends to squeeze out from between the semiconductor chip 5 and the base 1. However, since the adhesive 6A is not provided on at least a portion of the edge of the first chip surface 5a of the semiconductor chip 5, and at least a portion of the edge of the first chip surface 5a is an adhesive-free region 5b, the amount of adhesive 6A squeezing out from between the semiconductor chip 5 and the base 1 is reduced. The adhesive 6A squeezing out from between the semiconductor chip 5 and the base 1 is called a fillet F.

[0051] Next, in the same manner as above, a semiconductor chip 200 with adhesive is further stacked on the semiconductor chip 4 with adhesive layer, as shown in Fig. 9. In this way, a plurality of semiconductor chips 4 with adhesive layer are stacked on the base 1, and a semiconductor element 2 consisting of a plurality of semiconductor chips 4 with adhesive layer is mounted (mounting process).

[0052] 10, another semiconductor element 2 is mounted next to the semiconductor element 2 mounted on the base 1 in the same manner as the above semiconductor element 2. Thereafter, if necessary, another semiconductor element 2 is mounted on the base 1. In this way, a semiconductor device 300 is obtained.

[0053] As shown in FIG. 11 and FIG. 1, the sealing process includes a sealing structure forming step and a processing step.

[0054] 11, in the sealing structure forming step, the semiconductor element 2 of the semiconductor device 300 is covered with a sealing material 3 to form a sealing structure 400. The sealing material 3 used in the sealing structure forming step is not particularly limited as long as it is a material that has a sealing function, and examples of the sealing material 3 include resins such as epoxy resins. It is preferable that the sealing material 3 has a higher sealing function than the adhesive layer 6. In this case, the adhesive layer 6 is more sufficiently protected from the intrusion of moisture and oxygen.

[0055] 11 and 1, in the processing step, the sealing structure 400 is processed to manufacture the semiconductor package 100. For example, the sealing structure 400 is cut at the cutting locations 401 to manufacture the semiconductor package 100. In this manner, the semiconductor package 100 is obtained. The method for processing the sealing structure 400 is not particularly limited, but examples of the processing method include dicing. The dicing may be either dicing using a rotary blade or dicing using laser light.

[0056] As described above, in the method for manufacturing a semiconductor device according to the present disclosure, the base layer 7 is cut by dicing to produce a plurality of adhesive-attached semiconductor chips 200, and the adhesive-attached semiconductor chips 200 are bonded to the base 1, thereby manufacturing a semiconductor device 300 in which a semiconductor chip 5 is bonded to the base 1. Then, in the lamination step, the adhesive layer 9 is formed so that it is not disposed on at least a portion of the edge of the chip-intended region 7b on the first base material surface 7a, so that the adhesive 6A is not disposed on at least a portion of the edge of the first chip surface 5a of the semiconductor chip 5. This reduces the amount of adhesive 6A that protrudes from between the semiconductor chip 5 and the base 1 when bonding the adhesive-attached semiconductor chip 200 to the base 1, thereby reducing the fillet F.

[0057] Furthermore, in this semiconductor device manufacturing method, the adhesive layer 9 is formed so that it is not positioned in the center of each side of the chip-planned region 7b on the first substrate surface 7a, thereby reducing the maximum protrusion amount of the fillet F.

[0058] Furthermore, in this semiconductor device manufacturing method, the adhesive layer 9 is formed so that it is positioned at the four corners of the chip-planned area 7b on the first substrate surface 7a, thereby preventing the four corners of the semiconductor chip 5 from floating due to ungluing.

[0059] Furthermore, in this semiconductor device manufacturing method, the adhesive layer 9 is formed so that it is not positioned on the four sides of the chip-planned area 7b on the first substrate surface 7a, thereby reducing the amount of adhesive 6A that protrudes from the four sides of the semiconductor chip 5.

[0060] Furthermore, in this semiconductor device manufacturing method, after placing the adhesive layer 9 on the first substrate surface 7a, a portion of the adhesive layer 9 is removed from the first substrate surface 7a, thereby forming the adhesive layer 9 so that the adhesive layer 9 is not placed on at least a portion of the edge of the chip-planned region 7b on the first substrate surface 7a.

[0061] Furthermore, in this method for manufacturing a semiconductor device, by irradiating a part of the adhesive layer 9 with a laser, the part of the adhesive layer 9 can be easily removed from the first base surface 7a.

[0062] Furthermore, in this method for manufacturing a semiconductor device, by irradiating a portion of adhesive layer 9 with plasma, the portion of adhesive layer 9 can be easily removed from first substrate surface 7a.

[0063] Furthermore, in this semiconductor device manufacturing method, a portion of the photosensitive adhesive layer 9 is exposed using a photomask, and then the adhesive layer 9 is developed, thereby easily removing a portion of the adhesive layer 9 from the first substrate surface 7a.

[0064] In the method for manufacturing a semiconductor package according to the present disclosure, the semiconductor package 100 is manufactured by covering the semiconductor chip 5 of the semiconductor device 300 manufactured by the above-described method for manufacturing a semiconductor device with a sealing material, so that the fillet F can be reduced.

[0065] The present disclosure is not limited to the above-described embodiments, and modifications can be made as appropriate without departing from the spirit of the present disclosure.

[0066] For example, in the lamination step, instead of the arrangement step and removal step in the above embodiment, a molding step and arrangement step described below may be performed in this order.

[0067] 15 and 16 are cross-sectional views schematically showing a step of a manufacturing method of a semiconductor package according to a modified example. As shown in Fig. 15 and 16, the lamination step of the manufacturing method of a semiconductor package according to a modified example includes a molding step of molding the adhesive layer 9 into a shape such that when the adhesive layer 9 is disposed on the first base material surface 7a, the adhesive layer 9 is not disposed in a part of the chip-planned region 7b on the first base material surface 7a, and an arrangement step of arranging the adhesive layer 9 formed in the molding step on the first base material surface 7a.

[0068] 15, in the molding step of the semiconductor package manufacturing method of the modified example, before the adhesive layer 9 is placed on the first base surface 7a, the adhesive layer 9 is molded into the same shape as the adhesive layer 9 from which a portion has been removed in the removing step of the above embodiment. The adhesive layer 9 molded in the molding step can have the same shape as the adhesive layer 9 shown in FIGS. 12 to 14, for example.

[0069] 16 , in the arrangement step of the semiconductor package manufacturing method of the modified example, the adhesive layer 9 formed in the molding step is arranged on the first base material surface 7a, so that the adhesive layer 9 is not arranged on at least a part of the edge of the chip-intended region 7b on the first base material surface 7a, similar to the state in which the removal step of the above embodiment is performed. In other words, at least a part of the edge of the chip-intended region 7b on the first base material surface 7a is exposed from the adhesive layer 9.

[0070] In this modified example of the method for manufacturing a semiconductor device, the adhesive layer 9 is formed into a shape such that when the adhesive layer 9 is placed on the first substrate surface 7a, the adhesive layer 9 is not placed on a portion of the first substrate surface 7a, and then the adhesive layer 9 is placed on the first substrate surface 7a, thereby forming the adhesive layer 9 so that the adhesive layer 9 is not placed on at least a portion of the edge of the chip-planned area 7b on the first substrate surface 7a. [Example]

[0071] Next, examples of the present disclosure will be described, although the present disclosure is not limited to the examples described below.

[0072] (Comparative Example 1) A 12 μm thick adhesive film was laminated onto the bump side of a semiconductor wafer with 12 μm high bumps. A WALTS-TEG WM40-0103JY (Waltz Corporation) was used for the semiconductor wafer. A PN-500 (Resonac Corporation) was used for the adhesive film. The adhesive film was laminated using a vacuum laminator (CV-300, Nikko Materials Co., Ltd.) with a diaphragm temperature of 90°C, a stage temperature of 60°C, a pressure of 0.5 MPa, and a time of 120 seconds.

[0073] Next, the semiconductor wafer was cut by blade dicing to produce multiple adhesive-coated semiconductor chips, each with an adhesive applied to the first chip surface. Blade dicing was performed using a laser saw (DFD6362, manufactured by Disco Corporation) with a ZH05-SD4000-N1-70-DE blade at a rotation speed of 35,000 rpm, a height of 90 μm, and a speed of 20 mm / s. The size of the semiconductor chips was 10 mm long, 8 mm wide, and 50 μm thick.

[0074] Next, the adhesive-attached semiconductor chip was mounted on a substrate having 2.5 μm-high pads by flip-chip bonding, and the width of the fillet protruding from between the semiconductor chip and the substrate was measured. Flip-chip bonding was performed using a flip-chip bonder (FC3000W, manufactured by Toray Engineering Co., Ltd.) with a stage temperature of 70°C, pre-bonding at 100°C / 2 seconds and 60 N, and post-bonding at 100°C / 1 second, 200°C / 5 seconds, 260°C / 5 seconds, and 100°C / 5 seconds and 90 N. The fillet width was measured as the maximum width of the fillet on each side of the semiconductor chip (the maximum protruding length from each side).

[0075] Figure 17(a) shows a photograph taken before blade dicing, Figure 17(b) shows a photograph taken after blade dicing, and Figure 18 shows a photograph taken after mounting. The black cross lines in Figure 17(b) are the cut marks caused by blade dicing. Figure 21 also shows the measured fillet widths. In Figure 21, the average measured fillet widths are shown in a bar graph, and the range of measured fillet widths is indicated by error bars.

[0076] Example 1 The conditions were the same as those of Comparative Example 1, except that before blade dicing, the adhesive film was irradiated with laser light to remove a portion of the adhesive film. The removal of the portion of the adhesive film was performed using a laser saw (DISCO Corporation, DFL7160) with a Type-A laser head, a laser frequency of 100 kHz, a laser output of 0.7 W, a feed rate of 100 mm / s, and a defocus of -0.4 mm. The adhesive film was then removed by performing laser cutting multiple times while shifting the laser light irradiation position from the scribe center, using the scribe center of the semiconductor wafer as a reference. As a result, the edge of the first chip surface of the semiconductor chips separated by blade dicing was exposed with a width of 77 μm.

[0077] Figure 19(a) shows a photograph taken before blade dicing, Figure 19(b) shows a photograph taken after blade dicing, and Figure 20 shows a photograph taken after mounting. The black cross-shaped lines in Figure 19(b) are the cut marks caused by blade dicing. The measured fillet width is shown in Figure 21.

[0078] 18 to 21, in Comparative Example 1, the average fillet width was 138 μm, whereas in Example 1, the average fillet width was 110 μm, which was significantly reduced compared to Comparative Example 1. Furthermore, in Comparative Example 1, there were locations where the fillet width significantly exceeded 150 μm, whereas in Example 1, there were no locations where the fillet width exceeded 150 μm. [Explanation of symbols]

[0079] 1...base, 1a...mounting surface, 2...semiconductor element, 3...encapsulant, 4...semiconductor chip with adhesive layer, 5...semiconductor chip, 5a...first chip surface, 5b...non-adhesive area, 6...adhesive layer, 6A...adhesive, 7...substrate layer, 7a...first substrate surface, 7b...chip intended area, 7c...non-adhesive layer area, 8...dicing tape, 9...adhesive layer, 100...semiconductor package, 200...semiconductor chip with adhesive, 300...semiconductor device, 400...encapsulating structure, 401...cutting point, A...push-up tool, B...bonding tool, B1...mounting portion, F...fillet, P...pick-up tool, P1...mounting portion.

Claims

1. a lamination step of disposing an adhesive layer on a first substrate surface of a substrate layer; a dicing step of cutting the base material layer by dicing to produce a plurality of adhesive-attached semiconductor chips, each having an adhesive disposed on a first chip surface of the semiconductor chip; a bonding step of bonding the adhesive-attached semiconductor chip to a substrate, In the laminating step, the adhesive layer is formed so as not to be disposed on at least a part of an edge portion of a chip-planned region on the first base surface that will become the semiconductor chip by the dicing step. A method for manufacturing a semiconductor device.

2. In the laminating step, the adhesive layer is formed so as not to be positioned at the center of each side of the chip planned region on the first base material surface. The method for manufacturing a semiconductor device according to claim 1 .

3. In the laminating step, the adhesive layer is formed so that the adhesive layer is disposed at four corners of the chip planned region on the first base material surface. The method for manufacturing a semiconductor device according to claim 1 .

4. In the laminating step, the adhesive layer is formed so that the adhesive is not disposed on four sides of the chip planned region on the first base material surface. The method for manufacturing a semiconductor device according to claim 1 .

5. The lamination step includes: a disposing step of disposing the adhesive layer on the first substrate surface; a removing step of removing a portion of the adhesive layer from the first substrate surface, The method for manufacturing a semiconductor device according to claim 1 .

6. In the removing step, a portion of the adhesive layer is removed from the first substrate surface by irradiating the portion of the adhesive layer with a laser. The method for manufacturing a semiconductor device according to claim 5 .

7. In the removing step, a portion of the adhesive layer is removed from the first substrate surface by irradiating the portion of the adhesive layer with plasma. The method for manufacturing a semiconductor device according to claim 5 .

8. the adhesive layer is photosensitive, In the removing step, a portion of the adhesive layer is exposed to light using a photomask, and then the adhesive layer is developed, thereby removing the portion of the adhesive layer from the first substrate surface. The method for manufacturing a semiconductor device according to claim 5 .

9. The lamination step includes: a molding step of molding the adhesive layer into a shape such that when the adhesive layer is disposed on the first substrate surface, the adhesive layer is not disposed on a part of the first substrate surface; and a placement step of placing the adhesive layer formed in the molding step on the first substrate surface. The method for manufacturing a semiconductor device according to claim 1 .

10. a sealing step of manufacturing a semiconductor package by covering the semiconductor chip of the semiconductor device manufactured by the semiconductor device manufacturing method according to any one of claims 1 to 9 with a sealing material, A method for manufacturing semiconductor packages.

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