High frequency power source and plasma processing apparatus

Abstract

To provide a high frequency power source and a plasma processing apparatus that can attain both high efficiency and bandwidth expansion.SOLUTION: A high frequency power source has an amplifier part, an output terminal, an input power part, a first setting part, and a second setting part. The amplifier part comprises a gate terminal, a drain terminal, and a source terminal. The output terminal is electrically connected to the drain terminal. The input power part is electrically connected to the gate terminal, and configured to supply input power to the amplifier part and vary a frequency supplied in a frequency band suppliable for the input power. The first setting part is electrically connected to the gate terminal, and sets a gate bias voltage of the amplifier part. The second setting part is electrically connected to the drain terminal, and sets a drain bias voltage of the amplifier part. The indication part outputs, for each frequency in the frequency band, an indication value for maximum efficiency of the high frequency power output from the output terminal to the input power part, the first setting part, and the second setting part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a high frequency power supply and a plasma processing apparatus. [Background technology]

[0002] Patent Document 1 discloses an EER system comprising: "a phase component extraction means for extracting a phase component of an input high frequency modulated signal; an amplitude component extraction means for extracting an amplitude component of the high frequency modulated signal; a high frequency saturated amplification means for amplifying the phase component signal from the phase component extraction means; a voltage generation means for generating a voltage corresponding to the amplitude component signal from the amplitude component extraction means; a variable attenuation means for adjusting the level of the phase component signal input to the high frequency saturated amplification means; and a control means for adjusting the output voltage of the voltage generation means to obtain a required output level based on input information about the required output level, while controlling the attenuation of the variable attenuation means to obtain an input level at which the high frequency saturated amplification means operates with optimum efficiency for the output voltage." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-140911 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a high frequency power supply and a plasma processing apparatus that can achieve both high efficiency and wide bandwidth. [Means for solving the problem]

[0005] A radio frequency power supply according to one embodiment of the present disclosure includes an amplifier section, an output terminal, an input power section, a first setting section, a second setting section, and an instruction section. The amplifier section includes a gate terminal, a drain terminal, and a source terminal. The output terminal is electrically connected to the drain terminal. The input power section is electrically connected to the gate terminal and is configured to supply input power to the amplifier section and to change the frequency of the input power within a frequency band that can be supplied. The first setting section is electrically connected to the gate terminal and is configured to set a gate bias voltage of the amplifier section. The second setting section is electrically connected to the drain terminal and is configured to set a drain bias voltage of the amplifier section. The instruction section is configured to output, for each frequency within the frequency band, an instruction value to the input power section, the first setting section, and the second setting section that maximizes the efficiency of the radio frequency power output from the output terminal. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to achieve both high efficiency and wide bandwidth. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of the configuration of a plasma processing apparatus according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a block diagram showing an example of the functional configuration of the first high frequency power supply in this embodiment. [Figure 3] FIG. 3 is a block diagram showing an example of connections when setting parameters. [Figure 4] FIG. 4 is a diagram showing an example of a parameter table in this embodiment. [Figure 5] FIG. 5 is a diagram showing an example of a parameter table that focuses on input power Pin that provides maximum efficiency for each frequency. [Figure 6] FIG. 6 is a diagram showing an example of a parameter table that focuses on the power monitor value Pfm that provides maximum efficiency for each frequency. [Figure 7]FIG. 7 is a diagram showing an example of a correction table in this embodiment. [Figure 8] FIG. 8 is a graph showing an example of the relationship between the gate voltage Vg and the efficiency for each drain voltage Vd at the center frequency. [Figure 9] FIG. 9 is a graph showing an example of the relationship between the gate voltage Vg and the output Pout at maximum efficiency for each drain voltage Vd at the center frequency. [Figure 10] FIG. 10 is a graph showing an example of the relationship between the gate voltage Vg and the input power Pin at maximum efficiency for each drain voltage Vd at the center frequency. [Figure 11] FIG. 11 is a graph showing an example of the relationship between input power Pin and efficiency for each drain voltage Vd at the center frequency. [Figure 12] FIG. 12 is a graph showing an example of the relationship between input power Pin and output power Pout for each drain voltage Vd at the center frequency. [Figure 13] FIG. 13 is a graph showing an example of the relationship between the drain voltage Vd and the output Pout at the center frequency when the input power Pin is constant and when the efficiency is at maximum. [Figure 14] FIG. 14 is a graph showing an example of the relationship between the drain voltage Vd and the input power Pin at the center frequency when the input power Pin is constant and when the efficiency is at maximum. [Figure 15] FIG. 15 is a graph showing an example of the relationship between the output Pout and the efficiency when the drain voltage Vd and the input power Pin are varied at the center frequency. [Figure 16] FIG. 16 is a graph showing an example of the relationship between input power Pin and efficiency when the frequency is variable. [Figure 17] FIG. 17 is a graph showing an example of the relationship between frequency and input power Pin. [Figure 18] FIG. 18 is a graph showing an example of the relationship between frequency and maximum efficiency. [Figure 19] FIG. 19 is a graph showing an example of the relationship between the frequency and the output Pout. [Figure 20] FIG. 20 is a graph showing an example of the relationship between the frequency and the initial value of the gate voltage Vg. [Figure 21] FIG. 21 is a graph showing an example of the relationship between the drain voltage Vd and the initial value of the input power Pin for each frequency. [Figure 22] FIG. 22 is a graph showing an example of the relationship between drain voltage Vd and efficiency for each frequency. [Figure 23] FIG. 23 is a diagram showing an example of the relationship between the drain voltage Vd and the efficiency for each frequency. [Figure 24] FIG. 24 is a graph showing an example of the relationship between the drain voltage Vd and the output Pout for each frequency. [Figure 25] FIG. 25 is a graph showing an example of the relationship between the output Pout and the efficiency for each frequency. [Figure 26] FIG. 26 is a flowchart showing an example of the parameter generation process in this embodiment. [Figure 27] FIG. 27 is a flowchart showing an example of the correction value generation process in this embodiment. [Figure 28] FIG. 28 is a flowchart showing an example of the power control process in this embodiment. [Figure 29] FIG. 29 is a flowchart showing an example of the input power adjustment process in this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the disclosed high frequency power supply and plasma processing apparatus will be described in detail with reference to the drawings. Note that the disclosed technology is not limited to the following embodiments.

[0009] In plasma processing equipment, settings such as the output and frequency of an RF (Radio Frequency) power supply may be changed depending on process conditions. For example, if the load impedance of the plasma changes depending on the process conditions, the RF power supply may change its frequency to a frequency appropriate for the load impedance. Furthermore, in RF power supplies, switching amplifiers are sometimes used instead of linear amplifiers to improve the efficiency of RF conversion. However, changing the frequency can reduce the output of the RF power supply and prevent it from reaching its rated output. Furthermore, changing the frequency of a switching amplifier used in an RF power supply can change the operating point at which it achieves maximum efficiency, resulting in a decrease in efficiency. Therefore, there is a need to achieve both a wider adjustable frequency band and high efficiency within that frequency band.

[0010] [Configuration of plasma processing apparatus 1] Fig. 1 is a schematic cross-sectional view showing an example of the configuration of a plasma processing apparatus according to an embodiment of the present disclosure. The plasma processing apparatus 1 shown in Fig. 1 is configured as a plasma processing apparatus using capacitively coupled plasma (CCP). The plasma processing apparatus 1 includes an apparatus main body 10 and a control unit 11 that controls the entire plasma processing apparatus 1. The apparatus main body 10 also includes a substantially cylindrical processing vessel 12, a first high-frequency power supply 60, a second high-frequency power supply 80, and a host controller 90.

[0011] The inner wall surface of processing vessel 12 is made of, for example, anodized aluminum. Processing vessel 12 is safety grounded. A substantially cylindrical support 14 is provided on the bottom of processing vessel 12. Support 14 is made of, for example, an insulating material. Support 14 extends vertically from the bottom of processing vessel 12 within processing vessel 12. A lower electrode 18 that functions as a stage for supporting substrate W is also provided within processing vessel 12. Lower electrode 18 is supported by support 14. Note that a wafer is an example of a substrate W.

[0012] The lower electrode 18 holds the substrate W on its upper surface. The lower electrode 18 includes a first plate 18a and a second plate 18b. The first plate 18a and the second plate 18b are made of a metal such as aluminum and have a substantially disk shape. The second plate 18b is provided on the first plate 18a and is electrically connected to the first plate 18a.

[0013] An electrostatic chuck 19 is provided on the second plate 18b of the lower electrode 18. The electrostatic chuck 19 has a structure in which an electrode, which is a conductive film, is disposed between a pair of insulating layers or insulating sheets. A DC power supply 22 is electrically connected to the electrode of the electrostatic chuck 19 via a switch 23. The electrostatic chuck 19 attracts the substrate W by electrostatic force, such as Coulomb force, generated by a DC voltage from the DC power supply 22. This enables the electrostatic chuck 19 to hold the substrate W.

[0014] A focus ring FR is disposed on the peripheral portion of the second plate 18b of the lower electrode 18 so as to surround the edge of the substrate W and the electrostatic chuck 19. The focus ring FR is provided to improve etching uniformity. The focus ring FR is made of a material appropriately selected depending on the material of the film to be etched, and may be made of quartz, for example. The focus ring FR is an example of an edge ring.

[0015] A coolant flow path 24 is provided inside the second plate 18b. The coolant flow path 24 constitutes a temperature control mechanism. A heat transfer fluid such as brine or gas flows through the coolant flow path 24. For example, a coolant supplied from a chiller unit provided outside the processing chamber 12 circulates through the coolant flow path 24. By controlling the temperature of this coolant, the temperature of the substrate W supported by the electrostatic chuck 19 is controlled. The lower electrode 18 may also include a heat transfer gas supply unit configured to supply a heat transfer gas to a gap between the back surface of the substrate W and the upper surface of the electrostatic chuck 19.

[0016] The apparatus main body 10 also includes an upper electrode 30. The upper electrode 30 is disposed above the lower electrode 18 and faces the lower electrode 18. The lower electrode 18 and the upper electrode 30 are disposed substantially parallel to each other. A processing space S for performing plasma processing on a substrate W is provided between the upper electrode 30 and the lower electrode 18.

[0017] The upper electrode 30 is supported on the upper part of the processing chamber 12 via an insulating shielding member 32. The upper electrode 30 is connected to GND. The upper electrode 30 may include an electrode plate 34 and an electrode support 36. The electrode plate 34 faces the processing space S and has a plurality of gas discharge holes 34a formed therein. The electrode plate 34 is made of, for example, silicon.

[0018] The electrode support 36 detachably supports the electrode plate 34 and may be made of a conductive material such as aluminum. The electrode support 36 may have a water-cooled structure. A gas diffusion chamber 36a is provided inside the electrode support 36. A plurality of gas flow holes 36b extend downward from the gas diffusion chamber 36a and communicate with the gas discharge holes 34a. The electrode support 36 also has a gas inlet 36c formed therein for introducing a process gas into the gas diffusion chamber 36a, and a gas supply pipe 38 is connected to the gas inlet 36c.

[0019] A gas source group 40 is connected to the gas supply pipe 38 via a valve group 42 and a flow rate controller group 44. The gas source group 40 includes multiple gas sources, such as a fluorocarbon gas source, a rare gas (noble gas) source, and an oxygen (O2) gas source. The fluorocarbon gas is, for example, a gas containing at least one of C4F6 gas and C4F8 gas. The rare gas is a gas containing at least one of various rare gases, such as Ar gas and He gas.

[0020] The valve group 42 includes a plurality of valves, and the flow rate controller group 44 includes a plurality of flow rate controllers such as mass flow controllers. The gas sources in the gas source group 40 are each connected to the gas supply pipe 38 via a corresponding valve in the valve group 42 and a corresponding flow rate controller in the flow rate controller group 44.

[0021] An exhaust port 12e is provided at the bottom of the processing vessel 12. An exhaust device 50 is connected to the exhaust port 12e via an exhaust pipe 52. The exhaust device 50 has a vacuum pump such as a turbomolecular pump, and can reduce the pressure inside the processing vessel 12 to a desired vacuum level. In addition, a loading / unloading port 12g for the substrate W is provided on the sidewall of the processing vessel 12, and this loading / unloading port 12g can be opened and closed by a gate valve 54.

[0022] The control unit 11 has a memory, a processor, and an input / output interface. The memory stores programs to be executed by the processor and recipes including conditions for each process. The processor reads the programs from the memory, executes them, and controls each part of the plasma processing apparatus 1 via the input / output interface based on the recipes stored in the memory.

[0023] For example, the control unit 11 controls each unit of the plasma processing apparatus 1 so as to perform a power control method described later. In a detailed example, the control unit 11 controls the set frequency F and the set power P f Based on this, the first high frequency power supply 60 is controlled to read parameters corresponding to the nearby frequency and power from a parameter table that stores the parameters of the amplifier section, which will be described later. The control section 11 determines the set frequency F and set power P from the nearby parameters. f The control unit 11 calculates and sets parameters corresponding to the set frequency F and set power P and controls the first high frequency power supply 60 to start outputting high frequency power. f The control unit 11 controls the first high frequency power supply 60 to read the correction value k corresponding to the nearby frequency and power from the correction table based on the nearby correction value.f The correction value k corresponding to the correction value k and the forward power P fd Based on the power monitor value P fm The control unit 11 controls the first high frequency power supply 60 to calculate the set power P f and the power monitor value P fm The first high frequency power supply 60 is controlled to adjust the parameters of the amplifier unit so that the values ​​of the first high frequency power supply 60 and the second high frequency power supply 60 coincide with each other.

[0024] The first high frequency power supply 60 outputs high frequency power of a specific frequency within the available frequency band. In other words, the first high frequency power supply 60 generates high frequency power for plasma generation. For example, the first high frequency power supply 60 outputs high frequency power of a specific frequency within a frequency band with a center frequency of 220 MHz. The first high frequency power supply 60 receives a set frequency F and set power P of the high frequency power from a host controller 90 (described later). f The high frequency power output from the first high frequency power supply 60 is supplied to the lower electrode 18. Note that the high frequency power output from the first high frequency power supply 60 may be supplied to the upper electrode 30.

[0025] The second high frequency power supply 80 generates a high frequency wave for attracting ions to the substrate W. The second high frequency power supply 80 generates a high frequency wave with a lower frequency than the high frequency wave generated by the first high frequency power supply 60. The second high frequency power supply 80 generates a high frequency wave of, for example, 600 kHz. Hereinafter, to distinguish between the high frequency wave generated by the second high frequency power supply 80 and the high frequency wave generated by the first high frequency power supply 60, the high frequency wave generated by the second high frequency power supply 80 will be referred to as a "bias high frequency wave." The second high frequency power supply 80 is connected to the lower electrode 18 via a matching box 81. The matching box 81 matches the output impedance of the second high frequency power supply 80 with the input impedance on the load side (lower electrode 18 side). The second high frequency power supply 80 and matching box 81 used for the bias high frequency wave may be a first high frequency power supply 60' with a variable frequency that is prepared separately from the first high frequency power supply 60.

[0026] The upper controller 90 is a controller that controls the first high frequency power supply 60 in accordance with instructions from the control unit 11. The upper controller 90 controls the set frequency F and set power P of the high frequency power in accordance with the recipe input from the control unit 11. f to the first high frequency power supply 60. The upper controller 90 also receives a power monitor value P fm The upper controller 90 receives the input power monitor value P fm to the control unit 11. The upper controller 90 may be included in the control unit 11.

[0027] Next, the first high-frequency power supply 60 will be described in detail with reference to FIG. 2. FIG. 2 is a block diagram showing an example of the functional configuration of the first high-frequency power supply in this embodiment. As shown in FIG. 2, the first high-frequency power supply 60 includes a DDS (Direct Digital Synthesizer) 61, a first variable DC (Direct Current) voltage source 62, a preamplifier 63, a second variable DC voltage source 64, a main amplifier 65, a buffer amplifier 66, a directional coupler 67, a detector 68, a buffer amplifier 69, and a control unit 70. The control unit 70 also includes a processing unit 71, a storage unit 72, and an input / output unit 73. The storage unit 72 stores a parameter table and a correction table, which will be described later. The first high-frequency power supply 60 has an output terminal 74 connected to the lower electrode 18 (plasma load 91). A matching unit (not shown) may be provided between the output terminal 74 and the lower electrode 18.

[0028] The DDS 61 is a digital direct synthesis oscillator, and receives a frequency setting value F st Based on this, a high frequency signal with an arbitrary set frequency F is generated. stThe data includes, for example, the frequency and amplitude (waveform data) of the high-frequency signal to be generated. The generated high-frequency signal is output to the preamplifier 63. Here, the generated high-frequency signal is, for example, a sine wave. Note that the DDS 61 may be of another type, such as a VF converter (voltage-controlled frequency generator), as long as it can generate a high-frequency signal of the set frequency F.

[0029] The first variable DC voltage source 62 is a DC power source that can vary the voltage, and supplies power to the preamplifier 63. A commercial power source is connected to the first variable DC voltage source 62, and an AC (Alternating Current) input P ac The first variable DC voltage source 62 receives an input power setting value V past Based on this, the voltage supplied to the preamplifier 63 is controlled, and the power supplied to the preamplifier 63 is controlled. The first variable DC voltage source 62 can supply a power of about 50 dBm (100 W) to the preamplifier 63, for example.

[0030] The preamplifier 63 amplifies the high frequency signal input from the DDS 61 and outputs the input power P in The output of the preamplifier 63, that is, the input power P in is controlled by the voltage supplied from the first variable DC voltage source 62. in is, for example, about 50 dBm (100 W). That is, the DDS 61, the first variable DC voltage source 62, and the preamplifier 63 constitute an input power unit. That is, the input power unit is electrically connected to the gate terminal of the transistor of the main amplifier 65, and supplies the input power P in and supplies input power P in The frequency to be supplied can be changed within the frequency band that can be supplied.

[0031] The second variable DC voltage source 64 is a DC power source that can vary the voltage, and supplies power to the main amplifier 65. A commercial power source is connected to the second variable DC voltage source 64, and an AC input P acThe second variable DC voltage source 64 receives a drain voltage setting value V dst Based on this, the drain bias voltage V supplied to the main amplifier 65 d is controlled, thereby controlling the power supplied to the main amplifier 65. That is, the second variable DC voltage source 64 is electrically connected to the drain terminal of the main amplifier 65, and controls the drain bias voltage V d In the following description, the drain bias voltage V d is the drain voltage V d The second variable DC voltage source 64 can supply the main amplifier 65 with a power of, for example, about 3000 W.

[0032] The main amplifier 65 receives the high-frequency signal from the preamplifier 63 as an input power P in to a target value or more and outputs it to directional coupler 67. Main amplifier 65 is an example of a switching amplifier circuit, and includes a FET (Field Effect Transistor) having a gate terminal, a drain terminal, and a source terminal. Note that a FET is an example of a transistor. In other words, main amplifier 65 is an example of an amplifier unit having a gate terminal, a drain terminal, and a source terminal. Main amplifier 65 is also a switching amplifier (switching amplifier circuit) in which the FET operates by zero-cross switching, performing class E operation.

[0033] The gate terminal of the main amplifier 65 is connected to the preamplifier 63 of the input power section described above, and the gate bias voltage V of the FET. g The buffer amplifier 66 is electrically connected to the control unit 70 and receives a gate voltage setting value V gst That is, the buffer amplifier 66 is electrically connected to the gate terminal of the main amplifier 65, and the gate bias voltage V g In the following description, the gate bias voltage V gis the gate voltage V g It may be expressed as:

[0034] The output of the main amplifier 65, that is, the output P output from the output terminal 74 via the directional coupler 67 out is the input power P of the main amplifier 65 (FET) in , gate voltage V g , and the drain voltage V d The output terminal 74 is electrically connected to the drain terminal. out In the available frequency band, the power is preferably 2000 W or more, and more preferably 2200 W or more.

[0035] In the ideal operation of the zero-cross switching described above, the drain voltage V of the FET d and the drain current I d Since switching occurs when one or more of these voltages become zero, V d ×I d In this case, the drain efficiency η1 is theoretically 100%. However, in reality, it is difficult to make the FET loss zero due to the frequency characteristics of the FET, etc. In contrast, in this embodiment, the input power P of the FET is in , drain voltage V d , and gate voltage V g By adjusting the frequency, it is possible to achieve both high efficiency and wide bandwidth.

[0036] The directional coupler 67 is provided in the transmission path between the main amplifier 65 and the lower electrode 18, and transmits the traveling wave power P fd and reflected wave power P rd That is, the directional coupler 67 is provided between the drain terminal and the output terminal 74. In FIG. 2, the lower electrode 18 side is represented as a plasma load 91. The extracted small signal, traveling wave signal S fd and the reflected wave signal S rd is input to the detector 68.

[0037] The detector 68 detects the traveling wave signal S fd and the reflected wave signal S rd The detector 68 detects the forward wave voltage V fd and the reflected wave voltage V rd is output to the control unit 70 via a buffer amplifier 69.

[0038] The control unit 70 controls each part in the first high frequency power supply 60. The control unit 70 receives from the upper controller 90 the set frequency F and set power P of the high frequency power. f The control unit 70 also receives the forward wave voltage V from the detector 68 via the buffer amplifier 69. fd and the reflected wave voltage V rd The control unit 70 receives the set frequency F and set power P f , traveling wave voltage V fd and the reflected wave voltage V rd is input to the processing unit 71 via the input / output unit 73, and the traveling wave voltage V fd and the reflected wave voltage V rd is the forward wave power P fd and reflected wave power P rd is converted to

[0039] On the other hand, the processing unit 71 outputs the frequency setting value F st , and the input power setting value V past are output to the DDS 61 and the first variable DC voltage source 62 via the input / output unit 73. The processing unit 71 also outputs the drain voltage setting value V dst , and the gate voltage setting value V gst are output to the second variable DC voltage source 64 and the buffer amplifier 66 via the input / output unit 73, respectively.

[0040] That is, the control unit 70 outputs, for each set frequency F, to the DDS 61, the first variable DC voltage source 62, the second variable DC voltage source 64, and the buffer amplifier 66, an instruction value that maximizes the efficiency of the high-frequency power output from the output terminal 74. That is, for each set frequency F st , input power setting value V past , drain voltage setting value Vdst , and the gate voltage setting value V gst is an example of an instruction value and an example of a parameter of the switching amplifier circuit. fm is output to the upper controller 90 via the input / output unit 73.

[0041] In other words, the control unit 70 is an example of an instruction unit configured to output, for each frequency within the frequency band, to the input power unit, the first setting unit, and the second setting unit, instruction values ​​that maximize the efficiency of the high-frequency power output from the output terminal 74. That is, the control unit 70 controls the parameters of the switching amplifier circuit so that the high-frequency power is equal to or greater than a target value for each specific frequency within the available frequency band. In addition, the control unit 70 controls a plurality of drain bias voltages V, as will be described later. d For each, the input power P in The control unit 70 outputs instruction values ​​to the input power unit, the first setting unit, and the second setting unit by referring to the storage unit 72 that stores the respective associated values. d For each, the input power P in The input power P in , gate bias voltage V g and the drain bias voltage V d Control.

[0042] Furthermore, the control unit 70 controls the input power P in and the gate bias voltage V at which the high frequency power is equal to or greater than the target value for each frequency. g and multiple drain bias voltages V d and the drain bias voltage V d The input power P in and the input power P inThe control unit 70 outputs instruction values ​​to the input power unit, the first setting unit, and the second setting unit by referring to the storage unit 72 that stores a plurality of set powers of high frequency powers corresponding to each of the input powers. g , drain bias voltage V d , input power P in and the set power P f The control unit calculates instruction values ​​for the input power unit, the first setting unit, and the second setting unit by proportionally dividing the nearby discrete values, and outputs the calculated instruction values.

[0043] Furthermore, the control unit 70 controls the input power P in and multiple set powers P f The memory unit 72 stores the correction value k of the high frequency power in association with each of the values, and calculates the forward power P fd and the correction value k, the power monitor value P fm Calculate the calculated power monitor value P fm is the current setting of the RF power P f The control unit 70 outputs instruction values ​​to the input power unit and the second setting unit so that the frequency and set power P f and the correction value k, the control unit 70 calculates the instruction values ​​for the input power unit and the second setting unit by proportionally dividing the nearby discrete values, and outputs the calculated instruction values. fd Similar to the processing of the reflected wave power P rd Also calculate.

[0044] [Parameter table and correction table] Next, the parameter table and the correction table stored in the storage unit 72 will be described with reference to Figs. 3 to 7. Fig. 3 is a block diagram showing an example of connections when setting parameters. When generating the parameter table and the correction table, that is, when setting parameters, a power meter 92 and a dummy load 93 are connected to the output terminal 74 of the first high frequency power supply 60, as shown in Fig. 3. In addition, a power meter value P fpm is input to the control unit 70.

[0045] 4 is a diagram showing an example of a parameter table in this embodiment. The parameter table 100 shown in FIG. out The parameter table 100 stores the parameters that provide the rated power and maximum efficiency for the frequency band. The rated power is, for example, 2000 W. The parameter table 100 includes, for example, a table for each of a plurality of discrete frequencies in the frequency band that can be output. The discrete frequencies can be, for example, the set frequency F. The tables are provided for each of the frequencies, for example, 209 MHz, 214.5 MHz, 220 MHz, 225.5 MHz, and 231 MHz.

[0046] For example, the 220MHz table is "n", "F(220,n)", and "V g (220,n)" and "V d (220,n)" and "P in (220,n)" and "P fm (220,n)"

[0047] "n" indicates the number of discrete values ​​for each parameter at each frequency. "F(220,n)" indicates the set frequency F for the number of discrete values ​​"n". In the 220MHz table, "F(220,n)" is always "220". "V g (220,n) is the gate voltage V at the number of discrete values ​​"n". g It indicates that "V g Since "(220,n)" is set as the initial value for each set frequency F, in the 220 MHz table, all values ​​are the same, for example, "1.7."

[0048] "V d (220,n) is the drain voltage V at the number of discrete values ​​"n". d Indicates "P in (220,n) is the input power P in Indicates "P fm (220,n) is the power monitor value P at the number of discrete values ​​“n”. fm Shows.

[0049] Figure 5 shows the input power P that provides maximum efficiency for each frequency in the parameter table. in 5 is a diagram showing an example of a table focusing on the input power P in For example, when the set frequency F is 209.0 MHz, the gate voltage V g At 1.4V, the input power P in is the drain voltage V d is 45.9dBm at 10V, drain voltage V d is 50.0 dBm at 20 V, 30 V, 40 V, 50 V and 60 V. Note that the input power P in The blanks indicate the drain voltage V d indicates that it is not set.

[0050] Similarly, for example, if the set frequency F is 214.5MHz, the gate voltage V g At 0.2V, the input power P in is the drain voltage V d is 43.1dBm at 10V, drain voltage V d is 45.9dBm at 20V, drain voltage V d becomes 47.2dBm at 30V. Also, the input power P in is the drain voltage V d is 50.0dBm at 40V, 50V and 60V.

[0051] For example, if the set frequency F is 220.0 MHz, the gate voltage V gAt 1.7V, the input power P in is the drain voltage V d is 33.3dBm at 10V, drain voltage V d is 34.6dBm at 20V, drain voltage V d At 30V, the input power P in is the drain voltage V d is 37.8dBm at 40V, drain voltage V d is 39.7dBm at 50V, drain voltage V d is 41.1dBm at 60V, drain voltage V d becomes 42.3dBm at 70V.

[0052] For example, if the set frequency F is 225.5MHz, the gate voltage V g At 2.7V, the input power P in is the drain voltage V d is 41.2dBm at 10V, and the drain voltage V d is 41.5dBm at 20V, drain voltage V d At 30V, the input power P in is the drain voltage V d is 40.9dBm at 40V, drain voltage V d is 38.6dBm at 50V, drain voltage V d is 37.6dBm at 60V, drain voltage V d is 37.6dBm at 70V, drain voltage V d becomes 37.9dBm at 80V.

[0053] For example, if the set frequency F is 231.0MHz, the gate voltage V g At 2.7V, the input power P in is the drain voltage V d is 42.7dBm at 10V, drain voltage V d is 43.9dBm at 20V, drain voltage V d At 30V, the input power P in is the drain voltage V d is 41.5dBm at 40V, drain voltage V dis 40.8dBm at 50V, drain voltage V d is 40.6dBm at 60V, drain voltage V d is 40.6dBm at 70V, drain voltage V d becomes 40.6dBm at 80V.

[0054] Figure 6 shows the power monitor value P that maximizes efficiency for each frequency in the parameter table. fm 6 is a diagram showing an example of a table focusing on the power monitor value P that provides the maximum efficiency for each frequency in the parameter table 100. fm This is an example of a table that focuses on the set frequency F and gate voltage V g , drain voltage V d Input power P in corresponds to the values ​​in Figure 5. For example, when the set frequency F is 209.0 MHz, the gate voltage V g At 1.4V, the power monitor value P fm is the drain voltage V d is 10V and P in 45.9dBm at 97W, drain voltage V d is 20V and P in 418W at 50.0dBm, drain voltage V d is 30V and P in is 50.0 dBm and becomes 851 W. Also, the power monitor value P fm is the drain voltage V d is 40V and P in 1343W at 50.0dBm, drain voltage V d is 50V and P in 1814W at 50.0dBm, drain voltage V d is 60V and P in is 50.0 dBm, which is 2213 W. Note that the power monitor value P fm The blanks indicate the drain voltage V d indicates that it is not set.

[0055] Similarly, for example, if the set frequency F is 214.5MHz, the gate voltage V g At 0.2V, the power monitor value P fmis the drain voltage V d is 10V and P in is 43.1dBm at 50W, drain voltage V d is 20V and P in 45.9dBm at 250W, drain voltage V d is 30V and P in is 47.2 dBm, which is 608 W. Also, the power monitor value P fm is the drain voltage V d is 40V and P in 1195W at 50.0dBm, drain voltage V d is 50V and P in 1861W at 50.0dBm, drain voltage V d is 60V and P in At 50.0 dBm, this becomes 2616 W.

[0056] For example, if the set frequency F is 220.0 MHz, the gate voltage V g At 1.7V, the power monitor value P fm is the drain voltage V d is 10V and P in 33.3dBm at 29W, drain voltage V d is 20V and P in 34.6dBm at 129W, drain voltage V d is 30V and P in is 36.0 dBm, which is 321 W. Also, the power monitor value P fm is the drain voltage V d is 40V and P in 37.8dBm at 633W, drain voltage V d is 50V and P in 39.7dBm at 1072W, drain voltage V d is 60V and P in 41.1dBm at 1609W, drain voltage V d is 70V and P in This is 42.3dBm, or 2246W.

[0057] For example, if the set frequency F is 225.5MHz, the gate voltage V g At 2.7V, the power monitor value P fmis the drain voltage V d is 10V and P in 41.2dBm at 37W, drain voltage V d is 20V and P in 41.5dBm at 156W, drain voltage V d is 30V and P in is 41.8 dBm, which is 358 W. Also, the power monitor value P fm is the drain voltage V d is 40V and P in 40.9dBm at 637W, drain voltage V d is 50V and P in 38.6dBm at 947W, drain voltage V d is 60V and P in 37.6dBm at 1355W, drain voltage V d is 70V and P in 37.6dBm at 1802W, drain voltage V d is 80V and P in is 37.9dBm, which is 2309W.

[0058] For example, if the set frequency F is 231.0MHz, the gate voltage V g At 2.7V, the power monitor value P fm is the drain voltage V d is 10V and P in is 42.7dBm at 38W, and the drain voltage V d is 20V and P in 43.9dBm at 160W, drain voltage V d is 30V and P in is 44.6 dBm, which is 368 W. Also, the power monitor value P fm is the drain voltage V d is 40V and P in 41.5dBm at 639W, drain voltage V d is 50V and P in 40.8dBm at 977W, drain voltage V d is 60V and P in 40.6dBm at 1372W, drain voltage V d is 70V and P in 40.6dBm at 1816W, drain voltage Vd is 80V and P in This is 40.6dBm, or 2295W.

[0059] 7 is a diagram showing an example of a correction table in this embodiment. The correction table 103 shown in FIG. 7 is a correction table for setting the set power P f The correction table 103 stores a correction value k for each frequency. The correction table 103 includes, for example, a table for each of a plurality of discrete frequencies in the frequency band that can be output. The discrete frequencies can be, for example, the set frequency F. The tables are provided for frequencies such as 209 MHz, 214.5 MHz, 220 MHz, 225.5 MHz, and 231 MHz.

[0060] For example, the 220MHz table is "n", "F(F st ,n)," "P f (F st ,n) and k(F st ,n)" where "n" indicates the number of discrete values ​​of the correction value k at each frequency. st ,n) is the set frequency F (frequency set value F st ) and "F(F st ,n)" will all be "220" in the 220MHz table. f (F st ,n) is the set power P f indicates that k(F st ,n) is the set power P f The corresponding correction value k is shown.

[0061] [Parameter calculation example] Next, an example of calculating parameters at a center frequency of 220 MHz will be described with reference to Figures 8 to 12. Figure 8 shows the drain voltage V d Gate voltage per V g 8 is a graph showing an example of the relationship between the drain voltage V at the center frequency. d Gate voltage per Vg For example, when the efficiency is set to 80% or more, the graph 104 shows the relationship between the drain voltage V d Whether the gate voltage V is 65V, 70V or 75V, g It can be seen that it is sufficient if the voltage is 1.7V or less.

[0062] Figure 9 shows the drain voltage V d Gate voltage per V g and the output P at maximum efficiency out 9 is a graph showing an example of the relationship between the drain voltage V d Gate voltage per V g and the output P at maximum efficiency out From the graph 105, the output P out If the power consumption is 2000W or more, the drain voltage V d is the gate voltage V g It can be seen that the voltage should be 70V or higher in the range of -2.0V to 2.2V.

[0063] Figure 10 shows the drain voltage V d Gate voltage per V g and the input power P at maximum efficiency in Graph 106 shown in FIG. 10 is a graph showing an example of the relationship between the drain voltage V d Gate voltage per V g and the input power P at maximum efficiency in From the graph 106, for example, the drain voltage V d When the gate voltage V is set to 70V, g When the input voltage is less than 1.7V, the input power P in The smallest gate voltage V g is 1.7V. Here, the input power P in By making the value of V as small as possible, it is possible to prevent the FET rating from being exceeded instantaneously. Therefore, at 220 MHz, the gate voltage V g is 1.7V, drain voltage V dWhen the voltage is 70V, the input power P in can be calculated as 42.3 dBm.

[0064] Figure 11 shows the drain voltage V d Input power per P in 11 is a graph showing an example of the relationship between the gate voltage V g When the drain voltage V d Input power per P in Graph 107 shows an example of the relationship between drain voltage V d is 70V, input power P in When the drain voltage V is 42.3 dBm, the maximum efficiency is about 80.2%, as shown by the arrow 108. d For 10V to 65V, the input power P in The relationship between the power consumption and efficiency is shown.

[0065] Figure 12 shows the drain voltage V d Input power per P in and output P out Graph 109 shown in FIG. g When the drain voltage V d Input power per P in and output P out From the graph 109, the output P out When the drain voltage V is set to 2000W or more, d and input power P in The relationship between is understood.

[0066] [Power control according to output] Next, using Figs. 13 to 15, the output P out This section explains high-efficiency power control in the range from low to high output. inThe drain voltage V d and output P out Graph 110 shown in FIG. in When the drain voltage V is constant, d and output P out On the other hand, graph 111 shows an example of the relationship between the drain voltage V d The input power P that provides maximum efficiency in The drain voltage V d and output P out Graph 110 and graph 111 show an example of the relationship between the drain voltage V d When the voltage is 70V, both have the same output P out However, the drain voltage V d As the output P out There is a difference.

[0067] Figure 14 shows the input power P in The drain voltage V d and input power P in Graph 112 shown in FIG. in When the drain voltage V is constant, d and input power P in On the other hand, graph 113 shows an example of the relationship between the drain voltage V d The input power P that provides maximum efficiency in The drain voltage V d and input power P in That is, the graph 113 shows an example of the relationship between the input power P in and the drain voltage V d The input power P that provides maximum efficiency depending on in It can be seen that is changing.

[0068] Figure 15 shows the drain voltage V d and input power P inWhen the output P out 15 is a graph showing an example of the relationship between the drain voltage V d is set to 70V, and the input power P in By changing the output P out Graph 114 shows an example of the case where the output P out The lower the input power P in is set to 42.3 dBm, and the drain voltage V d By changing the output P out Graph 115 shows an example of the case where the output P out The graph 116 shown in FIG. 15 shows the efficiency improvement when the drain voltage V d By changing the output P out While controlling the input power P in Graph 116 shows an example of a case where the output P out The efficiency is improved when the drain voltage V is low (for example, in the range below 1000W). d By changing the output P out While controlling the input power P in By controlling the above, highly efficient power control becomes possible in the low output range.

[0069] [Efficiency when frequency is variable] Next, the change in efficiency when the frequency is variable will be explained using Fig. 16 to Fig. 19. In Fig. 16 to Fig. 19, the drain voltage V d is set to 70V, and the gate voltage V g The input power P in 16 is a graph showing an example of the relationship between the input power P and the efficiency when the set frequency F is changed to 209.0 MHz, 214.5 MHz, 220.0 MHz, 225.5 MHz, and 231.0 MHz. inThe relationship between the efficiency and the power dissipation varies depending on the frequency. Also, the further away from the center frequency of 220 MHz the higher the maximum efficiency becomes.

[0070] Figure 17 shows the relationship between frequency and input power P in 17, at a set frequency F lower than the center frequency of 220 MHz, the input power P in becomes larger.

[0071] FIG. 18 is a graph showing an example of the relationship between frequency and maximum efficiency. In the example of graph 119 shown in FIG. 18, the maximum efficiency is approximately 80.2% at the center frequency of 220 MHz, but the maximum efficiency decreases as the frequency moves away from 220 MHz. In other words, graph 119 is a graph of the maximum efficiency at each set frequency F of graph 117 in FIG. 16, with the set frequency F plotted on the horizontal axis. As such, in main amplifier 65, the maximum efficiency varies with frequency. Therefore, when the set frequency F is 209.0 MHz, 214.5 MHz, 225.5 MHz, and 231.0 MHz, the maximum efficiency is less than 80%, but each parameter is adjusted to achieve maximum efficiency at each frequency.

[0072] Figure 19 shows the relationship between frequency and output power P out In the example of graph 120 shown in FIG. 19, at a center frequency of 220.0 MHz, the output P out When the set frequency F is 225.5MHz and 231.0MHz, the output P out In this way, the main amplifier 65 has an output P out Therefore, when the set frequency F is 225.5MHz and 231.0MHz, the output P out Each parameter will be adjusted so that the power is 2000W or more, more preferably 2200W or more.

[0073] [Example of parameter calculation when frequency is variable] Next, an example of calculating the initial values ​​of the parameters when the frequency is varied will be described with reference to Figures 20 to 25. Note that, for the calculation of the parameters when the frequency is varied, numerical analysis is performed using ADS (Advanced Design System) as an example of a circuit simulator, but other circuit simulators may also be used. Furthermore, in the examples of Figures 20 to 25, the above-mentioned set frequency F of 209.0 MHz, 214.5 MHz, 220.0 MHz, 225.5 MHz, and 231.0 MHz is used as the multiple discrete frequencies. In other words, the following parameter calculation example is an example of generating the initial values ​​of the parameter table 100.

[0074] Figure 20 shows the relationship between frequency and gate voltage V g 20 is a graph showing an example of the relationship between the gate voltage V and the initial value of the set frequency F. g The analysis results of the graph 121 are shown in Tables 100 to 102 of FIGS. g corresponds to the column.

[0075] Figure 21 shows the drain voltage V d and input power P in 21 is a graph showing an example of the relationship between the drain voltage V and the initial value of the set frequency F. d and input power P in The analysis results of the graph 122 are shown in the table 101 of FIG. d Input power per P in In other words, the graph 122 corresponds to each column of the drain voltage V for each set frequency F in the table 101. d and input power P in This is a graph of the above.

[0076] Figure 22 shows the drain voltage V d 23 is a graph showing an example of the relationship between the drain voltage V and the efficiency at each frequency. d22 and the table 124 in FIG. 23 show an example of the relationship between the drain voltage V and the efficiency for each set frequency F. d That is, the graph 123 and the table 124 show the analysis results of the efficiency at the set frequency F and the drain voltage V d The table 124 may be included in the parameter table 100.

[0077] Figure 24 shows the drain voltage V d and output P out 24 is a graph showing an example of the relationship between the drain voltage V and the set frequency F. d Output P at out The analysis results of the graph 125 are shown in the table 102 of FIG. d Output per P out In other words, the graph 125 corresponds to each column of the drain voltage V for each set frequency F in the table 102. d and output P out As shown in graph 125, the output P out is the drain voltage V d It can be seen that by adjusting the above, the estimated output exceeds 2200 W, which is an example of a target value. In other words, the main amplifier 65 can output high-frequency power of 2200 W or more in the 209.0 MHz to 231.0 MHz range, which is an example of a frequency band that can be output.

[0078] Figure 25 shows the output P out 25 is a graph showing an example of the relationship between the output P and the efficiency for each set frequency F. out The analysis results of the graph 126 are obtained by plotting the efficiency of the graph 123 in FIG. 22, the table 124 in FIG. 23, and the graph 125 in FIG. 24 on the vertical axis, with the efficiency as the vertical axis, and the output P out The graph 126 may be tabulated and included in the parameter table 100.

[0079] [Parameter generation method] Next, a parameter generation method according to this embodiment will be described below. Fig. 26 is a flowchart showing an example of parameter generation processing according to this embodiment.

[0080] The parameter generation process according to this embodiment is executed when generating a parameter table 100 to be stored in advance in the storage unit 72 of the first high frequency power supply 60. That is, the parameter generation process is executed by an information processing device (not shown) connected via the upper controller 90 based on the specifications of the first high frequency power supply 60. The information processing device stores the parameter table 100 in the storage unit 72 of the control unit 70 of the first high frequency power supply 60.

[0081] The information processing device analyzes each parameter of the amplifier section (main amplifier 65) that provides rated power at each frequency in the available frequency band and is also maximized in efficiency based on the specifications of the first high frequency power supply 60 (step S1).

[0082] The information processing device stores the analysis results in the parameter table 100 in the storage unit 72 (step S2). This allows the parameter table 100 to be generated. That is, as the initial values ​​of the parameter table 100, a plurality of discrete set frequencies F in the frequency band that can be output, gate voltages V g , drain voltage V d , input power P in , and the set power P f The power monitor value P corresponding to fm It should be noted that each parameter stored in the parameter table 100 may be set based on an actual measurement value.

[0083] [Correction value generation method] Next, a correction value generating method according to this embodiment will be described. Fig. 27 is a flowchart showing an example of a correction value generating process according to this embodiment.

[0084] The correction value generation process according to this embodiment is executed when generating a correction table 103 to be stored in advance in the storage unit 72 of the first high frequency power supply 60. That is, the correction value generation process is executed by the control unit 70 in a state in which a power meter 92 and a dummy load 93 are connected to the first high frequency power supply 60, as shown in FIG. 3 . The control unit 70 stores the correction table 103 in the storage unit 72. The correction value generation process may be executed by the host controller 90 or by the control unit 11 of the plasma processing apparatus 1. Furthermore, the correction value generation process may be executed by an information processing device (not shown) connected via the host controller 90.

[0085] The control unit 70 refers to the parameter table 100 stored in the storage unit 72, and starts outputting high-frequency power at an initial value at a certain frequency (step S11). For example, the control unit 70 starts outputting high-frequency power at an initial value at a certain frequency (step S12). For example, when the set frequency F is 220.0 MHz and the set power P f Gate voltage V at 2000W g , drain voltage V d , and input power P in The control unit 70 reads the values ​​of n "1" and "2" in the parameter table 100. The control unit 70 divides the read values ​​of n "1" and "2" proportionally to obtain the set power P f When the frequency setting value F is 2000W st , and the input power setting value V past Similarly, the control unit 70 calculates the set power P f When the drain voltage setting value V is 2000W dst , and the gate voltage setting value V gst The control unit 70 outputs the calculated set values ​​to the DDS 61, the first variable DC voltage source 62, the second variable DC voltage source 64, and the buffer amplifier 66 as instruction values.

[0086] The control unit 70 sets the set power P f and the power meter value P input from the power meter 92 fpm The drain voltage V dThat is, the control unit 70 adjusts the drain voltage setting value V, which is the instruction value for the second variable DC voltage source 64 (step S12). dst Adjust.

[0087] The control unit 70 sets the set power P f is the power meter value P fpm The forward wave voltage V input from the detector 68 coincides with fd The forward wave power P converted from fd Based on this, a correction value k is obtained and stored in the correction table 103. f (n)=set power P f Then, the correction value k(F st , n) (step S13). For example, the control unit 70 stores the set power P f is 2000W and the power meter value P fpm When the forward wave power P fd If it is 4000, the correction value k=P f / P fd =P fpm / P fd Specifically, the control unit 70 calculates and stores the value F(220,1)=220, P f The control unit 70 stores the values ​​of (220,1)=2000 and k(220,1)=0.5. f For example, values ​​that become the correction value k for 1800 W, 1600 W, . . . , 0 W, etc. are calculated in the same manner, and the correction table 103 in the storage unit 72 is stored with F(220, 2)=220, P f The values ​​of (220,2) = 1800, k(220,2) = 0.56, F(220,3) = 220, Pf(220,3) = 1600, k(220,3) = 0.64, etc. are stored.

[0088] The control unit 70 determines whether or not to acquire a correction value k for another frequency (step S14). If the control unit 70 determines to acquire a correction value k for another frequency (step S14: Yes), it returns to step S11 and selects one frequency from another frequency, for example, 209.0 MHz, 214.5 MHz, 225.5 MHz, and 231.0 MHz. The control unit 70 starts outputting high-frequency power using the initial value at the selected frequency and similarly acquires a correction value k. On the other hand, if it determines not to acquire a correction value k for another frequency (step S14: No), it stops outputting high-frequency power and ends the correction value generation process. This allows the correction table 103 to be generated not only for the center frequency but also for other frequencies.

[0089] [Power control method] Next, a power control method according to this embodiment will be described below. Fig. 28 is a flowchart showing an example of power control processing according to this embodiment.

[0090] The power control process according to this embodiment is executed by the control unit 70 of the first high frequency power supply 60 in response to instructions from the control unit 11 of the plasma processing apparatus 1. That is, the power control process is executed by the control unit 70 in the plasma processing apparatus 1 in a state where a plasma load 91 is connected to the first high frequency power supply 60, as shown in FIG. 2 . The power control process may be executed by the host controller 90 or by the control unit 11 of the plasma processing apparatus 1.

[0091] The control unit 70 receives the set frequency F and set power P f Based on this, the set frequency F and the set power P f The parameters of the neighborhood corresponding to the parameter are read (step S21).

[0092] The control unit 70 determines the set frequency F and set power P from the nearby parameters. f For example, if the set frequency F is 220.0 MHz and the set power P fis 2000 W, the control unit 70 selects the power monitor value P fm The control unit 70 reads the values ​​of "1" and "2" for the gate voltage V g , drain voltage V d , and input power P in The read n is divided into the value of "1" and the value of "2" and the set power P f Calculate each setting value when the power is 2000W.

[0093] The control unit 70 sets the calculated parameters in the DDS 61, the first variable DC voltage source 62, the second variable DC voltage source 64, and the buffer amplifier 66, and starts outputting high-frequency power (step S23). st , input power setting value V past , drain voltage setting value V dst , and the gate voltage setting value V gst is output as an instruction value to the DDS 61, the first variable DC voltage source 62, the second variable DC voltage source 64, and the buffer amplifier 66. The control unit 70 receives the reflected wave voltage V rd The reflected wave power P rd The frequency setting value F st It is also possible to perform load control by feeding back the above parameters to keep the power consumption of the load constant.

[0094] The control unit 70 determines the set frequency F and the set power P f Based on this, the set frequency F and set power P are calculated from the correction table 103. f The control unit 70 reads the correction value k corresponding to the set frequency F and the set power P from the correction value k. f A correction value k corresponding to the above is calculated (step S25).

[0095] The control unit 70 calculates the correction value k and the forward power P fd Based on the power monitor value P fm(Step S26). The control unit 70 calculates the set power P f and the power monitor value P fm The input power setting value V output to the first variable DC voltage source 62 and the second variable DC voltage source 64 is set to match past , and the drain voltage setting value V dst (step S27). That is, the control unit 70 adjusts the set power P f and the power monitor value P fm The parameters (drain voltage V d , and input power P in ) is adjusted by feedback control. This makes it possible to broaden the variable frequency band while also achieving high efficiency in that frequency band.

[0096] [Input power adjustment method] Next, the input power P in 29 is a flowchart showing an example of input power adjustment processing in this embodiment.

[0097] The input power adjustment process according to this embodiment is executed by the control unit 70 of the first high frequency power supply 60 in response to instructions from the control unit 11 of the plasma processing apparatus 1. That is, the input power adjustment process is executed by the control unit 70 in the plasma processing apparatus 1 with a power meter 92 inserted between the first high frequency power supply 60 and the plasma load 91. Note that, similar to the correction value generation process, the input power adjustment process may be executed by the control unit 70 in a state where the power meter 92 and the dummy load 93 are connected to the first high frequency power supply 60. Furthermore, the input power adjustment process may be executed by the host controller 90 or the control unit 11 of the plasma processing apparatus 1.

[0098] The control unit 70 receives the set frequency F and set power P f Based on this, the above-described power control process (steps S21 to S27) is executed, and the output of high frequency power is started (step S31).

[0099] The control unit 70 receives the power meter value P fpm (Step S32). The control unit 70 obtains the power consumption P ft (Step S33). Here, the power consumption P ft is the drain voltage V of the FET of the main amplifier 65, as shown in the following equation (1). d and the drain current I d It is the product of multiplication of and.

[0100] P ft =V d ×I d ···(1)

[0101] The control unit 70 calculates the drain efficiency η1 of the FET of the main amplifier 65 by out and power consumption P ft Based on this, the output P is calculated using the following formula (2) (step S34). out is the power meter value P fpm If the correction value generation process is executed and the correction value k is stored, the power monitor value P fm = Power meter value P fpm = Output P out is controlled by.

[0102] η1=P out / P ft ···(2)

[0103] The control unit 70 controls the input power P in That is, the control unit 70 fine-tunes the input power setting value V, which is the instruction value for the first variable DC voltage source 62 (step S35). past Fine-tune the.

[0104] The control unit 70 calculates the adjusted input power P in The corresponding input power P in(Step S36). This allows adjustment for individual differences in the FETs of the main amplifier 65, and also makes it possible to broaden the variable frequency band and achieve high efficiency in that frequency band. By performing the above-mentioned processes, the reflected wave (reflected wave power P rd ) to suppress the output P out When increasing the efficiency of g By adopting this, the rated power is met and the drain voltage V d Furthermore, the drain voltage V d Input power P that matches in to the FET (main amplifier 65), it is possible to realize amplifier operation with high efficiency even when the frequency is varied.

[0105] In the input power adjustment process, the input power P is adjusted so that the power-added efficiency η2 or the power supply efficiency η3 is maximized in addition to the drain efficiency η1. in That is, the maximum efficiency is the drain efficiency η1, power added efficiency η2 or power supply efficiency η3 of the amplifier section (main amplifier 65). The power added efficiency η2 and power supply efficiency η3 can be calculated by the following equations (3) and (4), respectively. The power added efficiency η2 is also expressed as power added efficiency PAE (Power Added Efficiency), and is expressed as the output P at the drain efficiency η1. out from input power P in Excluding power consumption P ft The power supply efficiency η3 is the conversion efficiency of the entire power supply from the commercial power supply to high frequency power in the first high frequency power supply 60. In other words, the power supply efficiency η3 is the conversion efficiency of the entire power supply from the commercial power supply to high frequency power in the first high frequency power supply 60. out AC power P ac The value is obtained by dividing by .

[0106] η2=(P out -P in ) / P ft ···(3) η3=P out / P ac ···(4)

[0107] As described above, according to this embodiment, the high frequency power supply (first high frequency power supply 60) has an amplifier section (main amplifier 65), an output terminal 74, an input power section (DDS 61, first variable DC voltage source 62, preamplifier 63), a first setting section (buffer amplifier 66), a second setting section (second variable DC voltage source 64), and an instruction section (control section 70). The amplifier section has a gate terminal, a drain terminal, and a source terminal. The output terminal 74 is electrically connected to the drain terminal. The input power section is electrically connected to the gate terminal and supplies input power P in and supplies input power P in The first setting unit is electrically connected to the gate terminal and is configured to change the frequency to be supplied within a frequency band that can be supplied for the amplifier unit. g The second setting unit is electrically connected to the drain terminal and is configured to set a drain bias voltage V d The instruction unit is configured to output, for each frequency within the frequency band, to the input power unit, the first setting unit, and the second setting unit, an instruction value that maximizes the efficiency of the high frequency power output from output terminal 74. As a result, it is possible to achieve both high efficiency and a wide bandwidth.

[0108] Furthermore, according to this embodiment, the amplifier section is configured to operate with zero-cross switching, which results in improved efficiency of the amplifier section.

[0109] Furthermore, according to this embodiment, the instruction unit outputs a plurality of drain bias voltages V d For each, the input power P in The instruction values ​​are output to the input power unit, the first setting unit, and the second setting unit by referring to the storage unit (storage unit 72, parameter table 100) that stores the respective values ​​in association with each other. As a result, it is possible to achieve both a wider range of the changeable frequency band and high efficiency in that frequency band.

[0110] Furthermore, according to this embodiment, the instruction unit inThe gate bias voltage V is set to a set of frequencies (F) at which the RF power is equal to or greater than the target value for each frequency. g and multiple drain bias voltages V d and the drain bias voltage V d The input power P in and the input power P in Multiple set powers of high frequency power (set power P f The power monitor value P corresponding to fm ) in association with each other, and outputs instruction values ​​to the input power unit, the first setting unit, and the second setting unit. As a result, it is possible to achieve both a wider range of changeable frequency bands and high efficiency in those frequency bands.

[0111] According to this embodiment, the instruction unit also receives the frequency, the gate bias voltage V g , drain bias voltage V d , input power P in The instruction values ​​for the input power section, the first setting section, and the second setting section are calculated proportionally from the set power and the set power, and the calculated instruction values ​​are output. As a result, even for frequencies not included in the parameter table 100, the gate bias voltage V g , drain bias voltage V d , and input power P in The indicated value can be output.

[0112] According to this embodiment, the high frequency power supply further includes a directional coupler 67 provided between the drain terminal and the output terminal 74. The instruction unit is configured to select a plurality of frequencies of the input power and a plurality of set power levels P f The memory unit (memory unit 72, correction table 103) that stores the corresponding correction value k of the high frequency power is referenced to calculate the forward wave (forward wave power P fd ) and the correction value k, the power monitor value P fm Calculate the calculated power monitor value P fm is the current setting of the RF power Pf As a result, the characteristics of the directional coupler 67 with respect to frequency and power can be corrected.

[0113] According to the present embodiment, the instruction unit receives the frequency, the set power P f and the correction value k, the instruction values ​​for the input power section and the second setting section are calculated by proportionally dividing them, and the calculated instruction values ​​are output. As a result, even for frequencies not included in the correction table 103, the drain bias voltage V d , and input power P in The indicated value can be output.

[0114] Furthermore, according to this embodiment, the maximum efficiency is the drain efficiency, power added efficiency, or power supply efficiency of the amplifier section, and as a result, the internal or overall efficiency of the first high frequency power supply 60 can be maximized.

[0115] Furthermore, according to this embodiment, the high frequency power supply (first high frequency power supply 60) is a high frequency power supply that outputs high frequency power at a specific frequency (set frequency F) in an available frequency band, and includes a switching amplifier circuit (main amplifier 65) and a control unit 70 that controls parameters of the switching amplifier circuit so that the high frequency power for each specific frequency in the frequency band is equal to or greater than a target value. As a result, it is possible to achieve both high efficiency and a wide bandwidth.

[0116] According to the present embodiment, the switching amplifier circuit includes a transistor having a gate terminal, a drain terminal, and a source terminal. The parameters are an input power P in , gate bias voltage V g , and the drain bias voltage V d As a result, it is possible to achieve both high efficiency and wide bandwidth.

[0117] Furthermore, according to this embodiment, the control unit 70 controls a plurality of drain bias voltages V dFor each, the input power P in The input power P in , gate bias voltage V g and the drain bias voltage V d As a result, it is possible to achieve both a wider variable frequency band and high efficiency in that frequency band.

[0118] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive, and various omissions, substitutions, and modifications may be made to the above-described embodiments without departing from the spirit and scope of the appended claims.

[0119] Furthermore, in the above-described embodiment, the plasma processing apparatus 1 is described as an example in which a process such as etching is performed on a substrate W using capacitively coupled plasma as a plasma source, but the disclosed technology is not limited to this. As long as the apparatus is one that performs a process on a substrate W using plasma and uses a high-frequency power source, the plasma source is not limited to capacitively coupled plasma, and any plasma source such as inductively coupled plasma, microwave plasma, or magnetron plasma can be used.

[0120] The present disclosure can also be configured as follows. (1) an amplifier section having a gate terminal, a drain terminal, and a source terminal; an output terminal electrically connected to the drain terminal; an input power unit electrically connected to the gate terminal, supplying input power to the amplifier unit, and configured to be able to change the frequency of the input power within a frequency band that can be supplied; a first setting unit electrically connected to the gate terminal and configured to set a gate bias voltage of the amplifier unit; a second setting unit electrically connected to the drain terminal and configured to set a drain bias voltage of the amplifier unit; an instruction unit configured to output, for each frequency within the frequency band, to the input power unit, the first setting unit, and the second setting unit, an instruction value that maximizes the efficiency of the high frequency power output from the output terminal; A high frequency power supply having (2) The amplifier unit is configured to operate by zero-cross switching. The high frequency power supply according to (1) above. (3) the instruction unit references a storage unit that stores the input powers at which the high frequency power has the highest efficiency in association with each of the plurality of drain bias voltages, and outputs the instruction values ​​to the input power unit, the first setting unit, and the second setting unit. The high frequency power supply according to (1) or (2). (4) the instruction unit references the storage unit that stores, in association with one another, the plurality of frequencies of the input power, the gate bias voltage at which the high frequency power is equal to or greater than a target value for each frequency, the plurality of drain bias voltages, the input power at which the high frequency power is at its most efficient for each drain bias voltage, and a plurality of set powers of the high frequency power corresponding to each of the input powers, and outputs the instruction values ​​to the input power unit, the first setting unit, and the second setting unit. The high frequency power supply according to (3) above. (5) the instruction unit calculates the instruction values ​​for the input power unit, the first setting unit, and the second setting unit by proportionally dividing the frequency, the gate bias voltage, the drain bias voltage, the input power, and the set power, which are stored in the storage unit as discrete values, and outputs the calculated instruction values. The high frequency power supply according to (4) above. (6) further comprising a directional coupler provided between the drain terminal and the output terminal; the instruction unit refers to a storage unit that stores correction values ​​for the high frequency power in association with each of the plurality of frequencies of the input power and each of the plurality of set power levels of the high frequency power, calculates a power monitor value based on the traveling wave output from the directional coupler and the correction values, and outputs the instruction value to the input power unit and the second setting unit so that the calculated power monitor value coincides with the current set power level of the high frequency power. The high frequency power supply according to any one of (1) to (5) above. (7) The instruction unit calculates the instruction values ​​for the input power unit and the second setting unit by proportionally dividing the frequency, the set power, and the correction value, which are stored in the storage unit as discrete values, and outputs the calculated instruction values. The high frequency power supply according to (6) above. (8) The maximum efficiency is a drain efficiency, a power added efficiency, or a power supply efficiency of the amplifier unit. The high frequency power supply according to any one of (1) to (7) above. (9) A high frequency power supply that outputs high frequency power of a specific frequency in an outputtable frequency band, a switching amplifier circuit; a control unit that controls parameters of the switching amplifier circuit so that the high-frequency power is equal to or greater than a target value for each specific frequency in the frequency band; A high frequency power supply having (10) the switching amplifier circuit includes a transistor having a gate terminal, a drain terminal, and a source terminal; The parameters are the input power, gate bias voltage, and drain bias voltage of the transistor. The high frequency power supply according to (9) above. (11) the control unit controls the input power, the gate bias voltage, and the drain bias voltage by referring to a storage unit that stores the input power at which the high frequency power has the highest efficiency in association with each of the plurality of drain bias voltages. The high frequency power supply according to (10) above. (12) A plasma processing apparatus, The plasma processing apparatus includes: A processing vessel; an electrode provided in the processing vessel; a high frequency power supply that outputs a high frequency wave of a set frequency to the electrode, The high frequency power source is an amplifier section having a gate terminal, a drain terminal, and a source terminal; an output terminal electrically connected to the electrode and the drain terminal; an input power unit electrically connected to the gate terminal, supplying input power to the amplifier unit, and configured to be able to change the frequency of the input power within a frequency band that can be supplied; a first setting unit electrically connected to the gate terminal and configured to set a gate bias voltage of the amplifier unit; a second setting unit electrically connected to the drain terminal and configured to set a drain bias voltage of the amplifier unit; an instruction unit configured to output, for each frequency within the frequency band, to the input power unit, the first setting unit, and the second setting unit, an instruction value that maximizes the efficiency of the high frequency power output from the output terminal; A plasma processing apparatus comprising: [Explanation of symbols]

[0121] 1. Plasma processing equipment 10. Device body 12 Processing container 18 Lower electrode 60 1st high frequency power supply 61 DDS 62 First variable DC voltage source 63 Preamp 64 Second variable DC voltage source 65 Main amplifier 66,69 Buffer amplifier 67 Directional coupler 68 Detector 70 Control Unit 71 Processing section 72 Memory section 73 Input / output section 74 Output terminal 90 Upper controller 92 Power Meter 100 Parameter Table 103 Correction Table F Setting frequency k correction value P f Set power P fd traveling wave power P fm Power monitor value P in Input Power V d Drain Bias Voltage V g Gate Bias Voltage W substrate η1 drain efficiency η2 power added efficiency η3 power supply efficiency

Claims

1. an amplifier section having a gate terminal, a drain terminal, and a source terminal; an output terminal electrically connected to the drain terminal; an input power unit electrically connected to the gate terminal, supplying input power to the amplifier unit, and configured to be able to change the frequency of the input power within a frequency band that can be supplied; a first setting unit electrically connected to the gate terminal and configured to set a gate bias voltage of the amplifier unit; a second setting unit electrically connected to the drain terminal and configured to set a drain bias voltage of the amplifier unit; an instruction unit configured to output, for each frequency within the frequency band, an instruction value to the input power unit, the first setting unit, and the second setting unit such that the high frequency power output from the output terminal has maximum efficiency; A high frequency power supply having

2. The amplifier unit is configured to operate by zero-cross switching.

2. The high frequency power supply according to claim 1.

3. the instruction unit references a storage unit that stores the input powers at which the high frequency power has the highest efficiency in association with the plurality of drain bias voltages, and outputs the instruction values ​​to the input power unit, the first setting unit, and the second setting unit.

3. The high frequency power supply according to claim 1 or 2.

4. the instruction unit references the storage unit that stores, in association with one another, the plurality of frequencies of the input power, the gate bias voltage at which the high frequency power is equal to or greater than a target value for each frequency, the plurality of drain bias voltages, the input power at which the high frequency power is at its most efficient for each drain bias voltage, and a plurality of set powers of the high frequency power corresponding to each of the input powers, and outputs the instruction values ​​to the input power unit, the first setting unit, and the second setting unit.

4. The high frequency power supply according to claim 3.

5. the instruction unit calculates the instruction values ​​for the input power unit, the first setting unit, and the second setting unit by proportionally dividing the frequency, the gate bias voltage, the drain bias voltage, the input power, and the set power, which are stored in the storage unit as discrete values, and outputs the calculated instruction values.

5. The high frequency power supply according to claim 4.

6. further comprising a directional coupler provided between the drain terminal and the output terminal; the instruction unit refers to a storage unit that stores correction values ​​for the high frequency power in association with each of the plurality of frequencies of the input power and each of the plurality of set power levels of the high frequency power, calculates a power monitor value based on the traveling wave output from the directional coupler and the correction values, and outputs the instruction value to the input power unit and the second setting unit so that the calculated power monitor value coincides with the current set power level of the high frequency power.

3. The high frequency power supply according to claim 1 or 2.

7. the instruction unit calculates the instruction values ​​for the input power unit and the second setting unit by proportionally dividing the frequency, the set power, and the correction value, which are stored in the storage unit as discrete values, and outputs the calculated instruction values.

7. The high frequency power supply according to claim 6.

8. The maximum efficiency is a drain efficiency, a power added efficiency, or a power supply efficiency of the amplifier unit.

3. The high frequency power supply according to claim 1 or 2.

9. A high frequency power supply that outputs high frequency power of a specific frequency in an outputtable frequency band, a switching amplifier circuit; a control unit that controls parameters of the switching amplifier circuit so that the high-frequency power is equal to or greater than a target value for each specific frequency in the frequency band; A high frequency power supply having

10. the switching amplifier circuit includes a transistor having a gate terminal, a drain terminal, and a source terminal; The parameters are the input power, gate bias voltage, and drain bias voltage of the transistor.

10. The high frequency power supply according to claim 9.

11. the control unit controls the input power, the gate bias voltage, and the drain bias voltage by referring to a storage unit that stores the input power at which the high frequency power has the highest efficiency in association with each of the plurality of drain bias voltages. The high frequency power supply according to claim 10.

12. A plasma processing apparatus, The plasma processing apparatus includes: A processing vessel; an electrode provided in the processing vessel; a high frequency power supply that outputs a high frequency wave of a set frequency to the electrode, The high frequency power source is an amplifier section having a gate terminal, a drain terminal, and a source terminal; an output terminal electrically connected to the electrode and the drain terminal; an input power unit electrically connected to the gate terminal, supplying input power to the amplifier unit, and configured to be able to change the frequency of the input power within a frequency band that can be supplied; a first setting unit electrically connected to the gate terminal and configured to set a gate bias voltage of the amplifier unit; a second setting unit electrically connected to the drain terminal and configured to set a drain bias voltage of the amplifier unit; an instruction unit configured to output, for each frequency within the frequency band, an instruction value to the input power unit, the first setting unit, and the second setting unit such that the high frequency power output from the output terminal has maximum efficiency; A plasma processing apparatus comprising:

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