Multilayer ceramic capacitor

Abstract

To provide a thin and tetragonal multilayer ceramic capacitor capable of suppressing bending and lowering of mechanical strength.SOLUTION: In a multilayer ceramic capacitor including a multilayer body 12 and four external electrodes 30a to 30d disposed in the multilayer body, when the dimension in a first direction y is L and the dimension in a second direction z is W, 0.85≤L / W≤1.00 is satisfied. A laminate includes a first inner electrode 16a having one end exposed on a third surface 12c and a fifth surface 12e and the other end exposed on a fourth surface 12d and a sixth surface 12f, a second inner electrode having one end exposed on the third surface and the sixth surface and the other end exposed on the fourth surface and the fifth surface, and peripheral electrodes 28a, 28b, .... A peripheral electrode 28a is disposed in a region between the first inner electrode and the third surface or the sixth surface.SELECTED DRAWING: Figure 8A

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] In recent years, electronic devices such as mobile phones and portable music players have become increasingly smaller and thinner. Accordingly, the multilayer ceramic capacitors used in these smaller and thinner electronic devices have also become smaller and thinner. In particular, multilayer ceramic capacitors that are becoming thinner are now being used, for example, by being embedded in wiring boards, or even when mounted on the surface of a wiring board, they are being mounted in very narrow spaces. As such, the thinner a multilayer ceramic capacitor becomes, the lower its mechanical strength becomes, and there is a strong demand for maintaining that mechanical strength. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-103730 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in the multilayer ceramic capacitor described in Patent Document 1, the region where adjacent internal electrodes face each other in the lamination direction is the thickest region, and the dimensional difference in the lamination direction between the region where internal electrodes are not arranged and the region where internal electrodes are arranged becomes large, which may cause the surface of the multilayer ceramic capacitor to curve, resulting in significant chip warping as the capacitor is made thinner.In addition, the multilayer ceramic capacitor described in Patent Document 1 has two adjacent sides with lengths of 0.9 to 1.1 times, and the multilayer ceramic capacitor has a roughly tetragonal crystal structure, which increases the distance between the external electrodes arranged on the diagonal line, resulting in more significant curvature and a risk of reducing mechanical strength due to nozzle pickup during mounting, etc.

[0005] Therefore, a primary object of the present invention is to provide a thin multilayer ceramic capacitor having a tetragonal crystal structure, which is capable of suppressing bending of the multilayer ceramic capacitor and suppressing a decrease in mechanical strength. [Means for solving the problem]

[0006] A multilayer ceramic capacitor according to the present invention comprises a laminate having a first surface and a second surface that face each other in a stacking direction, a third surface and a fourth surface that face each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface that face each other in a second direction perpendicular to the stacking direction and the first direction, and four external electrodes arranged on the laminate, wherein, where L is the dimension of the multilayer ceramic capacitor in the first direction and W is the dimension of the multilayer ceramic capacitor in the second direction, 0.85≦L / W≦1.00 is satisfied, and the laminate has a first internal electrode having one end exposed on the third surface and the fifth surface and the other end exposed on the fourth surface and the sixth surface, a second internal electrode having one end exposed on the third surface and the sixth surface and the other end exposed on the fourth surface and the fifth surface, and a peripheral electrode, and the peripheral electrode is arranged in a region between the first internal electrode and the third surface to the sixth surface.

[0007] According to the multilayer ceramic capacitor of the present invention, when the dimension of the multilayer ceramic capacitor in the first direction is L and the dimension of the multilayer ceramic capacitor in the second direction is W, 0.85≦L / W≦1.00 is satisfied, and the laminate has a first internal electrode having one end exposed on the third surface and the fifth surface and the other end exposed on the fourth surface and the sixth surface, a second internal electrode having one end exposed on the third surface and the sixth surface and the other end exposed on the fourth surface and the fifth surface, and a peripheral electrode, and the peripheral electrode is disposed in a region between the first internal electrode and the third surface to the sixth surface. Therefore, it is possible to provide a multilayer ceramic capacitor that is thin and can suppress bending of the tetragonal multilayer ceramic capacitor due to steps between each dielectric layer corresponding to the thickness of the internal electrode layers, and can suppress a decrease in mechanical strength. [Effects of the Invention]

[0008] According to the present invention, a thin multilayer ceramic capacitor having a tetragonal crystal structure is provided, which can prevent the multilayer ceramic capacitor from bending and thus prevent a decrease in mechanical strength.

[0009] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2] 1 is a front view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 3] 1 is a side view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 2 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8A] FIG. 8 is a cross-sectional view taken along line VIIIA-VIIIA in FIG. [Figure 8B] FIG. 8 is a cross-sectional view taken along line VIIIB-VIIIB in FIG. [Figure 9] FIG. 2 is an exploded perspective view of the laminate shown in FIG. [Figure 10A] FIG. 4 is a plan view showing another example of a peripheral electrode arranged in the multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 10B] FIG. 4 is a plan view showing another example of a peripheral electrode arranged in the multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 11A] FIG. 4 is a plan view showing another example of a peripheral electrode arranged in the multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 11B] FIG. 4 is a plan view showing another example of a peripheral electrode arranged in the multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 12A] FIG. 4 is a plan view showing another example of a peripheral electrode arranged in the multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 12B] FIG. 4 is a plan view showing another example of a peripheral electrode arranged in the multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 13] FIG. 3 is a cross-sectional view schematically illustrating an example of a multilayer ceramic capacitor according to a first modified example of the first embodiment of the present invention. [Figure 14] FIG. 4 is a cross-sectional view schematically illustrating an example of a multilayer ceramic capacitor according to a second modified example of the first embodiment of the present invention. [Figure 15] FIG. 10 is a cross-sectional view schematically illustrating an example of a multilayer ceramic capacitor according to a third modified example of the first embodiment of the present invention. [Figure 16]FIG. 4 is an external perspective view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 17] FIG. 4 is a front view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 18] 18 is a schematic cross-sectional view taken along line XVIII-XVIII in FIG. 16, illustrating the structure of an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. [Figure 19] FIG. 17 is a cross-sectional view taken along line XIX-XIX in FIG. 16. [Figure 20] FIG. 17 is a cross-sectional view taken along line XX-XX in FIG. [Figure 21] FIG. 17 is a cross-sectional view taken along line XXI-XXI in FIG. 16. [Figure 22A] FIG. 18 is a cross-sectional view taken along line XXIIA-XXIIA in FIG. 17. [Figure 22B] FIG. 18 is a cross-sectional view taken along line XXIIB-XXIIB in FIG. 17. [Figure 23] FIG. 17 is an exploded perspective view of the laminate shown in FIG. [Figure 24] FIG. 10 is an external perspective view, seen from one side, showing an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. [Figure 25] FIG. 10 is an external perspective view, seen from another side, showing an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 24. [Figure 27] FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 24. [Figure 28] FIG. 25 is a cross-sectional view taken along line XXVIII-XXVIII in FIG. 24. [Figure 29] FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 24. DETAILED DESCRIPTION OF THE INVENTION

[0011] A. First Embodiment 1. Multilayer ceramic capacitors Next, an example of the multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0012] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line VV in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1. FIG. 8A is a cross-sectional view taken along line VIIIA-VIIIA in FIG. 2. FIG. 8B is a cross-sectional view taken along line VIIIB-VIIIB in FIG. 2. FIG. 9 is an exploded perspective view of the laminate shown in FIG. 1.

[0013] The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30.

[0014] (Laminate) The laminate 12 has a first surface 12a and a second surface 12b that face in a stacking direction x, a third surface 12c and a fourth surface 12d that face in a first direction y that is perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f that face in a second direction z that is perpendicular to the stacking direction x and the first direction y. The direction connecting the first surface 12a and the second surface 12b of the laminate 12 is the stacking direction x.

[0015] Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. Note that the corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on part or all of the third face 12c, the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0016] In addition, either the first surface 12a or the second surface 12b may have a roughened surface.

[0017] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 include a first internal electrode 16a and a second internal electrode 16b.

[0018] The laminate 12 also has an inner layer portion 18, a first outer layer portion 20a located on the first surface 12a side, and a second outer layer portion 20b located on the second surface 12b side.

[0019] The first outer layer portion 20a is located on the first surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0020] The second outer layer portion 20b is located on the second surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the second surface 12b and the internal electrode 16 closest to the second surface 12b.

[0021] The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0022] The inner layer portion 18 has a first inner electrode 16a having one end exposed to the third surface 12c and the fifth surface 12e and the other end exposed to the fourth surface 12d and the sixth surface 12f, a second inner electrode 16b having one end exposed to the third surface 12c and the sixth surface 12f and the other end exposed to the fourth surface 12d and the fifth surface 12e, and an inner dielectric layer 14a.

[0023] The dielectric layer 14 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics composed primarily of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components. The inner dielectric layer 14a and the outer dielectric layer 14b may be made of the same dielectric material, or may be made of different dielectric materials to separate the functions of the inner layer portion 18 and the outer layer portions 20a and 20b. At least one of Si, Mg, Ba, and Mn may also be added as an additive.

[0024] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it difficult for dielectric breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited thereto, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the layer be made of a material with a high dielectric constant, such as BaTiO3.

[0025] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0026] The thinner the dielectric layer 14, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0027] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 3 to 300, including the first outer layer portion 20a and the second outer layer portion 20b. The thickness of the inner dielectric layer 14a is preferably 0.4 μm to 2.0 μm, and the thickness of the outer dielectric layer 14b is preferably 2.0 μm to 100.0 μm.

[0028] When the direction in which the third surface 12c and the fourth surface 12d face each other is defined as a first direction y and the direction in which the fifth surface 12e and the sixth surface 12f face each other is defined as a second direction z, the dimension L of the laminate 12 in the first direction y and the dimension W of the laminate 12 in the second direction z satisfy the condition 0.85≦L / W≦1.00. In other words, the laminate 12 has a substantially tetragonal shape.

[0029] (Internal electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0030] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0031] The first internal electrode 16a is extended to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extension electrode portion 24a, and is extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the second extension electrode portion 24b. The width of the first extension electrode portion 24a extended to the third surface 12c may be approximately equal to the width of the first extension electrode portion 24a extended to the fifth surface 12e, and the width of the second extension electrode portion 24b extended to the fourth surface 12d may be approximately equal to the width of the second extension electrode portion 24b extended to the sixth surface 12f.

[0032] Furthermore, the first internal electrode 16a is continuously extended to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extension electrode portion 24a, and is continuously extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the second extension electrode portion 24b, but this is not limited to this and the electrode may be extended discontinuously.

[0033] The second internal electrode 16b is arranged on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is arranged. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0034] The second internal electrode 16b is extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d. The width of the third extension electrode portion 24c extended to the third surface 12c may be approximately equal to the width of the third extension electrode portion 24c extended to the sixth surface 12f, and the width of the fourth extension electrode portion 24d extended to the fourth surface 12d may be approximately equal to the width of the fourth extension electrode portion 24d extended to the fifth surface 12e.

[0035] Furthermore, the second internal electrode 16b is continuously extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is continuously extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d, but this is not limited to this and the second internal electrode 16b may be extended discontinuously.

[0036] Furthermore, when the multilayer ceramic capacitor 10 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a intersects with a straight line connecting the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0037] As shown in FIG. 7, the laminate 12 also includes a side portion (W gap) 26a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22b of the second internal electrode 16b and the third surface 12c, and a side portion (W gap) 26b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22a of the first internal electrode 16a and the fourth surface 12d.

[0038] Furthermore, as shown in FIG. 6, the laminate 12 includes an end portion (L gap) 27a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22b of the second internal electrode 16b and the fifth surface 12e, and a side portion (L gap) 27b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the sixth surface 12f.

[0039] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, but not limited to, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys. The first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0040] Furthermore, by including Sn in the first internal electrode 16a and the second internal electrode 16b, the potential barrier height at the interface between the internal electrode 16 and the dielectric layer 14 is increased, and electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b.

[0041] The total number of the first internal electrodes 16a and the second internal electrodes 16b is preferably 3 to 300. The thickness of the first internal electrodes 16a and the second internal electrodes 16b is not particularly limited, but is preferably 0.2 μm to 2.0 μm, for example.

[0042] The laminate 12 of the multilayer ceramic capacitor 10 may have the following configuration.

[0043] In the multilayer ceramic capacitor 10, the third surface 12c to the sixth surface 12f of the laminate 12 may be curved to form a concave shape toward the center of the laminate 12 when viewed in the stacking direction x. In other words, the third surface 12c to the sixth surface 12f of the laminate 12 may be warped. In this case, the center of the curvature or warpage is preferably near the center of the third surface 12c to the sixth surface 12f. This allows the distance between adjacent external electrodes 30, which will be described later, to be increased, thereby reducing the risk of electrical conduction between the external electrodes 30.

[0044] Furthermore, when viewed in at least one of the first direction y and the second direction z, the region where the internal electrode 16 is drawn out onto the third surface 12c to the sixth surface 12f preferably has a curved shape from the first surface 12a to the second surface 12b, thereby increasing the exposed area of ​​the internal electrode 16 and improving the contact area between the internal electrode 16 and the external electrode 30.

[0045] (surrounding electrodes) The inner layer portion 18 of the laminate 12 further has a first peripheral electrode 28 and a second peripheral electrode 29. The first peripheral electrode 28 is disposed around the first internal electrode 16a. The second peripheral electrode 29 is disposed around the second internal electrode 16b.

[0046] The first peripheral electrode 28 has one first peripheral electrode 28a and the other first peripheral electrode 28b.

[0047] The first peripheral electrodes 28a, 28b are alternately stacked with the inner dielectric layers 14a and are arranged on the same plane as the first internal electrode 16a arranged on the inner dielectric layer 14a. As shown in Fig. 8A, each of the first peripheral electrodes 28a, 28b is arranged spaced apart from the first internal electrode 16a.

[0048] The first peripheral electrode 28a is disposed in a region between the first internal electrode 16a and the third and sixth surfaces 12c, 12f. One end of the first peripheral electrode 28a is connected to the first lead electrode portion 24a of the first internal electrode 16a, and the other end of the first peripheral electrode 28a is connected to the second lead electrode portion 24b of the first internal electrode 16a. The first peripheral electrode 28b is disposed in a region between the first internal electrode 16a and the fourth and fifth surfaces 12d, 12e. One end of the first peripheral electrode 28b is connected to the first lead electrode portion 24a of the first internal electrode 16a, and the other end of the first peripheral electrode 28a is connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0049] The distance t between the first peripheral electrode 28a and the third surface 12c at the closest point a11 is preferably 5.0 μm or more and 20 μm or less, and the distance t a12 is preferably 5.0 μm or more and 20 μm or less. The distance t between the first peripheral electrode 28b and the fifth surface 12e is the closest to the first peripheral electrode 28b. b11 is preferably 5.0 μm or more and 20 μm or less, and the distance t b12 It is preferable that the thickness is 5.0 μm or more and 20 μm or less, which can increase the distance from moisture that penetrates from the outside, thereby suppressing deterioration of moisture resistance.

[0050] The shortest distance t between the first peripheral electrode 28a and the first internal electrode 16a on the third surface 12c side a21 is preferably 20 μm or more and 80 μm or less, and the shortest distance t a22 is preferably 20 μm or more and 80 μm or less. The shortest distance t between the first peripheral electrode 28b and the first internal electrode 16a on the fifth surface 12e side is b21is preferably 20 μm or more and 80 μm or less, and the shortest distance t b22 The thickness is preferably 20 μm or more and 80 μm or less, which prevents electrical conduction between the first peripheral electrodes 28a, 28b, which are close to the outside, and the first internal electrode 16a, thereby suppressing deterioration in insulation.

[0051] The width w of the first peripheral electrode 28a on the third surface 12c side a11 is the width w between the first internal electrode 16a and the third surface 12c. a21 The width w of the first peripheral electrode 28a on the sixth surface 12f side is preferably 1.0% or more and 30% or less of the width w of the first peripheral electrode 28a on the sixth surface 12f side. a12 is the width w between the first internal electrode 16a and the sixth surface 12f. a22 It is preferable that the content is 1.0% or more and 30% or less of the above. The width w of the first peripheral electrode 28b on the fifth surface 12e side b11 is the width w between the first internal electrode 16a and the fifth surface 12e. b21 The width w of the first peripheral electrode 18b on the fourth surface 12d side is preferably 1.0% or more and 30% or less of the width w of the first peripheral electrode 18b on the fourth surface 12d side. b12 is the width w between the first internal electrode 16a and the fourth surface 12d. b22 It is preferable that the content is 1.0% or more and 30% or less of the above.

[0052] The difference in thickness between the first internal electrode 16a and the first peripheral electrodes 28a, 28b in the stacking direction is preferably 90% or more and 110% or less. This makes it possible to eliminate the difference in thickness caused by the first internal electrode 16a and the second internal electrode 16b. This makes it possible to suppress structural defects caused by peeling between the dielectric layers 14 of the laminate 12.

[0053] Furthermore, it is preferable that the first internal electrode 16a and the first peripheral electrodes 28a, 28b have the same main component. If the first internal electrode 16a and the first peripheral electrodes 28a, 28b have the same main component, structural defects due to differences in internal shrinkage can be suppressed during the firing process in manufacturing the multilayer ceramic capacitor 10.

[0054] Furthermore, the same metal components as those of the first internal electrode 16a and the first peripheral electrodes 28a, 28b may be present in the region between the first peripheral electrodes 28a, 28b and the first internal electrode 16a.

[0055] The second peripheral electrode 29 has one second peripheral electrode 29a and the other second peripheral electrode 29b.

[0056] The second peripheral electrodes 29a, 29b are alternately stacked with the inner dielectric layers 14a and are arranged on the same plane as the second internal electrode 16b arranged on the inner dielectric layer 14a. As shown in Fig. 8B, each of the second peripheral electrodes 29a, 29b is arranged spaced apart from the second internal electrode 16b.

[0057] The second peripheral electrode 29a is disposed in a region between the second internal electrode 16b and the third and fifth surfaces 12c, 12e. One end of the second peripheral electrode 29a is connected to the third lead electrode portion 24c of the second internal electrode 16b, and the other end of the second peripheral electrode 29a is connected to the fourth lead electrode portion 24d of the second internal electrode 16b. The second peripheral electrode 29b is disposed in a region between the second internal electrode 16b and the fourth and sixth surfaces 12d, 12f. One end of the second peripheral electrode 29b is connected to the third lead electrode portion 24c of the second internal electrode 16b, and the other end of the second peripheral electrode 29b is connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0058] The distance t between the second peripheral electrode 29a and the part closest to the third surface 12c a13 is preferably 5.0 μm or more and 20 μm or less, and the distance t a14 is preferably 5.0 μm or more and 20 μm or less. The distance t between the second peripheral electrode 29b and the fourth surface 12d is the closest to the second peripheral electrode 29b. b13 is preferably 5.0 μm or more and 20 μm or less, and the distance tb14 It is preferable that the thickness is 5.0 μm or more and 20 μm or less, which can increase the distance from moisture that penetrates from the outside, thereby suppressing deterioration of moisture resistance.

[0059] The shortest distance t between the second peripheral electrode 29a and the second internal electrode 16b on the third surface 12c side a23 is preferably 20 μm or more and 80 μm or less, and the shortest distance t a24 is preferably 20 μm or more and 80 μm or less. The shortest distance t between the second peripheral electrode 29b and the second internal electrode 16b on the sixth surface 12f side b23 is preferably 20 μm or more and 80 μm or less, and the shortest distance t b24 It is preferable that the thickness is 20 μm or more and 80 μm or less. This makes it possible to prevent electrical conduction between the second peripheral electrodes 29a, 29b, which are close to the outside, and the second internal electrode 16b, thereby suppressing deterioration in insulation.

[0060] The width w of the second peripheral electrode 29a on the third surface 12c side a13 is the width w between the second internal electrode 16b and the third surface 12c. a23 The width w of the second peripheral electrode 29a on the fifth surface 12e side is preferably 1.0% or more and 30% or less of the width w of the second peripheral electrode 29a on the fifth surface 12e side. a14 is the width w between the second internal electrode 16b and the fifth surface 12e. a24 It is preferable that the content is 1.0% or more and 30% or less of the above. The width w of the second peripheral electrode 29b on the sixth surface 12f side b13 is the width w between the second internal electrode 16b and the sixth surface 12f. b23 The width w of the second peripheral electrode 29b on the fourth surface 12d side is preferably 1.0% or more and 30% or less of the width w of the second peripheral electrode 29b on the fourth surface 12d side. b14 is the width w between the second internal electrode 16b and the fourth surface 12d. b24 It is preferable that the content is 1.0% or more and 30% or less of the above.

[0061] The difference in thickness between the second internal electrode 16b and the second peripheral electrodes 29a, 29b in the stacking direction is preferably 90% or more and 110% or less. This makes it possible to eliminate the step caused by the thickness of the first internal electrode 16a and the second internal electrode 16b. Therefore, structural defects due to peeling between the dielectric layers 14 in the laminate 12 can be suppressed.

[0062] Furthermore, the second internal electrode 16b and the second peripheral electrodes 29a, 29b preferably have the same main component, which can prevent structural defects due to differences in internal shrinkage during the firing process in manufacturing the multilayer ceramic capacitor 10.

[0063] Furthermore, the same metal component as that of the second internal electrode 16b and the second peripheral electrodes 29a, 29b may be present in the region between the second peripheral electrodes 29a, 29b and the second internal electrode 16b.

[0064] The peripheral electrodes 28 and 29 are not limited to the structures shown in FIGS. 8A and 8B, but may have the structures described below.

[0065] As shown in FIG. 10A, the first peripheral electrodes 28a, 28b do not have to be arranged on the line connecting the intersection of the third surface 12c and the sixth surface 12f and the intersection of the fourth surface 12d and the fifth surface 12e. 10A, one of the first peripheral electrodes 28a may be further divided into first peripheral electrode 28a1 and first peripheral electrode 28a2. In this case, first peripheral electrode 28a1 is disposed on side portion 26a of stack 12 located on the third surface 12c side. Furthermore, first peripheral electrode 28a2 is disposed on end portion 27b of stack 12 located on the sixth surface 12f side. The other first peripheral electrode 28b may be further divided into first peripheral electrode 28b1 and first peripheral electrode 28b2. In this case, first peripheral electrode 28b1 is disposed at end 27a of stack 12 located on the fifth surface 12e side. First peripheral electrode 28b2 is disposed at side portion 26b of stack 12 located on the fourth surface 12d side.

[0066] Furthermore, as shown in FIG. 10A, in the direction connecting the intersection of the third surface 12c and the sixth surface 12f and the intersection of the fourth surface 12d and the fifth surface 12e, the first peripheral electrodes 28a, 28b do not have to be arranged 1.0 μm or more and 10 μm or less from the corner located at the longest part of the length of the first internal electrode 16a.

[0067] Also, as shown in FIG. 10B, the second peripheral electrodes 29a, 29b do not have to be arranged on the line connecting the intersection of the third surface 12c and the fifth surface 12e and the intersection of the fourth surface 12d and the sixth surface 12f. 10B, one of the second peripheral electrodes 29a may be further divided into a second peripheral electrode 29a1 and a second peripheral electrode 29a2. In this case, the second peripheral electrode 29a1 is disposed on the side portion 26a of the laminate 12 that faces the third surface 12c. The second peripheral electrode 29a2 is disposed on the end portion 27a of the laminate 12 that faces the fifth surface 12e. The other second peripheral electrode 29b may be further divided into second peripheral electrode 29b1 and second peripheral electrode 29b2. In this case, second peripheral electrode 29b1 is disposed at end 27b of stack 12 located on the sixth surface 12f side. Second peripheral electrode 29b2 is disposed at side portion 26b of stack 12 located on the fourth surface 12d side.

[0068] Furthermore, as shown in FIG. 10B, in the direction connecting the intersection of the third surface 12c and the fifth surface 12e and the intersection of the fourth surface 12d and the sixth surface 12f, the second peripheral electrodes 29a, 29b may not be arranged 1.0 μm or more and 10 μm or less from the corner located at the longest part of the length of the second internal electrode 16b.

[0069] Moreover, the peripheral electrodes 28 and 29 may have the following structure. 11A, the first lead electrode portion 24a of the first internal electrode 16a exposed on the third surface 12c and the fifth surface 12e may not be connected to one end of the first peripheral electrode 28a. In this case, the distance l between the first lead electrode portion 24a of the first internal electrode 16a and one end of the first peripheral electrode 28a is a11 is preferably 1.0 μm or more and 10 μm or less. In addition, the second lead electrode portion 24b of the first internal electrode 16a exposed on the fourth surface 12d and the sixth surface 12f may not be connected to the other end of the first peripheral electrode 28b. In this case, the distance l between the second lead electrode portion 24b of the first internal electrode 16a and the other end of the first peripheral electrode 28b is a12 It is preferable that the thickness is 1.0 μm or more and 10 μm or less.

[0070] Similarly, the first lead electrode portion 24a of the first internal electrode 16a exposed on the third surface 12c and the fifth surface 12e may not be connected to one end of the first peripheral electrode 28b. In this case, the distance l between the first lead electrode portion 24a of the first internal electrode 16a and one end of the first peripheral electrode 28b is b11 is preferably 1.0 μm or more and 10 μm or less. In addition, the second lead electrode portion 24b of the first internal electrode 16a exposed on the fourth surface 12d and the sixth surface 12f may not be connected to the other end of the first peripheral electrode 28b. In this case, the distance l between the second lead electrode portion 24b of the first internal electrode 16a and the other end of the first peripheral electrode 28b is b12 is preferably 1.0 μm or more and 10 μm or less.

[0071] 11B, the third lead electrode portion 24c of the second internal electrode 16b exposed on the third surface 12c and the sixth surface 12f may not be connected to one end of the second peripheral electrode 29a. In this case, the distance l between the third lead electrode portion 24c of the second internal electrode 16b and one end of the second peripheral electrode 29a is a21is preferably 1.0 μm or more and 10 μm or less. In addition, the fourth lead electrode portion 24d of the second internal electrode 16b exposed on the fourth surface 12d and the fifth surface 12e may not be connected to the other end of the second peripheral electrode 29b. In this case, the distance l between the fourth lead electrode portion 24d of the second internal electrode 16b and the other end of the second peripheral electrode 29b is a22 is preferably 1.0 μm or more and 10 μm or less.

[0072] Similarly, the third lead electrode portion 24c of the second internal electrode 16b exposed on the third surface 12c and the sixth surface 12f may not be connected to one end of the second peripheral electrode 29b. In this case, the distance l between the third lead electrode portion 24c of the second internal electrode 16b and one end of the second peripheral electrode 29b is b21 is preferably 1.0 μm or more and 10 μm or less. In addition, the fourth lead electrode portion 24d of the second internal electrode 16b exposed on the fourth surface 12d and the fifth surface 12e may not be connected to the other end of the second peripheral electrode 29b. In this case, the distance l between the fourth lead electrode portion 24d of the second internal electrode 16b and the other end of the second peripheral electrode 29b is b22 is preferably 1.0 μm or more and 10 μm or less.

[0073] Furthermore, the peripheral electrodes 28 and 29 may have the following structure. 12A, first peripheral electrode 28a may be configured with a plurality of peripheral electrodes 281-287, which may be arranged discontinuously. In first peripheral electrode 28a, the plurality of peripheral electrodes 281-284 may be arranged discontinuously in second direction z. Furthermore, in first peripheral electrode 28a, the plurality of peripheral electrodes 284-287 may be arranged discontinuously in first direction y. The first peripheral electrode 28b is made up of a plurality of peripheral electrodes 288 to 28 14 The first peripheral electrode 28b may be configured by a plurality of peripheral electrodes 288 to 28 11 may be arranged discontinuously in the first direction y.11 ~28 14 may be arranged discontinuously in the second direction z. This makes it possible to prevent moisture from reaching the first internal electrode 16a through the first peripheral electrodes 28a, 28b when the first peripheral electrodes 28a, 28b are arranged discontinuously.

[0074] In addition, when the first peripheral electrodes 28a are arranged discontinuously, the distance d between the adjacent peripheral electrodes 281 to 287 is 11 In addition, when the first peripheral electrodes 28b are arranged discontinuously, the distance between the adjacent peripheral electrodes 288 to 288 is preferably 1.0 μm or more and 10 μm or less. 14 Distance between the spaces d 12 is preferably 1.0 μm or more and 10 μm or less. This has the effect of suppressing steps because the periphery of the first internal electrode 16a is sufficiently filled even if the first peripheral electrodes 28a, 28b are arranged discontinuously.

[0075] 12B, the second peripheral electrode 29a may be configured with a plurality of peripheral electrodes 291 to 297, which may be arranged discontinuously. In the second peripheral electrode 29a, the plurality of peripheral electrodes 291 to 294 may be arranged discontinuously in the second direction z. In the second peripheral electrode 29a, the plurality of peripheral electrodes 294 to 297 may be arranged discontinuously in the first direction y. The second peripheral electrode 29b is made up of a plurality of peripheral electrodes 298 to 29 14 The second peripheral electrode 29b may be configured by a plurality of peripheral electrodes 298 to 299. 11 may be arranged discontinuously in the first direction y. 11 ~29 14 may be arranged discontinuously in the second direction z. This makes it possible to prevent moisture from reaching the second internal electrode 16b through the second peripheral electrodes 29a and 29b when the second peripheral electrodes 29a and 29b are arranged discontinuously.

[0076] In addition, when the second peripheral electrodes 29a are arranged discontinuously, the distance d between the adjacent peripheral electrodes 291 to 297 is 21 In addition, when the second peripheral electrodes 29b are arranged discontinuously, the distance between the adjacent peripheral electrodes 298 to 299 is preferably 1.0 μm or more and 10 μm or less. 14 Distance between the spaces d 22 is preferably 1.0 μm or more and 10 μm or less. This has the effect of suppressing steps because the periphery of the second internal electrode 16b is sufficiently filled even if the second peripheral electrodes 29a, 29b are arranged discontinuously.

[0077] (external electrode) As shown in FIGS. 1 to 7, external electrodes 30 are disposed on the laminate 12. The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0078] The first external electrode 30a is disposed on the third surface 12c and the fifth surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a and a portion of the second surface 12b. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0079] The second external electrode 30b is disposed on the fourth surface 12d and the sixth surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0080] The third external electrode 30c is disposed on the third surface 12c and the sixth surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0081] The fourth external electrode 30d is disposed on the fourth surface 12d and the fifth surface 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0082] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode 16a and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode 16b, thereby realizing the characteristics of a capacitor.

[0083] Each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c and the fourth external electrode 30d preferably has a thin film layer 32, an underlayer plating layer 34 and a surface plating layer 36.

[0084] In other words, the first external electrode 30a preferably has a first thin film layer 32a, a first under-layer plating layer 34a, and a first surface plating layer 36a. The second external electrode 30b preferably has a second thin film layer 32b, a second under-layer plating layer 34b, and a second surface plating layer 36b. The third external electrode 30c preferably has a third thin film layer 32c, a third under-layer plating layer 34c, and a third surface plating layer 36c. The fourth external electrode 30d preferably has a fourth thin film layer 32d, a fourth under-layer plating layer 34d, and a fourth surface plating layer 36d.

[0085] (thin film layer) The thin film layer 32 includes a first thin film layer 32a, a second thin film layer 32b, a third thin film layer 32c, and a fourth thin film layer 32d.

[0086] The first thin film layer 32a is arranged so as to cover a portion of the first surface 12a and the second surface 12b of the laminate 12 on the third surface 12c side and the fifth surface 12e side, and not to cover the third surface 12c and the fifth surface 12e of the laminate 12.

[0087] The second thin film layer 32b is arranged so as to cover a portion of the first surface 12a and the second surface 12b of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side, and not to cover the fourth surface 12d and the sixth surface 12f.

[0088] The third thin film layer 32c is arranged so as to cover a portion of the first surface 12a and the second surface 12b of the laminate 12 on the third surface 12c side and the sixth surface 12f side, and not to cover the third surface 12c and the sixth surface 12f.

[0089] The fourth thin film layer 32d is arranged so as to cover a portion of the first surface 12a and the second surface 12b of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side, and not to cover the fourth surface 12d and the fifth surface 12e.

[0090] Each of the first to fourth thin film layers 32a to 32d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 32a to 32d in the direction connecting the first surface 12a and the second surface 12b of the laminate 12 to be 1 μm or less, which allows the dimension of the multilayer ceramic capacitor 10 in the stacking direction x to be sufficiently small, thereby allowing the multilayer ceramic capacitor 10 to have a low profile.

[0091] The dimensions of the first to fourth thin film layers 32a to 32d in the stacking direction x can be measured as follows. That is, when the thin film layers are formed by depositing metal particles, a fluorescent X-ray device can be used to convert the thickness from the concentration of a predetermined element using a calibration curve method for the relevant metal species. Alternatively, a cross section of a component obtained by FIB can be observed using a scanning microscope, and the thickness can be measured from the actual observation image.

[0092] Furthermore, when the first to fourth thin film layers 32a to 32d are formed by a thin film formation method, these thin film layers are preferably made of a metal such as Cu or Ni.

[0093] The thin film layers 32 of the multilayer ceramic capacitor 10 shown in Fig. 1 are formed by depositing metal particles by sputtering. In this case, if the thickness of the thin film layers 32 is 1 µm or less, the dimension in the stacking direction x can be made sufficiently small.

[0094] The first to fourth thin film layers 32a to 32d can be configured taking into consideration their respective functions. For example, it is preferable that the main component be NiCr or NiCu in consideration of adhesion to the laminate 12. The first to fourth thin film layers 32a to 32d may be multiple layers or may have a two-layer structure of NiCr and NiCu.

[0095] The thin film layer 32 may be formed by screen printing or the like and contain a dielectric material and a metal component. This allows the thin film layer 32 to adhere to the ceramic of the laminate 12, further improving the adhesive strength between the laminate 12 and the external electrode 30. In this case, the thin film layer 32 may contain a ceramic component having the same main component as the inner dielectric layer 14a in addition to the metal component. The ceramic component in the thin film layer 32 reduces the difference in thermal expansion coefficient between the laminate 12 and the thin film layer 32, thereby alleviating stress on the thin film layer 32. However, the metal component may be other metal components besides Cu and Ni, or a glass component may be included in addition to the ceramic component. Examples of the glass component include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Other metal components may include Mg, Cr, Sr, Al, Na, Fe, etc. The thin film layer 32 may also have a discontinuous shape. The term "discontinuous" means that the film is formed discontinuously when viewed in a direction perpendicular to the longitudinal direction.

[0096] For example, when forming the thin film layer 32 using a material containing ceramic, one method is to polish the cross section, then take a cross section photograph using a digital microscope (Keyence Corporation: VHX-5000), and use the cross section photograph to calculate the thickness, etc. Another method is to measure the thickness, etc., from the actual observation image of the cross section of the part taken by FIB using a scanning microscope.

[0097] (Undercoat layer) The lower plating layer 34 includes a first lower plating layer 34a, a second lower plating layer 34b, a third lower plating layer 34c, and a fourth lower plating layer 34d.

[0098] The first underlayer plating layer 34 a is disposed so as to cover the first thin film layer 32 a and the third and fifth surfaces 12 c and 12 e of the laminate 12 . The second underlayer plating layer 34b is disposed so as to cover the second thin film layer 32b and the fourth and sixth faces 12d and 12f of the laminate 12. The third under-plated layer 34c is disposed so as to cover the third thin film layer 32c and the third and sixth faces 12c and 12f of the laminate 12. The fourth underlayer plating layer 34d is disposed so as to cover the fourth thin film layer 32d and the fourth and fifth surfaces 12d and 12e of the laminate 12.

[0099] The lower plating layer 34 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The lower plating layer 34 is preferably Cu plating. In this case, the lower plating layer 34 may be directly connected to the internal electrode 16. In addition to this, another Cu plating layer with a different particle size may be provided.

[0100] The thickness of the lower plating layer 34 is preferably, for example, not less than 1 μm and not more than 10 μm.

[0101] (surface plating layer) The surface plating layer 36 includes a first surface plating layer 36a, a second surface plating layer 36b, a third surface plating layer 36c, and a fourth surface plating layer 36d.

[0102] The first surface plating layer 36a is disposed so as to cover the first under-layer plating layer 34a. The second surface plating layer 36b is disposed so as to cover the second under-layer plating layer 34b. The third surface plating layer 36c is disposed so as to cover the third under-layer plating layer 34c. The fourth surface plating layer 36d is disposed so as to cover the fourth under-layer plating layer 34d.

[0103] The surface plating layer 36 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0104] The thickness of the surface plating layer 36 is preferably, for example, not less than 0.5 μm and not more than 10 μm.

[0105] The plating layer may be composed of only the lower plating layer 34. In this case, the first lower plating layer 34a is disposed so as to cover the first thin film layer 32a, and the second lower plating layer 34b is disposed so as to cover the second thin film layer 32b. Similarly, the third lower plating layer 34c is disposed so as to cover the third thin film layer 32c, and the fourth lower plating layer 34d is disposed so as to cover the fourth thin film layer 32d.

[0106] The plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0107] The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0108] The thickness of each plating layer is preferably 0.5 μm or more and 10.0 μm or less.

[0109] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the first direction y is defined as dimension L, the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the stacking direction x is defined as dimension T, and the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the second direction z is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 0.2 mm to 3.2 mm, the T dimension in the stacking direction x is 0.04 mm to 0.22 mm, and the W dimension in the second direction z is 0.2 mm to 3.2 mm. The dimensions of the multilayer ceramic capacitor 10 are preferably 0.85≦L / W≦1.00. This allows the laminate 12 to have a substantially tetragonal shape, improving the flexibility of mounting.

[0110] In the multilayer ceramic capacitor 10 shown in FIG. 1, the dimension L in the first direction y and the dimension W in the second direction z of the laminate 12 satisfy the condition 0.85≦L / W≦1.00, the first peripheral electrode 28a is arranged in the region between the first internal electrode 16a and the third surface 12c and the sixth surface 12f, and the first peripheral electrode 28b is arranged in the region between the first internal electrode 16a and the fourth surface 12d and the fifth surface 12e. Therefore, it is possible to provide a multilayer ceramic capacitor that is thin and can suppress bending of the tetragonal multilayer ceramic capacitor 10 due to steps between each dielectric layer that are equivalent to the thickness of the internal electrode layers, thereby preventing a decrease in mechanical strength.

[0111] 2. Variations (1) First Modification Next, an example of a multilayer ceramic capacitor 10A according to a first modified example of the first embodiment of the present invention will be described. Fig. 13 is a cross-sectional view schematically showing an example of a multilayer ceramic capacitor according to a first modified example of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 7, and detailed descriptions thereof will be omitted.

[0112] In the multilayer ceramic capacitor 10A according to the first modification, the thin film layers 32 are formed so as to extend around to each side surface of the laminate 12, as shown in FIG.

[0113] Specifically, the first thin film layer 32a of the first external electrode 30a covers a portion of the first surface 12a and the second surface 12b, and is formed to wrap around from the first surface 12a and the second surface 12b to cover the third surface 12c and the fifth surface 12e. In addition, the second thin film layer 32b of the second external electrode 30b is formed so as to cover a portion of the first surface 12a and the second surface 12b, and to wrap around from the first surface 12a and the second surface 12b to cover the fourth surface 12d and the sixth surface 12f. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0114] The first thin film layer 32a is directly and electrically connected to the first lead electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c and the fifth surface 12e, and the second thin film layer 32b is directly and electrically connected to the second lead electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d and the sixth surface 12f. Although not shown, the third thin film layer 32c is directly electrically connected to the third extraction electrode portion 24c of the second internal electrode 16b, and the fourth thin film layer 32d is directly electrically connected to the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0115] The first thin film layer 32a may be formed so that the thin film layers formed on the first surface 12a and the second surface 12b are continuously connected to the thin film layers formed on the third surface 12c and the fifth surface 12e, or may be formed discontinuously. The second thin film layer 32b may be formed so that the thin film layers formed on the first surface 12a and the second surface 12b are continuously connected to the thin film layers formed on the fourth surface 12d and the sixth surface 12f, or may be formed discontinuously. The same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0116] The multilayer ceramic capacitor 10A according to the first embodiment shown in FIG. 13 has the same effects as the multilayer ceramic capacitor 10 described above.

[0117] (2) Second Modification Next, an example of a multilayer ceramic capacitor 10B according to a second modified example of the first embodiment of the present invention will be described. Fig. 14 is a cross-sectional view showing an example of a multilayer ceramic capacitor according to the second modified example of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 7, and detailed descriptions thereof will be omitted.

[0118] As shown in FIG. 14, the external electrodes 30 of the multilayer ceramic capacitor 10B according to the second modified example of the first embodiment include a direct plating layer 33.

[0119] (direct plating layer) The first external electrode 30a includes a first direct plating layer 33a, the second external electrode 30b includes a second direct plating layer 33b, and although not shown, the third external electrode 30c includes a third direct plating layer, and the fourth external electrode 30d includes a fourth direct plating layer.

[0120] The first direct plating layer 33a is disposed so as to cover a portion of each of the third surface 12c and the fifth surface 12e of the laminate 12, as well as the ridge portion sandwiched therebetween. The first direct plating layer 33a is electrically connected directly to the first extraction electrode portion 24a of the first internal electrode 16a. The second direct plating layer 33b is disposed so as to cover a portion of each of the fourth surface 12d and the sixth surface 12f of the laminate 12, as well as the ridge portion sandwiched therebetween. The second direct plating layer 33b is electrically connected directly to the second extraction electrode portion 24b of the first internal electrode 16a. Although not shown, the same applies to the third direct plating layer of the third external electrode 30c and the fourth direct plating layer of the fourth external electrode 30d.

[0121] It is preferable that the upper end of the first direct plating layer 33a of the first external electrode 30a is positioned so as to overlap the underside of the first thin film layer 32a on the ridge formed by the first surface 12a and the third and fifth surfaces 12c and 12e of the laminate 12. It is preferable that the upper end of the second direct plating layer 33b of the second external electrode 30b is positioned so as to overlap the underside of the second thin film layer 32b on the ridge formed by the first surface 12a and the fourth and sixth surfaces 12d and 12f of the laminate 12. Although not shown, the same applies to the third direct plating layer of the third external electrode 30c and the fourth direct plating layer of the fourth external electrode 30d.

[0122] Note that a portion of the first direct plating layer 33a may be disposed so as to extend around to the second surface 12b, and a portion of the second direct plating layer 33b may be disposed so as to extend around to the second surface 12b. Also, a portion of the third direct plating layer and a portion of the fourth direct plating layer may be disposed so as to extend around to the second surface 12b.

[0123] The upper ends of the first direct plating layer 33a and the second direct plating layer 33b may be spaced apart from the first thin film layer 32a and the second thin film layer 32b, respectively. The upper ends of the third direct plating layer and the fourth direct plating layer may be spaced apart from the third thin film layer 32c and the fourth thin film layer 32d, respectively.

[0124] The direct plating layer 33 is not particularly limited as long as it contains, as a main metal component, at least one metal selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. For example, when the first internal electrode 16a and the second internal electrode 16b are formed using Ni, it is preferable to use Cu plating as the direct plating layer 33, which has good bonding properties with Ni.

[0125] The direct plating layer 33 is formed by plating growing from the internal electrode 16 .

[0126] The thickness of each direct plating layer 33 is preferably 0.5 μm or more and 10.0 μm or less.

[0127] The multilayer ceramic capacitor 10B according to the first embodiment shown in FIG. 14 has the same effects as the multilayer ceramic capacitor 10 described above. That is, by forming the plating layer 33 directly on each side surface of the laminate 12, the thickness in the lamination direction of the external electrodes 30 formed on the first surface 12a and the second surface 12b can be further reduced, thereby providing a multilayer ceramic capacitor with an even lower profile without impairing mountability during mounting.

[0128] (3) Third Modification Next, a multilayer ceramic capacitor 10C according to a third modified example of the first embodiment of the present invention will be described. Fig. 15 is a cross-sectional view showing an example of a multilayer ceramic capacitor according to the third modified example of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 7, and detailed descriptions thereof will be omitted.

[0129] The external electrodes 30 of the multilayer ceramic capacitor 10C according to the third modification do not include a plating layer and are composed of a plurality of thin film layers. In the multilayer ceramic capacitor 10C shown in Fig. 15, the first external electrode 30a does not include a plating layer and is composed of only four thin film layers 32a1-32a4, and the second external electrode 30b does not include a plating layer and is composed of only four thin film layers 32b1-32b4.

[0130] In the first external electrode 30a, a thin film layer 32a1 is formed so as to wrap around and cover the first surface 12a, the third surface 12c, and the fifth surface 12e. Then, a thin film layer 32a2, a thin film layer 32a3, and a thin film layer 32a4 are formed in this order on the surface of the thin film layer 32a1. In the second external electrode 30b, a thin film layer 32b1 is formed so as to wrap around and cover the first surface 12a to the fourth surface 12d and the sixth surface 12f. Then, a thin film layer 32b2, a thin film layer 32b3, and a thin film layer 32b4 are formed in this order on the surface of the thin film layer 32b1. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0131] In the first external electrode 30a, the respective edge portions of the laminate 12 of the four thin film layers 32a1-32a4 near the center may or may not be formed to cover the respective edge portions of the lower layers. Similarly, in the second external electrode 30b, the respective edge portions of the laminate 12 of the four thin film layers 32b1-32b4 near the center may or may not be formed to cover the respective edge portions of the lower layers. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0132] The multilayer ceramic capacitor 10C according to the first embodiment shown in FIG. 15 has the same effects as the multilayer ceramic capacitor 10 described above, and also has the following effects. That is, the multilayer ceramic capacitor 10C does not include a plating layer, and the first external electrode 30a is composed only of thin film layers 32a1 to 32a4, the second external electrode 30b is composed only of thin film layers 32b1 to 32b4, and in addition, the third external electrode 30c and the fourth external electrode 30d have a similar configuration, thereby reducing the T dimension in the stacking direction x, the L dimension in the first direction y, and the W dimension in the second direction z, and thereby making it possible to reduce the dimensions of the multilayer ceramic capacitor.

[0133] 3. Manufacturing method of multilayer ceramic capacitors A method for manufacturing the multilayer ceramic capacitor according to the first embodiment will be described below.

[0134] First, a dielectric sheet, a conductive paste for the internal electrodes, and a conductive paste for the peripheral electrodes are prepared. The dielectric sheet, the conductive paste for the internal electrodes, and the conductive paste for the peripheral electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0135] Next, conductive paste for the internal electrodes and conductive paste for the peripheral electrodes are printed in predetermined patterns on the dielectric sheets by, for example, inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are formed, and a dielectric sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are formed. Thereafter, the sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are printed and the sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are printed are laminated to form the portion that becomes the inner layer portion 18.

[0136] In printing the patterns using each conductive paste, first, the patterns using the conductive paste for the internal electrodes are printed, and then the patterns using the conductive paste for the peripheral electrodes are printed.

[0137] Furthermore, for example, when forming the printing pattern of the internal electrodes by gravure printing, the desired internal electrodes can be formed by designing the gravure plate used in the gravure printing to the graphic pattern of the first internal electrode and then modifying the structure corresponding to the graphic pattern of the second internal electrode. When forming the printing pattern of the peripheral electrodes by gravure printing, the desired peripheral electrodes can be formed by designing the gravure plate used in the gravure printing to the graphic pattern of the first peripheral electrode and then modifying the structure corresponding to the graphic pattern of the second peripheral electrode. In this case, the thickness in the stacking direction x can be changed by modifying the grooves in the gravure plate, and the shape of the peripheral electrodes in this configuration can be changed by modifying the groove width of the gravure plate.

[0138] Furthermore, when forming the printing pattern of the internal electrode layer by screen printing, the desired internal electrode can be formed by designing the screen printing mask to the graphic pattern of the first internal electrode and changing the main structure corresponding to the graphic pattern of the second internal electrode. Also, when forming the printing pattern of the peripheral electrode by screen printing, the desired peripheral electrodes can be formed by designing the screen printing mask to the graphic pattern of the first peripheral electrode and changing the main structure corresponding to the graphic pattern of the second peripheral electrode.

[0139] Next, a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0140] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0141] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0142] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900°C or higher and 1400°C or lower.

[0143] Subsequently, the external electrodes 30 are formed on the laminate 12 . That is, the obtained laminate 12 is aligned on a work table, and the thin film layer 32 is formed on the first surface 12a and the second surface 12b by sputtering.

[0144] Thereafter, an underlayer plating layer 34 is formed on the thin film layer 32 and the surface of the laminate 12, and a surface plating layer 36 is formed to cover the underlayer plating layer 34. More specifically, a Cu plating layer is formed on the thin film layer 32 as the underlayer plating layer 34. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0145] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in Fig. 1 can be manufactured. When manufacturing the multilayer ceramic capacitor 10A of the first modified example shown in Fig. 13, the multilayer ceramic capacitor 10B of the second modified example shown in Fig. 14, and the multilayer ceramic capacitor 10B of the third modified example shown in Fig. 15, the shapes of corresponding parts are made different in each process as appropriate.

[0146] B. Second Embodiment 1. Multilayer ceramic capacitors An example of the multilayer ceramic capacitor 110 according to the second embodiment of the present invention will be described.

[0147] FIG. 16 is an external perspective view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 17 is a front view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 16, illustrating the structure of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 16. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 16. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 16. FIG. 22A is a cross-sectional view taken along line XXIIA-XXIIA in FIG. 17. FIG. 22B is a cross-sectional view taken along line XXIIB-XXIIB in FIG. 17. FIG. 23 is an exploded perspective view of the laminate shown in FIG. 16. Note that the same or corresponding components as those in FIGS. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0148] The multilayer ceramic capacitor 110 includes a laminate 112 and external electrodes 130 .

[0149] (Laminate) The laminate 12 includes a plurality of dielectric layers 114 and a plurality of internal electrodes 116. The dielectric layers 114 include an inner dielectric layer 114a and an outer dielectric layer 114b. The internal electrodes 116 include a first internal electrode 116a and a second internal electrode 116b.

[0150] The laminate 112 also has an inner layer portion 118, a first outer layer portion 120a located on the first surface 112a side, and a second outer layer portion 120b located on the second surface 112b side.

[0151] The first outer layer portion 120a is located on the first surface 112a side of the laminate 112 and is an aggregate of multiple outer dielectric layers 114b located between the first surface 112a and the internal electrode 116 closest to the first surface 112a.

[0152] The second outer layer portion 120b is located on the second surface 112b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 114b located between the second surface 112b and the internal electrode 116 closest to the second surface 112b.

[0153] The region sandwiched between the first outer layer portion 1120a and the second outer layer portion 120b is the inner layer portion 118.

[0154] The inner layer portion 118 has a first inner electrode 116a having one end exposed to the third surface 112c and the other end exposed to the fourth surface 112d, a second inner electrode 116b having one end exposed to the third surface 112c and the other end exposed to the fourth surface 112d, and an inner dielectric layer 114a.

[0155] The material of the dielectric layer 114 is the same as that of the dielectric layer 14, and therefore a description thereof will be omitted.

[0156] (Internal electrode) The internal electrodes 116 include a plurality of first internal electrodes 116a and a plurality of second internal electrodes 116b. The first internal electrodes 116a and the second internal electrodes 116b are alternately stacked with the dielectric layers 114 interposed therebetween.

[0157] The first internal electrode 116a is disposed on the surface of the inner dielectric layer 114a. The first internal electrode 116a faces the first surface 112a and the second surface 112b, has a first opposing electrode portion 122a facing the second internal electrode 116b, and is laminated in the direction connecting the first surface 112a and the second surface 112b.

[0158] The first internal electrode 116a is led out to the third surface 112c of the laminate 112 by a first lead electrode portion 124a, and is led out to the fourth surface 112d of the laminate 112 by a second lead electrode portion 124b. The first lead electrode portion 124a is led out to the fifth surface 112e of the laminate 112, and the second lead electrode portion 124b is led out to the sixth surface 112f of the laminate 112.

[0159] The second internal electrode 116b is arranged on a surface of the inner dielectric layer 114a different from the inner dielectric layer 114a on which the first internal electrode 116a is arranged. The second internal electrode 116b faces the first surface 112a and the second surface 112b, has a second opposing electrode portion 122b facing the first internal electrode 116a, and is laminated in the direction connecting the first surface 112a and the second surface 112b.

[0160] The second internal electrode 116b is extended to the third surface 112c of the laminate 12 by a third extension electrode portion 124c, and is extended to the fourth surface 112d of the laminate 112 by a fourth extension electrode portion 124d. The third extension electrode portion 124c is extended to the sixth surface 112f side of the laminate 112, and the fourth extension electrode portion 124d is extended to the fifth surface 112e side of the laminate 112.

[0161] The first internal electrode 116a and the second internal electrode 116b are not exposed on the fifth surface 112e and the sixth surface 112f of the laminate 112.

[0162] Furthermore, when the multilayer ceramic capacitor 110 is viewed from the stacking direction x, it is preferable that a line connecting the first extraction electrode portion 124a and the second extraction electrode portion 124b of the first internal electrode 116a intersects with a line connecting the third extraction electrode portion 124c and the fourth extraction electrode portion 124d of the second internal electrode 116b.

[0163] Furthermore, on the surfaces 112c, 112d, 112e, and 112f of the laminate 112, it is preferable that the first extraction electrode portion 124a of the first internal electrode 116a and the fourth extraction electrode portion 124d of the second internal electrode 116b are extracted to opposing positions, and that the second extraction electrode portion 124b of the first internal electrode 116a and the third extraction electrode portion 124c of the second internal electrode 116b are extracted to opposing positions.

[0164] As shown in FIG. 21, the laminate 112 also includes a side portion (W gap) 126a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 122b of the second internal electrode 116b and the third surface 112c, and a side portion (W gap) 26b of the laminate 112 located between the other end in the first direction y of the first opposing electrode portion 122a of the first internal electrode 116a and the fourth surface 112d.

[0165] Furthermore, as shown in FIG. 20, the laminate 112 includes an end portion (L gap) 127a of the laminate 112 located between one end in the second direction z of the second opposing electrode portion 122b of the second internal electrode 116b and the fifth surface 112e, and a side portion (L gap) 127b of the laminate 112 located between the other end in the second direction z of the first opposing electrode portion 122a of the first internal electrode 116a and the sixth surface 112f.

[0166] (surrounding electrodes) The inner layer portion 118 of the laminate 112 further includes a first peripheral electrode 128 and a second peripheral electrode 129. The first peripheral electrode 128 is disposed around the first internal electrode 116a. The second peripheral electrode 129 is disposed around the second internal electrode 116b.

[0167] The first peripheral electrode 128 has one first peripheral electrode 128a and the other first peripheral electrode 128b.

[0168] The first peripheral electrodes 128a, 128b are alternately stacked with the inner dielectric layers 114a and are arranged on the same plane as the first internal electrode 116a arranged on the inner dielectric layer 114a. As shown in Fig. 22A, each of the first peripheral electrodes 128a, 128b is arranged spaced apart from the first internal electrode 116a.

[0169] The first peripheral electrode 128a is disposed in the region between the first internal electrode 116a and the third and sixth surfaces 112c and 112f. One end of the first peripheral electrode 128a is connected to the first extraction electrode portion 124a of the first internal electrode 116a, and the other end of the first peripheral electrode 128a is exposed on the fourth surface 112d. This increases the bonding area between the first peripheral electrode 128a and the metal component in the external electrode 130. Note that the other end of the first peripheral electrode 128a does not necessarily have to be exposed on the fourth surface 112d. The first peripheral electrode 128b is disposed in the region between the first internal electrode 116a and the fourth and fifth surfaces 112d, 112e. One end of the first peripheral electrode 128b is exposed on the third surface 112c, and the other end of the first peripheral electrode 128a is connected to the second extraction electrode portion 124b of the first internal electrode 116a. This increases the bonding area between the first peripheral electrode 128b and the metal component in the external electrode 130. Note that one end of the first peripheral electrode 128b does not have to be exposed on the third surface 112c.

[0170] The second peripheral electrode 129 has one second peripheral electrode 129a and the other second peripheral electrode 129b.

[0171] The second peripheral electrodes 129a, 129b are alternately stacked with the dielectric layers 114 and are arranged on the same plane as the second internal electrode 116b arranged on the dielectric layer 114. As shown in Fig. 22B, each of the second peripheral electrodes 129a, 129b is arranged spaced apart from the second internal electrode 116b.

[0172] The second peripheral electrode 129a is disposed in the region between the second internal electrode 116b and the third and fifth surfaces 12c and 12e. One end of the second peripheral electrode 129a is connected to the third extraction electrode portion 24c of the second internal electrode 116b, and the other end of the second peripheral electrode 29a is exposed on the fourth surface 112d. This increases the bonding area between the second peripheral electrode 129a and the metal component in the external electrode 130. The other end of the second peripheral electrode 129a does not have to be exposed on the fourth surface 112d. The second peripheral electrode 129b is disposed in the region between the second internal electrode 116b and the fourth and sixth surfaces 112d, 112f. One end of the second peripheral electrode 129b is exposed on the third surface 112c, and the other end of the second peripheral electrode 129b is connected to the fourth extraction electrode portion 124d of the second internal electrode 116b. This increases the bonding area between the second peripheral electrode 129b and the metal component in the external electrode 130. Note that one end of the second peripheral electrode 129b does not have to be exposed on the third surface 112c.

[0173] (external electrode) As shown in FIGS. 1 to 7, an external electrode 130 is disposed on the laminate 12. The external electrodes 130 include a plurality of external electrodes 130 connected to the first internal electrode 116a and the second internal electrode 116b. The external electrodes 130 include a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0174] The first external electrode 130a is disposed on the third surface 112c so as to cover the first lead electrode portion 124a of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a and a portion of the second surface 112b. The first external electrode 130a is electrically connected to the first lead electrode portion 124a of the first internal electrode 116a.

[0175] The second external electrode 130b is disposed on the fourth surface 112d so as to cover the second lead electrode portion 124b of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a and a portion of the second surface 112b. The second external electrode 130b is electrically connected to the second lead electrode portion 124b of the first internal electrode 116a.

[0176] The third external electrode 130c is disposed on the third surface 112c so as to cover the third lead electrode portion 124c of the second internal electrode 116b, and further so as to cover a portion of the first surface 112a and a portion of the second surface 112b. The third external electrode 130c is electrically connected to the third lead electrode portion 124c of the second internal electrode 116b.

[0177] The fourth external electrode 130d is disposed on the fourth surface 112d so as to cover the fourth lead electrode portion 124d of the second internal electrode 116b, and further so as to cover a portion of the first surface 112a and a portion of the second surface 112b. The fourth external electrode 130d is electrically connected to the fourth lead electrode portion 124d of the second internal electrode 116b.

[0178] Furthermore, as shown in FIG. 16, it is preferable that the external electrode 130 arranged on the fifth surface 112e or the sixth surface 112f from which the internal electrode 116 is not drawn out covers in a U-shape one of the short sides of the side surface from which the internal electrode 116 is not drawn out and the portion from the end of that short side to the middle of both long sides.

[0179] In the laminate 112, the first opposing electrode portion 122a of the first internal electrode 116a and the second opposing electrode portion 122b of the second internal electrode 116b face each other via the internal dielectric layer 114a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 130a and the second external electrode 130b to which the first internal electrode 116a is connected, and the third external electrode 130c and the fourth external electrode 130d to which the second internal electrode 116b is connected, thereby realizing the characteristics of a capacitor.

[0180] Each of the first external electrode 130a, the second external electrode 130b, the third external electrode 130c, and the fourth external electrode 130d preferably has a thin film layer 132, an underlayer plating layer 134, and a surface plating layer 136.

[0181] The multilayer ceramic capacitor 110 shown in FIG. 16 provides the same effects as the multilayer ceramic capacitor 10 according to the first embodiment.

[0182] The multilayer ceramic capacitor 110 according to the second embodiment of the present invention may also be combined with all or part of the first to third modified examples described above. Furthermore, it may also be combined with all or part of the first to third modified examples of the multilayer ceramic capacitor 10 according to the first embodiment, and with other modified examples shown in the respective drawings.

[0183] 2. Manufacturing method of multilayer ceramic capacitors A method for manufacturing a multilayer ceramic capacitor according to the second embodiment will be described below.

[0184] First, a dielectric sheet, a conductive paste for the internal electrodes, and a conductive paste for the peripheral electrodes are prepared. The dielectric sheet, the conductive paste for the internal electrodes, and the conductive paste for the peripheral electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0185] Next, conductive paste for the internal electrodes and conductive paste for the peripheral electrodes are printed in predetermined patterns on the dielectric sheets by, for example, inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are formed, and a dielectric sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are formed. Thereafter, the sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are printed and the sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are printed are laminated to form the portion that becomes the inner layer portion 18.

[0186] In printing the patterns using each conductive paste, first, the patterns using the conductive paste for the internal electrodes are printed, and then the patterns using the conductive paste for the peripheral electrodes are printed.

[0187] Next, a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked to form the portion that will become the first outer layer portion 120a on the first surface 112a side. After that, the portion that will become the inner layer portion 118 prepared above is stacked, and a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked on top of this portion that will become the inner layer portion 118 to form the portion that will become the second outer layer portion 120b on the second surface 112b side. In this way, a laminated sheet is produced.

[0188] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0189] Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0190] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900°C or higher and 1400°C or lower.

[0191] Next, the obtained laminate 12 is aligned on a work table, and the thin film layer 32 is formed on the first surface 12a and the second surface 12b by sputtering.

[0192] At this time, the first lead electrode portion 124a of the first internal electrode 116a and the third lead electrode portion 124c of the second internal electrode 116b are exposed from the third surface 112c of the laminate 112. Furthermore, the second lead electrode portion 124b of the first internal electrode 116a and the fourth lead electrode portion 124d of the second internal electrode 116b are exposed from the fourth surface 112d of the laminate 112.

[0193] Subsequently, the external electrodes 130 are formed on the laminate 112 . That is, the obtained laminate 112 is aligned on a work table, and the thin film layer 132 is formed on the first surface 112a and the second surface 112b by sputtering.

[0194] Thereafter, an underlayer plating layer 134 is formed on the thin film layer 132 and the surface of the laminate 112, and a surface plating layer 136 is formed to cover the underlayer plating layer 134. More specifically, a Cu plating layer is formed on the thin film layer 132 as the underlayer plating layer 134. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 134 as the surface plating layer 136. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0195] At this time, the external electrode 130 arranged on the side surface from which the internal electrode 116 is not pulled out is formed in a U-shape by the underlayer plating layer 134 and the surface plating layer 136 so as to cover both short sides of the side surface from which the internal electrode 116 is not pulled out and the portions from the ends of both short sides to the middle parts of both long sides.

[0196] In this manner, a multilayer ceramic capacitor 110 as shown in FIG. 16 is manufactured.

[0197] C. Third embodiment 1. Multilayer ceramic capacitors An example of the multilayer ceramic capacitor 210 according to the third embodiment of the present invention will be described.

[0198] Fig. 24 is an external perspective view, from one side, showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Fig. 25 is an external perspective view, from the other side, showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI in Fig. 24. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII in Fig. 24. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII in Fig. 24. Fig. 29 is a cross-sectional view taken along line XXIX-XXIX in Fig. 24. Note that the same or corresponding components as those in Figs. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0199] The multilayer ceramic capacitor 210 includes a laminate 12 and a plurality of external electrodes 230 .

[0200] (Laminate) In the multilayer ceramic capacitor 210 according to the second embodiment, the laminate 12 has the same configuration as the laminate 12 according to the first embodiment of the present invention shown in FIG.

[0201] (Internal electrode) The first internal electrode 16a is extended to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extension electrode portion 24a, and is extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the second extension electrode portion 24b.

[0202] The second internal electrode 16b is extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d.

[0203] (surrounding electrodes) The inner layer portion 18 of the laminate 12 further has a first peripheral electrode 28 and a second peripheral electrode 29. The first peripheral electrode 28 is disposed around the first internal electrode 16a. The second peripheral electrode 29 is disposed around the second internal electrode 16b.

[0204] The first peripheral electrode 28 has one first peripheral electrode 28a and the other first peripheral electrode 28b.

[0205] The first peripheral electrodes 28a, 28b are alternately stacked with the dielectric layers 14 and are arranged on the same plane as the first internal electrode 16a arranged on the dielectric layer 14. Each of the first peripheral electrodes 28a, 28b is arranged spaced apart from the first internal electrode 16a.

[0206] The first peripheral electrode 28a is disposed in a region between the first internal electrode 16a and the third and sixth surfaces 12c, 12f. One end of the first peripheral electrode 28a is connected to the first lead electrode portion 24a of the first internal electrode 16a, and the other end of the first peripheral electrode 28a is connected to the second lead electrode portion 24b of the first internal electrode 16a. The first peripheral electrode 28b is disposed in a region between the first internal electrode 16a and the fourth and fifth surfaces 12d, 12e. One end of the first peripheral electrode 28b is connected to the first lead electrode portion 24a of the first internal electrode 16a, and the other end of the first peripheral electrode 28a is connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0207] The second peripheral electrode 29 has one second peripheral electrode 29a and the other second peripheral electrode 29b.

[0208] The second peripheral electrodes 29a, 29b are alternately stacked with the dielectric layers 14 and are arranged on the same plane as the second internal electrode 16b arranged on the dielectric layer 14. Each of the second peripheral electrodes 29a, 29b is arranged spaced apart from the second internal electrode 16b.

[0209] The second peripheral electrode 29a is disposed in a region between the second internal electrode 16b and the third and fifth surfaces 12c, 12e. One end of the second peripheral electrode 29a is connected to the third lead electrode portion 24c of the second internal electrode 16b, and the other end of the second peripheral electrode 29a is connected to the fourth lead electrode portion 24d of the second internal electrode 16b. The second peripheral electrode 29b is disposed in a region between the second internal electrode 16b and the fourth and sixth surfaces 12d, 12f. One end of the second peripheral electrode 29b is connected to the third lead electrode portion 24c of the second internal electrode 16b, and the other end of the second peripheral electrode 29b is connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0210] In the multilayer ceramic capacitor 210 according to the third embodiment, the external electrodes 230 are arranged so as to cover the first surface 12a of the multilayer body 12 but not the second surface 12b.

[0211] (external electrode) As shown in FIGS. 24 to 29, an external electrode 230 is disposed on the laminate 12. The external electrodes 230 include a plurality of external electrodes 230 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrodes 230 include a first external electrode 230a, a second external electrode 230b, a third external electrode 230c, and a fourth external electrode 230d.

[0212] The first external electrode 230a is disposed on the third surface 12c and the fifth surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The first external electrode 230a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0213] The second external electrode 230b is disposed on the fourth surface 12d and the sixth surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The second external electrode 230b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0214] The third external electrode 230c is disposed on the third surface 12c and the sixth surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a portion of the first surface 12a. The third external electrode 230c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0215] The fourth external electrode 230d is disposed on the fourth surface 12d and the fifth surface 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first surface 12a. The fourth external electrode 230d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0216] The multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 24 has the same effects as the multilayer ceramic capacitor 10 described above, and also has the following effects. That is, according to the multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 24, even in a multilayer ceramic capacitor in which the external electrodes 130 are disposed so as to cover only the first surface 12a of the laminate 12 and not cover the second surface 12b, it is possible to provide a multilayer ceramic capacitor having a reduced height without impairing mountability during mounting, similar to the multilayer ceramic capacitor 10 of FIG. 1.

[0217] The multilayer ceramic capacitor 210 according to the third embodiment may be configured such that the external electrodes 230 cover a portion of the second surface 12b and do not cover the first surface 12a.

[0218] The multilayer ceramic capacitor 210 according to the third embodiment of the present invention may also be combined with all or part of the first to third modified examples described above. Furthermore, it may also be combined with all or part of the first to third modified examples of the multilayer ceramic capacitor 10 according to the first embodiment, and with other modified examples shown in the respective drawings.

[0219] 2. Manufacturing method of multilayer ceramic capacitors A method for manufacturing a multilayer ceramic capacitor according to the third embodiment will be described below.

[0220] First, a dielectric sheet, a conductive paste for the internal electrodes, and a conductive paste for the peripheral electrodes are prepared. The dielectric sheet, the conductive paste for the internal electrodes, and the conductive paste for the peripheral electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0221] Next, conductive paste for the internal electrodes and conductive paste for the peripheral electrodes are printed in predetermined patterns on the dielectric sheets by, for example, inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are formed, and a dielectric sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are formed. Thereafter, the sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are printed and the sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are printed are laminated to form the portion that becomes the inner layer portion 18.

[0222] In printing the patterns using each conductive paste, first, the patterns using the conductive paste for the internal electrodes are printed, and then the patterns using the conductive paste for the peripheral electrodes are printed.

[0223] Next, a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0224] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0225] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0226] Subsequently, the external electrodes 230 are formed on the laminate 12 . That is, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900°C or higher and 1400°C or lower.

[0227] Next, the obtained laminate 12 is aligned on a work table, and a thin film layer 32 is formed on the first surface 12a by sputtering.

[0228] Thereafter, an underlayer plating layer 34 is formed on the thin film layer 32 and the surface of the laminate 12, and a surface plating layer 36 is formed to cover the underlayer plating layer 34. More specifically, a Cu plating layer is formed on the thin film layer 32 as the underlayer plating layer 34. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0229] In this manner, the multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 24 can be manufactured.

[0230] According to the method for manufacturing the multilayer ceramic capacitor of this embodiment, it is possible to reduce the thickness of the external electrode 230 formed on the first surface 12a in the stacking direction x, which is the dimension T, and therefore it is possible to provide a multilayer ceramic capacitor with a reduced height without impairing mountability during mounting.

[0231] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0232] <1> a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; four external electrodes arranged on the laminate; A multilayer ceramic capacitor comprising: where L is the dimension of the multilayer ceramic capacitor in the first direction and W is the dimension of the multilayer ceramic capacitor in the second direction, and 0.85≦L / W≦1.00; The laminate is a first internal electrode having one end exposed on the third surface and the fifth surface and the other end exposed on the fourth surface and the sixth surface; a second internal electrode having one end exposed on the third surface and the sixth surface and the other end exposed on the fourth surface and the fifth surface; a surrounding electrode; and The surrounding electrode is a multilayer ceramic capacitor disposed in a region between the first internal electrode and any one of the third surface to the sixth surface;

[0233] <2> The surrounding electrode is disposed in a region between the second internal electrode and the third surface to the sixth surface, <1> The multilayer ceramic capacitor according to claim 1.

[0234] <3> the shortest distance between the peripheral electrode and the third surface to the sixth surface is 5.0 μm or more and 20 μm or less; <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0235] <4> a width in the first direction of the peripheral electrode disposed between the third surface and the first internal electrode is 1.0% or more and 30% or less of a distance between the third surface and the first internal electrode; <1> Or <3> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0236] <5> a width in the second direction of the peripheral electrode disposed between the fifth surface and the first internal electrode is 1.0% or more and 30% or less of a distance between the fifth surface and the first internal electrode; <1> Or <4> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0237] <6> the peripheral electrodes disposed between the third surface and the first internal electrodes are discontinuously disposed in the second direction. <1> Or <5> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0238] <7> the peripheral electrode disposed between the fifth surface and the first internal electrode is discontinuously disposed in the first direction. <6> The multilayer ceramic capacitor according to claim 1.

[0239] <8> a distance in the second direction between two of the peripheral electrodes arranged between the third surface and the first internal electrode and adjacent to each other in the second direction is 1.0 μm or more and 10 μm or less; <6> The multilayer ceramic capacitor according to claim 1.

[0240] <9> a distance in the first direction between two of the peripheral electrodes arranged between the fifth surface and the first internal electrode and adjacent to each other in the first direction is 1.0 μm or more and 10 μm or less; <7> The multilayer ceramic capacitor according to claim 1.

[0241] <10> the peripheral electrode is not disposed on a line connecting an intersection of the third surface and the sixth surface and an intersection of the fourth surface and the fifth surface; <1> Or <9> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0242] <11> the peripheral electrodes are not arranged within 1.0 μm or more and 10 μm or less from a corner of the first internal electrode that is located at a portion of the first internal electrode that is longest in a direction connecting an intersection of the third surface and the sixth surface and an intersection of the fourth surface and the fifth surface; <10> The multilayer ceramic capacitor according to claim 1.

[0243] <12> the first internal electrode has an extraction electrode portion exposed on the third surface and the fifth surface, and the extraction electrode portion is not connected to the surrounding electrode; <1> Or <11> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0244] <13> The distance between the first internal electrode and the peripheral electrode is 1.0 μm or more and 10 μm or less. <12> The multilayer ceramic capacitor according to claim 1.

[0245] <14> a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; four external electrodes arranged on the laminate; A multilayer ceramic capacitor comprising: where L is the dimension of the multilayer ceramic capacitor in the first direction and W is the dimension of the multilayer ceramic capacitor in the second direction, and 0.85≦L / W≦1.00; The laminate is a first internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface; a second internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface; a surrounding electrode; and The surrounding electrode is a multilayer ceramic capacitor disposed in a region between the first internal electrode and any one of the third surface to the sixth surface;

[0246] <15> The surrounding electrode is disposed in a region between the second internal electrode and the third surface to the sixth surface, <14> The multilayer ceramic capacitor according to claim 1.

[0247] <16> the peripheral electrode is exposed on the third surface and the fourth surface; <14> or <15> The multilayer ceramic capacitor according to claim 1.

[0248] <17> a metal component of the same kind as the first internal electrode and the peripheral electrode is disposed in a region between the peripheral electrode and the first internal electrode; <14> Or <16> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0249] <18> the first internal electrode further has one end exposed on the fifth surface and the other end exposed on the sixth surface, the second internal electrode further has one end exposed on the sixth surface and the other end exposed on the fifth surface, a metal component of the same kind as the first internal electrode and the peripheral electrode is disposed in a region between the peripheral electrode and the first internal electrode; <14> Or <17> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0250] <19> a metal component of the same kind as the second internal electrode and the peripheral electrode is disposed in a region between the peripheral electrode and the second internal electrode; <15> or <18> The multilayer ceramic capacitor according to claim 1. [Explanation of symbols]

[0251] 10, 10A, 10B, 10C, 110, 210 Multilayer ceramic capacitors 12 Laminate 12a, 112a First side 12b, 112b Second Side 12c, 112c Third face 12d, 112d Fourth Face 12e, 112e Fifth Face 12f, 112f 6th side 14, 114 Dielectric layer 14a, 114a Inner dielectric layer 14b, 114b outer dielectric layer 16, 116 internal electrode 16a, 116a First internal electrode 16b, 116b Second internal electrode 18, 118 Inner layer 20a, 120a First outer layer 20b, 120b Second outer layer 22a, 122a First opposing electrode portion 22b, 122b Second opposing electrode portion 24a, 124a First extraction electrode portion 24b, 124b Second extraction electrode portion 24c, 124c Third extraction electrode portion 24d, 124d Fourth extraction electrode part 26a, 26b, 126a, 126b: Sides of stack (W gap) 27a, 27b, 127a, 127b Ends of stack (L gap) 28, 28a, 28a1, 28a2, 28b, 28b1, 28b2, 128a, 128b first peripheral electrodes 29, 29a, 29a1, 29a2, 29b, 29b1, 29b2, 129a, 129b second surrounding electrode 30, 130, 230 external electrode 30a, 130a, 230a: First outer electrode 30b, 130b, 230b Second outer electrodes 30c, 130c, 230c Third external electrode 30d, 130d, 230d Fourth external electrode 32, 132 thin film layer 32a, 132a First thin film layer 32b, 132b Second thin film layer 32c, 132c Third thin film layer 32d, 132d Fourth thin film layer 34, 134 Undercoat layer 34a, 134a First lower plating layer 34b, 134b Second lower plating layer 34c, 134c Third undercoat layer 34d, 134d Fourth lower plating layer 36, 136 Surface plating layer 36a, 136a First surface plating layer 36b, 136b Second surface plating layer 36c, 136c Third surface plating layer 36d, 136d Fourth surface plating layer 33 Direct plating layer 33a First direct plating layer 33b Second direct plating layer x stacking direction y primary direction z second direction L is the dimension of the multilayer ceramic capacitor in the first direction W is the dimension in the second direction of the multilayer ceramic capacitor T Dimension in the lamination direction of a multilayer ceramic capacitor

Claims

1. a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; four external electrodes disposed on the laminate; A multilayer ceramic capacitor comprising: where L is the dimension of the multilayer ceramic capacitor in the first direction and W is the dimension of the multilayer ceramic capacitor in the second direction, and 0.85≦L / W≦1.00; The laminate is a first internal electrode having one end exposed on the third surface and the fifth surface and the other end exposed on the fourth surface and the sixth surface; a second internal electrode having one end exposed on the third surface and the sixth surface and the other end exposed on the fourth surface and the fifth surface; a surrounding electrode; and The surrounding electrode is a multilayer ceramic capacitor disposed in a region between the first internal electrode and any one of the third surface to the sixth surface;

2. The surrounding electrode is 2. The multilayer ceramic capacitor according to claim 1, wherein the second internal electrode is disposed in a region between the second internal electrode and any one of the third surface to the sixth surface.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the shortest distance between said peripheral electrode and said third surface through said sixth surface is 5.0 μm or more and 20 μm or less.

4. 2. The multilayer ceramic capacitor according to claim 1, wherein the width in the first direction of the peripheral electrode disposed between the third surface and the first internal electrode is 1.0% or more and 30% or less of the distance between the third surface and the first internal electrode.

5. 4. The multilayer ceramic capacitor according to claim 3, wherein the width in the second direction of the peripheral electrode disposed between the fifth surface and the first internal electrode is 1.0% or more and 30% or less of the distance between the fifth surface and the first internal electrode.

6. 2. The multilayer ceramic capacitor according to claim 1, wherein the peripheral electrodes disposed between the third surface and the first internal electrodes are discontinuously disposed in the second direction.

7. The multilayer ceramic capacitor according to claim 6 , wherein the peripheral electrodes disposed between the fifth surface and the first internal electrodes are discontinuously disposed in the first direction.

8. 7. The multilayer ceramic capacitor according to claim 6, wherein the distance in the second direction between two of the peripheral electrodes arranged between the third surface and the first internal electrode and adjacent to each other in the second direction is 1.0 μm or more and 10 μm or less.

9. 8. The multilayer ceramic capacitor according to claim 7, wherein the distance in the first direction between two of the peripheral electrodes arranged between the fifth surface and the first internal electrode and adjacent to each other in the first direction is 1.0 μm or more and 10 μm or less.

10. 2. The multilayer ceramic capacitor according to claim 1, wherein the peripheral electrode is not disposed on a line connecting an intersection of the third surface and the sixth surface and an intersection of the fourth surface and the fifth surface.

11. 11. The multilayer ceramic capacitor according to claim 10, wherein the peripheral electrodes are not arranged within 1.0 μm to 10 μm from a corner of the first internal electrode located at a portion of the first internal electrode that is longest in a direction connecting an intersection of the third surface and the sixth surface and an intersection of the fourth surface and the fifth surface.

12. 2. The multilayer ceramic capacitor according to claim 1, wherein the first internal electrode has an extraction electrode portion exposed on the third surface and the fifth surface, and the extraction electrode portion is not connected to the peripheral electrode.

13. 13. The multilayer ceramic capacitor according to claim 12, wherein the distance between the lead electrode portion of the first internal electrode and the peripheral electrode is 1.0 μm or more and 10 μm or less.

14. a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; four external electrodes disposed on the laminate; A multilayer ceramic capacitor comprising: where L is the dimension of the multilayer ceramic capacitor in the first direction and W is the dimension of the multilayer ceramic capacitor in the second direction, and 0.85≦L / W≦1.00; The laminate is a first internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface; a second internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface; a surrounding electrode; and The surrounding electrode is a multilayer ceramic capacitor disposed in a region between the first internal electrode and any one of the third surface to the sixth surface;

15. The surrounding electrode is 15. The multilayer ceramic capacitor according to claim 14, wherein the second internal electrode is disposed in a region between the second internal electrode and any one of the third surface to the sixth surface.

16. 16. The multilayer ceramic capacitor according to claim 14, wherein the peripheral electrode is exposed on the third surface and the fourth surface.

17. 15. The multilayer ceramic capacitor according to claim 14, wherein the same metal component as the first internal electrode and the peripheral electrode is disposed in a region between the peripheral electrode and the first internal electrode.

18. the first internal electrode further has one end exposed on the fifth surface and the other end exposed on the sixth surface; the second internal electrode further has one end exposed on the sixth surface and the other end exposed on the fifth surface, 15. The multilayer ceramic capacitor according to claim 14, wherein the same metal component as the first internal electrode and the peripheral electrode is disposed in a region between the peripheral electrode and the first internal electrode.

19. 19. The multilayer ceramic capacitor according to claim 15, wherein the same kind of metal component as the second internal electrode and the peripheral electrode is disposed in a region between the peripheral electrode and the second internal electrode.

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